LAPIS FEDL7204-003-02 Voip codec Datasheet

FEDL7204-003-02
Issue Date: Oct 14, 2011
ML7204-003
VoIP CODEC
GENERAL DESCRIPTION
The ML7204-003 is a speech CODEC for VoIP. As a speech CODEC, this LSI allows selection of
G.729.A/G711 and supports the PLC (Packet Loss Concealment) function.
With an echo canceler that handles 32 ms-delay and FSK detection/generation, DTMF detection/generation, and
tone detection/generation functions, the ML7204-003 is the most suitable LSI for adding the VoIP function to
TAs and routers.
FEATURES
 Power supply voltage
Digital power supply voltage (DVDD0, 1, 2):
3.0 to 3.6 V
Analog power supply voltage (AVDD):
3.0 to 3.6 V
 Speech CODEC:
G.729.A (8 kbps)/G.711 (64 kbps) -law and A-law (supports individual setting for transmission and
reception)
Supports ITU-T G.711 Appendix 1 compliant PLC (Packet Loss Concealment) function
Supports the 2-channel processing function (for 3-way communication)
 Built-in FIFO buffer (640 bytes) for transmission/reception data transfer
Allows selection of Frame/DMA (slave) interface
 Provided with echo canceler for handling 32 ms delay and Range Controllers
 DTMF detection
 DTMF generation (the tone generation function enables generation of DTMF signals)
 Tone detection:
2 types (1650 Hz and 2100 Hz: Detection frequency can be changed)
 Tone generation:
2 types
 FSK detection
 FSK generation
 Built-in 16-bit timer:
1 channel
 Dial pulse detection function (secondary function of general-purpose I/O ports)
 Dial pulse transmission function (secondary function of general-purpose I/O ports)
 General-purpose I/O ports : Equipped with 7 ports (with some of them having secondary function allocation)
 Two types of built-in linear PCM CODEC (CODEC_A and CODEC_B)
 Analog interface
CODEC_A side: Incorporates one type each of input amplifier and output amplifier (10 k driving)
CODEC_B side: Incorporates one type each of input amplifier and output amplifier (10 k driving)
 PCM interface coding format:
Allows selection of 16-bit linear/G.711 (64 kbps) -law or A-law
 PCM serial transmission rate: 64 kHz to 2.048 MHz (fixed to 2.048 MHz for output)
 PCM time slot assignment function (allows up to 2 slots for input and 1 slot for output individually)
When set to -law/A-law: Supports up to 32 slots (BCLK: 2.048 MHz)
When set to 16-bit linear: Supports up to 16 slots (BCLK: 2.048 MHz)
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 Master clock frequency:
12.288 MHz (crystal; external input)
 Supports hardware and software power down
 Package:
64-pin plastic QFP (QFP64-P-1414-0.80-BK)
(ML7204-003GA)
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VGB
VREGOUT
AVDD
AGND
DGND0
DGND1
DGND2
DVDD0
DVDD1
DVDD2
AVREF
VFRO0
AIN0P
AIN0N
GSX0
VFRO1
AIN1N
GSX1
AMP2
POWER
VREF
10kΩ
AMP0
10kΩ
AMP3
10kΩ
AMP1
10kΩ
BPF
LPF
D/A0
CKGN
LPF
Linear PCM
Codec(A系)
A/D0
D/A1
OSC
12.288MHz
PLL
BPF
Linear PCM
Codec(B系)
A/D1
SYNC(8kHz)
MCK
CODECA_RXEN
RXDET
RXDET_PCM
TXDETB
TXDETA
各種検出器パス
RXGENA
RXGAINA
STGAINA
TXGAINA CODECA_TXEN
TXDETA
CODECB_RXEN
CODECB_TXEN
RXGENB
RXGAINB
STGAINB
TXGAINB
TXDETB
Rout
Sin
+
TONE_DET1
TONE_DET0
DTMF_REC
ATTr
TONE1_DET
TONE0_DET
DTMF_CODE[3:0]
FDET_D[7:0]
DTMF_DET
Rin
GPAD Sout
Echo Canceller
Center
Clip
FDET_RQ
FDET_FER/FDET_OER
GC
- ATTs
AFF
FSK_DET
LPAD
LPEN1
LPEN0
FSK_GEN
RXGENB_EN
RXGENA_EN
SC_RXEN
RXGAIN_SC
RXGEN
RXGENB
RXGENA
TXGEN
RXDET
RX_SIG
SC_TXEN
PCM_RXEN1
RXGAIN_PCM1
PCM_TXEN0
PCM_TXEN1
(注）入出力端子について
100ピンパッケージの場合だけ使用可能です。
FGEN_FLAG
TONE_GEN0
(TONEA/B)
TGEN0_EXFLAG
TONE_GEN1
(TONEC/D)
TGEN1_EXFLAG
各種生成器パス
RXGEN
PCM_RXEN0
TXGEN
RC0
TXGAIN_SC
RXDET_PCM
RXGAIN_PCM2
PCM_TXEN2
RC1
TXGAIN_PCM1
RXGAIN_PCM0
PCM_RXEN2
TXGAIN_PCM2
TXGAIN_PCM0
RX_SIG
RXGAIN
_CH2
RXGAIN
_CH1
RX1TX2
_GAIN
TXGAIN
_CH2
TXGAIN
_CH1
G.711
Decoder
DPDET
DPGEN
TIMER
DC_E
N
CH2
CH1
CH2
FDET_RQ
DP_DET
TONE1_DET
TONE0_DET
DTMF_CODE[3:0]
DTMF_DET
DP_DET
GPIO0
GPIO2
TIMOVF
DC_E
N
T
S
W
T
S
W
TIMOVF
FGEN_FLAG
FDET_FER/FDET_OER
G.711
Decoder
CH1
Speech Codec
G.729.A
RX2TX1
_GAIN
G.711
Encoder
G.729.A
RXGAIN_ITS2
RXGAIN_ITS1
G.711
Decoder
G.711
Encoder
G.711
Encoder
PCM Codec
PCM I/F
S/P
P/S
6
GPIOB
[5:0]
8
INT
Control
Register
Frame/DMA
Controller
RX
Buffer1
RX
Buffer0
Bus Control
Unit
TX
Buffer1
TX
Buffer0
ITS2
CONT
ITS1
CONT
ITS3
CONT
OTS2
CONT
OTS1
CONT
4
8b
16b
INTB/
GPIOA[6]
A0-A7
D0-D15
CSB
RDB
WRB
FR0B
ACK1B/
GPIOA[5]
ACK0B/
GPIOA[4]
FR1B
PCMI
CLKSEL
BCLK
SYNC
PCMO
FEDL7204-003-02
ML7204-003
BLOCK DIAGRAM
GPIOA
[3:0]
GPIOC
[7:0]
TST1
TST0
PDNB
CLKOUT
XI
XO
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33 DVDD1
34 A0
35 A1
36 A2
37 A3
38 A4
39 A5
40 A6
41 A7
42 PDNB
43 CLKSEL
44 DGND1
45 GPIOA[0]/DPI
46 GPIOA[1]
47 GPIOA[2]/DPO
48 GPIOA[3]
PIN CONFIGURATION (TOP VIEW)
AVDD 49
32 D15
AIN0P 50
31 D14
AIN0N 51
30 D13
GSX0
52
29 D12
GSX1 53
28 D11
AIN1N 54
27 D10
AVREF 55
26 D9
VFRO0
56
25 D8
VFRO1
57
24 D7
AGND
58
23 D6
DGND2 59
22 D5
XI
60
21 D4
DGND0 16
ACK1B/GPIOA[5]
WRB 15
9
RDB 14
8
ACK0B/GPIOA[4]
CSB 13
7
DVDD0
INTB/GPIOA[6] 12
6
SYNC
FR1B 11
5
BCLK
FR0B 10
4
PCMI
17 D0
3
VBG 64
PCMO
18 D1
2
VREGOUT 63
TST0
19 D2
1
20 D3
TST1
XO 61
DVDD2 62
64-Pin Plastic QFP
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PIN DESCRIPTIONS
Pin
Symbol
I/O
1
2
3
4
TST1
TST0
PCMO
PCMI
I
I
O
I
5
BCLK
I/O
QFP64
When
PDNB
= “0”
“0”
“0”
“Hi-z”
I
I
“L”
I
6
SYNC
I/O
“L”
7
DVDD0
—
—
8
ACK0B/GPIOA[4]
I/O
I
9
ACK1B/GPIOA[5]
I/O
I
10
FR0B
(DMARQ0B)
O
”H”
11
FR1B
(DMARQ1B)
O
“H”
12
INTB/GPIOA[6]
I/O
“H”
13
14
15
16
17
18
19
20
21
22
23
24
CSB
RDB
WRB
DGND0
D0
D1
D2
D3
D4
D5
D6
D7
I
I
I
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
—
I
I
I
I
I
I
I
I
Description
Test control input 1: Normally, input “0”.
Test control input 0: Normally, input “0”.
PCM data output [Open drain output pin]
PCM data input
CLKSEL = ”0”
PCM shift clock input
CLKSEL = ”1”
PCM shift clock output
CLKSEL = ”0”
PCM synchronous signal 8 kHz input
CLKSEL = ”1”
PCM synchronous signal 8 kHz output
Digital power supply
Transmit buffer DMA access acknowledge signal input
(primary function)
General-purpose I/O port A[4] (secondary function) [5
V tolerant pin]
Receive buffer DMA access acknowledge signal input
(primary function)
General-purpose I/O port A [5] (secondary function) [5 V
tolerant pin]
FR0B:(FD_SEL = ”0”)
Transmit buffer frame signal output
DMARQ0B: (FD_SEL = ”1”)
Transmit buffer DMA access request signal output
FR1B: (FD_SEL = ”0”)
Receive buffer frame signal output
DMARQ1B: (FD_SEL = ”1”)
Receive buffer DMA access request signal output
Interrupt request output (primary function)
General-purpose I/O port A [6] (secondary function) [5 V
tolerant pin]
Chip select control input
Read control input
Write control input
Digital ground (0.0 V)
Data input-output
Data input-output
Data input-output
Data input-output
Data input-output
Data input-output
Data input-output
Data input-output
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Symbol
I/O
When
PDNB
= “0”
25
D8
I/O
I
26
D9
I/O
I
27
D10
I/O
I
28
D11
I/O
I
29
D12
I/O
I
30
D13
I/O
I
31
D14
I/O
I
32
D15
I/O
I
33
34
35
36
37
38
39
40
41
DVDD1
A0
A1
A2
A3
A4
A5
A6
A7
—
I
I
I
I
I
I
I
I
—
I
I
I
I
I
I
I
I
42
PDNB
I
“0”
43
CLKSEL
I
I
44
DGND1
—
—
45
GPIOA[0]/DPI
I/O
I
46
GPIOA[1]
I/O
I
47
GPIOA[2]/DPO
I/O
I
48
49
50
51
GPIOA[3]
AVDD
AIN0P
AIN0N
I/O
—
I
I
I
—
I
I
Pin
QFP64
Description
Data input-output. Fix the input to “L” or “H” when using
the pin in 8-bit bus access (BW_SEL = ”1”).
Data input-output. Fix the input “L” or “H” when using the
pin in 8-bit bus access (BW_SEL = ”1”).
Data input-output. Fix the input “L” or “H” when using the
pin in 8-bit bus access (BW_SEL = ”1”).
Data input-output. Fix the input “L” or “H” when using the
pin in 8-bit bus access (BW_SEL = ”1”).
Data input-output. Fix the input “L” or “H” when using the
pin in 8-bit bus access (BW_SEL = ”1”).
Data input-output. Fix the input “L” or “H” when using the
pin in 8-bit bus access (BW_SEL = ”1”).
Data input-output. Fix the input “L” or “H” when using the
pin in 8-bit bus access (BW_SEL = ”1”).
Data input-output. Fix the input “L” or “H” when using the
pin in 8-bit bus access (BW_SEL = ”1”).
Digital power supply
Address input
Address input
Address input
Address input
Address input
Address input
Address input
Address input
Power-down input
“0”: Power-down reset
”1”: Normal operation
SYNC/BCLK input-output control input
“0”: SYNC/BCLK are configured to be input
“1”: SYNC/BCLK are configured to be output
Digital ground (0.0 V)
General-purpose I/O port A[0] [5 V tolerant pin]
Secondary function: Input pin for dial pulse detection
General-purpose I/O port A[1] [5 V tolerant pin]
General-purpose I/O port A[2] [5 V tolerant pin]
Secondary function: Output pin for dial pulse transmission
General-purpose I/O port A[3] [5 V tolerant pin]
Analog power supply
AMP0 non-inverting input
AMP0 inverted input
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Pin
QFP64
52
53
54
55
56
57
58
59
60
61
62
63
64
Symbol
I/O
GSX0
GSX1
AIN1N
AVREF
VFRO0
VFRO1
AGND
DGND2
XI
XO
DVDD2
VREGOUT
VBG
O
O
I
O
O
O
—
—
I
O
—
—
—
When
PDNB
= “0”
“Hi-z”
“Hi-z”
I
“L”
“Hi-z”
“Hi-z”
—
—
I
“H”
—
—
—
Description
AMP0 output (10 k driving)
AMP1 output (10 k driving)
AMP1 inverted input
Analog signal ground (1.4 V)
AMP2 output (10 k driving)
AMP3 output (10 k driving)
Analog ground (0.0 V)
Digital ground (0.0 V)
12.288 MHz crystal interface, 12.288 MHz clock input
12.288 MHz crystal interface
Digital power supply
Internal regulator voltage output pin (approx. 2.5 V)
Internal regulator reference voltage output pin
* Explanation of symbols used in the PDNB = “0” column
The symbols denote the following pin conditions when PDNB = “0”:
“I”
: Input a High or Low level signal to the pin.
“0”
: Input a Low level signal to the pin
“H”
: A High level signal is output from the pin.
“L”
: A Low level signal is output from the pin.
“Hi-Z” : The pin goes into a Hi-Z state.
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ABSOLUTE MAXIMUM RATINGS
Parameter
Analog power supply
voltage
Digital power supply
voltage
Analog input voltage
Symbol
Condition
Rating
Unit
AVDD
—
–0.3 to +4.6
V
DVDD
—
–0.3 to +4.6
V
VAIN
VDIN1
Analog pin
Normal digital pin
DVDD = 3.0 to 3.6 V
5 V tolerant pin
DVDD < 3.0 V
—
Ta = 60 C, per package
—
–0.3 to AVDD+0.3
–0.3 to DVDD+0.3
–0.3 to +6.0
–0.3 to DVDD+0.3
–20 to +20
350
–65 to +150
V
V
V
V
mA
mW
C
Digital input voltage
VDIN2
Output current
Power dissipation
Storage temperature
IO
PD
Tstg
RECOMMENDED OPERATING CONDITIONS
Parameter
Analog power supply voltage
Digital power supply voltage
Operating temperature range
Digital high-level input voltage
Digital low-level input voltage
Digital input rise time
Digital input fall time
Digital output load capacitance
Digital output load resistance
AVREF bypass capacitor
VREGOUT bypass capacitor
VBG bypass capacitor
Master clock frequency
PCM shift clock frequency
PCM synchronous signal
frequency
Clock duty ratio
PCM synchronous timing
PCM synchronous signal width
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
AVDD
—
3.0
3.3
3.6
V
DVDD
—
3.0
3.3
3.6
V
Ta
—
–20
—
+60
C
DVDD+
0.75 
V
—
VIH1
Normal digital pin
0.3
DVDD
0.75 
—
5.5
V
VIH2
5 V tolerant pin
DVDD
0.19 
V
VIL
Digital pin
–0.3
—
DVDD
tIR
Digital pin
—
2
20
ns
tIF
Digital pin
—
2
20
ns
CDL
Digital pin
—
—
50
pF
RDL
Pull-up resistance, PCMO
500
—
—

Cvref
Between AVREF-AGND
2.2+0.1
—
4.7+0.1
F
Cvout
Between VREGOUT-DGND
—
10+0.1
—
F
CVBG
Between VBG-DGND
—
150
—
pF
Fmck
MCK
–0.01% 12.288 +0.01%
MHz
2048
64
kHz
—
Fbclk
BCLK (at input)
(0.1%)
(0.1%)
Fsync
SYNC (at input)
–0.1%
8.0
+0.1%
kHz
DRCLK
tBS
tSB
tWS
MCK, BCLK (at input)
BCLK to SYNC (at input)
SYNC to BCLK (at input)
SYNC (at input)
40
100
100
1BCLK
50
—
—
—
60
—
—
100
%
ns
ns
s
(Note) On power-on/shut-down sequence
For the analog power supply voltage (AVDD) and the digital power supply voltage (DVDD) to be supplied to
this LSI, it is recommended that power be applied to them simultaneously. However, if simultaneous power-up
is difficult due to the power supply circuit configuration, power them up in the order of DVDD  AVDD.
The power supplies should be shut down in the reverse order of power-on sequence.
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ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
Power supply current
Digital input pin
Input leakage current
Digital I/O pin
Output leakage
current
High-level output
voltage
Low-level output
voltage
(AVDD = 3.0 to 3.6V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max. Unit
Standby state
—
200
500
A
ISS
(PDNB = ”0”, DVDD = AVDD=3.3 V, Ta = 25C)
Operating status 1
Speech CODEC activated/PCM I/F not used
—
45
55
mA
IDD1
SC_EN = ”1”, AFEA_EN = ”0”, AFEB_EN = ”1”,
XI, XO: 12.288 MHz crystal connected
Operating status 2
Speech CODEC activated/PCM I/F used
SC_EN = ”1”,PCMI1_EN = ”1”, PCMO1_EN
—
50
65
mA
IDD2
= ”1”,
AFEA_EN=”0”, AFEB_EN=”0”
XI, XO: 12.288 MHz crystal connected
IIH
Vin = DVDD
—
0.01
10
A
IIL
Vin = DGND
–10
–0.01
—
A
IOZH
Vout = DVDD
—
0.01
10
A
IOZL
VOH
VOL1
VOL2
Input capacitance (*1)
CIN1
CIN2
Vout = DGND
Digital output pins, I/O pin
IOH = 4.0 mA
IOH = 0.5 mA (XO pin)
IOH = 1 2.0 mA (CLKOUT pin)
Digital output pins, I/O pin
IOL = –4.0 mA
IOL = –0.5 mA (XO pin)
IO = –12.0 mA (CLKOUT pin)
Open drain output pins
IOL = –12.0 mA
Input pins
I/O pins
–10
—
—
A
0.78 
DVDD
—
—
V
—
—
0.4
V
—
—
0.4
V
—
—
6
10
—
—
pF
pF
*1 Design guaranteed value
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Analog Interface
Parameter
Input resistance (*1)
Output load resistance
Output load capacitance
Offset voltage
Output voltage level (*2)
(AVDD = 3.0 to 3.6 V, DVDD0, 1 ,2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
RIN
AIN0N, AIN0P, AIN1N
10
—
—
M
RL
GSX0, GSX1, VFRO0, VFRO1
10
—
—
k
CL
Analog output pins
—
—
50
pF
VOF
VFRO0, VFRO1
–40
—
+40
mV
GSX0, GSX1, VFRO0, VFRO1
1.158
1.3
1.458
Vpp
VO
RL = 10k, AMP input 1.3 Vpp
*1 Design guaranteed value
*2 –7.7 dBm (600) = 0 dBm0, +3.17 dBm0 = 1.3 Vpp
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AC Characteristics in Speech CODEC = G.711 (-law) Mode
Parameter
Transmit frequency
characteristics
Receive frequency
characteristics
Transmit
signal-to-noise ratio
(*1)
Receive
signal-to-noise ratio
(*1)
Transmit inter-level
loss errors
Receive inter-level
loss errors
Idle channel noise
(*1)
Transmit absolute
level (*2)
Receive absolute level
(*2)
Symbol
LT1
LT2
LT3
LT4
LT5
LT6
LR2
LR3
LR4
LR5
LR6
SDT1
SDT2
SDT3
SDT4
SDT5
SDR1
SDR2
SDR3
SDR4
SDR5
GTT1
GTT2
GTT3
GTT4
GTT5
GTR1
GTR2
GTR3
GTR4
GTR5
NIDLT
NIDLR
(AVDD = 3.0 to 3.6V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60C unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
Frequency (Hz)
Level (dBm0)
0 to 60
25
—
—
dB
300 to 3000
–0.15
—
0.20
dB
1020
Reference
—
0
3300
–0.15
—
0.80
dB
3400
0
—
0.80
dB
3968.75
13
—
—
dB
0 to 3000
–0.15
—
0.20
dB
1020
Reference
—
0
3300
–0.15
—
0.80
dB
3400
0
—
0.80
dB
3968.75
13
—
—
dB
3
35
—
—
dBp
0
35
—
—
dBp
1020
–30
35
—
—
dBp
–40
28
—
—
dBp
–45
23
—
—
dBp
3
35
—
—
dBp
0
35
—
—
dBp
1020
–30
35
—
—
dBp
–40
28
—
—
dBp
–45
23
—
—
dBp
3
–0.2
—
0.2
dB
–10
Reference
—
1020
–40
–0.2
—
0.2
dB
–50
–0.6
—
0.6
dB
–55
–1.2
—
1.2
dB
3
–0.2
—
0.2
dB
–10
Reference
—
1020
–40
–0.2
—
0.2
dB
–50
–0.6
—
0.6
dB
–55
–1.2
—
1.2
dB
Analog input =
—
—
–70
dBm0p
—
AVREF
—
PCMI = ”1”
—
—
–70
dBm0p
AVT
1020
0
0.285
0.320
0.359
Vrms
AVR
1020
0
0.285
0.320
0.359
Vrms
*1 P-message weighted filter used
*2 0.320 Vrms = 0 dBm0 = –7.7 dBm (600)
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AC Characteristics (Gain Setting) in Speech CODEC = G.711 (-law) mode
Parameter
Transmit/receive gain
setting accuracy
Symbol
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60C unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
GAC
For all gain set values
–1.0
—
1.0
dB
AC Characteristics (Tone Output) in Speech CODEC = G.711 (-law) Mode
Parameter
Frequency deviation
Output level
Symbol
fDFT
oLEV
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60C unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
For all frequency set values
–1.5
—
1.5
%
For all gain set values
–2.0
—
2.0
dB
AC characteristics (DTMF Detector and Other Detectors) in Speech CODEC = G.711 (-law) Mode
Parameter
Detection level accuracy
Symbol
dLAC
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60C unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
For all detection level set values
–2.5
—
2.5
dB
AC characteristics (Echo Canceler)
Parameter
Echo attenuation
Erasable echo delay time
Symbol
eRES
tECT
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60C unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
—
—
35
—
dB
—
—
—
32
ms
Measuring method
Echo Canceler
ATT
Sin
Sout
Rout
Rin
Level Meter
E.R.L
(echo return loss)
Delay
Echo delay time
LPF
5kHz
White noise generator
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Timings of PDNB, XO, and AVREF
Parameter
Power-down signal pulse
width
AVDD supply delay time
Oscillation activation time
AVREF rise time
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
tPDNB
PDNB pin
250
—
—
s
tAVDDON
txtal
—
—
AVREF = 1.4 (90%)
C5 = 4.7 F, C6 = 0.1 F
(See Figure 9)
AVREF = 1.4 (90%)
C5 = 2.2 F, C6 = 0.1 F
(See Figure 9)
0
—
—
—
—
20
ns
ms
—
—
600
ms
—
—
300
ms
tAVREF
DVDD
AVDD
DVDD AVDD
90%
DVDD
AVDD
0V
tAVDDON
VREGOUT
Approx.
2.5V
0V
90%
DVDD
PDNB
0V
tPDNB
AVDD
XO
0V
txtal
Approx.
1.4 V
AVREF
0V
tAVREF
Figure 1 Timings of PDNB, XO, and AVREF
(Note)
The capacitance of the AVREF capacitor (C5) affects the AVREF rise time and analog characteristics. If
weight is given to the analog characteristics, specify 4.7 F, and if it is given to the AVREF rise time, specify
2.2 F. The electrical characteristics for the analog characteristics that are described above are guaranteed in
both capacitances.
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PCM interface
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
fBCLK
CDL = 20 pF (during output)
–0.1%
2.048 +0.1%
MHz
dBCLK
CDL = 20 pF (during output)
45
50
55
%
fSYNC
CDL = 20 pF (during output)
–0.1%
8
+0.1%
kHz
dSYNC
CDL = 20 pF (during output)
45
50
55
%
1
BCLK = 2.048 MHz At output
tBS
BCLK to SYNC (during output)
100
—
—
ns
tSB
SYNC to BCLK (during output)
100
—
—
ns
tDS
50
—
—
ns
PCMI pin
tDH
50
—
—
ns
tSDX
—
—
100
ns
PCMO pin
tXD1
—
—
100
ns
Pull-up resistance RDL = 500
tXD2
—
—
100
ns
CDL = 50 pF
—
—
100
ns
tXD3
Parameter
Bit clock frequency
Bit clock duty ratio
Synchronous signal frequency
Synchronous signal duty ratio
Transmit/receive synchronous
timing
Input setup time
Input hold time
Digital output delay time
Digital output hold time
BCLK
0
1
tBS
2
3
4
5
6
7
8
-
16
tSB
tWS
SYNC
tDS
tDH
MSB
PCMI
LSB
LSB
G.711
16-bit linear
Figure 2 PCM Interface Input Timing (Long Frame)
BCLK
0
1
tBS
2
3
4
5
6
7
8
9
-
17
tSB
tWS
SYNC
tDS
PCMI
tDH
MSB
LSB
G.711
LSB
16-bit linear
Figure 3 PCM Interface Input Timing (Short Frame)
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BCLK
0
1
tBS
2
3
4
5
6
7
8
9
-
17
tSB
tWS
SYNC
tXD1
tXD2
tXD3
MSB
PCMO
tXD3
LSB
LSB
G.711
tSDX
16-bit linear
Figure 4 PCM Interface Output Timing (Long Frame)
BCLK
0
1
tBS
2
3
tXD1
tXD2
4
5
6
7
8
9
10
-
18
tSB
tWS
SYNC
PCMO
MSB
tXD3
tXD3
LSB
LSB
G.711
16-bit linear
Figure 5 PCM Interface Output Timing (Short Frame)
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Control Register Interface
Parameter
Address setup time (at Read)
Address hold time (at Read))
Address setup time (at Write)
Address hold time (at Write)
Write data setup time
Write data hold time
CSB setup time (at Read)
CSB hold time (at Read)
CSB setup time (at Write)
CSB hold time (at Write)
WRB pulse width
Read data output delay time
Read data output hold time
RDB pulse width
CSB disable time
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta= –20 to 60C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
tRAS
10
—
—
ns
tRAH
0
—
—
ns
tWAS
10
—
—
ns
tWAH
10
—
—
ns
tWDS
20
—
—
ns
tWDH
10
—
—
ns
tRCS
10
—
—
ns
CL = 50 pF
tRCH
0
—
—
ns
tWCS
10
—
—
ns
tWCH
10
—
—
ns
tWW
10
—
—
ns
tRDD
—
—
20
ns
tRDH
3
—
—
ns
tRW
25
—
—
ns
tCD
10
—
—
ns
A7-A0
Input
D7-D0
Inputoutput
A2
A1
tWAS
tWAH
tRAS
tRAH
D2
Output
D1
Input
tWDS tWDH
tRDD
tRDH
CSB
Input
tWCS
tWCH
tCD
tRCS
tRCH
WRB
Input
tWW
tRW
RDB
Input
Write timing
Read timing
Figure 6 Control Register Interface
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Transmit/Receive Buffer Interface (Frame Mode)
Parameter
FR1B setup time
FR1B output delay time
Address setup time (at Read)
Address hold time (at Read))
Address setup time (at Write)
Address hold time (at Write)
Write data setup time
Write data hold time
CSB setup time (at Read)
CSB hold time (at Read)
CSB setup time (at Write)
CSB hold time (at Write)
WRB pulse width
FR0B setup time
FR0B output delay time
Read data output delay time
Read data output hold time
RDB pulse width
CSB disable time
Symbol
tF1S
tF1D
tRAS
tRAH
tWAS
tWAH
tWDS
tWDH
tRCS
tRCH
tWCS
tWCH
tWW
tF0S
tF0D
tRDD
tRDH
tRW
tCD
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60C unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
3
—
—
ns
—
—
20
ns
10
—
—
ns
0
—
—
ns
10
—
—
ns
10
—
—
ns
20
—
—
ns
10
—
—
ns
10
—
—
ns
CL = 50 pF
0
—
—
ns
10
—
—
ns
10
—
—
ns
10
—
—
ns
3
—
—
ns
—
—
20
ns
—
—
30
ns
3
—
—
ns
35
—
—
ns
10
—
—
ns
FR0B
Output
tF0S
tF0D
FR1B
Output
tF1S
tF1D
A7-A0
Input
D15-D0
Inputoutput
A2
A1
tWAS
tWAH
tRAS
tRAH
D1
Input
D2
Output
tWDS tWDH
tRDD
tRDH
CSB
Input
WRB
Input
tWCS
tWCH
tWW
tCD
tRCS
tRCH
tRW
RDB
Input
Write timing
Read timing
Figure 7 Transmit/Receive Buffer Interface (Frame Mode)
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Transmit/Receive Buffer Interface (DMA Mode)
Parameter
DMARQ1B setup time
DMARQ1B output delay time
Address setup time (at Read)
Address hold time (at Read))
Address setup time (at Write)
Address hold time (at Write)
Write data setup time
Write data hold time
ACK0B setup time
ACK0B hold time
ACK1B setup time
ACK1B hold time
WRB pulse width
DMARQ0B setup time
DMARQ0B output delay time
Read data output delay time
Read data output hold time
RDB pulse width
ACKB disable time
(AVDD = 3.0 to 3.6V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60C unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
tDR1S
3
—
—
ns
tDR1RD
—
—
30
ns
tDR1FD
—
—
30
ns
tRAS
10
—
—
ns
tRAH
0
—
—
ns
tWAS
10
—
—
ns
tWAH
10
—
—
ns
tWDS
20
—
—
ns
tWDH
10
—
—
ns
tAK0S
10
—
—
ns
CL = 50 pF
tAK0H
0
—
—
ns
tAK1S
10
—
—
ns
tAK1H
10
—
—
ns
tWW
10
—
—
ns
tDR0S
3
—
—
ns
tDR0RD
—
—
30
ns
tDR0FD
—
—
30
ns
tRDD
—
—
30
ns
tRDH
3
—
—
ns
tRW
35
—
—
ns
tAD
10
—
—
ns
DMARQ0B
Output
tDR0S
tDR0RD
tDR0FD
DMARQ1B
Output
tDR1S
tDR1FD
tDR1RD
A7-A0
Input
D15-D0
Inputoutput
A2
A1
tWAS
tWAH
tRAS
tRAH
D2
Output
D1
Input
tWDS tWDH
tRDD
tRDH
ACK0B
Input
tAK0S
tAK0H
ACK1B
Input
WRB
Input
tAK1S
tAK1H
tWW
tAD
tRW
RDB
Input
Write timing
Read timing
Figure 8 Transmit/Receive Buffer Interface (DMA Mode)
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PIN FUNCTIONAL DESCRIPTION
AIN0N, AIN0P, GSX0, AIN1N, and GSX1
These are transmit analog input and transmit gain adjustment pins. AIN0N and AIN1N are connected to
inverted input pins of internal transmission amplifiers AMP0 and AMP1, and AIN0P is connected to a
noninverting input pin of AMP0. GSX0 and GSX1 are connected to output pins of AMP0 and AMP1. See
Figure 9 for the gain adjustment.
At power down (PDNB = “0” or SPDN = “1”), outputs of GSX0 and GSX1 are in a high impedance state.
When the application does not use AMP0, short-circuit GSX0 and AIN0N and connect AIN0P with AVREF.
When not using AMP1, short-circuit GSX1 and AIN1N.
VFRO0 and VFRO1
These are receive analog output pins. VFRO0 and VFRO1 are connected to output pins of amplifiers AMP2
and AMP3. Output signals, VFRO0 and VFRO1, can be selected using the VFRO0 selection register
(VFRO0_SEL) and VFRO1 selection register (VFRO1_SEL): When output is selected (“1”), the receive signal
is output and when output is not selected (“0”), AVREF (about 1.4 V) is output. In power down mode, these
output pins are set to a high impedance state. It is recommended to use output signals through a DC coupling
capacitor.
(Note)
If output selection is changed while the conversation is in progress, a micronoise is generated. Therefore, it is
recommended to select output before starting a call and then start a call.
Before canceling reset or resetting, it is recommended to select output of VFRO0 and VFRO1 to the AVREF
output side.
GSX1
Gain = R4/R3 <=32(+30dB)
R3 : Variable
R4 : 500k Max.
R4
C2
R3
10k
AIN1N
A/D1
AMP1
C4
Out : 1.3Vp-p Max.
VFRO1
VFRO1_SEL
10k
D/A1
AMP3
GSX0
R2
Gain = R2/R1 <=
32(+30dB)
R1 : Variable
R2 : 500k Max.
C1
R1
10k
AIN0N
A/D0
AIN0P
Out : 1.3Vp-p Max.
C3 VFRO0
AMP0
VFRO0_SEL
10k
D/A0
AMP2
AVREF
C5 +
2.2 to 4.7F
VREF
C6 0.1F
Figure 9 Analog Interface
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AVREF
This is an output pin of an analog signal ground potential. With the output potential of about 1.4 V, insert bypass
capacitors of 2.2 to 4.7 F (aluminum electrolysis type) and 0.1 F (ceramic type) in parallel. AVREF outputs
0.0 V at power down. AVREF starts being powered up after power-down reset, the system restarts from
( PDNB = “1” and SPDN = “0”).
XI and XO
These are the master clock input pin and the crystal connection pins for the master clock.
Oscillation stops at power down by PDNB or software power down by SPDN. Oscillation starts after
power-down is reset and the clock is supplied to the LSI internal section after oscillation stabilization delay time
has elapsed (about 21.3 ms). Figure 10 shows a master clock input and a crystal connection example.
XI
XO
R
Crystal
C1
XO
Open
XI
12.288 MHz
C2
Crystal1 (12.288 MHz)
HC-49/U-S [C L=12pF]
C1
C2
R
8 pF
8 pF
1 M
Figure 10 Example of an Oscillation Circuit and Clock Input
(Note)
For an oscillation circuit, connect a 12,288 MHz crystal and a 1 M feedback resistor (R) between XI and XO.
Since the values of capacitors C1 and C2 that are connected between XI and GND and between XO and GND
are affected by the production load capacitance of a crystal and the wiring capacitance of the board, contact the
manufacturer of the crystal to ask for matching evaluation to detemine the capacitor values.
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PDNB
This is a power-down control input pin. A power-down state can be set by setting this pin to “0”. This pin
also functions as an LSI reset pin. To prevent an LSI operation error, use PDNB for the initial power-down
reset after power is applied. To put the LSI into a power-down state, fix PDNB to “0” for 250 s or more.
LSI power-down reset can be performed by setting the software power down reset control register SPDN to “0”
 “1”  “0”.
After 200ms from power-down release, the initial mode display register (READY) is set to “1” and various
function setting modes (initial modes) are entered.
See Figure 1 for the timings of PDNB, AVREF, XO, and the initial mode.
(Note)
Turn on the power in a power-down state by PDNB.
When using the LSI by inputting a master clock to the XI pin, first maintain the power-down state (PDNB = 0)
until power is applied to the digital power supply (DVDD0, 1, and 2) and the analog power supply (AVDD)
(90% or more) and the master clock is input to the XI pin, then release the power-down state (PDNB = 0  1) .
In this case also, fix PDNB to “0” for 250 s or more.
DVDD0, DVDD1, DVDD2, and AVDD
These are power supply pins. DVDD0, DVDD1, and DVDD2 are connected to the power supply of a digital
circuit and AVDD is connected to a power supply of an analog circuit. Connect these pins near the LSI and
insert bypass capacitors of 10 F (electrolysis type) and 0.1 F (ceramic type) between DGND and AGND in
parallel.
DGND0, DGND1, DGND2, and AGND
These are ground pins. DGND0, DGND1, and DGND2 are connected to grounds of digital circuits and AGND
is connected to a ground of an analog circuit. Connect these pins near the LSI.
VREGOUT
This is an output pin of an internal regulator voltage (about 2.5 V).
Connect a capacitor of about 0.1 F (ceramic type) in parallel to about 10 F (ceramic or tantalum type) between
this pin and a ground pin.
VBG
This is a reference output pin for an internal regulator.
Connect a laminated ceramic capacitor of about 150 pF between this pin and a ground pin.
TST0 and TST1
These are input pins for testing. At normal use, input “0”.
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INTB/GPIOA[6]
Primary function: INTB
This in an interrupt request output pin.
When the interrupt cause is changed, this pin outputs a “L” level for about 1.0 s. When the interrupt factor is
not changed, “H” is output. The interrupt factor can be checked by reading CR16-CR22. Table 1 lists the
interrupt causes.
The interrupt causes can be masked individually in the internal memory (interrupt cause mask control).
Table 1 Interrupt Causes
CR
BIT
B2
CR16
B1
B0
CR17
B0
CR18
B0
B7
B4
CR19
B3
B2
B1
B6
CR20
B4
B3-B0
B3
B2
CR21
B1
B0
B3
B2
CR22
B1
B0
Register name
FSK receive overrun error notification register
(FDET_OER)
FSK receive framing error notification register
(FDET_FER)
FSK receive data read request notification register
(FDET_RQ)
FSK output data setting completion flag
(FGEN_FLAG)
Timer overflow display register (TMOVF)
DSP status register (DSP_ERR)
TONE1 detector detection status register
(TONE1_DET)
TONE0 detector detection status register
(TONE0_DET)
TGEN1 execution flag display register
(TGEN1_EXFLAG)
TGEN0 execution flag display register
(TGEN0_EXFLAG)
Dial pulse detector detection status register
(DP_DET)
DTMF detector detection status register
(DTMF_DET)
DTMF code display register (DTMF_CODE[3:0])
CH2 transmit error status register (TXERR_CH2)
CH1 transmit error status register (TXERR_CH1)
CH2 transmit request notification register
(FR0_CH2)
CH1 transmit request notification register
(FR0_CH1)
CH2 receive error status register (RXERR_CH2)
CH1 receive error status register (RXERR_CH1)
Receive invalid write error notification register
(RXBW_ERR)
Receive request notification register (FR1)
: With INTB interrupt generation function
Rising
edge
Falling
edge










































Remarks
: Without INTB interrupt generation function
Secondary function: GPIOA[6]
When the primary function/secondary function selection register (GPFA[6]) of GPIOA[6] is set to “1”, this pin
functions as a general-purpose I/O port GPIOA[6].
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A0-A7
These are address input pins for accessing a frame/DMA/control register. Each address is as follows.
Transmit buffer (TX Buffer)
A7-A0 = 80h
Receive buffer (RX Buffer)
A7-A0 = 81h
Control register (CR)
See Tables 5 to 9 for the addresses.
D0-D15
These are data I/O pins for accessing a frame/DMA/control register. Since these pins are I/O pins, connect
pull-up resistors. When an 8-bit bus access is selected in the MCU interface data width selection register
(BW_SEL), pins D0-D7 are enabled. When using the pins with 8-bit bus access (BW_SEL = “1”), fix the input
of high-order D8-D15 to either “0” or “1” since they are constantly in an input state.
CSB
This is a chip select input pin for accessing a frame/control register.
RDB
This is a read enable input pin for accessing a frame/DMA/control register.
WRB
This is a write enable input pin for accessing a frame/DMA/control register.
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FR0B (DMARQ0B)
 FR0B (FRAME/DMA selection register FD_SEL = “0” in frame mode)
This is a transmit frame output pin that outputs data when the transmit buffer for frame access becomes full.
When the transmit buffer becomes full, the pin outputs “L” and retains “L” until the specified number of words
are read from the MCU.
 DMARQ0B (FRAME/DMA selection register FD_SEL = “1” in DMA mode)
This is a DMA request output pin that outputs data when the transmit buffer for DMA access becomes full.
When the transmit buffer becomes full, the pin outputs “L” and the value is reset to “H” automatically when an
acknowledgment signal (ACK0B = “0”) and the fall of a read enable signal (RDB = “1”  “0”) are received
from the MCU side. This operation is repeated until the specified number of words are read from the MCU.
FR1B (DMARQ1B)
 FR1B (FRAME/DMA selection register FD_SEL = “0” in frame mode)
This receive frame output pin outputs data when the receive buffer for frame access becomes empty. When
the receive buffer becomes empty, the pin outputs “L” and retains “L” until the specified number of words are
written from the MCU.
 DMARQ1B (FRAME/DMA selection register FD_SEL = “1” in DMA mode)
This a DMA request output pin that outputs data when the receive buffer for DMA access becomes empty.
When the receive buffer becomes empty, the pin outputs “L” and the value is reset to “H” automatically when
an acknowledgment signal (ACK1B = “0”) and the fall of a write enable signal (WRB = “1”  “0”) are
received from the MCU side. This opeation is repeated until the specified number of words are written from
the MCU side.
ACK0B/GPIOA[4]
Primary function: ACK0B
This is a DMA acknowledgment input pin for DMARQ0B for transmit buffer DMA access; it is enabled in
DMA mode (FD_SEL = “1”).
When using the pin in frame mode (FD_SEL = “0”), fix this pin to “1”.
Secondary function: GPIOA[4]
When the primary function/secondary function selection register (GPFA[4]) of GPIOA[4] is set to “1”, the pin
functions as a general-purpose I/O port GPIOA[4].
ACK1B/GPIOA[5]
Primary function: ACK0B
This is a DMA acknowledgment input pin for DMARQ1B for receive buffer DMA access; it is enabled in DMA
mode (FD_SEL = “1”).
When using this pin in frame mode (FD_SEL = “0”), fix this pin to “1”.
Secondary function: GPIOA[5]
When the primary function/secondary function selection register (GPFA[5]) of GPIOA[5] is set to “1”, the pin
functions as a general-purpose I/O port GPIOA[5].
GPIOA[0], GPIOA[1], GPIOA[2], and GPIOA[3]
These are general-purpose I/O ports A[3:0].
However, the following secondary functions are assigned to GPIOA[0] and GPIOA[2].
Secondary function of GPIOA[0]: Input pin (DPI) of a dial pulse detecter (DPDET)
Secondary function of GPIOA[2]: Output pin (DPO) of a dial pulse transmitter (DPGEN)
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CLKSEL
This is an input-output control input pin of SYNC and BCLK. The pin controls input when it is set to “0” and
output when it is set to “1”.
(Note)
This LSI operates at either SYNC/BCLK that is generated inside the LSI or the clock generated based on
SYNC/BCLK to be input from the outside the LSI. For this reason, if the CLKSEL pin is set to “0”, it is
necessary to constantly input SYNC/BCLK from the time the power supply is truned on regardless of whether
PCM-IF is used or not.
SYNC
This is a 8 kHz synchronous signal I/O pin of PCM signals. When CLKSEL is “0”, constantly input an 8 kHz
clock synchronized with BCLK. When CLKSEL is “1”, this pin outputs an 8 kHz clock synchronized with
BCLK. When the SYNC frame control register (SYNC_SEL) is “0”, long frame synchronization is specified
and when the register is “1”, short frame synchronization is specified.
BCLK
This is a shift clock I/O pin of a PCM signal.
When CLKSEL is “0”, clock input synchronized with SYNC is necessary. When G.711 is selected, input a
clock of 64 kHz to 2.048 MHz and when 16-bit linear is selected, input a clock of 128 kHz to 2.048 MHz.
When CLKSEL is “1”, this pin outputs a clock of 2.048 MHz synchronized with SYNC.
(Remarks) Table 2 shows the input-output control of SYNC and BCLK and the frequencies.
Table 2 SYNC and BCLK Input-Output Control
CLKSEL
SYNC
BCLK
“0”
Input
(8 kHz)
Input
(64 kHz to
2048 kHz)
“1”
Output
(8 kHz)
Output
(2.048 MHz)
Remarks
Always input a clock after start of power supply.
When G.711 is selected, input a clock of 64 kHz to 2.048
MHz.
When 16-bit linear is selected, input a clock of 128 kHz to
2.048 MHz.
At power down, “L” is output.
PCMO
This is a PCM signal output pin. A PCM signal is output synchronized with the rise of BCLK or SYNC.
For the output from PCMO, data is output to only the applicable time slot section according to the selected
coding format and the setting of the time slot position and other sections are set to a high-impedance state. If a
PCM interface is not used, PCMO is set to a high impedance state.
(Note)
Be sure to connect a pull-up resistor externally to the PCMO pin, because the pin is an open drain output pin.
Do not use a pull-up voltage greater than the digital power supply voltage (DVDD).
PCMI
This is a PCM signal input pin. The signal is shifted at falling of BCLK and is input from MSB.
If a PCM interface is not used, fix the input to “0” or “1”.
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FUNCTIONAL DESCRIPTION
Transmit and receive buffers
Table 3 lists the controllable parameters of the transmit and receive buffers.
This LSI allows the setting of the Speech CODEC coding format and the buffering time for transmit and receive
buffers individually.
[Example] Transmit side (Tx): G.729.A/10 ms, Receive side (Rx): G.711/20 ms
Table 3 Controllable Parameters of Transmit and Receive Buffers
Contents
Speech
CODEC
Coding
format
Buffering
time
Modifiable parameter
Initial value
Tx side
G.729.A
G.711 (-law, A-law)
G.729.A
Rx side
G.729.A
G.711 (-law, A-law)
G.729.A
Tx side
10 ms
20 ms
10 ms
Rx side
10 ms
20 ms
10 ms
Access mode
FIFO data width
Frame
DMA
16 bits
8 bits
Remarks
The buffering size of the transmit buffer is
changed automatically according to the Speech
CODEC coding format of the transmit side.
The buffering size of the receive buffer is
changed automatically according to the Speech
CODEC coding format of the receive side.
The number of words of the transmit buffer is
changed automatically according to the setting of
buffering time on the transmit side.
The number of words of the receive buffer is
changed automatically according to the setting of
buffering time on the receive side.
Frame
16 bits
The number of words is changed automatically
according to the data width.
Transmit and receive buffer size
Each of the transmit and receive buffers comprises double buffers in FIFO (First In First Out) format, and
buffering is performed for data of 10 ms or 20 ms for one buffer.
When the transmit buffer is full or the receive buffer is empty, a requesting frame signal (FR0B or FR1B) or a
DMA request signal (DMARQ0B or DMARQ1B) is issued to the MCU. The number of FIFO words is
changed automatically according to the selected Speech CODEC and FIFO data width. Table 4 shows the
buffer size and the number of words determined by each of Speech CODEC and data width.
Table 4 Buffer Sizes and the Numbers of Words of Transmit and Receive Buffers
Speech CODEC
G.729.A (8 kbps)
G.711 (64 kbps)
Buffer size
10 bytes
80 bytes
10 ms mode
16 bits
5 words
40 words
8 bits
10 words
80 words
Buffer size
20 bytes
160 bytes
20 ms mode
16 bits
10 words
80 words
8 bits
20 words
160 words
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Structure of transmit/receive buffers
Figure 11 shows the transmit/receive access timing. Both the transmit and receive buffers are in a
double-buffer structure; however, either of them can be accessed as one buffer when accessed from the MCU
side.
(1) Single-channel operation (SC_EN = 1, DC_EN = 0)
10 ms/20 ms
Transmit buffer
TX Buffer0
TX Buffer1
TX Buffer0
RX Buffer1
RX Buffer0
Read from MCU
Receive buffer
RX Buffer0
Write from MCU
(2) 2-channel operation (SC_EN=1, DC_EN=1)
10 ms/20 ms
Transmit buffer
TX
Buffer0
TX
Buffer1
TX
Buffer0
TX
Buffer1
TX
Buffer0
TX
Buffer1
Read from MCU
Receive buffer
RX
Buffer0
RX
Buffer1
RX
Buffer0
RX
Buffer1
RX
Buffer0
RX
Buffer1
Write from MCU
Figure 11 Transmit/Receive Buffer Access Timing
Data width selection (16-bit mode, 8-bit mode)
16-bit mode or 8-bit mode can be selected in the MCU interface data width selection register (BW_SEL) as the
transmit/receive buffer access data width.
In 16-bit mode, data is accessed through a 16-bit data width of D15-D0 and in 8-bit mode, transmit and receive
data is input-output in D7-D0. In 8-bit access mode, D15-D8 always go into an input state.
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Data storage format
Figures 12 and 13 show the storage formats at transmit/receive processing in each parameter.
A. G.729.A
G.729.A(8 kbps)
· 1 frame 80 bits/10 ms
· 2 frames 160 bits/20 ms
G.729.A code and word structure
Symbol name
bit No
Number
of words
1
2
B15
L0
B14
L1
6
B13
L1
5
B12
L1
4
B11
L1
3
B10
L1
2
B9
L1
1
B8
L1
0
B7
L2
4
B6
L2
3
B5
L2
2
B4
L2
1
B3
L2
0
B2
L3
4
B1
L3
3
B0
L3
2
L3
1
L3
0
P1
7
P1
6
P1
5
P1
4
P1
3
P1
2
P1
1
P1
0
P0
C1
12
C1
11
C1
10
C1
9
C1
8
3
C1
7
C1
6
C1
5
C1
4
C1
3
C1
2
C1
1
C1
0
S1
3
S1
2
S1
1
S1
0
GA1
2
GA1
1
GA1
0
GB1
3
4
GB1
2
GB1
1
GB1
0
P2
4
P2
3
P2
2
P2
1
P2
0
C2
12
C2
11
C2
10
C2
9
C2
8
C2
7
C2
6
C2
5
5
C2
4
C2
3
C2
2
C2
1
C2
0
S2
3
S2
2
S2
1
S2
0
GA2
2
GA2
1
GA2
0
GB2
3
GB2
2
GB2
1
GB2
0
Word structure
D15
Number
D15
of words
1
D0
bit47 ························bit32
4
bit63 ························bit48
5
bit79 ························bit64
2nd frame
bit31 ························bit16
3
1st frame
bit15 bit0
2
D0
bit15 ························bit0
2
bit31 ························bit16
3
bit47 ························bit32
4
bit63 ························bit48
5
bit79 ························bit64
6
bit15 ························bit0
7
bit31 ························bit16
8
bit47 ························bit32
9
bit63 ························bit48
10
bit79 ························bit64
(a) 10 ms/16-bit mode
(b) 20 ms/16-bit mode
bit7········bit0
Number
of words
1
2
bit15········bit8
2
bit15········bit8
·
·
·
·
·
·
·
·
9
bit71········bit64
9
bit71········bit64
10
bit79········bit72
10
bit79········bit72
D0
1st frame
D7
2nd frame
Number
of words
1
1st frame
1st frame
Number
of words
1
(c) 10 ms/8-bit mode
D7
D0
bit7········bit0
11
bit7········bit0
12
bit15········bit8
·
·
·
·
19
bit71········bit64
20
bit79········bit72
(d) 20 ms/8-bit mode
Figure 12 G.729.A Data Format
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B. G.711 (64 kbps)
G.711 (64 kbps, -law/A-law)
· 8 bits/125 s
Buffer structure
· 80 sample/10 ms
· 160 sample/20 ms
PCM code structure
bit7
bit6
bit5
bit4
bit3
Word structure
Number
of words D15
1
D0
0
1
2
2
3
·
·
bit7···bit0
39
76
77
40
78
79
bit2
bit1
bit0
Number
of words D15
1
D0
0
1
2
2
3
·
·
bit7···bit0
79
156
157
80
158
159
·
·
·
·
·
·
·
·
·
·
·
·
(a) 10 ms/16-bit mode
(b) 20 ms/16-bit mode
Number
of words D7
1
D0
0
Number
of words D7
1
0
2
1
2
1
·
·
bit7···bit0
·
·
.
.
bit7···bit0
79
78
80
79
2
·
·
(c) 10 ms/8-bit mode
159
158
160
159
(d) 20 ms/8-bit mode
Figure 13 G.711 Data Format
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Init
T1
RE_SC1
T2
RE_SC2
T3
RE_SC3
T4
RE_SC4
Error
T5
RE_SC5
Approx. 250s
T6
RE_SC6
T7
RE_SC7
T8
Set SC_EN “1” to “0” and DEC_OUTON “1” to “0”. After the termination, encoding becomes invalid.
The encoder stops the writing of data within a maximum of 250 s after SC_EN is set to “0”.
RE_SC8
T9
Terminatio
n
Termination 250 s max.
Activation interval 10.0 ms or more
The data that has been encoded in the encoding period Tn is read by the MCU during the valid read period RE-SCn. This operation is repeated until the processing stops. (n = 1, 2, 3, 4, ...)
DEC_OUTON “0” and SC_EN “0” -> “1”
Speech CODEC starts within a maximum of 250 s after SC_EN is set to “1”.
The encoder is initialized within the initial 10 ms and starts encoding from T1 period.
Termination
Operation
INIT
Activation interval
An interval of 10.0 ms or more is required from termination to the next activation of Speech CODEC.
Valid read section: Terminate read processing from the TX buffer within 9.0 ms after the fall of FR0B or change of FR0_CH1 from “0” to “1”.
Error processing
Transmit error
This example shows the processing when an error occurs during the valid read period RE_SC4. When data read processing does not terminate within the valid read section, TXERR_CH1 is set to “1” and an interrupt occurs. From the
next valid read period, TXERR_CH1 is retained until just before the frame that has been read normally from the transmit buffer terminates.
The data of the transmit buffer is updated normally even if data read processing does not terminate.
Termination
Operation
Activation
INTB
(Pin output)
TXERR_CH1
FR0_CH1
MCU read
Valid read
section
FR0B
(Pin output)
Speech ENC
CODEC
10 ms
SC_EN
Activation 250 s max.
FEDL7204-003-02
ML7204-003
Transmit buffer control methods at single-channel operation
Figures 14 to 17 show the transmit buffer control methods at single-channel operation.
A. G.729.A (10 ms /frame mode)
Figure 14 G.729.A Transmit Buffer Control Method at
Single-Channel Operation (10 ms/frame mode)
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RE_SC1
T3
Approx. 250 s
This operation is repeated until the processing stops.
RE_SC3
Error
T5
(n = 1, 3, 5, ...)
RE_SC5
T7
RE_SC7
T9
Activation interval
An interval of 10.0 ms or more is required from termination to the next activation of Speech CODEC.
Valid read section: Terminate read processing from the TX buffer within 18.0 ms after the fall of FR0B or change of FR0_CH1 from “0” to “1”.
INIT
From the next valid
Termination
250 s max.
Activation interval 10.0 ms or more
Termination
Set SC_EN “1” to “0” and DEC_OUTON “1” to “0”. After the termination, encoding becomes invalid.
The encoder stops the writing of data withina maximum of 250 s after SC_EN is set to “0”.
Error processing
Transmit error
This example shows the processing when an error occurs during the valid read period RE_SC3. When data read processing does not terminate within the valid read section, TXERR_CH1 is set to “1” and an interrupt occurs.
read period, TXERR_CH1 is retained until just before the frame that has been read normally from the transmit buffer terminates.
The data of the transmit buffer is updated normally even if data read processing does not terminate.
Termination
The data that has been encoded in the encoding period Tn is read by the MCU during the valid read period RE-SCn.
T1
Operation
Init
DEC_OUTON “0”, SC_EN “0” -> “1”
Speech CODEC starts within a maximum of 250 s after SC_EN is set to “1”.
The encoder is initialized within the initial 10 ms and starts encoding from T1 period.
Termination
Approx. 10 ms
Operation
Activation
INTB
(Pin output)
TXERR_CH1
FR0_CH1
Valid read
section
MCU read
FR0B
(Pin output)
Speech
ENC
CODEC
20 ms
SC_EN
Activation 250 s max.
FEDL7204-003-02
ML7204-003
B. G.729.A (20 ms/frame mode)
Figure 15 G.729.A Transmit Buffer Control Method at Single-Channel
Operation (20 ms/frame mode)
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ENC
10 ms
RE_SC4
T5
Error
T6
RE_SC6
Approx.250 s
T7
RE_SC7
T8
(n = 1, 2, 3, 4, ...)
RE_SC8
T9
RE_SC9
T10
Termination/Init
250 s max.
T1
Activation interval 10.0 ms or more
Termination
Activation interval
An interval of 10.0 ms or more is required from termination to the next activation of Speech CODEC.
Valid read section: Terminate read processing from the TX buffer within 9.0 ms after the fall of FR0B or change of FR0_CH1 from “0” to “1”.
Error processing
Transmit error
This example shows the processing when an error occurs during the valid read period RE_SC5. When data read processing does not terminate within the valid read section, TXERR_CH1 is set to “1” and an interrupt occurs. From the
next valid read period, TXERR_CH1 is retained until just before the frame that has been read normally from the transmit buffer terminates.
The data of the transmit buffer is updated normally even if data read processing does not terminate.
This operation is repeated until the processing stops.
RE_SC5
The data that has been encoded in the encoding period Tn is read by the MCU during the valid read period RE-SCn.
RE_SC3
T4
Set SC_EN “1” to “0” and DEC_OUTON “1” to “0”. After the termination, encoding becomes invalid.
The encoder stops the writing of data within a maximum of 250 s after SC_EN is set to “0”.
RE_SC2
T3
Termination
RE_SC1
T2
Operation
T1
DEC_OUTON “0” and SC_EN “0” -> “1”
Speech CODEC starts within a maximum of 250 s after SC_EN is set to “1”.
The encoder is activated in the initialized state and starts encoding immediately after activation of Speech CODEC.
Termination/Init
Operation
Activation
INTB
(Pin output)
TXERR_CH1
FR0_CH1
Valid read section
MCU read
FR0B
(Pin output)
Speech
CODEC
SC_EN
Activation 250 s max.
FEDL7204-003-02
ML7204-003
C. G.711 (-law and A-law) (10 ms/frame mode)
Figure 16 G.711 (-law and A-law) Transmit Buffer Control Method at
Single-Channel Operation (10 ms/frame mode)
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RE_SC5
(n = 1, 3, 5, ...)
RE_SC7
T9
Termination/Init
Termination 250 s max.
Activation interval 10.0 ms or more
T1
Activation interval
An interval of 10.0 ms or more is required from termination to the next activation of Speech CODEC.
Valid read section: Terminate read processing from the TX buffer within 18.0 ms after the fall of FR0B or change of FR0_CH1 from “0” to “1”.
Error processing
Transmit error
This example shows the processing when an error occurs during the valid read period RE_SC3. When data read processing does not terminate within the valid read section, TXERR_CH1 is set to “1” and an interrupt occurs. From the
next valid read period, TXERR_CH1 is retained until just before the frame that has been read normally from the transmit buffer terminates.
The data of the transmit buffer is updated normally even if data read processing does not terminate.
Termination Set SC_EN “1 ” to “0” and DEC_OUTON “1” to “0”. After the termination, encoding becomes invalid.
The encoder stops the writing of data within a maximum of 250 s after SC_EN is set to “0”.
Approx. 250 s
T7
This operation is repeated until the processing stops.
RE_SC3
Error
T5
The data that has been encoded in the encoding period Tn is read by MCU during the valid read period RE-SCn.
RE_SC1
T3
Operation
T1
DEC_OUTON “0” and SC_EN “0” -> “1”
Speech CODEC starts within a maximum of 250 s after SC_EN is set to “1”.
The encoder is activated in the initialized state and starts encoding immediately after activation of Speech CODEC.
Termination/Init
Operation
Activation
INTB
(Pin output)
TXERR_CH1
FR0_CH1
Valid read section
MCU read
FR0B
(Pin output)
Speech
CODEC ENC
20 ms
SC_EN
Activation 250 s max.
FEDL7204-003-02
ML7204-003
D. G.711 (-law and A-law) (20 ms/frame mode)
Figure 17 G.711 (-law and A-law) Transmit Buffer Control Method at SingleChannel Operation (20 ms/frame mode)
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tDECON
WE_SC3
R1
WE_SC4
Error
WE_SC5
Approx. 250 s
R2
R3
WE_SC6
WE_SC7
R4 (BFI)
R5
WE_SC8
R6
WE_SC9
R
8
WE_SC10
R7
(n = 1, 2, 3, 4, ...)
Silent output
250 s max.
Silent output
/Init
Activation interval
An interval of 10.0 ms or more is required from termination to the next activation of Speech CODEC.
Valid write section: No time limit is imposed for the initial valid write period WE_SC1 after activation of Speech CODEC.
From the valid write period WE_SC2 on, terminate write processing to the RX buffer within 9.0 ms after the fall of FR1B or change of FR1 from “0” to “1”.
Error processing
Receive error:
This example shows the processing when an error occurs during the valid write period WE_SC4. When data write processing does not terminate within the valid write section, RXERR_CH1 is set to “1” and an interrupt occurs.
From the next valid write period, RXERR_CH1 is retained until just before the frame that has been written normally to the RX buffer terminates.
If an error occurs during the valid write period WE_SC4, frame loss compensation processing (BFI: Bad Frame Indicator) specified in G.729.A is performed.
Termination Set SC_EN “1” to “0” and DEC_OUTON “1” to “0”. After the termination, decoding becomes invalid.
The decoder stops within a maximum of 250 s after SC_EN is set to “0”, and silent data is output.
The data that has been written by the MCU during the valid write period WE_SCn is output during the decoding output period Rn. This operation is repeated until the LSI stops running.
WE_SC2
Silent
Approx. 15 ms
Operation
t WAIT
WE_SC1
Silent output/Init
Termination
Activation interval 10.0 ms or more
DEC_OUTON “0” and SC_EN “0” -> “1”
Speech CODEC starts within a maximum of 250 s after SC_EN is set to “1”.
The decoder is initialized and outputs silent data after activation of Speech CODEC.
If the initial receive data has been written and the tWAIT time has elapsed, the decoding output control register (DEC_OUTON) can be set to “1”. (tWAIT = TBD)
Decoding output starts about 15 (+tDECON)ms after DEC_OUTON is set to “1”.
The decoding output start offset time (tDECON) can be adjusted within the range from 0.125 to 32ms by setting a value in the internal data memory for decoding output start offset time control (DEC_ONTIM).
(tDECON: Initial value = 0 ms, setting unit = 125 s)
Silent output
Operation
Activation
INTB
(Pin output)
RXERR_CH1
FR1
DEC_OUTON
MCU write
Valid write
section
FR1B
(Pin output)
10 ms
Speech DEC
CODEC OUT
10 ms
SC_EN
Activation 250 s max.
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Receive buffer control method at single-channel operation
Figures 18 to 21 show the receive buffer control methods at single-channel operation.
A. G.729.A (10 ms/frame mode)
Figure 18 G.729.A Receive Buffer Control Method at Single-Channel
Operation (10 ms/frame mode)
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20 ms
DEC
OUT
t WAIT
WE_SC1
Silent output/Init
WE_SC3
Silent
Approx. 15 ms
R1
WE_SC5
Error
WE_SC7
Approx. 250 s
R3
R5(BFI)
WE_SC9
WE_SC11
R7
(n = 1, 3, 5, ...)
Activation interval
An interval of 10.0 ms or more is required from termination to the next activation of Speech CODEC.
Valid write section: No time limit is imposed for the initial valid write period WE_SC1 after activation of Speech CODEC.
From the valid write period WE_SC3 on, terminate write processing to the RX buffer within 18.0 ms after the falling of FR1B or change of FR1 from “0” to “1”.
Silent output
/Init
From the next
(tDECON: Initial value = 0 ms,
Error processing
Receive error:
This example shows the processing when an error occurs during the valid write period WE_SC5. When data write processing does not terminate within the valid write section, RXERR_CH1 is set to “1” and an interrupt occurs.
valid write period, RXERR_CH1 is retained until just before the frame that has been written normally to the RX buffer terminates.
If an error occurs during the valid write period WE_SC5, frame loss compensation processing (BFI: Bad Frame Indicator) specified in G.729.A is performed.
The data that has been written by the MCU during the valid write period WE_SCn is output during the decoding output period Rn. This operation is repeated until the LSI stops running.
Set SC_EN “1” to “0” and DEC_OUTON “1” to “0”. After the termination, decoding becomes invalid.
The decoder stops within a maximum of 250 s after SC_EN is set to “0”, and silent data is output.
Operation
250 s max.
Silent output
Termination
Activation interval 10.0 ms or more
DEC_OUTON “0” and SC_EN “0” -> “1”
Speech CODEC starts within a maximum of 250 s after SC_EN is set to “1”.
The decoder is initialized and outputs silent data after activation of Speech CODEC.
If the initial receive data has been written and the tWAIT time has elapsed, the decoding output control register (DEC_OUTON) can be set to “1”. (tWAIT = 1ms)
Decoding output starts about 15 (+tDECON) ms after DEC_OUTON is set to “1”.
The decoding output start offset time (tDECON) can be adjusted within the range from 0.125 to 32msec by setting a value in the internal data memory for decoding output start offset time control (DEC_CONTIM).
setting unit = 125 s)
Silent output
tDECON
Operation
Termination
Activation
INTB
(Pin output)
RXERR_CH1
FR1
DEC_OUTON
MCU write
Valid write
section
FR1B
(Pin output)
Speech
CODEC
20 ms
SC_EN
Activation 250 s max.
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B. G.729.A (20m/frame mode)
Figure 19 G.729.A Receive Buffer Control Method at Single-Channel
Operation (20 ms/frame mode)
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WE_SC4
Error
R2
Approx. 250 s
WE_SC5
R3
WE_SC6
R4 (PLC)
WE_SC7
R5
WE_SC8
R6
WE_SC9
R7
WE_SC10
R8
(n = 1, 2, 3, 4, ...)
Silent output/Init
(tDECON: Initial value = 0 ms, setting
R9
An interval of 10.0 ms or more is required from termination to the next activation of Speech CODEC.
Valid write section: No time limit is imposed for the initial valid write period WE_SC1 after activation of Speech CODEC.
For the valid write period WE_SC2, finish writing into the RX buffer within 4.0 ms after the fall of FR1B or change of FR1 status from”0” to “1.
From the valid write period WE_SC3 on, finish writing into the RX buffer within 9.0 ms after the fall of FR1B or change of FR1 from “0” to “1”.
Activation interval
Error processing
Receive error:
This example shows the processing when an error occurs during the valid write period WE_SC4. When data write processing does not terminate within the valid write section, RXERR_CH1 is set to “1” and an interrupt occurs. From the next
valid write period, RXERR_CH1 is retained until just before the frame that has been written normally to the RX buffer terminates.
If an error occurs during the valid write period WE_SC4, data is generated according to the PLC (Packet Loss Concealment) algorithm specified in G.711 Appendix I and then output during the decoding output period R4. However, if the G.711
PLC function is disabled, silent data is output.
Termination Set SC_EN “1” to “0” and DEC_OUTON “1” to “0”. After the termination, decoding becomes invalid.
The decoder stops within a maximum of 250 s after SC_EN is set to “0”, and silent data is output.
The data that has been written by the MCU during the valid write period WE_SCn is output during the decoding output period Rn. This operation is repeated until the processing stops.
WE_SC3
R1
Operation
WE_SC2
Silent
250 s max.
Activation interval 10.0 ms or more
Termination
DEC_OUTON “0” and SC_EN “0” -> “1”
Speech CODEC starts within a maximum of 250 s after SC_EN is set to “1”.
The decoder is initialized and outputs silent data after activation of Speech CODEC.
If the initial receive data has been written and the tWAIT time has elapsed, the decoding output control register (DEC_OUTON) can be set to “1”. (tWAIT=1ms)
After DEC OUTON is set to “1”, the decoder starts decoding output after outputting silent data for approx. 3.75 (+DECON) ms.
However, if the PLC function is disabled, decoding output starts tDECON ms after DEC_OUT_ON is set to “1”.
The decoding output start offset time (tDECON) can be adjusted within the range from 0.125 to 32 ms by setting a value in the internal data memory for decoding output start offset time control (DEC_ONTIM).
unit = 125 s)
WAIT
WE_SC1
Silent output/Init
Approx. 3.75 ms
tDECON
Operation
Activation
INTB
(Pin output)
RXERR_CH1
FR1
DEC_OUTON
MCU write
Valid write
section
FR1B
(Pin output)
10 ms
Speech DEC
CODEC OUT
10 ms
SC_EN
Activation 250 s max.
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C. G.711 (-law, A-law) (10 ms/frame mode)
Figure 20 G.711 (-law and A-law) Receive Buffer Control Method at
Single-Channel Operation (10 ms/frame mode)
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WE_SC5
Error
R3
Approx. 250 s
WE_SC7
R5(PLC)
WE_SC9
R7
WE_SC11
(n = 1, 3, 5, ...)
Silent output/Init
(tDECON: Initial value = 0 ms, setting
R
9
Activation interval
An interval of 10.0 ms or more is required from termination to the next activation of Speech CODEC.
Valid write section: No time limit is imposed for the initial valid write period WE_SC1 after activation of Speech CODEC.
For the valid write period WE_SC3, finish writing into the RX buffer within 13.0 ms after the fall of FR1B or change of FR1 status from “0” to “1”.
From the valid write period WE_SC5 on, finish writing into the RX buffer within 18.0 ms after the fall of FR1B or change of FR1 from “0” to “1”.
Error processing
Receive error:
This example shows the processing when an error occurs during the valid write period WE_SC5. When data write processing does not terminate within the valid write section, RXERR_CH1 is set to “1” and an interrupt occurs. From the next valid
write period, RXERR_CH1 is retained until just before the frame that has been written normally to the RX buffer terminates.
If an error occurs during the valid write period WE_SC5, data is generated according to the PLC (Packet Loss Concealment) algorithm specified in G.711 Appendix I and then output during the decoding output period R5. However, if the G.711 PLC
function is disabled, silent data is output.
Termination Set SC_EN “1” to “0” and DEC_OUTON “1” to “0”. After the termination, decoding becomes invalid.
The decoder stops within a maximum of 250 s after SC_EN is set to “0”, and silent data is output.
The data that has been written by the MCU during the valid write period WE_SCn is output during the decoding output period Rn. This operation is repeated until the processing stops.
WE_SC3
R1
Operation
Silent
Approx.3.75 ms
250 s max.
Activation interval 10.0 ms or more
Termination
DEC_OUTON “0” and SC_EN “0” -> “1”
Speech CODEC starts within a maximum of 250 s after SC_EN is set to “1”.
The decoder is initialized and outputs silent data after activation of Speech CODEC.
If the initial receive data has been written and the tWAIT time has elapsed, the decoding output control register (DEC_OUTON) can be set to “1”. (tWAIT=1ms)
After DEC OUTON is set to “1”, the decoder starts decoding output after outputting silent data for approx. 3.75 (+DECON) ms.
However, if the PLC function is disabled, decoding output starts tDECON ms after DEC_OUT_ON is set to “1”.
The decoding output start offset time (tDECON) can be adjusted within the range from 0.125 to 32 ms by setting a value in the internal data memory for decoding output start offset time control (DEC_CONTIM).
unit = 125 s)
t WAI
WE_SC1
Silent output/Init
tDECON
Operation
Activation
INTB
(Pin output)
RXERR_CH1
FR1
DEC_OUTON
MCU write
Valid write
section
FR1B
(Pin output)
20 ms
Speech DEC
CODEC OUT
20 ms
SC_EN
Activation 250 s max.
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D. G.711(-law, A-law) (20 ms/frame mode)
Figure 21 G.711 (-law and A-law) Receive Buffer Control Method at
Single-Channel Operation (20 ms/frame mode)
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Speech CODEC coding format switching control
This LSI allows the switching of Speech CODEC coding format on the transmit and receive sides independently
during single-channel operation (SC_EN = 1 and DC_EN = 0). However, only the following patterns are
supported for the Speech CODEC coding format switching and any other switching patterns are inhibited.
A) Speech CODEC coding format switching control on the transmit side
A-1) G.729.A  G.711(-law/A-law) [Buffering time: Fixed to 10 ms]
A-2) G.729.A  G.711(-law/A-law) [Buffering time: Fixed to 20 ms]
A-3) G.711(-law/A-law)  G.729.A [Buffering time: Fixed to 10 ms]
A-4) G.711(-law/A-law)  G.729.A [Buffering time: Fixed to 20 ms]
B) Speech CODEC coding format switching control on the receive side
B-1) G.729.A  G.711(-law/A-law) [Buffering time: Fixed to 10 ms]
B-2) G.729.A  G.711( -law/A-law) [Buffering time: Fixed to 20 ms]
B-3) G.711(-law/A-law)  G.729.A [Buffering time: Fixed to 10 ms]
B-4) G.711(-law/A-law)  G.729.A [Buffering time: Fixed to 20 ms]
Figures 22 to 29 show the detail control methods for the switching control indicated above.
(Note)
1. Changing a buffering time (10 ms/20 ms) during activation of Speech CODEC (SC_EN = 1) is inhibited.
2. Switching from G.711 (A-law) to G.711 (-law) or from G.711 (-law) to G.711 (A-law) is inhibited.
3. Wait 100 ms or more before switching the Speech CODEC coding format again after the format is switched.
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A. Speech CODEC coding format switching control on the transmit side
A-1. G.729.A  G.711 (-law and A-law) switching control (10 ms frame mode)
10 ms
Speech
ENC
CODEC
T3
T4(G.729.A)
T5(G.729.A)
T6(G.729.A)
FR0B
(Pin output)
MCU read
Valid read section
RE_SC3
RE_SC4
RE_SC5
FR0_CH1
INTB
(Pin output)
G.729.A operation (before switching)
Transmit SC coding
format setting
Switching processing
G.711 operation (after switching)
G.729.A
G.711
G.729.A
G.711
TX_SCSEL[1:0]
Transmit SC operation
mode notification
TX_SCFLAG
10 ms
Speech
ENC
CODEC
T7(G.711)
T8(G.711)
T9(G.711)
T10(G.711)
FR0B
(Pin output)
MCU read
Valid read section
RE_SC7
RE_SC8
RE_SC9
FR0_CH1
INTB
(Pin output)
Figure 22 Speech CODEC Format Switching Control Method on the Transmit
Side G.729.AG.711 <10 ms frame mode>
 G.729.A operation (before switching)
Operates according to the contents described in  Operation and  Error processing in Figure 14 G.729.A
transmit buffer control method at single-channel operation (10 ms/frame mode).
 Switching processing
Switch the Speech CODEC coding format from G729.A to G.711 within the valid MCU read period according
to the setting in the Speech CODEC selection register on the transmit side (TX_SCSEL[1:0]). When the
switching of the Speech CODEC coding format is detected, the LSI internal section discards the data currently
being encoded (T6 encoding data in the example shown above) and starts encoding in the G.711 coding format
from the next frame.
A read request is issued normally by FR0B also for the frame where coding format has been switched;
however, a transmit error (TXERR_CH1 = “1”) does not occur even if data read processing does not terminate
within the valid read period. If a transmit error occurred before this frame, this transmit error is cleared to
“0” at termination of this frame.
(Note)
If the coding format is switched outside of the valid MCU read period, the G.729.A  G.711 switching
processing may be delayed by one frame. Therefore, check whether the transmit request is for the data
encoded in the G.729.A or encoded in the G.711 by referencing the transmit Speech CODEC operation mode
notification flag (TX_SCFLAG) when requesting transmission due to the fall of FR0B.
 G.711 operation (after switching)
Operates according to the contents that are described in  Operation and  Error processing in Figure 16
G.711 (-law and A-law) transmit buffer control method (10 ms/frame mode) at single-channel operation.
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A-2. G.729.A  G.711 (-law and A-law) switching control (20 ms frame mode)
20 ms
Speech
ENC
CODEC
T3(G.729.A)
T5(G.729.A)
FR0B
(Pin output)
MCU read
Valid read section
RE_SC1
RE_SC3
FR0_CH1
INTB
(Pin output)
G.729.A operation
(before switching)
Transmit SC coding
format setting
Switching processing
G.711 operation (after switching)
G.729.A
G.711
G.729.A
G.711
TX_SCSEL[1:0]
Transmit SC operation
mode notification
TX_SCFLAG
20 ms
Speech
ENC
CODEC
T7(G.711
T9(G.711)
T11(G.711)
FR0B
(Pin output)
MCU read
Valid read section
RE_SC7
RE_SC9
FR0_CH1
INTB
(Pin output)
Figure 23 Speech CODEC Coding Format Switching Method on the Transmit
Side G.729.AG.711 <20 ms frame mode>
 G.729.A operation (before switching)
Operates according to the contents described in Operation and Error processing in Figure 15. G.729.A
transmit buffer control method at single-channel operation (20 ms/frame mode).
 Switching processing
Switch the Speech CODEC coding format from G729.A to G.711 within the valid MCU read period
according to the setting in the Speech CODEC selection register on the transmit side (TX_SCSEL[1:0]).
When the switching of the Speech CODEC coding format is detected, the LSI internal section discards the
data currently being encoded (T5 encoding data in the example shown above) and starts encoding in the
G.711 coding format from the next frame.
A read request is issued normally by FR0B also for the frame where coding format has been switched;
however, a transmit error (TXERR_CH1 = “1”) does not occur even if data read processing does not
terminate within the valid read period. If a transmit error occurred before this frame, that transmit error is
cleared to “0” at termination of this frame.
(Note)
If the coding format is switched outside of the valid MCU read period, the G.729.A  G.711 switching
processing may be delayed by one frame. Therefore, check whether the transmit request is for the data
encoded in the G.729.A or encoded in the G.711 by referencing the transmit Speech CODEC operation mode
notification flag (TX_SCFLAG) when requesting transmission due to the fall of FR0B.
 G.711 operation (after switching)
Operates according to the contents that are described in Operation and Error processing in Figure 17
G.711 (-law and A-law) transmit buffer control method at single-channel operation (20 ms/frame mode).
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A-3. G.711 (-law, A-law)  G.729.A switching control (10 ms frame mode)
10 ms
Speech
CODEC
ENC
T4
T5(G.711)
T6(G.711)
FR0B
(Pin output)
MCU read
Valid read section
RE4
RE5
FR0_CH1
INTB
(Pin output)
 G.711 operation (before switching)
Transmit SC coding
format setting
TX_SCSEL[1:0]
Transmit SC operation
mode notification
TX_SCFLAG
 G.729.A operation (after switching)
 Switching processing
G.711
G.729.A
G.711
G.729.A
10 ms
Speech
CODEC
ENC
Init
T7(G.729.A)
T8(G.729.A)
T9(G.729.A)
FR0B
(Pin output)
MCU read
Valid read section
RE7
RE8
FR0_CH1
INTB
(Pin output)
Figure 24 Speech CODEC Coding Format Switching Control Method on the
Transmit Side G.711G.729.A <10 ms frame mode>
 G.711 operation (before switching)
Operates according to the contents described in  Operation and  Error processing in Figure 16 G.711
(-law and A-law) transmit buffer control method at single-channel operation (10 ms/frame mode).
 Switching processing
Switch the Speech CODEC coding format from G711 to G.729.A within the valid MCU read period according
to the setting in the Speech CODEC selection register on the transmit side (TX_SCSEL[1:0]). When the
switching of the Speech CODEC coding format is detected, the LSI internal section discards the data currently
being encoded (T6 encoding data in the example shown above) and starts encoding in the G.729.A coding
format from the next frame.
A read request is issued normally by FR0B also for the frame where coding format has been switched;
however, a transmit error (TXERR_CH1 = “1”) does not occur even if data read processing does not terminate
within the valid read period. If a transmit error occurred before this frame, that transmit error is cleared to
“0” at termination of this frame.
(Note)
If the coding format is switched outside of the valid MCU read period, the G.729.A  G.711 switching
processing may be delayed by one frame. Therefore, check if the transmit request is for the data encoded in
the G.729.A or encoded in the G.711 coding format by referencing the transmit Speech CODEC operation
mode notification flag (TX_SCFLAG) when requesting transmission due to the fall of FR0B.
 G.729.A operation (after switching)
Operates according to the contents that are described in Operation and Error processing in Figure 14
G.729.A transmit buffer control method at single-channel operation (10 ms frame mode).
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A-4. G.711 (-law and A-law)  G.729.A switching control (20 ms frame mode)
20 ms
Speech
ENC
CODEC
T3(G.711)
T5(G.711)
FR0B
(Pin output)
MCU read
Valid read section
RE3
FR0_CH1
INTB
(Pin output)
 G.711 operation (before switching)
Transmit SC coding
format setting
TX_SCSEL[1:0]
Transmit SC operation
mode notification
TX_SCFLAG
 Switching processing
 G.729.A operation (after switching)
G.711
G.729.A
G.711
G.729.A
20 ms
Speech
ENC
CODEC
Init
T7(G.729.A)
T9(G.729.A)
FR0B
(Pin output)
MCU read
Valid read section
RE7
FR0_CH1
INTB
(Pin output)
Figure 25 Speech CODEC Coding Format Switching Control Method on the
Transmit Side G.711G.729.A <20 ms frame mode>
 G.711 operation (before switching)
Operates according to the contents described in Operation and Error processing in Figure 17 G.711
(-law and A-law) transmit buffer control method at single-channel operation (20 ms/frame mode).
 Switching processing
Switch the Speech CODEC coding format from G711 to G.729.A within the valid MCU read period
according to the setting in the Speech CODEC selection register on the transmit side (TX_SCSEL[1:0]).
When detecting the switching of the Speech CODEC coding format, the LSI internal section discards the data
currently being encoded (T5 encoding data in the example shown above) and starts encoding in the G.729.A
coding format from the next frame.
A read request is issued normally by FR0B also for the frame where coding format has been switched;
however, a transmit error (TXERR_CH1 = “1”) does not occur even if data read processing does not
terminate within the valid read period. If a transmit error occurred before this frame, that transmit error is
cleared to “0” at termination of this frame.
(Note)
If the coding format is switched outside of the valid MCU read period, the G.729.A  G.711 switching
processing may be delayed by one frame. Therefore, check whether the transmit request is for the data
encoded in the G.729.A or encoded in the G.711 by referencing the transmit Speech CODEC operation mode
notification flag (TX_SCFLAG) when requesting transmission due to the fall of FR0B.
 G.729.A operation (after switching)
Operates according to the contents that are described in Operation and Error processing in Figure 15
G.729.A transmit buffer control method at single-channel operation (20 ms frame mode).
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B. Speech CODEC coding format switching control on the receive side
B-1. G.729.A  G.711(-law and A-law) switching control (10 ms frame mode)
Fade-out function valid period (*1)
Speech DEC
CODEC OUT
R4(G.729.A)
R5(G.729.A)
R6(G.729.A)
R7(G.729.A)
10 ms
FR1B
(Pin output)
MCU write
Valid write section
WE7
WE8
FR1
INTB
(Pin output)
 G.729.A operation (before switching)
Receive SC coding
format setting
G.729.A
RX_SCSEL[1:0
Receive SC operation
mode notification
RX_SCFLA
 G.711 operation (after switching)
 Switching processing
G.711
G.729.A
G.711
Approx.13.75 ms
Approx. 10 ms
Fade-in function valid period(*1)
Speech DEC
CODEC OUT
PLC_EN=
R10(G.711)
Silent
R10(G.711)
Silent
PLC_EN=
R11(G.711)
R11(G.711)
R12(G.711)
R12(G.711)
10 msec
FR1B
(Pin output)
MCU write
Valid write section
FR1
WE10
WE11
WE12
WE13
INTB
(Pin output)
(*1) Fade-in/fade-out function valid period: Approx. 15 ms
Figure 26 Speech CODEC Coding Format Switching Control Method on the
Receive Side G.729.AG.711 <10 ms frame mode>
 G.729.A operation (before switching)
Operates according to the contents described in  Operation and  Error processing in Figure 18 G.729.A
receive buffer method at single-channel operation (10 ms/frame mode).
 Switching processing
Switch the Speech CODEC coding format from G729.A to G.711 within the valid MCU write period
according to the setting in the Speech CODEC selection register on the receive side (RX_SCSEL[1:0]).
When receive data is written from the MCU in the frame from which the switching of the Speech CODEC
coding format has been detected, the LSI internal section performs decoding processing in the next frame.
When receive data is not written from the MCU, the frame loss compensation processing (BFI) that is
specified in G.729.A is performed in the next frame; however, a receive error (RXERR_CH1 = “1”) does not
occur.
If a receive error occurred before this frame, that receive error is cleared to “0” at termination of this frame.
To avoid sudden transition from a voice state to a silent state, the function that gradually attenuates decoding
output (fade-out function) operates.
(Note)
If the coding format is switched outside of the valid MCU write period, the G.729.A  G.711 switching
processing may be delayed by one frame. Therefore, check whether the receive request is for the receive
data encoded in the G.729.A or encoded in the G.711 by referencing the receive Speech CODEC operation
mode notification flag (RX_SCFLAG) when requesting reception due to the fall of FR1B.
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 G.711 operation (after switching)
Operates according to the operation that is effective on and after the third receive request that is described in
 Operation and  Error processing in Figure 20 G.711 (-law and A-law) receive buffer control method at
single-channel operation (10 ms/ frame mode).
To avoid a sudden transition from a silent state to a voice state, the function that gradually amplifies the
initial decoding output (fade-in function) operates.
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B-2. G.729.A  G.711 (-law and A-law) switching control (20 ms frame mode)
Fade-out function valid period (*1)
Speech DEC
CODEC OUT
R3(G.729.A)
R5(G.729.A)
20 ms
FR1B
(Pin output)
MCU write
Valid write section
WE_SC7
FR1
INTB
(Pin output)
G.729.A operation (before switching)
Receive SC coding
format setting
RX_SCSEL[1:0]
Receive SC operation
mode notification
RX_SCFLAG
Switching processing
G.711 operation (after switching)
G.729.A
G.711
G.729.A
G.711
Approx. 23.75 ms
Approx. 20 ms
Fade-in function valid period (*1)
Speech DEC
CODEC OUT
PLC_EN=1
Silent
PLC_EN=0
Silent
R11(G.711)
R9(G.711)
R9(G.711)
R11(G.711)
20 msec
FR1B
(Pin output)
MCU write
Valid write section
WE_SC9
WE_SC11
WE_SC15
FR1
INTB
(Pin output)
(*1) Fade-in/fade-out function valid period: Approx. 15 ms
Figure 27 Speech CODEC Coding Format Switching Control Method on the
Receive Side G.729.AG.711 <20 ms frame mode>
 G.729.A operation (before switching)
Operates according to the contents described in  Operation and  Error processing in Figure 19 G.729A
receive buffer method at single-channel operation (20 ms/frame mode).
 Switching processing
Switch the Speech CODEC coding format from G729.A to G.711 within the valid MCU write period
according to the setting in the Speech CODEC selection register on the receive side (RX_SCSEL[1:0]).
When receive data is written from the MCU in the frame from which the switching of the Speech CODEC
coding format has been detected, the LSI internal section performs decoding processing for the data of 10 ms
in the next frame. When receive data is not written from the MCU, the frame loss compensation processing
(BFI) that is specified in G.729.A is performed in the next frame; however, a receive error (RXERR_CH =
“1”) does not occur.
If a receive error occurred before this frame, that receive error is cleared to “0” at termination of this frame.
To avoid sudden transition from a voice state to a silent state, the function that gradually attenuates decoding
output (fade-out function) operates.
(Note)
If the coding format is switched outside of the valid MCU write period, the G.729.A  G.711 switching
processing may be delayed by one frame. Therefore, check whether the receive request is for the receive
data encoded in the G.729.A or encoded in the G.711 by referencing the receive Speech CODEC operation
mode notification flag (RX_SCFLAG) when requesting reception due to the fall of FR1B.
 G.711 operation (after switching)
Operates according to the operation that is effective on and after the third receive request that is described in
 Operation and  Error processing in Figure 21 G.711 (-law and A-law) receive buffer control method at
single-channel operation (20 ms/ frame mode).
To avoid a sudden transition from a silent state to a voice state, the function that gradually amplifies the
initial decoded output that was initially written from the MCU (fade-in function) operates.
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B-3. G.711 (-law and A-law)  G.729.A switching control (10 ms frame mode)
Fade-out function valid period (*1)
PLC_EN=1
R6(G.711)
R5(G.711)
Speech DEC
CODEC OUT
R7(G.711)
R8(G.711 or PLC)
Fade-out function valid period (*1)
PLC_EN=0
R5(G.711)
R6(G.711)
R7(G.711)
R8(G.711 or silent)
10 ms
FR1B
(Pin output)
MCU write
Valid write section
WE_SC7
WE_SC8
FR1
INTB
(Pin output)
 G.711 operation (before switching)
Receive SC coding
format setting
RX_SCSEL[1:
Receive SC
operation mode
notification
G.711
 Switching processing
 G.729.A operation (after switching)
G.729.A
G.711
G.729.A
RX_SCFLA
Approx. 20 ms
Fade-in function valid period(*1)
Speech DEC
CODEC OUT
Silent
Silent
R10(G.729.A)
R11(G.729.A)
R12(G.729.A)
10 msec
FR1B
(Pin output)
MCU write
Valid write section
WE_SC10
WE_SC11
WE_SC12
WE_SC13
WE_SC14
FR1
INTB
(Pin output)
(*1) Fade-in/fade-out function valid period: Approx. 15 ms
Figure 28 Speech CODEC Coding Format Switching Control Method on the
Receive Side G.711G.729.A<10 ms frame mode>
 G.711 operation (before switching)
Operates according to the contents described in Operation and Error processing in Figure 20 G.711
(-law and A-law) receive buffer control method at single-channel operation (10 ms/frame mode).
 Switching processing
Switch the Speech CODEC coding format from G.711 to G.729A within the valid MCU write period
according to the setting in the Speech CODEC selection register on the receive side (RX_SCSEL[1:0]).
When receive data is written from the MCU in the frame from which the switching of the Speech CODEC
coding format has been detected, the LSI internal section performs decoding processing in the next frame.
When receive data is not written from the MCU, data is generated according to the PLC algorithm and then
output (silent output when the PLC function is disabled) in the next frame; however, a receive error
(RXERR_CH = “1”) does not occur.
If a receive error occurred before this frame, that receive error is cleared to “0” at termination of this frame.
To avoid a sudden transition from a voice state to a silent state, the function that gradually attenuates the
decoding output (fade-out function) operates.
(Note)
If the coding format is switched outside of the valid MCU write period, the G.729.A  G.711 switching
processing may be delayed by one frame. Therefore, check whether the receive request is for the receive
data encoded in the G.729.A or encoded in the G.711 by referencing the receive Speech CODEC operation
mode notification flag (RX_SCFLAG) when requesting reception due to the fall of FR1B.
 G.729.A operation (after switching)
Operates according to the operation that is effective on and after the second receive request that is described in
Operation and Error processing in Figure 18 G.729.A receive buffer control method at single-channel
operation (10 ms/ frame mode).
To avoid a sudden transition from a silent state to a voice state, the function that gradually amplifies the
decoding output of the receive data that was initially written from MCU (fade-in function) operates.
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B-4. G.711 (-law, A-law)  G.729.A switching control (20 ms frame mode)
Fade-out function valid period (*1)
PLC_EN=1
Speech DEC
CODEC OUT
PLC_EN=0
R3(G.711)
R5(G.711)
R7(G.711 or PLC)
Fade-out function valid period (*1)
R3(G.711)
R5(G.711)
R7(G.711 or silent)
20 ms
FR1B
(Pin output)
MCU write
Valid write section
WE7
FR1
INTB
(Pin output)
G.711 operation
(before switching)
Receive SC coding
format setting
RX_SCSEL[1:0]
Receive SC
operation mode
notification
RX_SCFL
AG
G.711
G.729.A operation (after switching)
Switching processing
G.729.A
G.711
G.729.A
Approx. 30 ms
20 ms
Fade-in function valid period(*2)
Speech DEC
CODEC OUT
Silent
Silent
R9(G.729.A)
20 ms
FR1B
(Pin output)
MCU write
Valid write section
WE9
WE11
WE13
FR1
INTB
(Pin output)
(*1) Fade-in/fade-out function valid period: Approx. 15ms
Figure 29 Speech CODEC Coding Format Switching Control Method on the
Receive Side G.711G.729.A <20 ms frame mode>
 G.711 operation (before switching)
Operates according to the contents described in  Operation and  Error processing in Figure 21 G.711
(-law and A-law) receive buffer control method at single-channel operation (20 ms/frame mode).
 Switching processing
Switch the Speech CODEC coding format from G.711 to G.729.A within the valid MCU write period
according to the setting in the Speech CODEC selection register on the receive side (RX_SCSEL[1:0]).
When receive data is written from the the MCU in the frame from which the switching of the Speech CODEC
coding format has benn detected, the LSI internal section performs decoding processing for the data of 10 ms
in the next frame. When receive data is not written from the MCU, data is generated according to the PLC
algorithm and then output (silent output when the PLC function is disabled) in the next frame; however, a
receive error (RXERR_CH1 = “1”) does not occur.
If a receive error occurred before this frame, that receive error is cleared to “0” at termination of this frame.
To avoid a sudden transition from a voice state to a silent state, the function that gradually attenuates the
decoding output (fade-out function) operates.
(Note)
If the coding format is switched outside of the valid MCU write period, the G.729.A  G.711 switching
processing may be delayed by one frame. Therefore, check whether the receive request is for the receive
data encoded in the G.729.A or encoded in the G.711 by referencing the receive Speech CODEC operation
mode notification flag (RX_SCFLAG) when requesting reception due to the fall of FR1B.
 G.729.A operation (after switching)
Operates according to the operation that is effective on and after the second receive request that is described in
Operation and Error processing in Figure 19 G.729.A receive buffer control method at single channel
operation (20 ms/ frame mode).
To avoid a sudden transition from a silent state to a voice state, the function that gradually amplifies the
decoding output of the receive data that was initially written from MCU (fade-in function) operates.
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Transmit/receive buffer control at 2-channel operation
When G.711 (-law/A-law) is selected as the Speech CODEC coding format for both transmission and reception
operations, the mode for the following operations can be switched through the settings in SC_ EN (Speech
CODEC control register) and DC_EN (2-channel operation control register).
Transmission and reception of voice data of a single channel
(SC_EN = 1, DC_EN = 0)
Transmission and reception of 2-channel voice data
(SC_EN = 1, DC_EN = 1)
The G.711 PLC function can be enabled or disabled by setting the option in the G.711 PLC function enable
control register (G711_PLCEN). However, G711_PLCEN must be set to “0” (disabled) before activating
2-channel operation.
Figure 30 shows the transition of Speech CODEC operation modes when G.711 (-law/A-law) is selected as the
Speech CODEC coding format for both transmission and reception operations.
Single-channel
operation
G.711 PLC enabled
SC_EN=1,DC_EN=0,
G711_PLCEN=1
SC_EN=0, G711_PLCEN=0
SC_EN=1, G711_PLCEN=1
Stop
SC_EN=0, DC_EN=0
SC_EN=1
DC_EN=1
SC_EN=0
SC_EN=1
SC_EN=0
DC_EN=0
Single-channel
operation
DC_EN=1
G.711 PLC disabled
SC_EN=1, DC_EN=0
G711_PLCEN=0
DC_EN=0
2-channel
operation
G.711 PLC disabled
SC_EN=1, DC_EN=1
G711_PLCEN=0
Figure 30 Transition of Speech CODEC Operation Modes (G.711 -law/A-law)
See Figures 16, 17, 20, and 21 for details of the transmit/receive buffer control method in single-channel
operation.
See below for the details of the transmit/receive control method in 2-channel operation in Speech CODEC.
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When 2-channel voice data transmission/reception is specified, Speech CODEC performs the following
operation. The receive side decodes the received data of CH1 and CH2 that has been written from MCU and
adds the data to the Speech CODEC output. The transmit side encodes the following two types of voice data
and requests the reading of the data to the MCU for CH1 and CH2 individually.
Encoder input signal (CH1)
= (Transmit data AIN_x input to Speech CODEC) + (CH2 receive data Rx_CH2)
Encoder input signal (CH2)
= (Transmit data AIN_x input to Speech CODEC)+ (CH1 receive data Rx_CH1)
This function enables 3-way communication between the NW side (2 parties) and the terminal side (1 party).
Figure 31 shows the transmit/receive data flow in Speech CODEC under the three-way communication that is
performed between the terminal (A), which is connected to the analog interface of this LSI, and the terminal (B)
and another terminal (C) on the NW side.
Figures 32 to 35 show the transmit/receive buffer control methods at 2-channel processing.
Speech Codec
TXGAIN Encoder
_CH1
G.711
TXGAIN
_CH2
Terminal A
RX1TX2_
GAIN
B+C
(to A)
RXGAIN
_CH1
CH2
DC_EN
Bus Control
Unit
Terminal B
Terminal C
G.729.A
CH1
G.711
CH2
DC_EN
Figure 31
A+C
(to B)
A+B
(to C)
RX2TX1_
GAIN
Decoder
RXGAIN
_CH2
TX
Buffer0
TX
Buffer1
TSW
A
CH1
TSW
G.729.A
RX
Buffer0
B
C
RX
Buffer1
Inhibited
Transmit/Receive Data Flow at 2-Channel Operation
(Note)
When G.729.A is selected as the Speech CODEC coding format, the setting of DC_EN = 1 is inhibited.
When the G.711 PLC function is enabled, the setting of DC_EN = 1 is inhibited.
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MCU read
FR0B
(Pin output)
INPUT SIGNAL
(Upper level +
lower level)
ENC
INTB
(Pin output)
RXREQ_DC
(CR22-B5)
RXERR_CH1
(CR22-B2)
RXERR_CH2
(CR22-B3)
RXBW_ERR
(CR22-B1)
RXREQ_First
(CR22-B4)
FR1
(CR22-B0)
RXFLAG[CH2:CH1]
(CR5-[B1:B0])
Valid write section
FR1B
(Pin output)
MCU write
CH1
CH2
10 ms
DC_EN
(Pin output)
INTB
TXREQ_DC
(CR21-B5)
TXERR_CH1
(CR21-B2)
TXERR_CH2
(CR21-B3)
TXREQ_First
(CR21-B4)
FR0_CH2
(CR21-B1)
FR0_CH1
(CR21-B0)
Valid read section
DEC OUT
(CH1+CH2)
CH1
CH2
INPUT SIGNAL
(Upper level +
lower level)
ENC
10 ms
DC_EN
RE_SC2
T3_CH1
AIN_3
WE_SC4
R3_CH1
WE_SC5
R4_CH1
R5_CH1
10
(CH2)
Approx. 250 s
01
(CH1)
WE_DC6
(CH1 & CH2)
Silent
RE_SC4
R5_CH1
AIN_5
Silent
T5_CH1
 Activating 2-channel operation
RE_SC3
T4_CH1
AIN_4
T5_CH2
AIN_5
R4_CH1
Activating 2-channel operation
01
(CH1)
WE_DC7
(CH1 & CH2)
R6_CH1
R6_CH2
Approx. 250 s
RE_DC5
(CH1 & CH2)
10
(CH2)
R6_CH2
R6_CH1
T7_CH1
AIN_7
T7_CH2
AIN_7
T8_CH1
AIN_8
T8_CH2
01
(CH1)
WE_DC8
(CH1 & CH2)
CH2 write not
completed
(Silent)
R8_CH1
R8_CH2
10
(CH2)
Receive error (CH2)
10
(CH2)
WE_DC9
(CH1 & CH2)
Discard
01
(CH1)
Invalid write error
Receive error (CH1)
10
(CH2)
RE_DC9
(CH1 & CH2)
250 s max.
R10_CH1
_10
01
(CH1)
WE_DC11
(CH1 & CH2)
R9_CH1 (Silent)
WE_DC10
(CH1 & CH2)
R10
T10_CH1
error
RE_SC11
R11_CH1
No receive error
occurred (CH2)
WE_SC13
Silent output/Init t
WE_SC12
AIN_12
T12_CH1
Stop / Init
RE_SC12
T13_
AIN_13
Performing single-channel operation
R12_CH1
 Performing single-channel operation
No
transmit
occurred (CH2)
RE_SC10
T11_CH1
AIN_11
 Terminating 2-channel operation
R9_CH2
Transmit error (CH2)
R10
AIN_10
T10_CH2
AIN_10
(Silent)
250 s max.
Terminating 2-channel operation
R9_CH2
Transmit error (CH1)
RE_DC8
(CH1 & CH2)
T9_CH1
Continuous write in the same channel
R7_CH1
R7_CH2
 Performing 2-channel operation
RE_DC7
(CH1 & CH2)
T9_CH2
AIN_9
R9_CH1
AIN_9
R8_CH2 (Silent)
AIN_8
R8_CH1
Read not completed
R7_CH2
R7_CH1
RE_DC6
(CH1 & CH2)
In the order of CH1CH2
T6_CH1
AIN_6
T6_CH2
AIN_6
Performing 2-channel operation
(Note) The frame timing on the transmit side and the frame timing on the receive side vary according to the timing of setting DEC_OUTON=1. In this diagram, the same timing is assumed for the transmit side and the receive side.
WE_SC3
R2_CH1
Silent output/Init
 Performing single-channel operation
RE_SC1
T2_CH1
AIN_2
Stop / Init
Performing single-channel operation
FEDL7204-003-02
ML7204-003
Figure 32 Transmit/Receive Buffer Control Method (10 ms frame, G.711) at
2-channel operation) <When changed from single-channel
operation to 2-channel operation>
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Description of operation (Figure 32)
 Performing single-channel operation
 Transmit
Operates according to the contents described in  Operation and  Error processing in Figure 16.
 Receive
Operates according to the contents described in  Operation and  Error processing in Figure 20. The
G.711PLC function enable control register (G711_PLCEN) must be set to “0” at activation of Speech CODEC.
 Activating 2-channel operation
To change the mode from a single-channel operation mode to a 2-channel operation mode, set DC_EN = 1 (&
SC_EN = 1).
Encoder: Starts encoding signals from CH1 and CH2 after processing of up to one frame following the setting of
DC_EN = 1.
Decoder: Starts two receive data write requests in one frame after processing of up to one frame following the
setting of DC_EN = 1.
(Note)
When G.729.A is selected as the Speech CODEC coding format, the setting of SC_EN = DC_EN = 1 is
inhibited.
When the G.711 PLC function is enabled, the setting of SC_EN = DC_EN = 1 is inhibited.
 Performing 2-channel operation
 Transmit
 2-channel transmit request notification register (TXREQ_DC)
The 2-channel transmit request notification register (TXREQ_DC) is set to “1” while two transmit data read
requests are issued in one frame.
 Channel data read sequence
Two transmit data read requests are issued in one frame in the order of CH1CH2.
However, when read operation from the MCU side does not terminate for the CH1 transmit data read request, a
read request for CH2 transmit data is not issued.
 Read sequence
After encoding processing for CH1 and CH2 of one frame terminates, an interrupt is generated by setting
FR0_CH1 = 1 and a CH1 transmit data read request is issued. Read CH1 transmit data (80 bytes) according
to the read request.
When CH1 transmit data read processing terminates, an interrupt is generated by setting FR0_CH2 = 1 and a
CH2 transmit data read request is issued.
Read CH2 transmit data (80 bytes) according to the read request.
In this operation state, the following signals are input to the encoder from CH1 and CH2.
Encoder input signal (CH1) = (Transmit data AIN_x input to Speech CODEC) + (CH2 receive data
Rx_CH2)
Encoder input signal (CH2) = (Transmit data AIN_x input to Speech CODEC) + (CH1 receive data
Rx_CH1)
 Valid read period RE_DCn (CH1 & CH2)
Terminate transmit data read processing from CH1 and CH2 within 9.0 ms after a CH1 transmit data read
request (FR0_CH1 = 1) is issued.
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 Transmit error processing
If read processing from the MCU side does not terminate within the valid read period, an interrupt is generated
by setting the transmit error flag of the relevant channel (CH1:TXERR_CH1, CH2:TXERR_CH2) to “1”.
The transmit error is retained from the next valid read period until just before termination of the frame for
which transmit data read processing has been performed normally for the channel. Even if data read
processing does not terminate, the data in the transmit buffer is updated normally.
 Receive
2-channel receive request notification register (RXREQ_DC)
In this operation state, the MCU side is notified that two receive data write requests will be issued in one frame
by setting the 2-channel receive request notification register (RXREQ_DC) to “1”.
 Data write channel sequence
Since data can be written to the channels in any sequence, write receive data in either sequence of CH1  CH2
or CH2CH1 in one frame.
(Note)
Do not write receive data of the same channel in one frame in such a manner as CH1  CH1 and CH2  CH2.
If receive data of the same channel is written in one frame, the receive data that is written by the first receive
request is decoded; however, the receive data that is written in the second receive request is discarded and an
interrupt is generated by setting a receive side invalid write error flag (RXBW_ERR) to “1”.
 Write procedure
This section describes the operation performed when receive data is written in the sequence of CH1  CH2.
Write CH1 receive data (80 bytes) according to the first receive data write request (FR1 = 1&RXREQ_First =
1).
Before starting write operation of CH1 receive data, notify the LSI that CH1 receive data will be written by
setting the receive data write channel notification register ((RXFLAG_[CH2:CH1]) to [0:1].
After termination of CH1 receive data write processing, the second receive data write request (FR1 = 1 &
RXREQ_First = 0) is issued.
Write CH2 receive data (80 bytes) according to the second write request. In this case also, notify the LSI that
CH2 receive data will be written by setting the receive data write channel notification register
((RXFLAG_[CH2:CH1]) to [1:0], before starting CH2 receive data write processing. When a receive data
write request is issued, an interrupt is generated by setting FR1 to “1” regardless of the first or second request.
(Note)
The setting of RXFLAG_[CH2:CH1] = [1:1] or [0:0] is inhibited at notification of a receive data channel.
If RXFLAG_[CH2:CH1] = [1:1] or [0:0] is set, the receive data is discarded and an interrupt is generated by
setting the receive side invalid write error flag (RXBW_ERR) to “1”.
 Valid write period WE_DCn (CH1 & CH2)
The valid write period is 9 ms.
 Receive error processing
Terminate write processing of CH1 receive data and CH2 receive data within the valid write period.
If write processing from the MCU does not terminate within the valid write period, an interrupt is generated by
setting the receive error flag of the relevant channel (CH1:RXERR_CH1 or CH2:RXERR_CH2) to “1”.
The receive error is retained from the next valid write period until immediately before the termination of the
frame for which receive data of the channel has been written normally. When write processing of the receive
data of the channel is not performed, silent data is output.
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When receive data of the same channel is written in one frame or the receive data channel notification is
invalid, an interrupt is generated by setting a receive side invalid write error flag (RXBW_ERR) to “1”.
RXBW_ERR is retained from the next valid write period until immediately before the termination of the frame
for which invalid receive data has no longer been written.
 Terminating 2-channel operation
When returning a 2-channel operation mode to a single-channel operation mode, it is possible to notify which
channel’s transmit/receive data is continuously encoded or decoded by setting an option in ACTCH_FLAG.
To continue encoding/decoding of transmit/receive data of channel 1, set ACTCH_FLAG to “0” and then set
SC_EN = 1 and DC_EN = 0. Encoding/decoding of channel 2 transmit/receive data stops within a maximum of
250 s; however, encoding/decoding of channel 1 transmit/receive data continues.
To continue encoding/decoding of channel 2 transmit/receive data, set ACTCH_FLAG to “1” and then set
SC_EN = 1 and DC_EN = 0. Encoding/decoding of channel 1 transmit/receive data stops within a maximum
of 250 s; however, encoding/decoding of channel 2 transmit/receive data continues. Figure 32 shows an
example where exchange of channel 1 transmit/receive data is continued.
(Note)
1. In the frame where SC_EN = 1 and DC_EN = 0 are set, CH1/CH2 transmit data read requests and receive data
write requests are issued normally. However, even if transmit data or receive data of the channel that was
terminated is not read or written, an error does not occur.
2. After RXREQ_DC is cleared to “0”, write processing to RXFLAG_[CH2:CH1] is not necessary.
3. To set DC_EN = 1 again after setting DC_EN = 0, a wait period of approx. 10 ms or more is required after
TXREQ_DC = 0 and RXREQ_DC = 0 are set.
 Performing single-channel operation
 Transmit
Operates according to the contents described in  Operation and  Error processing in Figure 16.
Note that FR0_CH1 is set to “1” when a transmit data read request is issued in this operation state or the CH1
transmit error flag (TXERR_CH1) is set to “1” at the occurrence of an error also in this operation state, even if
continuation of encoding/decoding of channel 2 transmit/receive data is set in  Terminating 2-channel
operation.
 Receive
Operates according to the contents described in  Operation and  Error processing in Figure 20. The G.711
PLC function enable control register (G711_PLCEN) is set to “0”.
Note that the CH1 receive error flag (RXERR_CH1) is set to “1” at the occurrence of an error in this operation
state even if continuation of encoding/decoding of the channel 2 transmit/receive data is set in  Terminating
2-channel operation.
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INTB
(Pin output)
TXREQ_DC
(CR21-B5)
TXERR_CH1
(CR21-B2)
TXERR_CH2
(CR21-B3)
TXREQ_First
(CR21-B4)
(CR21-B0)
FR0_CH2
(CR21-B1)
FR0_CH1
Valid read section
MCU read
FR0B
(Pin output)
INPUT SIGNAL
(Upper level +
ower level)
ENC
RE_SC1
T3 CH1
AIN_3
CH1
CH2
20 ms
WE_SC3
R1 CH1
WE_SC5
Silent output /Init
R3_CH1
 Activating 2-channel operation
RE_SC3
T5 CH1
AIN_5
Termination / Init
 Activating 2-channel operation
01
(CH1)
Silent
T7_CH1
AIN_7
T7_CH2
AIN_7
Approx. 250 s
(CH1 & CH2)
10
(CH2)
WE_DC7
RE_SC5
R3_CH1
R5_CH1
Silent
R5_CH1
R7_CH2
R7_CH1
01
(CH1)
WE_DC9
(CH1 & CH2)
CH2 write not completed
R7 CH
R7 CH
 Performing 2-channel operation
Approx. 250 s
RE_DC7
(CH1 & CH2)
In the order of CH1CH2
T9_CH1
AIN_9
T9_CH2
AIN_9
 Performing 2-channel operation
R9_CH2
Receive error
10
(CH2)
10
(CH2)
WE_DC11
(CH1 & CH2)
Discard
(Silent)
(Silent)
R9_CH1
R9_CH1
Continuous write in the same channel
(CH1 & CH2)
RE_DC9
Read not completed
T11_CH1
T11_CH2
AIN_11
R9_CH2
AIN_11
Invalid write error
Receive error
(CH1 & CH2)
01
10
(CH1)
(CH2)
WE_DC13
R11_CH1(Silent)
Transmit error (CH2)
Transmit error (CH1)
R11_CH2
T13_CH1
RE_DC11
(CH1 & CH2)
(Silent)
AIN_13
R11_CH1
T13_CH2
AIN_13
R11_CH1
(Note) The frame timing on the transmit side and the frame timing on the receive side vary according to the timing of setting DEC_OUTON=1. In this diagram, the same timing is assumed for the transmit side and the receive side.
INTB
(Pin output)
RXREQ_DC
(CR22-B5)
RXERR_CH1
(CR22-B2)
RXERR_CH2
(CR22-B3)
RXBW_ERR
(CR22-B1)
RXREQ_First
(CR22-B4)
(CR22-B0)
FR1
RXFLAG[CH2:CH1]
(CR5-[B1:B0])
Valid write section
MCU write
FR1B
(Pin output)
(CH1+CH2)
DEC OUT
DC_EN
 Performing single-channel operation
CH1
CH2
INPUT SIGNAL
(Upper level +
lower level)
ENC
20 ms
DC_EN
 Performing single-channel operation
01
(CH1)
WE DC15
(CH1 & CH2)
R13_CH2
 Performing
single-channel
operation
R13_CH1
WE_SC17
R15_CH1
occurred
No receive error
Silent output /Init
250 s max.
 Performing
single-channel
operation
occurred (CH2)
No transmit error
RE_SC15
T17_CH1
AIN_17
Termination / Init
250 s max.
 Terminating 2-channel operation
(CH1 & CH2)
RE_DC13
T15_CH1
AIN_15
R13_CH1
T15_CH2
AIN_15
R13_CH1
 Terminating 2-channel operation
FEDL7204-003-02
ML7204-003
Figure 33 Transmit/Receive Buffer Control Method at 2-Channel Operation (20 ms frame,
G.711) <When changed from single-channel operation to 2-channel operation>
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Description of operation (Figure 33)
 Performing single-channel operation
 Transmit
Operates according to the contents described in Operation and Error processing in Figure 17.
 Receive
Operates according to the contents described in Operation and Error processing in Figure 21. The
G.711PLC function enable control register (G711_PLCEN) must be set to “0” at activation of Speech CODEC.
 Activating 2-channel operation
To change the mode from a single-channel operation mode to a 2-channel operation mode, set DC_EN = 1 (&
SC_EN = 1).
Encoder: Starts encoding signals from CH1 and CH2 after processing of up to one frame following the setting of
DC_EN = 1.
Decoder: Starts two receive data write requests in one frame after processing of up to one frame following the
setting of DC_EN = 1.
(Note)
When G.729.A is selected as the Speech CODEC coding format, the setting of SC_EN = DC_EN = 1 is
inhibited.
When the G.711 PLC function is enabled, the setting of SC_EN = DC_EN = 1 is inhibited.
 Performing 2-channel operation
 Transmit
 2-channel transmit request notification register (TXREQ_DC)
The 2-channel transmit request notification register (TXREQ_DC) is set to “1” while two transmit data read
requests are issued in one frame.
 Channel data read sequence
Two transmit data read requests are issued in one frame in the order of CH1  CH2.
However, when read operation from the MCU side does not terminate for the CH1 transmit data read request, a
read request for CH2 transmit data is not issued.
 Read sequence
After encoding processing for CH1 and CH2 of one frame terminates, an interrupt is generated by setting
FR0_CH1 and a CH1 transmit data read request is issued. Read CH1 transmit data (160 bytes) according to
the read request.
When CH1 transmit data read processing terminates, an interrupt is generated by setting FR0_CH2 = 1 and a
CH2 transmit data read request is issued.
Read CH2 transmit data (160 bytes) according to the read request.
In this operation state, the following signals are input to the encoder from CH1 and CH2.
Encoder input signal (CH1) = (Transmit data AIN_x input to Speech CODEC) + (CH2 receive data
Rx_CH2)
Encoder input signal (CH2) = (Transmit data AIN_x input to Speech CODEC) + (CH1 receive data
Rx_CH1)
 Valid read period RE_DCn(CH1 & CH2)
Terminate transmit data read processing from CH1 and CH2 within 18.0 ms after a CH1 transmit data read
request (FR0_CH1 = 1) is issued.
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 Transmit error processing
If read processing from the MCU side does not terminate within the valid read period, an interrupt is generated
by setting the transmit error flag of the relevant channel (CH1: TXERR_CH1, CH2: TXERR_CH2) to “1”.
The transmit error is retained from the next valid read period until just before termination of the frame for
which transmit data read processing has been performed normally for the channel. Even if data read
processing does not terminate, the data in the transmit buffer is updated normally.
 Receive
 2-channel receive request notification register (RXREQ_DC)
In this operation state, the MCU side is notified that two receive data write requests will be issued in one frame
by setting the 2-channel receive request notification register (RXREQ_DC) to “1”.
 Data write channel sequence
Since data can be written to the channels in any sequence, write receive data in either sequence of CH1  CH2
or CH2  CH1 in one frame.
(Note)
Do not write receive data of the same channel in one frame in such a manner as CH1  CH1 and CH2  CH2.
If receive data of the same channel is written in one frame, the receive data that is written by the first receive
request is decoded; however, the receive data that is written in the second receive request is discarded and an
interrupt is generated by setting a receive side invalid write error flag (RXBW_ERR) to “1”.
 Write procedure
This section describes the operation performed when receive data is written in the sequence of CH1  CH2.
Write CH1 receive data (160 bytes) according to the first receive data write request (FR1 = 1 & RXREQ_First
= 1).
Before starting write operation of CH1 receive data, notify the LSI that CH1 receive data will be written by
setting the receive data write channel notification register ((RXFLAG_[CH2:CH1]) to [0:1].
After termination of CH1 receive data write processing, the second receive data write request (FR1 = 1 &
RXREQ_First = 0) is issued.
Write CH2 receive data (160 bytes) according to the second write request. In this case also, notify the LSI
that CH2 receive data will be written by setting the receive data write channel notification register
((RXFLAG_[CH2:CH1]) to [1:0], before starting CH2 receive data write processing. When a receive data
write request is issued, an interrupt is generated by setting FR1 to “1” regardless of the first or second request.
(Note)
The setting of RXFLAG_[CH2:CH1] = [1:1] or [0:0] is inhibited at notification of a receive data channel.
If RXFLAG_[CH2:CH1] = [1:1] or [0:0] is set, the receive data is discarded and an interrupt is generated by
setting the receive side invalid write error flag (RXBW_ERR) to “1”.
 Valid write period WE_DCn (CH1 & CH2)
The valid write period is 18.0 ms.
 Receive error processing
Terminate write processing of CH1 receive data and CH2 receive data within the valid write period.
If write processing from the MCU does not terminate within the valid write period, an interrupt is generated by
setting the receive error flag of the relevant channel (CH1: RXERR_CH1 or CH2: RXERR_CH2) to “1”.
The receive error is retained from the next valid write period until immediately before the termination of the
frame for which receive data of the channel has been written normally. When write processing of the receive
data of the channel is not performed, silent data is output.
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When receive data of the same channel is written in one frame or the receive data channel notification is
invalid, an interrupt is generated by setting a receive side invalid write error flag (RXBW_ERR) to “1”.
RXBW_ERR is retained from the next valid write period until immediately before the termination of the frame
for which invalid receive data has no longer been written.
 Terminating 2-channel operation
When returning a 2-channel operation mode to a single-channel operation mode, it is possible to notify which
channel’s transmit/receive data is continuously encoded or decoded by setting an option in ACTCH_FLAG.
To continue encoding/decoding of transmit/receive data of channel 1, set ACTCH_FLAG to “0” and then set
SC_EN = 1 and DC_EN = 0. Encoding/decoding of channel 2 transmit/receive data stops within a maximum of
250 s; however, encoding/decoding of channel 1 transmit/receive data continues.
To continue encoding/decoding of channel 2 transmit/receive data, set ACTCH_FLAG to “1” and then set
SC_EN = 1 and DC_EN = 0. Encoding/decoding of channel 1 transmit/receive data stops within a maximum
of 250 s; however, encoding/decoding of channel 2 transmit/receive data continues. Figure 33 shows an
example where exchange of channel 1 transmit/receive data is continued.
(Note)
1. In the frame where SC_EN = 1 and DC_EN = 0 are set, CH1/CH2 transmit data read requests and receive
data write requests are issued normally. However, even if transmit data or receive data of the channel that
was terminated is not read or written, an error does not occur.
2. After RXREQ_DC is cleared to “0”, write processing to RXFLAG_[CH2:CH1] is not necessary.
3. To set DC_EN = 1 again after setting DC_EN = 0, a wait period of about 10 ms or more is required after
TXREQ_DC = 0 and RXREQ_DC = 0 are set.
 Performing single-channel operation
 Transmit
Operates according to the contents described in  Operation and  Error processing in Figure 17.
Note that FR0_CH1 is set to “1” when a transmit data read request is issued in this operation state or the CH1
transmit error flag (TXERR_CH1) is set to “1” at the occurrence of an error also in this operation state, even if
continuation of encoding/decoding of channel 2 transmit/receive data is set in  Terminating 2-channel
operation.
 Receive
Operates according to the contents described in  Operation and  Error processing in Figure 21. The G.711
PLC function enable control register (G711_PLCEN) is set to “0”.
Note that the CH1 receive error flag (RXERR_CH1) is set to “1” at the occurrence of an error in this operation
state even if continuation of encoding/decoding of the channel 2 transmit/receive data is set in  Terminating
2-channel operation.
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ENC
01
(CH1)
10
(CH2)
R1_CH2
R1_CH1
T3_CH1
AIN_3
T3_CH2
AIN_3
R1_CH1
R1_CH2
R3_CH2
R3_CH1
R3_CH1
R3_CH2
01
(CH1)
WE_DC4
(CH1 & CH2)
10
(CH2)
R2_CH1
R2_CH2
Approx. 250 s
RE_DC3
(CH1 & CH2)
T4_CH1
AIN_4
T4_CH2
AIN_4
RE_DC4
(CH1 & CH2)
T5_CH1
AIN_5
T5_CH2
AIN_5
01
(CH1)
WE_DC5
(CH1 & CH2)
CH2 write not
completed
 Performing 2-channel operation
R2_CH2
R2_CH1
10
(CH2)
WE_DC3
(CH1 & CH2)
RE_DC2
(CH1 & CH2)
01
10
01
(CH1) (CH2) (CH1)
WE_DC2
(CH1 & CH2)
tDECON
approx. 250 s
RE_DC1
(CH1 & CH2)
In the order of CH1  CH2
T2_CH1
AIN_2
T2_CH2
AIN_2
 Performing 2-channel operation
T7_CH1
AIN_7
T7_CH2
(Silent)
10
(CH2)
Receive error (CH2)
10
(CH2)
WE_DC6
(CH1 & CH2)
01
(CH1)
T8_CH1
AIN_8
01
(CH1)
WE_DC8
(CH1 & CH2)
(Silent)
7
7
Termination/Init
_7
_7
00
(Automatic clearing)
Silent output/Init
Silent output/Init
 Terminating 2-channel operation
RE_DC7
(CH1 & CH2)
R6_CH2
Receive error (CH1)
10
(CH2)
WE_DC7
(CH1 & CH2)
Invalid write error
Discard
R6_CH1
Transmit error (CH2)
AIN_8
T8_CH2
Termination/Init
 Terminating 2-channel operation
250 s max.
(Silent)
R6_CH2
Transmit error (CH1)
RE_DC6
(CH1 & CH2)
R5_CH1
R5_CH2
RE_DC5
(CH1 & CH2)
(Silent)
R5_CH1
Read not completed
T6_CH1
AIN_6
R5_CH2
T6_CH2
AIN_7
R6_CH1
Continuous write in the same channel
R4_CH1
R4_CH2
R4_CH2
R4_CH1
AIN_6
(Note) The frame timing on the transmit side and the frame timing on the receive side vary according to the timing of setting DEC_OUTON = 1. In this diagram, the same timing is assumed for the transmit side and the receive side.
INTB
(Pin output)
RXERR_CH2
(CR22-B3)
RXBW_ERR
(CR22-B1)
RXERR_CH1
(CR22-B2)
RXREQ_DC
(CR22-B5)
RXREQ_First
(CR22-B4)
FR1
(CR22-B0)
(CR5-[B1:B0])
RXFLAG[CH2:CH1]
Valid write section
WE_DC1
(CH1 & CH2)
Silent output/Init
CH1
tWAIT
Silent output/Init
FR1B
(Pin output)
MCU write
Silent
T1_CH1
 Activating 2-channel operation
Termination/Init
AIN_1
CH2
10 ms
DEC_OUTON
INTB
(Pin output)
TXERR_CH1
(CR21-B2)
TXERR_CH2
(CR21-B3)
TXREQ_DC
(CR21-B5)
TXREQ_First
(CR21-B4)
FR0_CH2
(CR21-B1)
FR0_CH1
(CR21-B0)
Valid read section
MCU read
FR0B
(Pin output)
ENC
Silent
T1_CH2
AIN_1
 Activating 2-channel operation
Termination/Init
INPUT SIGNAL
(Upper level + lower level)
DEC OUT
(CH1+CH2)
CH1
CH2
INPUT SIGNAL
(Upper level + lower level)
10 ms
SC_EN
DC_EN
FEDL7204-003-02
ML7204-003
Figure 34 Transmit/Receive Buffer Control Method at 2-Channel Operation (10 ms
frame, G.711) <When performing 2-channel operation from the beginning>
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Description of operation (Figure 34)
 Activating 2-channel operation
To activate 2-channel operation from the Speech CODEC termination state, set SC_EN and DC_EN to “1”
concurrently.
Encoder: Starts encoding of CH1 and CH2 signals within a maximum of 250 s after SC_EN = DC_EN = 1 is
set.
Decoder: Issues a receive data write request within a maximum of 250 s after SC_EN = DC_EN = 1 is set.
(Note)
When G.729.A is selected as the Speech CODEC coding format, the setting of SC_EN = DC_EN = 1 is
inhibited.
When the G.711 PLC function is enabled, the setting of SC_EN = DC_EN = 1 is inhibited.
Performing 2-channel operation
 Transmit
 2-channel transmit request notification register (TXREQ_DC)
The 2-channel transmit request notification register (TXREQ_DC) is set to “1” while two transmit data read
requests are issued in one frame.
 Channel data read sequence
Two transmit data read requests are issued in one frame in the order of CH1  CH2.
However, when read operation from the MCU side does not terminate for the CH1 transmit data read request, a
read request for CH2 transmit data is not issued.
 Read sequence
After encoding processing for CH1 and CH2 of one frame terminates, an interrupt is generated by setting
FR0_CH1 = 1 and a CH1 transmit data read request is issued. Read CH1 transmit data (80 bytes) according
to the read request.
When CH1 transmit data read processing terminates, an interrupt is generated by setting FR0_CH2 = 1 and a
CH2 transmit data read request is issued.
Read CH2 transmit data (80 bytes) according to the read request.
In this operation state, the following signals are input to the encoder from CH1 and CH2.
Encoder input signal (CH1) = (Transmit data AIN_x input to Speech CODEC) + (CH2 receive data
Rx_CH2)
Encoder input signal (CH2) = (Transmit data AIN_x input to Speech CODEC) + (CH1 receive data
Rx_CH1)
 Valid read period RE_DCn(CH1 & CH2)
Terminate transmit data read processing from CH1 and CH2 within 9.0 ms after a CH1 transmit data read
request (FR0_CH1 = 1) is issued.
 Transmit error processing
If read processing from the MCU side does not terminate within the valid read period, an interrupt is generated
by setting the transmit error flag of the relevant channel (CH1: TXERR_CH1, CH2: TXERR_CH2) to “1”.
The transmit error is retained from the next valid read period until just before termination of the frame for
which transmit data read processing has been performed normally for the channel. Even if data read
processing does not terminate, the data in the transmit buffer is updated normally.
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 Receive
 2-channel receive request notification register (RXREQ_DC)
In this operation state, the MCU side is notified that two receive data write requests will be issued in one frame
by setting the 2-channel receive request notification register (RXREQ_DC) to “1”.
 Data write channel sequence
Since data can be written to the channels in any sequence, write receive data in either sequence of CH1  CH2
or CH2  CH1 in one frame.
(Note)
Do not write receive data of the same channel in one frame in such a manner as CH1  CH1 and CH2  CH2.
If receive data of the same channel is written in one frame, the receive data that is written by the first receive
request is decoded; however, the receive data that is written in the second receive request is discarded and an
interrupt is generated by setting a receive side invalid write error flag (RXBW_ERR) to “1”.
 Write procedure
This section describes the operation performed when receive data is written in the sequence of CH1  CH2.
Write CH1 receive data (80 bytes) according to the first receive data write request (FR1 = 1&RXREQ_First =
1).
Before starting write operation of CH1 receive data, notify the LSI that CH1 receive data will be written by
setting the receive data write channel notification register (RXFLAG_[CH2:CH1]) to [0:1].
After termination of CH1 receive data write processing, the second receive data write request (FR1 = 1 &
RXREQ_First = 0) is issued.
Write CH2 receive data (80 bytes) according to the second write request. In this case also, notify the LSI that
CH2 receive data will be written by setting the receive data write channel notification register
(RXFLAG_[CH2:CH1]) to [1:0], before starting CH2 receive data write processing. When a receive data
write request is issued, an interrupt is generated by setting FR1 to “1” regardless of the first or second request.
(Note)
The setting of RXFLAG_[CH2:CH1] = [1:1] or [0:0] is inhibited at notification of a receive data channel.
If RXFLAG_[CH2:CH1] = [1:1] or [0:0] is set, the receive data is discarded and an interrupt is generated by
setting the receive side invalid write error flag (RXBW_ERR) to “1”.
 Valid write period WE_DCn (CH1 & CH2)
WE_DC1 (CH1 & CH2)
There is no time restriction on the initial valid write period after activation of Speech CODEC (CH1 & CH2).
DEC_OUTON can be set to “1” after a lapse of the tWAIT time following completion of receive data write
processing for CH1 and CH2. Decoding output starts tDECON after DEC_OUTON is set to “1”. (*)
(tWAIT=1ms, tDECON = 0 ms[initial value] ... Can be set within the range from 0.125 to 32 ms in the internal
data memory.)
WE_DC2 (CH1 & CH2)
The second valid write period is 4 ms.
WE_DCn (CH1 & CH2) n = 3, 4, 5, ...
The third valid write period is 9 ms.
(Note) (*)
It is prohibited to change the mode to a single-channel operation mode (SC_EN = 1, DC_EN = 0) before the
decoding output starting offset time elapses after DEC_OUTON is set to “1”.
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 Receive error processing
Terminate write processing of CH1 receive data and CH2 receive data within the valid write period.
If write processing from the MCU does not terminate within the valid write period, an interrupt is generated by
setting the receive error flag of the relevant channel (CH1: RXERR_CH1 or CH2: RXERR_CH2) to “1”.
The receive error is retained from the next valid write period until immediately before the termination of the
frame for which receive data of the channel has been written normally. When write processing of the receive
data of the channel is not performed, silent data is output.
When receive data of the same channel is written in one frame or the receive data channel notification is
invalid, an interrupt is generated by setting a receive side invalid write error flag (RXBW_ERR) to “1”.
RXBW_ERR is retained from the next valid write period until immediately before the termination of the frame
for which invalid receive data has no longer been written.
 Terminating 2-channel operation
To return from a 2-channel mode to a termination mode, set SC_EN = 0 and DC_EN = 0. The encoder of
Speech CODEC (CH1 & CH2) stops data write processing within a maximum of 250 s after SC_EN = 0 and
DC_EN = 0 are set.
(Note)
1. After SC_EN = 0 and DC_EN = 0 are set, RXFLAG_[CH2:CH1] are cleared to 00b automatically within a
maximum of 250 s.
2. A wait period of 10 ms or more is required after SC_EN = 0 is set until SC_EN = 1 is set again.
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MCU read
FR0B
(Pin output)
INPUT SIGNAL
(Upper level +
lower level)
ENC
CH1
01
(CH1)
01
(CH1)
WE_DC5
(CH1 & CH2)
CH2 write not
completed
R3_CH1
R3_CH2
R5_CH1
T7_CH2
Continuous write in the
same channel
(Silent)
01
(CH1)
WE_DC9
(CH1 & CH2)
Transmit error (CH2)
Transmit error (CH1)
R5_CH1
R5_CH2
AIN_7
T7_CH2
(Silent)
RE_DC1
(CH1 & CH2)
R5_CH2
Discard
10
(CH2)
Receive error (CH2)
10
(CH2)
WE_DC7
(CH1 & CH2)
T5_CH1
AIN_5
T5_CH2
AIN_7
(Note) The frame timing on the transmit side and the frame timing on the receive side vary according to the timing of setting DEC_OUTON=1. In this diagram, the same timing is assumed for the transmit side and the receive side.
INTB
(Pin output)
R7_CH2
R7_CH2
R7_CH1
AIN_9
9
Termination/Init
Termination/Init
(Silent)
01
(CH1)
WE_DC11
(CH1 & CH2)
_9
_9
00
(Automatic clearing)
Silent output/Init
Silent output/Init
Terminating 2-channel operation
T9_CH1
AIN_9
9
250 s max.
Terminating 2-channel operation
T9_CH2
(Silent)
RE_DC5
(CH1 & CH2)
R7_CH1
10
(CH2)
Invalid write error
10
(CH2)
WE_DC3
(CH1 & CH2)
R1_CH1
R1_CH2
RE_DC3
(CH1 & CH2)
R3_CH2
R3_CH1
Performing 2-channel operation
In the order of
CH1CH2
T3_CH1
AIN_3
T3_CH2
AIN_5
Receive error (CH1)
Approx. 250 s
10
(CH2)
tDECON
Approx. 250 s
RE_DC1
(CH1 & CH2)
R1_CH2
R1_CH1
AIN_3
Performing 2-channel operation
RXERR_CH2
(CR22-B3)
RXBW_ER
(CR22-B1)
01
(CH1)
AIN_1
T1_CH1
Silent
WE_DC1
(CH1 & CH2)
Silent output/Init
Silent output/Init
tWAIT
AIN_1
T1_CH2
Silent
Activating 2-channel operation
Termination/Init
Termination/Init
Activating 2-channel operation
RXREQ_DC
(CR22-B5)
RXERR_CH1
(CR22-B2)
RXREQ_First
(CR22-B4)
FR1
(CR22-B0)
RXFLAG[CH2:CH1]
(CR5-[B1:B0])
Valid write section
MCU write
FR1B
(Pin output)
DEC OUT
(CH1+CH2)
CH2
20 ms
DEC_OUTON
INTB
(Pin output)
TXREQ_DC
(CR21-B5)
TXERR_CH1
(CR21-B2)
TXERR_CH2
(CR21-B3)
TXREQ_First
(CR21-B4)
FR0_CH2
(CR21-B1)
FR0_CH1
(CR21-B0)
Valid read section
CH1
CH2
INPUT SIGNAL
(Upper level +
lower level)
ENC
20 ms
SC_EN
DC_EN
FEDL7204-003-02
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Figure 35 Transmit/Receive Buffer Control Method at 2-Channel Operation (20 ms
frame, G.711) <When performing 2-channel operation from the beginning>
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Description of operation (Figure 35)
 Activating 2-channel operation
To activate 2-channel operation from the Speech CODEC termination state, set SC_EN and DC_EN to “1”
concurrently.
Encoder: Starts encoding of CH1 and CH2 signals within a maximum of 250 s after SC_EN = DC_EN = 1 is
set.
Decoder: Issues a receive data write request within a maximum of 250 s after SC_EN = DC_EN = 1 is set.
(Note)
When G.729.A is selected as the Speech CODEC coding format, the setting of SC_EN = DC_EN = 1 is
inhibited.
When the G.711 PLC function is enabled, the setting of SC_EN = DC_EN = 1 is inhibited.
 Performing 2-channel operation
 Transmit
 2-channel transmit request notification register (TXREQ_DC)
The 2-channel transmit request notification register (TXREQ_DC) is set to “1” while two transmit data read
requests are issued in one frame.
 Channel data read sequence
Two transmit data read requests are issued in one frame in the order of CH1  CH2.
However, when read operation from the MCU side does not terminate for the CH1 transmit data read request, a
read request for CH2 transmit data is not issued.
 Read sequence
After encoding processing for CH1 and CH2 of one frame terminates, an interrupt is generated by setting
FR0_CH1 = 1 and a CH1 transmit data read request is issued. Read CH1 transmit data (160 bytes) according
to the read request.
When CH1 transmit data read processing terminates, an interrupt is generated by setting FR0_CH2 = 1 and a
CH2 transmit data read request is issued.
Read CH2 transmit data (160 bytes) according to the read request.
In this operation state, the following signals are input to the encoder from CH1 and CH2.
Encoder input signal (CH1) = (Transmit data AIN_x input to Speech CODEC) + (CH2 receive data
Rx_CH2)
Encoder input signal (CH2) = (Transmit data AIN_x input to Speech CODEC) + (CH1 receive data
Rx_CH1)
 Valid read period RE_DCn(CH1 & CH2)
Terminate transmit data read processing from CH1 and CH2 within 18.0 ms after a CH1 transmit data read
request (FR0_CH1 = 1) is issued.
 Transmit error processing
If read processing from the MCU side does not terminate within the valid read period, an interrupt is generated
by setting the transmit error flag of the relevant channel (CH1: TXERR_CH1, CH2: TXERR_CH2) to “1”.
The transmit error is retained from the next valid read period until just before termination of the frame
processing for which transmit data read processing has been performed normally for the channel. Even if
data read processing does not terminate, the data in the transmit buffer is updated normally.
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 Receive
 2-channel receive request notification register (RXREQ_DC)
In this operation state, the MCU side is notified that two receive data write requests will be issued in one frame
by setting the 2-channel receive request notification register (RXREQ_DC) to “1”.
 Data write channel sequence
Since data can be written to the channels in any sequence, write receive data in either sequence of CH1  CH2
or CH2  CH1 in one frame.
(Note)
Do not write receive data of the same channel in one frame in such a manner as CH1  CH1 and CH2  CH2.
When receive data of the same channel is written in one frame, the receive data that is written by the first receive
request is decoded; however, the receive data that is written in the second receive request is discarded and an
interrupt is generated by setting a receive side invalid write error flag (RXBW_ERR) to “1”.
 Write procedure
This section describes the operation performed when receive data is written in the sequence of CH1  CH2.
Write CH1 receive data (160 bytes) according to the first receive data write request (FR1 = 1 & RXREQ_First
= 1).
Before starting write operation of CH1 receive data, notify the LSI that CH1 receive data will be written by
setting the receive data write channel notification register ((RXFLAG_[CH2: CH1]) to [0:1].
After termination of CH1 receive data write processing, the second receive data write request (FR1 = 1 &
RXREQ_First = 0) is issued.
Write CH2 receive data (160 bytes) according to the second write request. In this case also, notify the LSI
that CH2 receive data will be written by setting the receive data write channel notification register
((RXFLAG_[CH2:CH1]) to [1:0]., before starting CH2 receive data write processing. When a receive data
write request is issued, an interrupt is generated by setting FR1 to “1” regardless of the first or second request.
(Note)
The setting of RXFLAG_[CH2:CH1] = [1:1] or [0:0] is inhibited at notification of a receive data channel.
If RXFLAG_[CH2:CH1] = [1:1] or [0:0] is set, the receive data is discarded and an interrupt is generated by
setting the receive side invalid write error flag (RXBW_ERR) to “1”.
 Valid write period WE_DCn (CH1 & CH2)
WE_DC1 (CH1 & CH2)
There is no time restriction on the initial valid write period after activation of Speech CODEC (CH1 & CH2).
DEC_OUTON can be set to “1” after a lapse of the tWAIT time following completion of receive data write
processing for CH1 and CH2. Decoding output starts tDECON after DEC_OUTON is set to “1”. (*)
(tWAIT = 1ms, tDECON = 0 ms[initial value] ... Can be set within the range from 0.125 to 32 ms in the
internal data memory.)
WE_DC2 (CH1 & CH2)
The second valid write period is 13 ms.
WE_DCn (CH1 & CH2) n = 3, 4, 5, ...
The third valid write period is 18 ms.
(Note) (*)
It is inhibited to change the mode to a single-channel operation mode (SCN=1, DC_EN=0) before the decoding
output starting offset time elapses after DEC_OUTON is set to “1”.
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 Receive error processing
Terminate write processing of CH1 receive data and CH2 receive data within the valid write period.
If write processing from the MCU does not terminate within the valid write period, an interrupt is generated by
setting the receive error flag of the relevant channel (CH1: RXERR_CH1 or CH2: RXERR_CH2) to “1”.
The receive error is retained from the next valid write period until immediately before the termination of the
frame for which receive data of the channel has been written normally. When write processing of the receive
data of the channel is not performed, silent data is output.
When receive data of the same channel is written in one frame or the receive data channel notification is
invalid, an interrupt is generated by setting a receive side invalid write error flag (RXBW_ERR) to “1”.
RXBW_ERR is retained from the next valid write period until immediately before the termination of the frame
for which invalid receive data has no longer been written.
 Terminating 2-channel operation
To return from a 2-channel operation mode to a termination mode, set SC_EN = 0 and DC_EN = 0. The
encoder of Speech CODEC (CH1 & CH2) stops data write processing within a maximum of 250 s after
SC_EN = 0 and DC_EN = 0 are set.
(Note)
1. After SC_EN = 0 and DC_EN = 0 are set, RXFLAG_[CH2:CH1] are cleared to 00b automatically within a
maximum of 250 s.
2. A wait period of 10 ms or more is required after SC_EN = 0 is set until SC_EN = 1 is set again.
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Control Register Control Method
Figure 36 shows the control register control method.
This LSI incorporates control registers CR0-CR47 and GPCR0-GPCR8 for performing control. The LSI also
performs control by changing the DSP internal data memory that is built into the LSI using the following control
registers allocated in those control registers.
Internal data memory 1-word write control register (XDMWR)
Internal data memory 2-word write control register (XDMWR_2)
Internal data memory address and data setting registers (CR6-CR9)
See the INTERNAL DATA MEMORY ACCESS AND CONTROL METHOD that are described later for the
access method of the DSP internal data memory.
See Tables 5 to 9 for control register addresses.
The control registers are controlled with an 8-bit width of D7 to D0 regardless of the data width of 16 bits or 8
bits that is selected in the MCU interface data width selection register (BW_SEL). When a data bus is used in
16-bit access mode, input-output of D15-D8 depends on the write or read control of the control register. At
write processing, “1” or “0” is set in D15-D8 and at read processing, “1” is read.
A7-A0
Address
D7-D0
Data
Address
Data
CSB
WRB
RDB
Write
Read
Figure 36 Control Register Control Method
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Transmit/Receive Buffer Access Method
A. Frame mode (FRAME/DMA selection register FD_SEL = “0”)
Figure 37 shows the transmit buffer (TX Buffer) control timing and access method in frame mode.
When the transmit buffer storing compressed voice data on the transmit side (voice data compression side)
becomes full, a read request is issued to the MCU side by changing FR0B from “H” to “L”. Read data from
the data transmit buffer in the following timing. The transmit buffer read address is “80h”. FR0B
maintains “L” until the entire data in the transmit buffer is read.
FR0B
A7-A0
Address
D15-D0
Data 0
Address
Data n-1
CSB
WRB
RDB
(Transmit buffer full)
Address = 80h (fixed)
Number of data items: n words
(Transmit buffer empty)
Figure 37 Transmit Buffer Control Timing
Figure 38 shows the receive buffer (RX Buffer) control timing in frame mode. When the receive buffer
storing compressed voice data on the receive side (voice expansion side) becomes empty, a write request is
issued to the MCU side by setting FR1B from “H” to “L”. Write data in the receive buffer in the following
timing. The receive buffer write address is “81h”. FR1B maintains “L” until the receive buffer becomes
full.
FR1B
A7-A0
D15-D0
Address
Address
Data 0
Data n-1
CSB
WRB
RDB
(Receive buffer empty)
(Receive buffer full)
Address = 81h (fixed)
Number of data items: n words
Figure 38 Receive Buffer Control Timing
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B. DMA mode (FRAME/DMA selection register FD_SEL = “1”)
Figure 39 shows the transmit buffer control timing in DMA mode. When the transmit buffer for storing
compressed voice data on the transmit side (voice data compression side) becomes full, DMARQ0B goes to
“L” from “H”, thereby issuing a DMA request to the MCU side. After the DMA request is issued, when
DMAACK0B becomes “0” from “1”, acknowledgement is input. Then, when the fall of the read enable
signal (RDB = “1”  “0”) is accepted, DMARQ0B is automatically cleared (“L”  “H”). Read the data
from the transmit buffer in the following timing concurrently with acknowledgment input. DMARQ0B
continues issuing a DMA request until the entire data in the transmit buffer is read.
DMARQ0B
DMAACK0B
A7-A0
D15-D0
Address
Data 0
Address
Data n-1
WRB
RDB
(Transmit buffer full)
(Transmit buffer empty)
Address = 80h (fixed)
Number of data items: n words
Figure 39 Transmit Buffer Control Timing in DMA Mode
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Figure 40 shows the receive buffer control timing in DMA mode. When the receive buffer that stores
compressed voice data on the receive side (voice data expansion side) becomes empty, DMARQ1B goes to
“L” from “H”, thereby issuing a DMA request to the MCU side. When DMAACK1B is set from “1” to “0”
after the DMA request is issued, acknowledgment is input. Then, when the fall of the write enable signal
(WRB=”1”  “0”) is accepted, DMARQ1B is automatically cleared (“L”  “H”). Write data to the
receive buffer in the following timing concurrently with acknowledgement input. DMARQ1B continues
issuing a DMA request until the receive buffer becomes full.
DMARQ1B
DMAACK1B
A7-A0
Address
Address
D15-D0
Data 0
Data n-1
(Receive buffer empty)
(Receive buffer full)
WRB
RDB
Address = 81h (fixed)
Number of data items: n words
Figure 40 Receive Buffer Control Timing in DMA Mode
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PCM Interface
A. Example of PCM interface bit configuration
Figure 41 shows an example of PCM interface bit configuration.
 Long-frame synchronous mode
 G.711 (-law/A-law)
SYNC
BCLK
TS #1
Time Slot
PCMO
PCMI
TS #2
TS #3
TS #4
TS #n-1
TS #n
TS #1
7 65 4 32 1 0
7 654 3 210
7 6543210
76 5 432 10
76 543 210
7 6 54 321 0
 16-bit linear
SYNC
BCLK
TS #1
Time Slot
TS #2
TS #n/2
TS #1
PCMO
151413121110 9 8 7 6 5 4 3 2 1 0 151413121110 9 8 7 6 5 4 3 2 1 0
151413121110 9 8
PCMI
151413121110 9 8 7 6 5 4 3 2 1 0 151413121110 9 8 7 6 5 4 3 2 1 0
151413121110 9 8
 Short-frame synchronous mode
 G.711 (-law/A-law)
SYNC
BCLK
Time Slot
PCMO
PCMI
TS #1
TS #2
TS #3
TS #4
TS #n-1
TS #n
TS #1
7 65 4 32 10
7 6 5 4 3 2 10
765 43 21
76 5 43 210
7 654 32 10
7654 321
 16-bit linear
SYNC
BCLK
Time Slot
PCMO
PCMI
TS #1
TS #2
TS #n/2
TS #1
151413121110 9 8 7 6 5 4 3 2 1 0 151413121110 9 8 7 6 5 4 3 2 1 0
151413121110 9
151413121110 9 8 7 6 5 4 3 2 1 0 151413121110 9 8 7 6 5 4 3 2 1 0
151413121110 9
(*1) n is the value calculated from the following expression.
n = (BCLK frequency)  64 kHz Example: BCLK = 2.048 MHz n = 32
(*2) The number of bits of one time slot is changed automatically to the following, according to
the setting of the PCM coding format (PCM_SEL[1:0]).
16-bit linear setting: 16 bits
G.711 ( -law/A-law): 8 bits
(*3) The above diagram shows an example of timing for PCM data transmit/receive
processing by the two devices connected to the PCM interface, with the two using the
following:
16-bit linear setting: Time slot 1 and time slot 2
G.711 (-law/A-law) setting: Time slot 1 and time slot 3
Figure 41 Example of PCM Interface Bit Configuration
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B. Time slot assignment function
The PCM interface of this LSI is compatible with the serial transmission rate from 64 kHz to 2.048 MHz.
Therefore, by connecting multiple LSIs on the PCM interface, it is possible to logically achieve PCM data
multiplexing of up to 32 slots at G.711(-law/A-law) setting and up to 16 slots at 16-bit linear setting.
This LSI can be set up to 3 input time slots independently by using the following registers:
PCM input time slot selection register 1 (PCM_ITS1[4:0])
PCM input time slot selection register 2 (PCM_ITS2[4:0])
PCM input time slot selection register 3 (PCM_ITS3[4:0])
Also, 2 output time slots can be set independently by using the following registers:
PCM output time slot selection register 1(PCM_OTS1[4:0])
PCM output time slot selection register 2(PCM_OTS2[4:0])
Note that the following rules are applied for the setting of time slots.
(Note)
The number of bits of one time slot changes automatically according to the setting of the PCM coding format
(PCM_SELL [1:0])as follows.
16-bit linear setting: 16 bits
G.711 (-law/A-law) setting: 8 bits
Therefore, the maximum number of time slots that can be set will be as follows:
16-bit linear setting: n/2
G.711 (-law/A-law) setting: n
[n = (BCLK frequency)  64 kHz]
Setting a time slot number greater than the largest time slot number indicated above is inhibited.
C. Application example
By connecting multiple LSIs on the PCM interface, two-way communication or three-way communication is
enabled.
C-1. Two-way communication
Figure 42 shows an application example of two-way communication by transmitting/receiving PCM data
between two ML7204 devices connected on the PCM interface.
XI
Crystal unit
PCMO
XO
ML7204
#1
A-TEL1
+3.3V
PCMI
BCLK
CLKSEL
SYNC
CLKOUT
PCMO
XI
ML7204
#2
A-TEL2
<Time slot setting example>
 Output time slot selection register 1 (PCM_OTS1[4:0])
ML7204 #1: 00000b (output time slot “1”)
ML7204 #2: 00001b (output time slot “2”)
 Input time slot selection register 1 (PCM_ITS1[4:0])
ML7204 #1: 00001b (input time slot “2”)
ML7204 #2: 00000b (input time slot “1”)
Two-way communication can be achieved between A-TEL1 and A-TEL2 by
setting both the PCM output time slot 1 enable control register (PCM01_EN)
and the PCM input time slot 1 enable control register (PCMI1_EN) to “1” while
setting the time slots as shown above.
PCMI
BCLK
SYNC
CLKSEL
Figure 42 Example of Connection for Two-Way Communication via PCM I/F
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C-2. Three-way communication
Figure 43 shows an application example of three-way communication performed by transmitting/receiving
PCM data between three ML7204 devices connected on the PCM interface.
Connect to
crystal unit
XI
XO
PCMO
ML7204
#1
A-TEL1
+3.3V
PCMI
BCLK
CLKSEL
CLKOUT
SYNC
PCMO
XI
ML7204
#2
A-TEL2
PCMI
BCLK
CLKOUT
CLKSEL
SYNC
XI
PCMO
ML7204
#3
A-TEL3
<Time slot setting example>
 Output time slot selection register 1 (PCM_OTS1[4:0])
ML7204 #1: 00000b (output time slot “1”)
ML7204 #2: 00001b (output time slot “2”)
ML7204 #3: 00010b (output time slot “3”)
 Input time slot selection register 1 (PCM_ITS1[4:0])
ML7204 #1: 00001b (input time slot “2”)
ML7204 #2: 00000b (input time slot “1”)
ML7204 #3: 00000b (input time slot “1”)
 Input time slot selection register 2 (PCM_ITS2[4:0])
ML7204 #1: 00010b (input time slot “3”)
ML7204 #2: 00010b (input time slot “3”)
ML7204 #3: 00001b (input time slot “2”)
Three-way communication is enabled between A-TEL1, A-TEL2
and A-TEL3 by setting all of the following registers to “1” while
setting the time slots as indicated above.
PCM output time slot 1 enable control register (PCMO1_EN)
PCM input time slot 1 enable control register (PCMI1_EN)
PCM input time slot 2 enable control register (PCMI2_EN)
PCMI
BCLK
SYNC
CLKSEL
Figure 43 Example of Connection for Three-Way Communication via PCM I/F
(Note)
The maximum digital pin output load capacitance (recommended value) is 50pF. When the load connected to
the PCMO pin exceeds the recommended value, insertion of a buffer external to the LSI is recommended.
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Control Registers
Tables 5 shows the maps of control registers. CR6-CR9 are used for DSP internal data memory access.
changeable operation mode is indicated below each register name.
The
Table 5 Control Register Map (1 of 4)
Reg
Address
Name
A7-A0
CR0
00h
CR1
CR2
CR3
01h
02h
03h
CR4
04h
CR5
05h
Contents
B6
B5
AFEB
AFEA
_EN
_EN
/E
I/
XDMWR
B7
B4
B3
B2
#
#
#
I/
—
—
XDMRD
#
#
I/E
I/E
—
—
TGEN0
TGEN0
TGEN0
_RXAB
_RX
_CNT5
I/E
I/E
TGEN1
_RXAB
B1
B0
SYNC
OPE
_SEL
_STAT
—
I/
I/
#
#
#
I/E
—
—
—
TGEN0
TGEN0
TGEN0
TGEN0
TGEN0
_CNT4
_CNT3
_CNT2
_CNT1
_CNT0
I/E
I/E
I/E
I/E
I/E
I/E
TGEN1
TGEN1
TGEN1
TGEN1
TGEN1
TGEN1
TGEN1
_TX
_CNT5
_CNT4
_CNT3
_CNT2
_CNT1
_CNT0
I/E
I/E
I/E
I/E
I/E
I/E
I/E
I/E
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
READY
#
#
#
#
#
RXFLAG
RXFLAG
_CH2
_CH1
—
—
—
—
—
—
I/E
I/E
A15/D15
A14/D14
SPDN
XDMWR
_2
R/W
R/W
R/W
R/W
R/W
/
R/W
Internal data memory access (high-order address/high-order data)
CR6
06h
A13/D13
A12/D12
A11/D11
A8/D8
/W
A1/D1
A0/D0
/W
D9
D8
R/W
D2
D1
D0
R/W
VFRO1
VFRO0
_SEL
_SEL
A10/D10
A9/D9
I/E
Internal data memory access (low-order access/low-order data)
CR7
07h
A7/D7
A6/D6
A5/D5
A4/D4
A3/D3
A2/D2
I/E
Internal data memory access (high-order data)
CR8
08h
D15
D14
D13
D12
D11
D10
I/E
Internal data memory access (low-order data)
CR9
09h
D7
D6
D5
D4
D3
I/E
CR10
CR11
0Ah
0Bh
#
#
#
#
#
—
—
—
—
—
I/E
I/E
—
PCMI3
PCMO2
PCMI2
PCMI1
PCMO1
_EN
_EN
_EN
_EN
_EN
/E
/E
/E
/E
/E
PCM
PCM
_SEL1
_SEL0
I/
I/
#
—
#
R/W
R/W
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Table 5 Control Register Map (2 of 4)
Reg
Name
Address
A7-A0
B7
B6
B5
B4
B3
B2
B1
B0
CR12
0Ch
$
$
$
$
$
$
$
$
CR13
0Dh
FD_
SEL
I/
BW_
SEL
I/
TXSC
_SEL1
I/E
TXSC
_SEL0
I/E
TXBUF
_TIM
I/
RXSC
_SEL1
I/E
RXSC
_SEL0
I/E
CR14
0Eh
#
#
#
#
#
#
#
RXBUF
_TIM
I/
MGEN_
FRFLAG
—
—
—
—
—
—
—
—
$
$
$
$
$
$
$
$
#
#
#
#
#
—
—
—
—
—
FDET
_OER
/E
FDET
_FER
/E
#
#
#
#
#
#
#
—
—
—
—
—
—
—
#
#
#
#
#
#
#
FDET
_RQ
/E
FGEN
_FLAG
I/E
TMOVF
—
DSP
_ERR
—
—
—
#
#
—
—
INT
DP_DET
#
—
TX_SC
FLAG
—
RX_SC
FLAG
—
—
TX_BT
FLAG
—
RX_BT
FLAG
—
—
TGEN0_
EXFLAG
—
DTMF_
CODE1
—
FR0_
CH2
—
RXBW
_ERR
—
—
DTMF_
CODE0
—
FR0_
CH1
—
DC_EN
#
#
#
I/E
I/E
—
TONE0_
DET
—
DTMF_
CODE3
—
TXERR
_CH2
—
RXERR
_CH2
—
G711_
PLCEN
I/E
—
TGEN1_
EXFLAG
—
DTMF_
CODE2
—
TXERR
_CH1
—
RXERR
_CH1
—
SC_EN
—
TXREQ
_DC
—
RXREQ_
DC
—
DEC_
OUTON
/E
—
TONE1_
DET
—
DTMF
_DET
—
TXREQ
_First
—
RXREQ_
First
—
ACTCH
_FLAG
/E
—
#
#
#
#
#
#
—
—
—
—
—
—
—
PCM_
TXEN2
I/E
—
PCM_
RXEN2
I/E
CR15
0Fh
CR16
10h
CR17
CR18
CR19
CR20
11h
12h
13h
14h
CR21
15h
CR22
16h
CR23
CR24
17h
18h
Contents
R/W
/
R/W
/
/
R/W
R/W
R/W
/E
#
FR1
R/
R/
R/
R/
—
R/W
R/W
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Table 5 Control Register Map (3 of 4)
Reg
Name
Address
Contents
A7-A0
B7
B6
B5
B4
B3
B2
B1
B0
CR25
19h
FDET
_D7
FDET
_D6
FDET
_D5
FDET
_D4
FDET
_D3
FDET
_D2
FDET
_D1
FDET
_D0
R/
DPDET_
DATA3
DPDET_
DATA2
DPDET_
DATA1
DPDET_
DATA0
R/
FGEN
_D3
FGEN
_D2
FGEN
_D1
FGEN
_D0
R/W
TDET0
_EN
I/E
DPGEN_
DATA3
I/E
TDET1_
SEL1
I/E
CODEC
A_TXEN
I/E
PCM_
TXEN1
I/E
PCM_
ITS1[3]
I/E
PCM_
ITS2[3]
I/E
PCM_
OTS1[3]
I/E
PCM_
ITS3[3]
I/E
DTMF
_EN
I/E
DPGEN_
DATA2
I/E
TDET1_
SEL0
I/E
CODEC
A_RXEN
I/E
PCM_
TXEN0
I/E
PCM_
ITS1[2]
I/E
PCM_
ITS2[2]
I/E
PCM_
OTS1[2]
I/E
PCM_
ITS3[2]
I/E
EC_EN
#
I/E
DPGEN_
DATA1
I/E
TDET0_
SEL1
I/E
SC_
TXEN
I/E
PCM_
RXEN1
I/E
PCM_
ITS1[1]
I/E
PCM_
ITS2[1]
I/E
PCM_
OTS1[1]
I/E
PCM_
ITS3[1]
I/E
—
DPGEN_
DATA0
I/E
TDET0_
SEL0
I/E
SC_
RXEN
I/E
PCM_
RXEN0
I/E
PCM_
ITS1[0]
I/E
PCM_
ITS2[0]
I/E
PCM_
OTS1[0]
I/E
PCM_
ITS3[0]
I/E
R/W
CR26
1Ah
DPDET_
DATA7
DPDET_
DATA6
DPDET_
DATA5
DPDET_
DATA4
—
CR27
1Bh
FGEN
_D7
FGEN
_D6
FGEN
_D5
FGEN
_D4
I/E
CR28
CR29
1Ch
1Dh
—
FGEN
_EN
I/E
DPGEN_
EN
I/E
FDET
_SEL
I/E
LPEN1
LPEN0
I/E
I/E
#
#
—
—
—
CODEC
B_TXEN
I/E
RXGEN
A_EN
I/E
#
#
#
—
—
—
#
#
#
—
—
—
#
#
#
—
—
—
#
#
#
—
—
—
TDET1
_EN
I/E
DPGEN_
PPS
I/E
DTMF
_SEL
I/E
CODEC
B_RXEN
I/E
RXGEN
B_EN
I/E
PCM_
ITS1[4]
I/E
PCM_
ITS2[4]
I/E
PCM_
OTS1[4]
I/E
PCM_
ITS3[4]
I/E
$
$
$
$
$
$
$
$
/
#
#
#
—
—
PCM_
OTS2[3]
I/E
PCM_
OTS2[2]
I/E
PCM_
OTS2[1]
I/E
PCM_
OTS2[0]
I/E
R/W
—
PCM_
OTS2[4]
I/E
$
$
$
$
$
$
$
$
/
#
#
#
#
#
#
—
—
—
—
—
DPDET
_EN
I/E
R/W
—
DPDET
_POL
I/
$
$
$
$
$
$
$
$
/
$
$
$
$
$
$
$
$
/
FDET
_EN
I/E
#
—
CR30
CR31
CR32
CR33
CR34
CR35
CR36
1Eh
1Fh
20h
21h
22h
23h
24h
CR37
25h
CR38
26h
CR39
to
CR42
27h
to
2Ah
CR43
2Bh
CR44
to
CR47
—
2Ch
to
2Fh
30h
to
3Fh
#
TIM_EN
I/E
DPGEN_
POL
I/
#
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Table 5 Control Register Map (4 of 4)
Reg
Name
Address
A7-A0
GP
CR0
40h
GP
CR1
41h
GP
CR2
42h
GP
CR3
43h
GP
CR4
44h
GP
CR5
45h
GP
CR6
46h
GP
CR7
47h
GP
CR8
48h
—
—
Contents
B7
#
—
#
#
—
49h
to
7Fh
82h
to
FFh
B6
B5
B4
B3
B2
B1
B0
GPMA
[6]
I/E
GPDA
[6]
I/E
GPFA
[6]
I/E
GPMA
[5]
I/E
GPDA
[5]
I/E
GPFA
[5]
I/E
GPMA
[4]
I/E
GPDA
[4]
I/E
GPFA
[4]
I/E
GPMA
[3]
I/E
GPDA
[3]
I/E
GPMA
[2]
I/E
GPDA
[2]
I/E
GPFA
[2]
I/E
GPMA
[1]
I/E
GPDA
[1]
I/E
GPMA
[0]
I/E
GPDA
[0]
I/E
GPFA
[0]
I/E
#
—
#
—
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
$
$
$
$
$
$
$
$
/
$
$
$
$
$
$
$
$
/
R/W
R/W
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Notation:
Register name
#
: Reserved bit. Do not change the initial value (“0”).
$
: Access inhibit bit. Do not make R/W access to this bit.
Changeability mode
I/E : Can be changed during initial mode or operating mode
I/
: Can be changed during initial mode only
/E
: Can be changed during operating mode only
R/W
R/W : Read and write processing are enabled
/W : Write only
R/ : Read only
/
: Access inhibit
(Note)
When any of the following control registers is set during operation, maintain the state for 250 s or more
since read processing is performed synchronized with the SYNC signal (8 kHz).
CR1-CR3, CR5, CR11, CR13, CR16-CR18, CR23, CR24, CR27-CR36, CR38, and CR43
See the INTERNAL DATA MEMORY ACCESS AND CONTROL METHOD for the method of setting
the following control registers.
CR6, CR7, CR8, and CR9
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(1) CR0
CR0
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
SPDN
AFEB
_EN
AFEA
_EN
#
#
#
SYNC
_SEL
OPE
_STAT
/E
I/
I/
—
—
—
I/
I/
0
0
0
0
0
0
0
0
R/W
R/W
B7: Software power-down reset control register
0: Normal operating mode
1: Power-down reset
This LSI can be put into a power-down reset state by setting this bit to “1” for 200 ns or more.
At power-down reset, the contents of the control register and internal data memory are cleared
automatically. Power-down reset can be released by setting “0” after setting “1”.
B6: Analog front end power-down control register on the CODEC_B side
0: Normal operating state
1: Power-down state (excluding AVREF)
Power-down can be applied to the analog front end on the CODEC_B side by setting this bit to “1”.
It is recommended to set this bit to “1” when the analog front end on the CODEC_B side is not used.
When setting this bit to “1”, set output of VFRO1 to the AVREF side (“0”) using the VFRO1 selection
register (VFRO1_SEL).
B5: Analog front end power-down control register on the CODEC_A side
0: Normal operating state
1: Power-down state (excluding AVREF)
Power-down can be applied to the analog front end on the CODEC_A side by setting this bit to “1”.
It is recommended to set this bit to “1” when the analog front end on the CODEC_A side is not used.
When setting this bit to “1”, set output of VFRO0 to the AVREF side (“0”) using the VFRO0 selection
register (VFRO0_SEL).
B4-B2: Reserved bit. Change of the initial value is inhibited.
B1: SYNC frame control register
0: Long frame synchronous signal
1: Short frame synchronous signal
B0: Operation start control register
0: Operation hold
1: Operation start
After release of power-down reset, the LSI enters an initial mode. In initial mode, control register
settings and internal data memory contents can be changed. Start changing the control registers or the
contents of the internal memory after reading the initial mode display register (READY) continuously and
detecting “1”.
When this bit is set to “1” after completion of changing the control register settings or internal data
memory write processing, the READY register is set to “0”, returning the mode to a normal operation
mode.
To change the control register settings or the contents of the internal data memory again after setting this
bit to “1”, change the mode to the normal operating mode. Figure 44 shows the flowchart in initial
mode.
See the internal data memory change method described later for the method of changing the internal data
memory.
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PDNB = 0 or SPDN = 1
Power-down state
PDNB = 1 & SPDN = 0
Power-down reset
released
Wait for approx.
200 ms
Initial mode
READY = 1
Change the internal data
memory contents
Change the control register settings
tAVREF
or more
Initial mode
OPE_STAT = 1
LSI internal section initialized
Control register and internal
data memory access inhibit
period
READY = 0
Normal operation started
Setting externally
Normal operation mode
LSI internal automatic processing
Figure 44 Flowchart in Initial Mode
(Note)
A wait period of the AVERF rise time (tAVREF) or more is required from release of power-down reset
by PDNB or software power-down reset by SPDN to the setting of OPE_STAT to “1”. See Figure 1 for
the AVERF rise time (tAVREF).
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(2) CR1
CR1
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
XDMWR
XDMRD
#
#
XDMWR
_2
#
#
#
I/E
I/E
—
—
I/E
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
B7: Internal data memory one-word write control register
0: Stops write processing
1: Writes one word
Use this register for writing one word to the address areas that are distributed in the internal data memory.
Write the data that is set in CR8 and CR9 (D15 to D0) to the addresses that are set in CR6 and CR7 (A15
to A0). At termination of write processing, this bit is automatically cleared to “0”. When setting data
continuously, check that this bit is set to “0” before setting.
See the INTERNAL DATA MEMORY ACCESS AND CONTROL METHOD described later for the
details of the control method.
B6: Internal data memory read control register
0: Stops read processing
1: Reads data
Use this register for reading the internal memory data by setting the internal memory address into CR6
and CR7 (A15 to A0). The data is stored into CR8 and CR9 (D15 to D0). At termination of read
processing, this bit is automatically cleared to “0”. When reading data continuously, check this bit is set
to “0” before reading data.
See the INTERNAL DATA MEMORY ACCESS AND CONTROL METHOD described later for the
details of the control method.
B5-B4: Reserved bits Change of the initial values is inhibited
B3: Internal data memory two-word write control register
0: Stops write processing
1: Writes two words
Use this register to write multiple words in continuous address areas of the internal data memory.
See the INTERNAL DATA MEMORY ACCESS AND CONTROL METHOD described later for the
details of the control method.
B2-B0: Reserved bits Change of the initial values is inhibited
(Note)
One-word write control, two-word write control and read control cannot be performed simultaneously for the
internal data memory. Namely, Only one bit of CR1 can be set to “1” at a time.
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(3) CR2
CR2
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
TGEN0
_RXAB
TGEN0
_RX
TGEN0
_CNT5
TGEN0
_CNT4
TGEN0
_CNT3
TGEN0
_CNT2
TGEN0
_CNT1
TGEN0
_CNT0
R/W
I/E
0
0
0
0
R/W
0
0
0
0
B7: TGEN0 Output control register on the RXAB side
0: Stops output
1: Outputs tone to the RXGENA/RXGENB side
(Note)
Connection/non-connection control is enabled for output paths to RXGENA and RXGENB using the
RXGENA_EN connection path control register (RXGENA_EN) and the RXGENB_EN connection path
control register (RXGENB_EN). Non-connection is set as the initial value.
B6: TGEN0 Output control register on the RX side
0: Stops output
1: Outputs tone to the RXGEN side
See the various generator paths in the block diagram that is shown earlier in this document for RXGENA,
RXGENB, and RXGEN.
B5: Addition and multiplication control register for TONE A/B
0: Addition (Adds output of TONE A and TONE B)
1: Multiplication (Multiplies output of TONE A and TONE B)
B4: Output control register of TONE A/B
0: Single output
Stops by outputting the signal for the time period created by adding TIM_M0 and TIM_M1.
After stopping, this register is automatically cleared within the LSI.
1: Continuous output
Outputs repeatedly the signal that is controlled by the time created by adding TIM_M0 and
TIM_M1.
Set 00h to this register when stopping signal output.
(Note)
Do not set any value other than 00h since only 00h is permitted as the value that is written to this register
from continuous output.
At single output, make the next setting after checking that this register is set to 00h.
When outputting signals again after termination of continuous output, wait for a period of “FADE OUT
time + 250 s” or more before starting output.
B3-B2: Output control registers of TONE A
00: Tone is not output.
01: Stops output to the M0 section and outputs tone to the M1 section.
10: Outputs tone to the M0 section and stops output to the M1 section.
11: Outputs tone to the M0 and M1 sections.
B1-B0: Output control registers of TONE B
00: Tone is not output.
01: Stops output to the M0 section and outputs tone to the M1 section.
10: Outputs tone to the M0 section and stops output to the M1 section.
11: Outputs tone to the M0 and M1 sections.
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(Note)
When output control of TONE A and TONE B is set exclusively and the addition result is output, TONE
A and TONE B can be output alternately. However, as each signal phase is independent, the waveform
after addition is non-continuous.
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(4) CR3
CR3
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
TGEN1
_RXAB
TGEN1
_TX
TGEN1
_CNT5
TGEN1
_CNT4
TGEN1
_CNT3
TGEN1
_CNT2
TGEN1
_CNT1
TGEN1
_CNT0
R/W
I/E
0
0
0
0
R/W
0
0
0
0
B7: TGEN1 Output control register on the RXAB side
0: Stops output
1: Outputs tone to the RXGENA/RXGENB side
(Note)
Connection/non-connection control is enabled for output paths to RXGENA and RXGENB using the
RXGENA_EN connection path control register (RXGENA_EN) and the RXGENB_EN connection path
control register (RXGENB_EN). Non-connection is set as the initial value.
B6: TGEN1 Output control register on the TX side
0: Stops output
1: Outputs tone to the TXGEN side
See the various generator paths in the block diagram that is shown earlier in this document for RXGENA,
RXGENB, and TXGEN.
B5: Addition and multiplication control register for TONE C/D
0: Addition (Adds output of TONE C and TONE D)
1: Multiplication (Multiplies output of TONE C and TONE D)
B4: Output control register of TONE C/D
0: Single output
Stops by outputting the signal for the time period created by adding TIM_M0 and TIM_M1.
After stopping, this register is automatically cleared within the LSI.
1: Continuous output
Outputs repeatedly the signal that is controlled by the time created by adding TIM_M0 and TIM_M1.
Set 00h to this register when stopping signal output.
(Note)
Do not set any value other than 00h since only 00h is permitted as the value that is written to this register
from continuous output.
At single output, make the next setting after checking that this register is set to 00h.
When outputting signals again after termination of continuous output, wait for a period of “FADE OUT
time + 250 s” or more before starting output.
B3-B2: Output control registers of TONE C
00: Tone is not output.
01: Stops output to the M0 section and outputs tone to the M1 section.
10: Outputs tone to the M0 section and stops output to the M1 section.
11: Outputs tone to the M0 and M1 sections.
B1-B0: Output control registers of TONE D
00: Tone is not output.
01: Stops output to the M0 section and outputs tone to the M1 section.
10: Outputs tone to the M0 section and stops output to the M1 section.
11: Outputs tone to the M0 and M1 sections.
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(Note)
When output control of TONE C and TONE D is set exclusively and the addition result is output, TONE
C and TONE D can be output alternately. However, as each signal phase is independent, the waveform
after addition is non-continuous.
Figure 45 shows the block diagram of the tone generation sections (TONE_GEN0 and TONE_GEN1).
Since the same tone generation method is applied by TONE_GEN0 and TONE_GEN1, TONE_GEN0 is used as
the examples for the tone output control method in Figure 46 and tone output control parameters in Figures 47
and 48.
[TONE_GEN0]
TGEN0_GAIN_A
TONE_A
RXGENA/RXGENB
TGEN0_RXABGAIN_
TOTAL
TGEN0_FREQ_A
TONE_B
TGEN0_FREQ_B
[TONE_GEN1]
TGEN0_GAIN_B
TGEN1_GAIN_C
TONE_C
TGEN0_RXGAIN_
TOTAL
TGEN0_CNT5
RXGEN
RXGENA/RXGENB
TGEN1_RXABGAIN_
TOTAL
TGEN1_FREQ_C
TONE_D
TGEN1_FREQ_D
TGEN1_GAIN_D
TGEN1_TXGAIN_
TOTAL
TGEN1_CNT5
TXGEN
Figure 45 Block Diagram of Tone Generation Sections
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Figure 46 Tone Output Control Method (TONE_GEN0)
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FREQ
Single output
GAIN
TIM_M0
M0 ON
TIM_M1
M1 ON
FREQ
TIM_M0
M0 ON
TIM_M1
M1 OFF
FREQ
TIM_M0
M0 OFF
TIM_M1
M1 ON
FREQ
Continuous
output
GAIN
TIM_M0
TIM_M1
TIM_M0
TIM_M1
M0 OFF
M1 ON
M0 OFF
M1 ON
Setting of single output is output continuously.
Figure 47 Tone Output Control Parameters (TONE_GEN0/TGEN0_FADE_CONT OFF)
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TIM_M0
TIM_M1
Single output GAIN
F-i
F-i
M0 ON
F-o
M1 ON
F-o
M0 ON
M1 OFF
F-i
Continuous
output
M0 OFF
F-o
M1 ON
TIM_M0
TIM_M1
*”F-i” and “F-o” are the times required for
“fade-in” and “fade-out”. The values are
determined by the parameters that are
described later.
TIM_M0
TIM_M1
GAIN
F-i
M0 OFF
F-o
M1 ON
F-i
M0 OFF
F-o
M1 ON
The setting of single output is output repeatedly.
CR2="00h"
GAIN
F-i
M0 OFF
F-o
M1 ON
F-i
M0 OFF
F-o
M1 ON
The setting of single output is output repeatedly.
(When CR2 = "00h" is set halfway)
GAIN_B
GAIN_A
F-i
F-o
F-i
F-o
F-i
F-o
F-i
F-o
M0 ON
M1 ON
M0 ON
M1 ON
TONE_A
TONE_B
TONE_A
TONE_B
The setting of single output is output repeatedly.
(Alternate output of TONE_A and TONE_B)
Figure 48 Tone Output Control Parameters (TONE_GEN0/TGEN0_FADE_CONT ON)
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(5) CR4
CR4
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
B3
B2
B1
B0
RXFLAG
_CH1
R/W
/
B7-B0: Reserved bits Change of the initial values is inhibited.
(6) CR5
B7
CR5
Change enable
mode
Initial value
B6
B5
B4
READY
#
#
#
#
#
RXFLAG
_CH2
—
—
—
—
—
—
I/E
I/E
0
0
0
0
0
0
0
0
R/W
R/W
B7: Initial mode display register
0: Mode other than initial mode
1: Initial mode
After release of power-down reset, this LSI enters an initial mode. In initial mode, this bit is set to “1”.
B6-B1: Reserved bits Change of the initial values is inhibited.
B1-B0: Receive data write channel notification register
A receive request is issued twice in one frame during 2-channel receive request processing
(RXREQ_DC=1).
Write receive data of channel 1 or channel 2 for each receive request.
Since data can be written in any sequence, notify this LSI of the channel of the receive data by setting
RXFLAG_[CH2:CH1] to the following before writing receive data.
RXFLAG_[CH2:CH1] = [1:0]
: Channel 2 receive data write notification
RXFLAG_[CH2:CH1] = [0:1]
: Channel 1 receive data write notification
See Figures 32 to 35 for the detailed control methods.
(7) CR6
CR6
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
A15/D15
A14/D14
A13/D13
A12/D12
A11/D11
A10/D10
A9/D9
A8/D8
R/W
/W
I/E
0 (*)
0 (*)
0 (*)
0 (*)
0 (*)
0 (*)
0 (*)
0 (*)
B7-B0: Internal data memory high-order address/high-order data setting register
This is an internal data memory high-order address/high-order data setting register.
See the section of INTERNAL DATA MEMORY ACCESS AND CONTROL METHOD for the write
method.
(Note)*
Although the initial value of CR6 is 00h, it is set to 72h automatically before the initial mode starts.
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(8) CR7
CR7
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
A7/D7
A6/D6
A5/D5
A4/D4
A3/D3
A2/D2
A1/D1
A0/D0
R/W
/W
I/E
0 (*)
0 (*)
0 (*)
0 (*)
0 (*)
0 (*)
0 (*)
0 (*)
B7-B0: Internal data memory low-order address/low-order data setting register
This is an internal data memory low-order address/low-order data setting register.
See the section of INTERNAL DATA MEMORY ACCESS AND CONTROL METHOD for the write
method.
(Note)*
Although the initial value of CR7 is 00h, it is set to 04h automatically before the initial mode starts.
At the start of initial mode, the LSI type (ML7204) can be checked by reading the values of CR6 and
CR7.
(9) CR8
CR8
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
I/E
0 (*)
0 (*)
0 (*)
0 (*)
0 (*)
0 (*)
0 (*)
0 (*)
B7-B0: Internal data memory high-order data setting register
This is an internal data memory high-order data setting register.
See the section of INTERNAL DATA MEMORY ACCESS AND CONTROL METHOD for the write
and read method.
(Note)*
Although the initial value of CR8 is 00h, it is set to 01h automatically before the initial mode starts.
(10) CR9
CR9
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
I/E
0 (*)
0 (*)
0 (*)
0 (*)
R/W
0 (*)
0 (*)
0 (*)
0 (*)
B7-B0: Internal data memory low-order data setting register
This is an internal data memory low-order data setting register.
See the section of INTERNAL DATA MEMORY ACCESS AND CONTROL METHOD for the write
and read method.
(Note)*
Although the initial value of CR9 is 00h, it is set to 03h automatically before the initial mode starts. At the
start of initial mode, the code type (-003) can be checked by reading the value of CR9.
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(11) CR10
CR10
Change enable
mode
Initial value
B7-B3: Reserved bits
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
#
#
VFRO1
_SEL
VFRO0
_SEL
#
—
—
—
—
—
I/E
I/E
—
0
0
0
0
0
0
0
0
R/W
R/W
Change of the initial values is inhibited.
B2: VFRO1 selection register
0: AVREF (outputs about 1.4 V)
1: Voice output on the receive side
B1: VFRO0 selection register
0: AVREF (outputs about 1.4 V)
1: Voice output on the receive side
B0: Reserved bits Change of the initial values is inhibited.
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(12) CR11
CR11
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
PCM
_SEL1
PCM
_SEL0
#
PCMI3
_EN
PCMO2
_EN
PCMI2
_EN
PCMI1
_EN
PCMO1
_EN
I/
I/
—
/E
/E
/E
/E
/E
0
0
0
0
0
0
0
0
R/W
R/W
B7 and B6: PCM I/F coding format selection control register
These are PCM I/F coding format selection bits.
( 0 , 0 ): 16-bit linear (two’s complement format)
( 0 , 1 ): G.711(-law)
( 1 , 0 ): Inhibited
( 1 , 1 ): G.711(A-law)
(Note) When G.711 (A-law) is selected by setting the PCM I/F coding format selection control register
(PCM_SEL[1:0]) to (1,1), decrease your target gain setting of a very next gain control following
G.711 decoder such as RXGAIN_ITS1 by 18.6dB, and increase your target gain setting of the
following gain control such as RXGAIN_PCM0 by 18.6dB.
Examples in a case where the PCM input time slot 1 enable control register (PCMI1_EN)=”1”
and the VFRO0-pin is assigned as an LSI output pin for PCMI-pin input signals are shown in a
table below.
When a tone detector (TONE_DET0 and/or TONE_DET1) located between the concerned two
gain controls is enabled, adjust the detection level accordingly.
Gain Control
RXGAIN_ITS1
RXGAIN_PCM0
Your Target (example)
0008h (0dB)
0039h (-7.03dB)
001Ah (-13.8dB)
000Bh (-21.3dB)
Recommendation
000Fh (-18.6dB)
01E6h (+11.60dB)
00DEh (+4.78dB)
005Eh (-2.69dB)
Remarks
B5: Reserved bits Change of the initial values is inhibited.
B4: PCM input time slot selection 3 enable control register
0: Stops PCM input time slot selection 3
1: Activates PCM input time slot selection 3
When this bit is set to “1”, the PCM data in the time slot position that has been set in the PCM input time
slot selection register 3 (PCM_ITS3[4:0]) is fetched and decoding processing is performed with the
coding format selected in the PCM I/F coding format selection control register (PCM_SEL[1:0]). PCM
data fetching starts from the frame following the frame where this bit has been detected having been set to
“1”. Figure 50 shows the PCM input timing.
(Note) When G.711 (A-law) is selected by setting the PCM I/F coding format selection control register
(PCM_SEL[1:0]) to (1,1), it’s recommended to set this PCM input time slot 3 enable control
register (PCMI3_EN) to “0” (Stops PCM input time slot selection 3).
B3: PCM output time slot selection 2 enable control register
0: Stops PCM output time slot selection 2
1: Activates PCM output time slot selection 2
When this bit is set to “1”, the PCM data that was encoded with the coding format selected by the PCM
I/F coding format selection control register (PCM_SEL[1:0]) is output to the time slot position that has
been set in the PCM output time slot selection register 2 (PCM_OTS2[4:0]). PCM data encoding starts
from the frame following the frame where this bit has been detected having been set to “1”. Figure 51
shows the PCM output timing.
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B2: PCM input time slot selection 2 enable control register
0: Stops PCM input time slot selection 2
1: Activates PCM input time slot selection 2
When this bit is set to “1”, the PCM data in the time slot position that has been set in the PCM input time
slot selection register 2 (PCM_ITS2[4:0]) is fetched and decoding processing is performed with the
coding format selected in the PCM I/F coding format selection control register (PCM_SEL[1:0]). PCM
data fetching starts from the frame following the frame where this bit has been detected having been set to
“1”. Figure 50 shows the PCM input timing.
B1: PCM input time slot selection 1 enable control register
0: Stops PCM input time slot selection 1
1: Activates PCM input time slot selection 1
When this bit is set to “1”, the PCM data in the time slot position that has been set in the PCM input time
slot selection register 1 (PCM_ITS1[4:0]) is fetched and decoding processing is performed with the
coding format selected in the PCM I/F coding format selection control register (PCM_SEL[1:0]). PCM
data fetching starts from the frame following the frame where this bit has been detected having been set to
“1”. Figure 50 shows the PCM input timing.
When both of B2 and B1 are set to “1”, each decoding result is added and output on the speech path.
B0: PCM output time slot selection 1 enable control register
0: Stops PCM output time slot selection 1
1: Activates PCM output time slot selection 1
When this bit is set to “1”, the PCM data that was encoded with the coding format selected by the PCM
I/F coding format selection control register (PCM_SEL[1:0]) is output to the time slot position that has
been set in the PCM output time slot selection register 1 (PCM_OTS1[4:0]). PCM data encoding starts
from the frame following the frame where this bit has been detected having been set to “1”. Figure 51
shows the PCM output timing.
SYNC
00000b
PCM_ITSn
[4:0]
PCMIn_EN
1
PCMI
Stop (silent output)
DECODE
1
DEC1 (silent output)
1
DEC2
1
DEC4
DEC3
Stop (silent output)
Figure 50 PCM Input Timing
SYNC
PCM_OTS1
[4:0]
00000b
PCMO1_EN
Silent output
1
Hi-Z
PCM0
ENCODE
Stop
ENC1
Hi-Z
1
1
ENC2
1
ENC3
ENC4
Stop
(Note) The silent output to the PCM0 pin or the start of ENCODE may be delayed by 1 sync depending on the timing of setting PMC0n_EN to “1”.
Figure 51 PCM Output Timing
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(Note)
The frame following the frame where PCMO1_EN or PCMO2_EN has been detected having been set to
“1” outputs the following silent data according to the coding format selected in PCM_SEL[1:0].
16-bit linear (two’s complement format)
: 0000h
G.711(-law)
: FFh
G.711(A-law)
: D5h
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(13) CR12
CR12
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
$
$
$
$
$
$
$
$
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R/W
/
B7-B0: Reserved bits Access is inhibited.
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(14) CR13
CR13
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
FD_
SEL
BW_
SEL
TXSC
_SEL1
TXSC
_SEL0
TXBUF
_TIM
RXSC
_SEL1
RXSC
_SEL0
RXBUF
_TIM
I/
I/
I/E
I/E
I/
I/E
I/E
I/
0
0
0
0
0
0
0
0
R/W
R/W
B7: FRAME/DMA selection register
0: FRAME access
1: DMA slave interface access
Select a transmit buffer or a receive buffer access method. Frame access is set as the initial value.
B6: MCU interface data width selection register
0: 16-bit data width interface
1: 8-bit data width interface
Select a data path width to a transmit buffer or a receive buffer. The initial value is 16 bits.
When selecting a 8-bit data width, fix D15 to D18 to “1” or “0”.
B5-B4: Speech CODEC selection register on the transmit side
( 0 , 0 ): G.729.A
( 0 , 1 ): G.711 (-law)
( 1 , 0 ): Inhibited
( 1 , 1 ): G.711 (A-law)
B3: Transmit buffering time selection register
0: 10 ms
1: 20 ms
Select a buffering time of a transmit buffer. The initial value is 10 ms.
B2-B1: Speech CODEC selection register on the receive side
( 0 , 0 ): G.729.A
( 0 , 1 ): G.711 (-law)
( 1 , 0 ): Inhibited
( 1 , 1 ): G.711 (A-law)
(Note) When G.711 (A-law) is selected by setting the PCM I/F coding format selection control register
(PCM_SEL[1:0]) to (1,1), decrease your target gain setting of a very next gain control following
G.711 decoder such as RXGAIN_ITS1 by 18.6dB, and increase your target gain setting of the
following gain control such as RXGAIN_PCM0 by 18.6dB.
Examples in a case where the PCM input time slot 1 enable control register (PCMI1_EN)=”1”
and the VFRO0-pin is assigned as an LSI output pin for PCMI-pin input signals are shown in a
table below.
When a tone detector (TONE_DET0 and/or TONE_DET1) located between the concerned two
gain controls is enabled, adjust the detection level accordingly.
Gain Control
RXGAIN_ITS1
RXGAIN_PCM0
Your Target (example)
0008h (0dB)
0039h (-7.03dB)
001Ah (-13.8dB)
000Bh (-21.3dB)
Recommendation
000Fh (-18.6dB)
01E6h (+11.60dB)
00DEh (+4.78dB)
005Eh (-2.69dB)
Remarks
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B0: Receive buffering time selection register
0: 10 ms
1: 20 ms
Select a buffering time of a receive buffer. The initial value is 10 ms.
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(15) CR14
CR14
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
R/W
/
B7-B0: Reserved bits Change of the initial values is inhibited.
(16) CR15
CR15
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
$
$
$
$
$
$
$
$
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R/W
/
B7-B0: Reserved bits Access is inhibited.
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(17) CR16
CR16
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
#
#
FDET
_OER
FDET
_FER
FDET
_RQ
—
—
—
—
—
/E
/E
/E
0
0
0
0
0
0
0
0
R/W
R/W
B7-B3: Reserved bits Change of the initial values is inhibited.
B2: FSK receive overrun error notification register
0: No overrun error occurred
1: Overrun error occurred
When an overrun error occurred during FSK data receive processing, this bit is also set to “1”at the next
read request (FDET_RQ=1). When FDET_RQ is cleared, make sure this bit is also cleared by writing
“0” to this bit.
B1: FSK receive framing error notification register
0: No framing error occurred
1: Framing error occurred
When SP (Stop Bit “1”) is not detected normally at reception of FSK data, this bit is also set to “1” when
the reading of the relevant data is requested(FDET_RQ=1). When FDET_RQ is cleared, make sure that
this bit is also cleared by writing “0” to this bit.
B0: FSK receive data read request notification register
0: No read request issued
1: Read request issued
When receiving FSK data (10 bits), the LSI stores the data bits (8 bits) excluding ST (Start Bit “0”) and
SP (Stop Bit “1”) in FDET_D[7:0] and sets this bit to “1”. After completion of receive data read
processing, clear this bit by writing “0” to this bit.
For details of the control method relating to FSK_DET, see the section of the FSK receiver (FSK_DET) of the
internal data memory access and control method that are described later.
When the setting of the bits B2-B0 is changed (“0”  “1”), an INTB interrupt occurs.
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(18) CR17
CR17
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
#
#
#
#
FGEN
_FLAG
—
—
—
—
—
—
—
/E
0
0
0
0
0
0
0
0
R/W
R/W
B7-B1: Reserved bits Change of the initial values is inhibited.
B0: FSK output data setting completion flag
Set this bit to “1” after writing data to the FSK output data setting register (FGEN_D[7:0]). This bit is
cleared to “0” automatically at completion of the fetching of data to the internal buffer of the FSK signal
generation section and an interrupt occurs. Do not write any data to this register while this bit is “1”.
For details, see the section of the FSK generator of the internal data memory access and control method
that are described later.
When the setting of the B0 bit is changed (“1”  “0”), an INTB interrupt occurs.
(19) CR18
CR18
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
#
#
#
#
TMOVF
—
—
—
—
—
—
—
/E
0
0
0
0
0
0
0
0
R/W
R/W
B7-B1: Reserved bits Change of the initial values is inhibited.
B0: Timer overflow display register
0: No timer overflow occurred.
1: Timer overflow occurred.
When the timer counter value and the data setting value match and consequently a timer overflow occurs,
the timer overflow display register (TMOVF) is set to “1” and an INTB interrupt occurs.
The timer overflow interrupt is cleared to “0” when the timer is stopped as a result of writing “0” to
TMOVF from the MCU side or writing “0” to the timer control register (TIM_EN).
When the setting of the B0 bit is changed (“0”  “1”), an INTB interrupt occurs.
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(20) CR19
CR19
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
DSP
_ERR
#
#
TONE1_
DET
TONE0_
DET
TGEN1_
EXFLAG
TGEN0_
EXFLAG
#
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
R/W
R/
B7: DSP status register
0: Normal operating status
1: Abnormal operating status
This LSI is equipped with a built-in watchdog timer. When a DSP program loses control due to a
disturbance surrounding this LSI or power supply abnormality, the DSP status register (DSP_ERR) is set
to “1” and an interrupt occurs. When this bit is set to “1”, set power-down reset by using PDNB or the
software power-down reset control register (SPDN). This bit is cleared by setting power-down reset.
(Note)
The DSP status register (DSP_ERR) does not detect all the abnormal operations. The register cannot
detect the abnormal operating status that causes the clearing of the watchdog timer even if DSP loses
control.
B6-B5: Reserved bits
Change of the initial values is inhibited.
B4: TONE1 detecter detection status register
0: Non-detection
1: Detection
B3: TONE0 detecter detection status register
0: Non-detection
1: Detection
For details of TDET0 and TDET1, see the sections of tone detecter 0 and tone detecter 1 of the internal data
memory access and the control method that are described later.
B2: TGEN1 execution status flag display register
0: Inactive
1: Active
B1: TGEN0 execution status flag display register
0: Inactive
1: Active
For details of TGEN0_EXFLAG/TGEN1_EXFLAG, see the sections of tone generater 0/tone generator 1 of the
internal data memory access and the control method that are described later.
B0: Reserved bit
Change of the initial value is inhibited.
When the setting of the B7 bit is changed (“0”  “1”) or the setting of the bits B4-B1 is changed (“0”  “1” or
“1”  “0”), an INTB interrupt occurs.
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(21) CR20
CR20
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
INT
DP_DET
#
DTMF
_DET
DTMF_
CODE3
DTMF_
CODE2
DTMF_
CODE1
DTMF_
CODE0
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
R/W
R/
B7: Interrupt occurrence status register
This is a direct connection register with inverted INTB logic.
When INTB is “L”, “1” is read. In other cases, “0” is read.
0: Section where INTB is “H”
1: Section where INTB is “L”
(Note)
When DSP_ERR occurs, the INT register and the status of INTB may not match.
B6: Dial pulse detector detection status register
The bit is set to “1” in the section from which a dial pulse signal is detected. The bit is set to “0” in
other cases.
0: No dial pulse detected
1: Dial pulse detected.
B5: Reserved bits Change of the initial values is inhibited.
B4: DTMF detector detection status register
This bit is set to “1” in the section from which a DTMF signal is detected. The bit is set to “0” in other
cases.
0: Non-detection
1: Detection
B3-B0: DTMF code display register
When the DTMF detector control register (DTMF_EN) is set to “1”, a valid code is stored in this register
for the time period in which a DTMF signal is being detected (DTMF detector detection status register
DTMF_DET = “1”).
When the DTMF signal is not detected (DTMF_DET = “0”), “0000” is output.
Table 6 lists the codes.
When the setting of B6 or B4-B0 is changed (“0”  “1” or “1”  “0”), an INTB interrupt occurs.
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Table 6 DTMF Detection Codes
DTMF_3
DTMF_2
DTMF_1
DTMF_0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Low group
[Hz]
697
770
852
941
697
770
852
941
697
770
852
941
697
770
852
941
High group
[Hz]
1209
1209
1209
1209
1336
1336
1336
1336
1477
1477
1477
1477
1633
1633
1633
1633
Dial number
1
4
7
*
2
5
8
0
3
6
9
#
A
B
C
D
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(22) CR21
CR21
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
TX_SC
FLAG
TX_BT
FLAG
TXREQ
_DC
TXREQ
_First
TXERR
_CH2
TXERR
_CH1
FR0_
CH2
FR0_
CH1
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
R/W
R/
B7: Transmit side Speech CODEC operating mode notification flag
0: G.729.A
1: G.711 (-law/A-law)
The operating mode of Speech CODEC on the transmit side can be checked by referencing this bit at
switching of the Speech CODEC coding format on the transmit side. If this bit is “0” when a transmit
request is issued due to the fall of FR0B, it indicates that the transmit data has been encoded in the
G.729.A coding format. If this bit is set to “1” when transmission is requested due to the fall of FR0B, it
indicates that the transmit data has been encoded in the G.711 coding format (-law/A-law).
See Figures 22 to 25 for Speech CODEC coding format switching control on the transmit side.
B6: Transmit side buffering time operating mode notification flag
0: 10 ms
1: 20 ms
By referencing this bit, the operating mode of the transmit side buffering time can be checked. If this bit
is set to “0” when transmission is requested due to the fall of FR0B, encoded data of 10 ms is buffered.
If this bit is set to “1” when transmission is requested, encoded data of 20 ms is buffered in the transmit
buffer.
B5: 2-channel transmit request notification register
0: Not in cases where 2-channel transmission is being requested
1: 2-channel transmission is being requested
Transmission is requested twice within one frame while 2-channel transmission is being requested
(TXREQ_DC = 1).
Read transmit data of channel 1 in response to CH1 transmit request (FR0_CH1 = 1) and read transmit
data of channel 2 in response to CH2 transmit request (FR0_CH2).
B4: Transmit frame start notification register
Transmission is requested twice within one frame while 2-channel transmission is being requested
(TXREQ_DC = 1). This bit enables the checking of the start timing of each transmit frame.
While 2-channel transmit is being requested (TXREQ_DC = 1), this bit is set to “1” immediately before
CH1 transmit request (FR0_CH1 = 1) and the bit is cleared to “0” immediately before CH2 transmit
request (FR0_CH2 = 1).
See the transmit/receive buffer control method at 2-channel processing in Figures 32 to 35.
B3: CH2 transmit error status register
0: No CH2 transmit error occurred
1: CH2 transmit error occurred
This bit is set to “1” when the CH2 transmit data read processing is not completed within the valid read
period and in other cases, the bit is set to “0”.
B2: CH1 transmit error status register
0: No CH1 transmit error occurred
1: CH1 transmit error occurred
When read processing of CH1 transmit data is not completed within the valid read period, this bit is set to
“1” and in other cases, the bit is set to “0”.
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B1: CH2 transmit request notification register
0: No CH2 transmit request generated
1: CH2 transmit request generated
When the transmit buffer storing the CH2 transmit data becomes full, this bit is set to “1” and the bit is set to “0”
at completion of reading of the data from the transmit buffer or the processing time exceeded the specified time.
B0: CH1 transmit request notification register
0: No CH1 transmit request generated
1: CH1 transmit request generated
When the transmit buffer storing CH1 transmit data becomes full, this bit is set to “1” and the bit is set to
“0” at completion of reading of the data from the transmit buffer or the processing time exceeded the
specified time.
In frame mode (FD_SEL = 0), the signal obtained by NORing bit B1 with bit B0 is output to the FR0B pin. (*)
(Note)*
In DMA mode (FD_SEL = 1), the bit B1, bit B0, and FR0B (DMARQ0B) pin statuses do not match.
When the setting of the bits B3-B2 (“0”  “1” or “1”  “0” ) or bits B1-B0 (“0”  “1”) changes, an INTB
interrupt occurs.
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(23) CR22
CR22
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
RX_SC
FLAG
RX_BT
FLAG
RXREQ
_DC
RXREQ
_First
RXERR
_CH2
RXERR
_CH1
RXBW
_ERR
FR1
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
R/W
R/
B7: Receive side Speech CODEC operating mode notification flag
0: G.729.A
1: G.711 (-law/A-law)
The operating mode of Speech CODEC on the receive side can be checked by referencing this bit at
switching of the Speech CODEC coding format on the receive side. If this bit is set to “0” when a
receive request is issued due to the fall of FR1B, it indicates that receive data in the G.729.A coding
format is being requested.
If this bit is set to “1” when a receive request is issued due to the fall of
FR1B, it indicates that receive data in the G.711 coding format (-law/A-law) is being requested.
See Figures 26 to 29 for Speech CODEC coding format switching control on the receive side.
B6: Receive side buffering time operating mode notification flag
0: 10 ms
1: 20 ms
The buffering time operating mode on the receive side can be checked by referencing this bit. If this bit
is set to “0” when a receive request is issued due the fall of FR1B, it indicates that the receive buffer is
requesting the writing of data of 10 ms. If this bit is set to “1” when a receive request is issued due the
fall of FR1B, it indicates that the receive buffer is requesting the writing of data of 20 ms.
B5: 2-channel receive request notification register
0: Not in cases where 2-channel reception is being requested
1: 2-channel reception is being requested
While 2-channel reception is being requested (RXREQ_DC = 1), a receive request is issued twice within
one frame.
Write receive data of channel 1 or channel 2 for each receive request (FR1 = 1).
B4: Receive frame start notification register
While 2-channel reception is being requested (RXREQ_DC = 1), a receive request is issued twice within
one frame. Use this bit to check if the request is the first receive request.
If this bit is set to “1” when a receive request is generated (FR1 = 1), the request is the first request and if
the bit is set to “0”, the request is the second receive request. See also the transmit/receive buffer control
method at 2-channel processing in Figures 32 to 35.
B3: CH2 receive error status register
0: No CH2 receive error occurred
1: CH2 receive error occurred
This bit is set to “1” when CH2 receive data write processing is not completed within the valid write
period and set to “0” in other cases.
B2: CH1 receive error status register
0: No CH1 receive error occurred
1: CH1 receive error occurred
This bit is set to “1” when CH1 receive data write processing is not completed within the valid write
period and set to “0” in other cases.
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B1: Invalid receive data write error notification register
0: No invalid receive data write generated
1: Invalid receive data write generated
This bit is set to “1” if receive data channel notification is issued from the MCU side without observing
the following prohibition while 2-chanel reception is being requested (RXREQ_DC = 1). In other cases,
the bit is set to “0”.
 Prohibition 1: Do not write receive data of the same channel in the same frame consecutively.
If receive data of the same channel of the same frame is written consecutively, RXBW_ERR is set to “1”.
In this case, the data that is written in response to the first receive request (FR1 = 1 & RXREQ_First = 1)
is decoded, but the data that is written in response to the second receive request (FR1 = 1 & RXREQ_First
= 0) is discarded.
 Prohibition 2: Do not set RXFLAG_[CH2:CH1] = [1:1] or [0:0].
If RXFLAG_[CH2:CH1] is set to [1:1] or [0:0], the receive data is discarded and RXBW_ERR is set to
“1”.
B0: Receive request notification register
0: No receive request issued
1: Receive request issued
This bit is set to “1” when the receive buffer that stores receive data becomes empty. When the receive
buffer becomes full or the processing exceeds the specified time, the bit is set to “0”.
In frame mode (FD_SEL = 0), the signal generated by inverting the logic of bit B0 is output to the FR1B
pin. (*)
(Note)*
In DMA mode (FD_SEL = 1), bit B0 and the FR1B (DMARQ1B) pin statuses do not match.
When the status of bits B3-B1 is changed (“0”  “1” or “1”  “0” ) or that of bit B0 changed(“0”  “1”) , an
INTB interrupt occurs.
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Table 7 lists the transmit/receive buffer control registers.
Note that the register that is referenced or set on the MCU side varies depending on the operating mode
(1-channel operation/2-channel operation) of Speech CODEC.
Table 7 Transmit/Receive Buffer Control Registers
Bit
Register name (abbreviation)
CR21
B0
B1
B2
B3
B4
B5
CH1 transmit request notification register (FR0_CH1)
CH2 transmit request notification register (FR0_CH2)
CH1 transmit error status register (TXERR_CH1)
CH2 transmit error status register (TXERR_CH2)
Transmit frame start notification register (TXREQ_First)
2-channel transmit request notification register
(TXREQ_DC)
Transmit side buffering time operating mode notification
flag
(TX_BTFLAG)
Transmit side Speech CODEC operating mode
notification flag
(TX_SCFLAG)
Receive request notification register (FR1)
Invalid receive data write error notification register
(RXBW_ERR)
CH1 receive error status register (RXERR_CH1)
CH2 receive error status register (RXERR_CH2)
Receive frame start notification register (RXREQ_First)
2-channel receive request notification register
(RXREQ_DC)
Receive side buffering time operating mode notification
flag
(RX_BTFLAG)
Receive side Speech CODEC operating mode
notification flag
(RX_SCFLAG)
Receive data write channel notification register
RXFLAG_[CH2:CH1]
Transmit control
CR
B6
B7
CR22
B0
B1
Receive control
B2
B3
B4
B5
B6
B7
CR5
B1B0
Single-channel
operation
SC_EN=1,DC_EN=0






2-channel operation
SC_EN=1,DC_EN=1




























(Remarks) : Used, : Unused
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(24) CR23
CR23
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
SC_EN
DC_EN
DEC_
OUTON
ACTCH
_FLAG
G711_
PLCEN
#
#
#
I/E
I/E
/E
/E
I/E
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
B7: Speech CODEC control register
0: Stops Speech CODEC
The encoder stops and storing data into the transmit buffer is stopped. The decoder stops and outputs
silent data constantly.
1: Activates Speech CODEC
Setting this bit to “1” starts the Speech CODEC operation. Speech CODEC is initialized and starts
operation.
(Note)
When stopping Speech CODEC
When stopping Speech CODEC, be sure to make the following settings in advance:
- Writing 00FFh to CR21 rising edge interrupt mask control (CR21_INTR_MSKCNT)
- Writing 00FFh to CR22 rising edge interrupt mask control (CR22_INTR_MSKCNT)
B6: Speech CODEC 2-channel processing control register
0: Stops Speech CODEC 2-channel processing.
1: Activates Speech CODEC 2-channel processing.
B5: Decoded data output control register
This bit controls the first decoded data output timing after activation of Speech CODEC.
After activation of Speech CODEC, this bit can be set to “1” if the initial receive data has been written
and the tWAIT time has elapsed. When this bit is set to “1”, the following decoded data is output in the
selected Speech CODEC coding format.
 When G.711 (-law/A-law) is selected:
When the PLC function is enabled, silent data is output for about 3.75 ms and decoded data is output
after this bit is set to “1”.
When the PLC function is disabled, decoded data is output after this bit is set to “1”.
 When G.729.A is selected:
Decoded data is output about 15 ms after this bit is set to “1”.
The decoded data output delay time can be increased in steps of 0.125 ms by setting the time in the
internal data memory (DEC_ONTIM) for controlling decoded data output starting offset time.
(Allowable DEC_ONTM setting range: 0.125 ms to 32 ms)
Clear this bit to “0” when stopping Speech CODEC by setting SC_EN to ”0”.
See the diagrams of receive buffer control timing in Figures 18 to 21 for details of the control method.
(Note) The tWAIT delay time of 1 ms or more is required after activation of Speech CODEC.
(Note)
It is also possible to set DEC_OUTON to “1” at the same time as setting SC_EN to “1”. If soing so,
however, set the offset time to a value between 0008h (1 ms) and 0100h (32 ms) in the internal data
memory for controlling decoded output starting offset time (DEC_ONTIM) in advance.
Output of decoded data will start when the writing of the first receive data after the activation of Speech
CODEC is completed and when the above offset time elapses.
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B4: Operation channel notification register
0: Continues encoding and decoding for CH1
1: Continues encoding and decoding for CH2
When changing the mode from 2-channel operation (SC_EN = 1, DC_EN = 1) to single-channel
operation (SC_EN = 1, DC_EN = 0), notify the channel (CH1 or CH2) for which encoding and decoding
is continued using this bit. When stopping Speech CODEC (SC_EN = 0) in single-channel operation
mode (SC_EN = 1, DC_EN = 0), clear this bit to “0” from the MCU side.
Even if encoding and decoding for CH2 are continued, LSI performs the processing as single-channel
operation and displays statuses of CH1 as statuses of receive requests, transmit requests, and so on.
B3: G.711 PLC function enable control register
The G.711 PLC function can be enabled by setting this bit to “1”.
0: Disable
1: Enable
(Note) When setting G711_PLCEN to “1”, make sure that SC_EN is “0”.
B2-B1: Reserved bits Change of the initial value is inhibited.
B0: Reserved bit
Change of the initial value is inhibited.
(25) CR24
B7
CR24
Change enable
mode
Initial value
B6
B5
B4
B3
B2
B1
B0
PCM_
PCM_
TXEN2
RXEN2
#
#
#
#
#
#
—
—
—
—
—
—
I/E
I/E
0
0
0
0
0
0
0
0
R/W
R/W
B7-B2: Reserved bits Change of the initial value is inhibited.
B1: PCM_TXEN2 connection path control
0: Does not connect the path
1: Connects the path
B0: PCM_RXEN2 connection path control
0: Does not connect the path
1: Connects the path
(26) CR25
CR25
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
FDET
_D7
FDET
_D6
FDET
_D5
FDET
_D4
FDET
_D3
FDET
_D2
FDET
_D1
FDET
_D0
R/
—
0
0
0
0
R/W
0
0
0
0
B7-B0: FSK received data storage register
For details, see the section of the FSK Receiver (FSK_DET) in INTERNAL DATA MEMORY ACCESS AND
CONTROL METHOD described later.
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(27) CR26
CR26
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
DPDET_
DATA7
DPDET_
DATA6
DPDET_
DATA5
DPDET_
DATA4
DPDET_
DATA3
DPDET_
DATA2
DPDET_
DATA1
DPDET_
DATA0
R/
—
0
0
0
0
R/W
0
0
0
0
B7-B0: Detected dial pulse count display register
Displays the dial pulse count that was detected.
For details, see the section of the Dial Pulse Detector (DPDET) in INTERNAL DATA MEMORY
ACCESS AND CONTROL METHOD described later.
(Note)
Read the “detected dial pulse count display register (DPDET_DATA [7:0]) when the setting of the dial
pulse detection status register (DP_DET) is changed from “1” to “0”.
(28) CR27
CR27
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
FGEN
_D7
FGEN
_D6
FGEN
_D5
FGEN
_D4
FGEN
_D3
FGEN
_D2
FGEN
_D1
FGEN
_D0
R/W
I/E
0
0
0
0
R/W
0
0
0
0
B7-B0: FSK output data setting register
For details, see the section of the FSK Generator (FSK_GEN) in INTERNAL DATA MEMORY
ACCESS AND CONTROL METHOD described later.
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(29) CR28
CR28
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
FDET
_EN
FGEN
_EN
TIM_EN
TDET1
_EN
TDET0
_EN
DTMF
_EN
EC_EN
#
I/E
I/E
I/E
I/E
I/E
I/E
I/E
—
0
0
0
0
0
0
0
0
R/W
R/W
B7: FSK_DET control register
0: Stops FSK_DET
1: Activates FSK_DET
When this bit is set to “1”, the FSK receiver (FSK_DET) starts operation. For details, see the section of
the FSK Receiver (FSK_DET) in INTERNAL DATA MEMORY ACCESS AND CONTROL METHOD
described later.
B6: FSK_GEN control register
0: Stops FSK_GEN
1: Activates FSK_GEN
When this bit is set to “1”, the FSK generator (FSK_GEN) starts operation. For details, see the section
of the FSK Generator in INTERNAL DATA MEMORY ACCESS AND CONTROL METHOD
described later.
B5: Timer control register
When this bit is set to “1”, the timer starts counting.
When “0” is set, the timer stops counting and the counter value is cleared.
0: Stops counting
1: Starts counting
B4: TONE1 detector control register
0: Stops TONE_DET1
1: Activates TONE_DET1
When this bit is set to “1”, the TONE1 detector starts operation. The TONE1 detector detection status
register (TONE1_DET) is set to “1” while the tone of 2100 Hz* is detected.
(Remarks)
* The detection frequency can be changed. When changing the frequency, contact ROHM's responsible
sales person.
B3: TONE0 detection control register
0: Stops TONE_DET0
1: Activates TONE_DET0
When this bit is set to “1”, the TONE0 detector starts operation. The TONE0 detector detection status
register (TONE0_DET) is set to “1” while the tone of 1650Hz* is detected.
(Remarks)
* The detection frequency can be changed. When changing the frequency, contact ROHM's responsible
sales person.
B2: DTMF detection control register
0: Stops the DTMF detection function
1: Activates the DTMF detection function
When this bit is set to “1”, the DTMF detector starts operation. The DTMF detector detection register
(DTMF_DET) is set to “1” while DTMF signals are detected.
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B1: Echo canceler control register
0: Stops the echo canceler function (The echo canceler is bypassed.)
1: Activates the echo canceler function
(Remarks) The echo canceler internal coefficient is cleared to start the operation.
B0: Reserved bit
Change of the initial value is inhibited.
(30) CR29
CR29
Change enable
mode
Initial value
B7: Reserved bit
B7
B6
B5
B4
B3
B2
B1
B0
#
DPGEN
_EN
DPGEN
_POL
DPGEN
_PPS
DPGEN
_DATA3
DPGEN
_DATA2
DPGEN
_DATA1
DPGEN
_DATA0
—
I/E
I/
I/E
I/E
I/E
I/E
I/E
0
0
0
0
0
0
0
0
R/W
R/W
Change of the initial value is inhibited.
B6: Dial pulse transmitting control register
0: Stops dial pulse output
1: Activates dial pulse output
B5: Dial pulse output polarity control register
0: Positive logic (Low: Break zone, High: Make zone)
1: Negative logic (Low: Make zone, High: Break zone)
B4: Dial pulse speed control register
0: 10 pps
1: 20 pps
B3-B0: Dial pulse count setting register
Set a dial pulse count to be transmitted.
Upper limit: 10
(Data: Ah)
Lower limit: 1
(Data: 1h)
(Note) Be sure to set the following before activating DPGEN (DPGEN_EN = 1).
 Be sure to set the dial pulse output polarity control register (DPGEN_POL).
By this setting, the output level (initial value) of the dial pulse output pin is set as follows.
When DPGEN_POL = 0 (positive logic) : GPO0[2]/DPO = “0”
When DPGEN_POL = 1 (negative logic) : GPO0[2]/DPO = “1”
 After setting the above, set the secondary function (dial pulse output pin) by setting the primary
function/secondary function selection register (GPFA[2]) of GPIOA[2] to “1”.
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(31) CR30
CR30
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
FDET
_SEL
#
DTMF
_SEL
TDET1_
SEL1
TDET1_
SEL0
TDET0_
SEL1
TDET0_
SEL0
—
I/E
—
I/E
I/E
I/E
I/E
I/E
0
0
0
0
0
0
0
0
R/W
R/W
Select signals to be input to the various detectors in this LSI. For TXDETA, TXDETB, RXDET, and
RXDET_PCM, see various detector paths that are shown in the block diagram provided earlier in this document.
B7: Reserved bits
Change of the initial value is inhibited.
B6: FSK detection path selection register
0: TXDETA
1: TXDETB
B5: Reserved bits
Change of the initial value is inhibited.
B4: DTMF detection path selection register
0: TXDETA
1: TXDETB
B3-B2: TONE_DET1 detection path selection register
00: TXDETA
01: TXDETB
10: RXDET
11: RXDET_PCM
B1-B0: TONE_DET0 detection path selection register
00: TXDETA
01: TXDETB
10: RXDET
11: RXDET_PCM
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(32) CR31
CR31
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
LPEN1
LPEN0
CODEC
B_TXEN
CODEC
B_RXEN
CODEC
A_TXEN
CODEC
A_RXEN
SC_
TXEN
SC_
RXEN
I/E
I/E
I/E
I/E
I/E
I/E
I/E
I/E
0
0
0
0
0
0
0
0
R/W
R/W
Set connection/non-connection of various communication paths that are shown in the block diagram provided
earlier in this document.
B7: LPEN1 connection path control
0: Non-connection
1: Connection
B6: LPEN0 connection path control
0: Non-connection
1: Connection
B5: CODECB_TXEN connection path control
0: Non-connection
1: Connection
B4: CODECB_RXEN connection path control
0: Non-connection
1: Connection
B3: CODECA_TXEN connection path control
0: Non-connection
1: Connection
B2: CODECA_RXEN connection path control
0: Non-connection
1: Connection
B1: SC_TXEN connection path control
0: Non-connection
1: Connection
B0: SC_RXEN connection path control
0: Non-connection
1: Connection
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(33) CR32
CR32
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
RXGEN
A_EN
RXGEN
B_EN
PCM_
TXEN1
PCM_
TXEN0
PCM_
RXEN1
PCM_
RXEN0
—
—
I/E
I/E
I/E
I/E
I/E
I/E
0
0
0
0
0
0
0
0
R/W
R/W
Set connection/non-connection of various communication paths that are shown in the block diagram provided
earlier in this document.
B7-B6: Reserved bits
Changing of the initial values is inhibited.
B5: RXGENA_EN connection path control
0: Non-connection
1: Connection
B4: RXGENB_EN connection path control
0: Non-connection
1: Connection
B3: PCM_TXEN1 connection path control
0: Non-connection
1: Connection
B2: PCM_TXEN0 connection path control
0: Non-connection
1: Connection
B1: PCM_RXEN1 connection path control
0: Non-connection
1: Connection
B0: PCM_RXEN0 connection path control
0: Non-connection
1: Connection
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(34) CR33
CR33
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
PCM_
ITS1[4]
PCM_
ITS1[3]
PCM_
ITS1[2]
PCM_
ITS1[1]
PCM_
ITS1[0]
—
—
—
I/E
I/E
I/E
I/E
I/E
0
0
0
0
0
0
0
0
R/W
R/W
B7-B5: Reserved bits Changing of the initial values is inhibited.
B4-B0: PCM input time slot selection register 1
Set the time slot number for fetching PCM data according to the selection table 8.
To receive PCM data in the selected time slot position, set the PCM input time slot 1 enable control
register (PCMI1_EN) to “1”.
Table 8 PCM Input Time Slot Selection Table 1
B4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Time Slot
Slot1
Slot2
Slot3
Slot4
Slot5
Slot6
Slot7
Slot8
Slot9
Slot10
Slot11
Slot12
Slot13
Slot14
Slot15
Slot16
B4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Time Slot
Slot17
Slot18
Slot19
Slot20
Slot21
Slot22
Slot23
Slot24
Slot25
Slot26
Slot27
Slot28
Slot29
Slot30
Slot31
Slot32
(Note)
Make sure that the PCM input time slot selection 1 enable control register (PCMI1_EN) is kept “0” when
the register is set.
(Note)
The number of bits of one time slot changes automatically according to the setting of the PCM coding
format (PCM_SEL[1:0]):
16-bit linear setting
: 16 bits
G.711 (-law/A-law) setting : 8 bits
Therefore, the maximum time slot number that can be set is as follows.
16-bit linear setting
: n/2
G.711 (-law/A-law) setting : n
[n = (BCLK frequency)  64 kHz]
Any number exceeding the maximum time slot number cannot be set.
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(35) CR34
CR34
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
PCM_
ITS2[4]
PCM_
ITS2[3]
PCM_
ITS2[2]
PCM_
ITS2[1]
PCM_
ITS2[0]
—
—
—
I/E
I/E
I/E
I/E
I/E
0
0
0
0
0
0
0
0
R/W
R/W
B7-B5: Reserved bits Changing of the initial values is inhibited.
B4-B0: PCM input time slot selection register 2
Set the time slot number for fetching PCM data according to the selection table 9.
To receive PCM data in the selected time slot position, set the PCM input time slot 2 enable control
register (PCMI2_EN) to “1”.
Table 9 PCM Input Time Slot Selection Table 2
B4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Time Slot
Slot1
Slot2
Slot3
Slot4
Slot5
Slot6
Slot7
Slot8
Slot9
Slot10
Slot11
Slot12
Slot13
Slot14
Slot15
Slot16
B4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Time Slot
Slot17
Slot18
Slot19
Slot20
Slot21
Slot22
Slot23
Slot24
Slot25
Slot26
Slot27
Slot28
Slot29
Slot30
Slot31
Slot32
(Note)
Make sure that the PCM input time slot selection 2 enable control register (PCMI2_EN) is kept “0” when
the register is set.
(Note)
The number of bits of one time slot changes automatically according to the setting of the PCM coding
format (PCM_SEL[1:0]):
16-bit linear setting
: 16 bits
G.711 (-law/A-law) setting : 8 bits
Therefore, the maximum time slot number that can be set is as follows.
16-bit linear setting
: n/2
G.711 (-law/A-law) setting : n
[n = (BCLK frequency)  64 kHz]
Any number exceeding the maximum time slot number cannot be set.
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(36) CR35
CR35
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
PCM_
OTS1[4]
PCM_
OTS1[3]
PCM_
OTS1[2]
PCM_
OTS1[1]
PCM_
OTS1[0]
—
—
—
I/E
I/E
I/E
I/E
I/E
0
0
0
0
0
0
0
0
R/W
R/W
B7-B5: Reserved bits Changing of the initial values is inhibited.
B4-B0: PCM output time slot selection register 1
Set the time slot number for outputting PCM data according to the selection table 10.
To output PCM data in the selected time slot position, set the PCM output time slot 1 enable control
register (PCMO1_EN) to “1”.
Table 10 PCM Output Time Slot Selection Table 1
B4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Time Slot
Slot1
Slot2
Slot3
Slot4
Slot5
Slot6
Slot7
Slot8
Slot9
Slot10
Slot11
Slot12
Slot13
Slot14
Slot15
Slot16
B4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Time Slot
Slot17
Slot18
Slot19
Slot20
Slot21
Slot22
Slot23
Slot24
Slot25
Slot26
Slot27
Slot28
Slot29
Slot30
Slot31
Slot32
(Note)
Make sure that the PCM output time slot selection 1 enable control register (PCMO1_EN) is kept “0”
when the register is set.
(Note)
The number of bits of one time slot changes automatically according to the setting of the PCM coding
format (PCM_SEL[1:0]):
16-bit linear setting
: 16 bits
G.711 (-law/A-law) setting : 8 bits
Therefore, the maximum time slot number that can be set is as follows.
16-bit linear setting
: n/2
G.711 (-law/A-law) setting : n
[n = (BCLK frequency)  64 kHz]
Any number exceeding the maximum time slot number cannot be set.
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(37) CR36
CR36
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
PCM_
ITS3[4]
PCM_
ITS3[3]
PCM_
ITS3[2]
PCM_
ITS3[1]
PCM_
ITS3[0]
—
—
—
I/E
I/E
I/E
I/E
I/E
0
0
0
0
0
0
0
0
R/W
R/W
B7-B5: Reserved bits Changing of the initial values is inhibited.
B4-B0: PCM input time slot selection register 3
Set the time slot number for fetching PCM data according to the selection table 11.
To receive PCM data in the selected time slot position, set the PCM input time slot 3 enable control
register (PCMI3_EN) to “1”.
Table 11 PCM Input Time Slot Selection Table 3
B4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Time Slot
Slot1
Slot2
Slot3
Slot4
Slot5
Slot6
Slot7
Slot8
Slot9
Slot10
Slot11
Slot12
Slot13
Slot14
Slot15
Slot16
B4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Time Slot
Slot17
Slot18
Slot19
Slot20
Slot21
Slot22
Slot23
Slot24
Slot25
Slot26
Slot27
Slot28
Slot29
Slot30
Slot31
Slot32
(Note)
Make sure that the PCM input time slot selection 3 enable control register (PCMI3_EN) is kept “0” when
the register is set.
(Note)
The number of bits of one time slot changes automatically according to the setting of the PCM coding
format (PCM_SEL[1:0]):
16-bit linear setting
: 16 bits
G.711 (-law/A-law) setting : 8 bits
Therefore, the maximum time slot number that can be set is as follows.
16-bit linear setting
: n/2
G.711 (-law/A-law) setting : n
[n = (BCLK frequency)  64 kHz]
Any number exceeding the maximum time slot number cannot be set.
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(38) CR37
CR37
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
$
$
$
$
$
$
$
$
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R/W
/
B7-B0: Reserved bits Access is inhibited.
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(39) CR38
CR38
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
PCM_
OTS2[4]
PCM_
OTS2[3]
PCM_
OTS2[2]
PCM_
OTS2[1]
PCM_
OTS2[0]
—
—
—
I/E
I/E
I/E
I/E
I/E
0
0
0
0
0
0
0
0
R/W
R/W
B7-B5: Reserved bits Changing of the initial values is inhibited.
B4-B0: PCM output time slot selection register 2
Set the time slot number for outputting PCM data according to the selection table 12.
To output PCM data in the selected time slot position, set the PCM output time slot 2 enable control
register (PCMO2_EN) to “1”.
Table 12 PCM Output Time Slot Selection Table 2
B4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Time Slot
Slot1
Slot2
Slot3
Slot4
Slot5
Slot6
Slot7
Slot8
Slot9
Slot10
Slot11
Slot12
Slot13
Slot14
Slot15
Slot16
B4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Time Slot
Slot17
Slot18
Slot19
Slot20
Slot21
Slot22
Slot23
Slot24
Slot25
Slot26
Slot27
Slot28
Slot29
Slot30
Slot31
Slot32
(Note)
Make sure that the PCM output time slot selection 2 enable control register (PCMO2_EN) is kept “0”
when the register is set.
(Note)
The number of bits of one time slot changes automatically according to the setting of the PCM coding
format (PCM_SEL[1:0]):
16-bit linear setting
: 16 bits
G.711 (-law/A-law) setting : 8 bits
Therefore, the maximum time slot number that can be set is as follows.
16-bit linear setting
: n/2
G.711 (-law/A-law) setting : n
[n = (BCLK frequency)  64 kHz]
Any number exceeding the maximum time slot number cannot be set.
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(40) CR39 to CR42
CR39 to CR42
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
$
$
$
$
$
$
$
$
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B5
B4
B3
B2
B1
B0
DPDET
_EN
R/W
/
B7-B0: Reserved bits Access is inhibited.
(41) CR43
B7
CR43
Change enable
mode
Initial value
B6
#
#
#
#
#
#
DPDET
_POL
—
—
—
—
—
—
I/
I/E
0
0
0
0
0
0
0
0
R/W
R/W
B7-B2: Reserved bits Changing of the initial values is inhibited.
B1: Dial pulse detection polarity control register
Controls the polarity that is input from the DPI pin.
0: Polarity not inverted
1: Polarity inverted
B0: Dial pulse detector control register
0: Stops a dial pulse detector
1: Activates a dial pulse detector
(42) CR44 to CR47
CR44 to CR47
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
$
$
$
$
$
$
$
$
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R/W
/
B7-B0: Reserved bits Access is inhibited.
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(43) GPCR0
GPCR0
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
GPMA
[6]
GPMA
[5]
GPMA
[4]
GPMA
[3]
GPMA
[2]
GPMA
[1]
GPMA
[0]
—
I/E
I/E
I/E
I/E
I/E
I/E
I/E
0
0
0
0
0
0
0
0
R/W
R/W
Using this register (GPMA[6:0]), the direction (input or output) of general-purpose I/O port A [6:0]
(GPIOA[6:0]) can be set in bit units.
B7: Reserved bits Changing of the initial values is inhibited.
B6: Input-output setting register of GPIOA[6]
0: Input
1: Output
When GPFA[6] is set to the secondary function (INTB), the pin is always set to the output state.
B5: Input-output setting register of GPIOA[5]
0: Input
1: Output
When GPFA[5] is set to the secondary function (ACK1B), the pin is always set to the input state.
B4: Input-output setting register of GPIOA[4]
0: Input
1: Output
When GPFA[4] is set to the secondary function (ACK0B), the pin is always set to the input state.
B3: Input-output setting register of GPIOA[3]
0: Input
1: Output
B2: Input-output setting register of GPIOA[2]
0: Input
1: Output
When GPFA[2] is set to the secondary function (DPO), the pin is always set to the output state.
B1: Input-output setting register of GPIOA[1]
0: Input
1: Output
B0: Input-output setting register of GPIOA[0]
0: Input
1: Output
When GPFA[0] is set to the secondary function (DPI), the pin is always set to the input state.
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(44) GPCR1
GPCR1
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
GPDA
[6]
GPDA
[5]
GPDA
[4]
GPDA
[3]
GPDA
[2]
GPDA
[1]
GPDA
[0]
I/E
I/E
I/E
I/E
I/E
I/E
I/E
*
*
*
*
*
*
*
0
R/W
R/W
* Depends on the pin status.
This register (GPDA[6:0]) is used to store input-output data of general-purpose I/O port A[6:0]. (GPIOA[6:0]).
When this register is set to a general-purpose output port and a value is written to an appropriate bit, the written
value is output from the corresponding pin. In this case, when read processing is performed for the bit, the
value in the bit is read.
When this register is set to a general-purpose input port, the status of an appropriate pin can be read by reading
the corresponding bit. Even if write processing is performed for the bit, the pin status remains unchanged
although the register value is updated.
When the port is set to the secondary function in the primary function/secondary function selection register, the
register value is updated when data is written to an appropriate bit, but, the pin status remains unchanged.
When input is set in GPMA[6:0], the pin status is read. When output is set, the bit value is read.
B7: Reserved bits Changing of the initial values is inhibited.
B6: Data register of GPIOA[6]
GPFA[6]
0: GPIOA[6]
GPMA[6]
0: Input
1: Output
At read processing
Pin status
Value of GPDA[6]
1: INTB
0: Input
1: Output
Pin status
Value of GPDA[6]
At write processing
Pin status remains unchanged
Written value is output from the
appropriate pin
Pin status remains unchanged
Pin status remains unchanged
B5: Data register of GPIOA[5]
GPFA[5]
0: GPIOA[5]
GPMA[5]
0: Input
1: Output
At read processing
Pin status
Value of GPDA[5]
1: ACK1B
0: Input
1: Output
Pin status
Value of GPDA[5]
At write processing
Pin status remains unchanged
Written value is output from the
appropriate pin
Pin status remains unchanged
Pin status remains unchanged
B4: Data register of GPIOA[4]
GPFA[4]
0: GPIOA[4]
GPMA[4]
0: Input
1: Output
At read processing
Pin status
Value of GPDA[4]
1: ACK0B
0: Input
1: Output
Pin status
Value of GPDA[4]
At write processing
Pin status remains unchanged
Written value is output from the
appropriate pin
Pin status remains unchanged
Pin status remains unchanged
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B3: Data register of GPIOA[3]
GPMA[3]
0: Input
1: Output
At read processing
Pin status
Value of GPDA[3]
At write processing
Pin status remains unchanged
Written value is output from the
appropriate pin
At write processing
Pin status remains unchanged
Written value is output from the
appropriate pin
Pin status remains unchanged
Pin status remains unchanged
B2: Data register of GPIOA[2]
GPFA[2]
0: GPIOA[2]
GPMA[2]
0: Input
1: Output
At read processing
Pin status
Value of GPDA[2]
1: DPO
0: Input
1: Output
Pin status
Value of GPDA[2]
B1: Data register of GPIOA[1]
GPMA[1]
0: Input
1: Output
At read processing
Pin status
Value of GPDA[1]
At write processing
Pin status remains unchanged
Written value is output from the
appropriate pin
At write processing
Pin status remains unchanged
Written value is output from the
appropriate pin
Pin status remains unchanged
Pin status remains unchanged
B0: Data register of GPIOA[0]
GPFA[0]
0: GPIOA[0]
GPMA[0]
0: Input
1: Output
At read processing
Pin status
Value of GPDA[0]
1: DPI
0: Input
1: Output
Pin status
Value of GPDA[0]
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(45) GPCR2
GPCR2
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
GPFA
[6]
GPFA
[5]
GPFA
[4]
#
GPFA
[2]
#
GPFA
[0]
—
I/E
I/E
I/E
—
I/E
—
I/E
0
1
1
1
0
0
0
0
R/W
R/W
Use this register (GPFA[6-4,2]) to select the primary function/secondary function of general-purpose I/O port A
[6-4,2,0] (GPIOA[6-4,2,0]).
B7: Reserved bits Changing of the initial values is inhibited.
B6: Primary/secondary selection register of GPIOA[6]
0: General-purpose I/O port A[6]
1: INTB
(Initial value)
B5: Primary/secondary selection register of GPIOA[5]
0: General-purpose I/O port A[5]
1: ACK1B
(Initial value)
B4: Primary/secondary selection register of GPIOA[4]
0: General-purpose I/O port A[4]
1: ACK0B
(Initial value)
B3: Reserved bit
Changing of the initial value is inhibited.
B2: Primary/secondary selection register of GPIOA[2]
0: General-purpose I/O port A[2]
(Initial value)
1: DPO (Dial pulse output pin)
B1: Reserved bits Changing of the initial values is inhibited.
B0: Primary/secondary selection register of GPIOA[0]
0: General-purpose I/O port A[0]
(Initial value)
1: DPI (Dial pulse input pin)
Table 13 lists primary functions/secondary functions of general-purpose I/O port A (GPIOA[6:0])
Table 13 GPIOA[6:0] Primary Functions/Secondary Functions
Pin
GPIOA[6]
GPIOA[5]
GPIOA[4]
GPIOA[3]
GPIOA[2]
GPIOA[1]
GPIOA[0]
Primary function
General-purpose I/O port A[6]
General-purpose I/O port A[5]
General-purpose I/O port A[4]
General-purpose I/O port A[3]
General-purpose I/O port A[2]
General-purpose I/O port A[1]
General-purpose I/O port A[0]
Secondary function
INTB
ACK1B
ACK0B
—
DPO (dial pulse output pin)
—
DPI (dial pulse input pin)
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(46) GPCR3
GPCR3
Changeable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
B7: Reserved bits Changing of the initial values is inhibited.
B6: Reserved bits Changing of the initial values is inhibited.
B5: Reserved bits Changing of the initial values is inhibited.
B4: Reserved bits Changing of the initial values is inhibited.
B3: Reserved bits Changing of the initial values is inhibited.
B2: Reserved bits Changing of the initial values is inhibited.
B1: Reserved bits Changing of the initial values is inhibited.
B0: Reserved bits Changing of the initial values is inhibited.
(Note) Access to this register is inhibited.
(47) GPCR4
GPCR4
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
B7: Reserved bits Changing of the initial values is inhibited.
B6: Reserved bits Changing of the initial values is inhibited.
B5: Reserved bits Changing of the initial values is inhibited.
B4: Reserved bits Changing of the initial values is inhibited.
B3: Reserved bits Changing of the initial values is inhibited.
B2: Reserved bits Changing of the initial values is inhibited.
B1: Reserved bits Changing of the initial values is inhibited.
B0: Reserved bits Changing of the initial values is inhibited.
(Note) Access to this register is inhibited.
(48) GPCR5
GPCR5
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
B7: Reserved bits Changing of the initial values is inhibited.
B6: Reserved bits Changing of the initial values is inhibited.
B5: Reserved bits Changing of the initial values is inhibited.
B4: Reserved bits Changing of the initial values is inhibited.
B3: Reserved bits Changing of the initial values is inhibited.
B2: Reserved bits Changing of the initial values is inhibited.
B1: Reserved bits Changing of the initial values is inhibited.
B0: Reserved bits Changing of the initial values is inhibited.
(Note) Access to this register is inhibited.
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(49) GPCR6
GPCR6
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
B7: Reserved bits Changing of the initial values is inhibited.
B6: Reserved bits Changing of the initial values is inhibited.
B5: Reserved bits Changing of the initial values is inhibited.
B4: Reserved bits Changing of the initial values is inhibited.
B3: Reserved bits Changing of the initial values is inhibited.
B2: Reserved bits Changing of the initial values is inhibited.
B1: Reserved bits Changing of the initial values is inhibited.
B0: Reserved bits Changing of the initial values is inhibited.
(Note) Access to this register is inhibited.
(50) GPCR7
GPCR7
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
B7: Reserved bits Changing of the initial values is inhibited.
B6: Reserved bits Changing of the initial values is inhibited.
B5: Reserved bits Changing of the initial values is inhibited.
B4: Reserved bits Changing of the initial values is inhibited.
B3: Reserved bits Changing of the initial values is inhibited.
B2: Reserved bits Changing of the initial values is inhibited.
B1: Reserved bits Changing of the initial values is inhibited.
B0: Reserved bits Changing of the initial values is inhibited.
(Note) Access to this register is inhibited.
(51) CRCR8
GPCR8
Change enable
mode
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
#
#
#
#
#
#
#
#
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
B7: Reserved bits Changing of the initial values is inhibited.
B6: Reserved bits Changing of the initial values is inhibited.
B5: Reserved bits Changing of the initial values is inhibited.
B4: Reserved bits Changing of the initial values is inhibited.
B3: Reserved bits Changing of the initial values is inhibited.
B2: Reserved bits Changing of the initial values is inhibited.
B1: Reserved bits Changing of the initial values is inhibited.
B0: Reserved bits Changing of the initial values is inhibited.
(Note) Access to this register is inhibited.
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INTERNAL DATA MEMORY ACCESS AND CONTROL METHOD
The 8-bit registers (CR6 to CR9) that are mapped in the control registers are assigned to the following:
16-bit address of the internal data memory
(A15 to A0)
16-bit data for write/read processing
(D15 to D0)
The LSI is set to an initial mode about 200 ms after resetting by power-down reset with PDNB or by software
power-down reset with SPDN, and the initial mode display register (READY) is set to “1”. In initial mode,
control register and internal data memory can be changed. This section describes how to write and read internal
data memory.
Write Method (Single-Word)
Single-word internal data write processing is completed by setting the internal data memory single-word write
control register (XDMWR) to “1” after an internal data memory address and data to be written are set in
CR6-CR9. After termination of write operation, XDMWR is automatically cleared to “0”. Figure 52 shows
the method of writing single-word to internal data memory.
To rewrite data to multiple memory spaces with distributed address arears, repeat the write operation described
above.
By setting the operation start control register (OPE_STAT) to “1” after completion of the entire write operation,
normal operation can be started.
Write operation to the internal data memory is allowed in normal operation mode also. In this case also, use the
method described above.
(Note)
When the internal data memory is changed during in normal operation mode, retain the changed data for 250 s
or more since read operation is performed synchronized with a SYNC signal (8 kHz).
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Start write operation
CR1 = 00h
NO
YES
CR6 (Internal memory high-order address)
CR7 (Internal memory low-order address)
CR8 (Internal memory high-order data)
CR9 (Internal memory low-order data)
XDMWR = 1
Update the internal memory
XDMWR cleared automatically
Time from the setting XDMWR to “1”
to clearing it to “0”:
Initial mode: 20 µs max.
Normal operation: 250 µs max.
Setting externally
LSI internal automatic processing
Figure 52 Internal Data Memory Write Method (Single-Word)
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Write Method (Multiple Words)
When data is written to consecutive address spaces in the internal data memory, multiple-word (2N words)
continuous write operation is allowed.
1) Setting a starting address
Use the write method (single-word) in Figure 52 for setting a starting address.
Set address 00E9h in CR6-CR7. This address is for setting the starting address for writing multiple words.
Also set in CR8-CR9 the starting address (START_ADDRESS) of the internal data memory to which
multiple words are to be written.
By setting the internal data memory single-word write control register (XDMWR) to “1”, the
START_ADDRESS is written in address 00E9h in the internal data memory. After termination of write
operation, XDMWR is automatically cleared to “0”.
2) Writing data
After termination of START_ADDRESS write operation, data can be written consecutively in 2-word units
without setting the addresses individually using the following procedure.
Set in CR6-CR7 first word of the data to be written and 2nd word in CR8-CR9 and set the internal data
memory 2-word write control register (XDMWR_2) to “1”. By doing this, the first word is written in
START_ADDRESS+0 and the second word is written in START_ADDRESS+1. After termination of
write operation, XMWR_2 is automatically cleared to “0”.
Subsequently, repeat 2-word data write operation using the data write procedure that is described in 2) until
completion of write operation for 2N words. (The write destination addresses are updated automatically.)
Figure 53 shows the internal data memory write method (multiple words).
Write operation to the internal data memory is allowed in normal operation mode also. In this case also, use
the method described above.
(Note)
When the internal data memory is changed during normal operation mode, retain the changed data for 250 s
or more since read operation is performed synchronized with a SYNC signal (8 kHz).
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Start multiple-word (2N words) write operation
Set a starting address
(Write single-word)
NO
CR1 = 00h
YES
CR6 (Internal memory high-order address)
Set the internal data memory address for setting a
starting address
CR7 (Internal memory low-order address)
CR8 (Internal memory high-order data)
Set a starting
address(START_ADDRESS)
CR9 (Internal memory low-order data)
XDMWR = 1
Time from setting XDMWR to “1” to clearing it to “0”:
Initial mode: 20 µs max.
Normal operation: 250 µs max.
Update the internal memory
XDMWR is cleared automatically
2-word data write operation
NO
CR1 = 00h
YES
CR6 (Internal memory high-order data)
Set the data of (2n-1)th word
Write- destination address:
START_ADDRESS + (2n-2)
CR7 (Internal memory low-order data)
[n=1, 2,- ,N]
CR8 (Internal memory high-order data)
Set the data of the 2nd word
Write- destination address:
START_ADDRESS + (2n-1)
CR9 (Internal memory low-order data)
[n=1, 2, -, N]
XDMWR_2 = 1
Time from setting XDMWR_2 to “1” to clearing it to “0”:
Initial mode: 20 µs max.
Normal operation: 250 µs max.
Update the internal memory
XDMWR_2 is cleared automatically
NO
Has write operation of 2N
words been completed?
YES
Termination of multiple word (2N words) write operation
Set externally
LSI internal automatic processing
Figure 53 Internal Data Memory Write Method (Multiple Words)
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Read Method
By setting an internal data memory address in CR6 and CR7 and setting the internal memory read control
register (XDMRD) to “1”, single-word data in the internal data memory is stored in CR8 and CR9. After
termination of read operation, XDMRD is cleared to “0” automatically. Figure 54 shows the internal data
memory read method.
Internal data memory read operation is allowed only for the internal data memory that is shown in Table 14 and
read only data memory in the related registers.
Read operation for the internal data memory is allowed in normal operation mode also. In this case also, use
the method described above.
(Note)
When internal data memory is read in normal operation mode, maintain the address that was set for 250 sec or
more since read operation is performed synchronized with a SYNC signal (8 kHz).
Start read operation
CR1 = 00h
NO
YES
CR6 (Internal memory high-order address)
CR7 (Internal memory low-order address)
XDMRD = 1
XDMRD = 0
NO
YES
Read CR8 (Internal memory high-order data)
After read data is stored in CR8 and
CR9, the register is cleared to 0
automatically
Time from setting of XDMRD to “1”
to clearing it to “0”:
Initial mode: 20 µs max.
Normal operation: 250 µs max.
Read CR9 (Internal memory low-order data)
Setting and reading externally
Figure 54 Internal Data Memory Read Method
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Table 14 Internal Data Memory/Related Control Registers (1 of 7)
Function
name
Internal data memory/related control
register name
Gain
control
Transmit path related
Speech CODEC transmit gain
(TXGAIN_SC)
CODECA transmit gain (TXGAINA)
CODECB transmit gain (TXGAINB)
Receive path related
Speech CODEC receive gain
(RXGAIN_SC)
CODECA receive gain (RXGAINA)
CODECB receive gain (RXGAINB)
Side tone related
CODECA side tone gain (STGAINA)
CODECB side tone gain (STGAINB)
PCM related
PCM transmit gain0 (TXGAIN_PCM0)
PCM transmit gain1 (TXGAIN_PCM1)
PCM transmit gain2 (TXGAIN_PCM2)
PCM receive gain0 (RXGAIN_PCM0)
PCM receive gain1 (RXGAIN_PCM1)
PCM receive gain2 (RXGAIN_PCM2)
PCM input time slot selection 1 receive gain
(RXGAIN_ITS1)
PCM input time slot selection 2 receive gain
(RXGAIN_ITS2)
Three-way communication related
CH1 receive gain (RXGAIN_CH1)
CH2 receive gain (RXGAIN_CH2)
CH1 transmit gain (TXGAIN_CH1)
CH2 transmit gain (TXGAIN_CH2)
CH2 receiveCH1 transmit loop back gain
(RX2TX1_GAIN)
CH1 receiveCH2 transmit loop back gain
(RX1TX2_GAIN)
Fade control related
Gain fade control 0
(GAIN_FADE_CONT0)
Gain fade control 1
(GAIN_FADE_CONT1)
Gain fade control 2
(GAIN_FADE_CONT2)
Gain fade-in step value control
(GAIN_FADE_IN_ST)
Gain fade-out step value control
(GAIN_FADE_OUT_ST)
Initial value
Address
Change/read enable mode
Initial
mode
Inactive
Active
0 dB



0080h
0080h
0 dB
0 dB






05E8h
0080h
0 dB



05E5h
05E6h
0080h
0080h
0 dB
0 dB






05DFh
05E0h
0000h
0000h
MUTE
MUTE






05EAh
05E9h
05F1h
05EBh
05ECh
05F2h
0080h
0080h
0080h
0080h
0080h
0080h
0 dB
0 dB
0 dB
0 dB
0 dB
0 dB


















05EDh
0080h
0 dB



05EEh
0080h
0 dB



0132h
0131h
0134h
0133h
0080h
0080h
0080h
0080h
0 dB
0 dB
0 dB
0 dB












0136h
0080h
0 dB



0135h
0080h
0 dB



05F3h
0000h
Stop



0137h
0040h
Stop



05F4h
0000h
Stop



05F5h
4C10h
+1.5 dB

(*1)

05F6h
35D9h
1.5 dB

(*1)

Data
Data value
05E7h
0080h
05E3h
05E4h
(*1) Applies when the gain fade control is inactive.
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Table 14 Internal Data Memory/Related Control Registers (2 of 7)
Function
name
Tone
generation 0
TONE
_GEN0
Tone
generation 1
TONE
_GEN1
Internal data memory/related control
register name
TGEN0 transmit control register
TONE A frequency control (TGEN0_FREQ_A)
TONE B frequency control (TGEN0_FREQ_B)
TONE A gain control (TGEN0_GAIN_A)
TONE B gain control (TGEN0_GAIN_B)
TGEN0 output time control 0
(TGEN0_TIM_M0)
TGEN0 output time control 1
(TGEN0_TIM_M1)
TGEN0 RXAB side tone total gain control
(TGEN0_RXABGAIN_TOTAL)
TGEN0 RX side tone total gain control
(TGEN0_RXGAIN_TOTAL)
TGEN0 fade control
(TGEN0_FADE_CONT)
TGEN0 fade-in step value control
(TGEN0_FADE_IN_ST)
TGEN0 fade-out step value control
(TGEN0_FADE_OUT_ST)
TGEN0 fade-out time control
(TGEN0_FADE_OUT_TIM)
TGEN0 total gain fade control
(TGEN0_GAIN_TOTAL_FADE_CONT)
TGEN0 total gain fade-in step value control
(TGEN0_GAIN_TOTAL_FADE_IN_ST)
TGEN0 total gain fade-out step value control
(TGEN0_GAIN_TOTAL_FADE_OUT_ST)
TGEN0 execution flag display register
(TGEN0_EXFLAG)
TGEN1 transmit control register
TONE C frequency control (TGEN1_FREQ_C)
TONE D frequency control (TGEN1_FREQ_D)
TONE C gain control (TGEN1_GAIN_C)
TONE D gain control (TGEN1_GAIN_D)
TGEN1 output time control 0 (TGEN1_TIM_M0)
TGEN1 output time control 1 (TGEN1_TIM_M1)
TGEN1 RXAB side tone total gain control
(TGEN1_RXABGAIN_TOTAL)
TGEN1 TX side tone total gain control
(TGEN1_TXGAIN_TOTAL)
Initial value
Address
Data
Data value
Change/read enable
mode
Initial
Inactive Active
mode



0CCDh
007Bh
0080h
0080h
Stop
transmission
400Hz
15Hz
13.3 dBm0
13.3 dBm0












02E8h
0FA0h
500 ms



02EBh
0FA0h
500 ms



02EFh
0080h
0 dB



02F0h
0080h
0 dB



02DAh
0000h
Stop



02DBh
47CFh
+1 dB



02DCh
390Ah
1 dB



02DDh
002Bh
43 Sync



02ECh
0000h
Stop



02EDh
4C10h
+1.5 dB



02EEh
35D9h
1.5 dB



CR19
-B1
0b
Stop



CR3
00h
02F9h
02FBh
02FDh
02FEh
02FFh
0302h
CR2
00h
02E2h
02E4h
02E6h
02E7h



0CCDh
007Bh
0080h
0080h
0FA0h
0FA0h
Stop
transmission
400Hz
15Hz
13.3 dBm0
13.3 dBm0
500 ms
500 ms


















0306h
0080h
0 dB



0307h
0080h
0 dB



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Table 14 Internal Data Memory/Related Control Registers (3 of 7)
Function
name
Tone
generation 1
TONE
_GEN1
FSK
generator
FSK
_GEN
FSK
receiver
FSK
_DET
Internal data memory/related control
register name
TGEN1 fade control
(TGEN1_FADE_CONT)
TGEN1 fade-in step value control
(TGEN1_FADE_IN_ST)
TGEN1 fade-out step value control
(TGEN1_FADE_OUT_ST)
TGEN1 fade-out time control
(TGEN1_FADE_OUT_TIM)
TGEN1 total gain fade control
(TGEN1_GAIN_TOTAL_FADE_CONT)
TGEN1 total gain fade-in step value control
(TGEN1_GAIN_TOTAL_FADE_IN_ST)
TGEN1 total gain fade-out step value control
(TGEN1_GAIN_TOTAL_FADE_OUT_ST)
TGEN1 execution flag display register
(TGEN1_EXFLAG)
Initial value
Address
Data
Data value
02F1h
0000h
Stop



02F2h
47CFh
+1 dB



02F3h
390Ah
1 dB



02F4h
002Bh
43 Sync



0303h
0000h
Stop



0304h
4C10h
+1.5 dB



0305h
35D9h
1.5 dB



0b
Stop



0b
Stop












FSK output data setting completion flag display
register (FGEN_FLAG)
FSK output data setting register (FGEN_D[7:0])
CR19
-B2
CR28
-B6
CR17
-B0
CR27
00h
FSK gain control (FGEN_GAIN)
0230h
0080h
FSK_GEN control register (FGEN_EN)
FSK_DET control register (FDET_EN)
Change/read enable mode
Initial
Inactive Active
mode
CR28
-B7
CR16
-B0
CR16
-B1
CR16
-B2
0b
Write
enable
00h
13.3
dBm0
0b
Stop



0b
No request



0b
No error



0b
No error



CR25
00h
00h



FSK detection level control (FDET_TH)
02B5h
1000h
39.3
dBm0



FSK receive mark guard time control
(FSK_MK_GT)
02CAh
00F0h
30 ms



FSK receive data read request notification
register (FDET_RQ)
FSK receive framing error notification register
(FDET_FER)
FSK receive overrun error notification register
(FDET_OER)
FSK receive data storage register
(FDET_D[7:0])
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Table 14 Internal Data Memory/Related Control Registers (4 of 7)
Function
name
TONE0
detector
TONE
_DET0
TONE1
detector
TONE
_DET1
DTMF
detector
DTMF
_REC
Internal data memory/related control
register name
TONE0 detector control register
(TDET0_EN)
TONE0 detector detection status register
(TONE0_DET)
TDET0 main signal detection level control
(TDET0_S_TH)
TDET0 noise detection level control
(TDET0_N_TH)
TDET0 detection ON guard timer control
(TDET0_ON_TM)
TDET0 detection OFF guard timer control
(TDET0_OFF_TM)
TDET0 detection frequency
(TDET0_FREQ)
TONE1 detector control register
(TDET1_EN)
TONE1 detector detection status register
(TONE1_DET)
TDET1 main signal detection level control
(TDET1_S_TH)
TDET1 noise detection level control
(TDET1_N_TH)
TDET1 detection ON guard timer control
(TDET1_ON_TM)
TDET1 detection OFF guard timer control
(TDET1_OFF_TM)
TDET1 detection frequency
(TDET1_FREQ)
DTMF detector control register (DTMF_EN)
DTMF code display register
(DTMF_CODE[3:0])
DTMF detector detection status register
(DTMF_DET)
DTMF detection level control (DTMF_TH)
DTMF detection ON guard timer
(DTMF_ON_TM)
DTMF detection OFF guard timer
(DTMF_OFF_TM)
DTMF noise detection function control
(DTMF_NDET_CONT)
Echo
canceler
Echo canceler control register (EC_EN)
Echo canceler control (EC_CR)
GLPAD control (GLPAD_CR)
Initial value
Address
Change/read enable mode
Initial
mode
Inactive
Active
Stop



0b
Non-detection



134Ch
1EBBh
5.3 dBm0



1361h
1EBBh
5.3 dBm0



1362h
0028h
5 ms



1363h
0028h
5 ms



----h
—
1650Hz



CR28-B4
0b
Stop



CR19-B4
0b
Non-detection



1378h
1EBBh
5.3 dBm0



138Dh
1EBBh
5.3 dBm0



138Eh
0028h
5 ms



138Fh
0028h
5 ms



----h
—
2100Hz



CR28-B2
CR20B[3:0]
0b
Stop



0000b
0000b



CR20-B4
0b
Non-detection



018Dh
1000h
37.0 dBm0



01F2h
00A0h
20 ms



01F4h
00A0h
20 ms



01F5h
0002h



CR28-B1
002Ch
002Dh
0b
0012h
000Fh









Data
Data value
CR28-B3
0b
CR19-B3
Noise
detection
enabled
Stop
HD ATT OFF
+6/6 dB
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Table 14 Internal Data Memory/Related Control Registers (5 of 7)
Function
name
Internal data memory/related control
register name
RC0
RC0 control (RC0_CR)
RC0 threshold 1 for loss (RC0_TH1)
RC0 threshold 2 for loss (RC0_TH2)
RC0 threshold 3 for loss (RC0_TH3)
RC0 threshold 4 for loss (RC0_TH4)
RC0 loss value in the case of threshold 1 or
2 for loss
(RC0_LOSS1)
RC0 loss value in the case of threshold 2 or
3 for loss
(RC0_LOSS2)
RC0 loss value in the case of threshold 3 or
4 for loss
(RC0_LOSS3)
RC0 loss value in the case of threshold 4 or
less for loss
(RC0_LOSS4)
RC0 plus step value (RC0_PL)
RC0 minus step value(RC0_MI)
RC0 input signal level detecting sensitivity 1
(RC0_POW_C1)
RC0 input signal level detecting sensitivity 2
(RC0_POW_C2)
RC1 control (RC1_CR)
RC1 threshold 1 for loss (RC1_TH1)
RC1 threshold 2 for loss (RC1_TH2)
RC1 threshold 3 for loss (RC1_TH3)
RC1 threshold 4 for loss (RC1_TH4)
RC1 loss value in the case of threshold 1 or
2 for loss
(RC1_LOSS1)
RC1 loss value in the case of threshold 2 or
3 for loss
(RC1_LOSS2)
RC1 loss value in the case of threshold 3 or
4 for loss
(RC1_LOSS3)
RC1 loss value in the case of threshold 4 or
less for loss
(RC1_LOSS4)
RC1 plus step value (RC1_PL)
RC1 minus step value(RC1_MI)
RC1 input signal level detecting sensitivity 1
(RC1_POW_C1)
RC input signal level detecting sensitivity 2
(RC1_POW_C2)
RC1
Initial value
Address
Change/read enable mode
Initial
Inactive
Active
mode















Data
Data value
00E6h
11C6h
11C7h
11C8h
11C9h
0000h
0090h
0051h
002Dh
000Eh
Stop
–40dBm0
–45dBm0
–50dBm0
–60dBm0
11CBh
005Ah
3dB



11CCh
0040h
6dB



11CDh
0020h
12dB



11CEh
0020h
12dB



11CFh
11D0h
47CFh
3F44h
1dB/SYNC
–0.1dB/SYNC






11C4h
3E00h
—



11C5h
0200h
—



00E7h
11D3h
11D4h
11D5h
11D6h
0000h
0090h
0051h
002Dh
000Eh
Stop
–40dBm0
–45dBm0
–50dBm0
–60dBm0















11D8h
005Ah
3dB



11D9h
0040h
6dB



11DAh
0020h
12dB



11DBh
0020h
12dB



11DCh
11DDh
47CFh
3F44h
1dB/SYNC
–0.1dB/SYNC






11D1h
3E00h
—



11D2h
0200h
—



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Table 14 Internal Data Memory/Related Control Registers (6 of 7)
Function
name
Internal data memory/related control
register name
Dial pulse
detector
DPDET
Dial pulse detector control register
(DPDET_EN)
Dial pulse detector detection status register
(DP_DET)
Dial pulse detection polarity control register
(DPDET_POL)
Detection dial pulse count display register
(DPDET_DATA[7:0])
Dial pulse detection ON guard timer control
(DPDET_ON_TIM)
Dial pulse detection OFF guard timer
control
(DPDET_OFF_TIM)
Detection termination timer control
(DPDET_DETOFF_TIM)
Dial pulse transmit control register
(DPGEN_EN)
Dial pulse count setting register
(DPGEN_DATA[3:0])
Dial pulse speed control register
(DPGEN_PPS)
Dial pulse output polarity control register
(DPGEN_POL)
Dial pulse make rate control
(DPGEN_DUTY)
Dial pulse output termination control
(DPGEN_OFF_TIM)
Timer control register (TIM_EN)
Timer overflow display register (TMOVF)
Timer counter value display (TIM_COUNT)
(Read Only data memory)
Timer data setting (TIM_DATA)
Dial pulse
transmitter
DPGEN
TIMER
Outband
control
Outband
G.729.Adata
Initial value
Address
Change/read enable mode
Initial
mode
Inactive
Active
Stop



0b
Non-detection



CR43-B1
0b
Positive logic



CR26
00h
Non-detection



13F7h
0028h
5 ms



13F8h
0028h
5 ms



0743h
03E8h
125 ms



CR29-B6
0b
Stop



CR29B[3:0]
0000b
Stop



CR29-B4
0b
10pps



CR29-B5
0b
Positive logic



016Bh
0108h
33 ms



016Dh
03E8h
125 ms



CR28-B5
CR18-B0
0b
0b
Stop
Stop/active






13BEh
0000h
Count value



13BFh
FFFFh
FFFFh max.



Outband control (OUTBAND_CONTROL)
021Dh
0000h
Stop



Outband G.729.A data
(OUTBAND_G729_DAT)
089Fh
08A0h
08A1h
08A2h
08A3h
7852h
80A0h
00FAh
C200h
07D6h
—



Data
Data value
C43-B0
0b
CR20-B6
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Table 14 Internal Data Memory/Related Control Registers (7 of 7)
Function
name
Interrupt
mask
control
Internal data memory/related control
register name
Rise mask control
CR16 rising edge interrupt mask control
(CR16_INTP_MSKCNT)
CR18 rising edge interrupt mask control
(CR18_INTP_MSKCNT)
CR19 rising edge interrupt mask control
(CR19_INTP_MSKCNT)
CR20 rising edge interrupt mask control
(CR20_INTP_MSKCNT)
CR21 rising edge interrupt mask control
(CR21_INTP_MSKCNT)
CR22 rising edge interrupt mask control
(CR22_INTP_MSKCNT)
Fall mask control
CR17 falling edge interrupt mask control
(CR17_INTN_MSKCNT)
CR19 falling edge interrupt mask control
(CR19_INTN_MSKCNT)
CR20 falling edge interrupt mask control
(CR20_INTN_MSKCNT)
CR21 falling edge interrupt mask control
(CR21_INTN_MSKCNT)
CR22 falling edge interrupt mask control
(CR22_INTN_MSKCNT)
Initial value
Address
Data
002Fh
00F8h
0031h
00FEh
0032h
0060h
0034h
0020h
0036h
00F0h
0038h
00F0h
0030h
00FEh
0033h
0060h
0035h
0020h
0037h
00F3h
0039h
00F1h
Data value
Mask setting
OFF
Mask setting
OFF
Mask setting
OFF
Mask setting
OFF
Mask setting
OFF
Mask setting
OFF
Mask setting
OFF
Mask setting
OFF
Mask setting
OFF
Mask setting
OFF
Mask setting
OFF
Change/read enable mode
Initial
mode
Inactive
Active

































Speech
CODEC
decoding
control
Decoding output start offset time control
(DEC_ONTIM)
0108h
0000h
(*1)
0 ms



Internal
RAM write
Multiple-word write starting address setting
(START_ADDRESS)
00E9h
0000h
0000h



(Remarks)
Initial mode:
Indicates the state in which the initial values of the control register and internal data memory can be
changed after power-down reset is released.
Inactive: Indicates the state in which the function indicated by the function name is inactive.
Active: Indicates the state in which the function indicated by the function name is active.
: Related control register
*1: Though 0000h (0 ms) is set as the initial value, be sure to set an offset time of 0001h (0.125 ms) to
0100h (32 ms).
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Gain Control
A. Transmit path related gain
A-1: Internal data memory for adjustment of Speech CODEC transmit gain (TXGAIN_SC)
Initial value: 0080h (0.0 dB)
Use the following calculation expression when changing the amount of gain.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: Approx. +40 dB (Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: Approx. 42 dB (Data: 0001h)
: MUTE
(Data: 0000h)
A-2: Internal data memory for adjustment of CODECA transmit gain (TXGAINA)
Initial value: 0080h (0.0 dB)
Use the following calculation expression when changing the amount of gain.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: Approx. +40 dB (Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: Approx. 42 dB (Data: 0001h)
: MUTE
(Data: 0000h)
A-3: Internal data memory for adjustment of CODECB transmit gain (TXGAINB)
Initial value: 0080h (0.0 dB)
Use the following calculation expression when changing the amount of gain.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: Approx. +40 dB (Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: Approx. 42 dB (Data: 0001h)
: MUTE
(Data: 0000h)
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B. Receive path related gain
B-1: Internal data memory for adjustment of Speech CODEC receive gain (RXGAIN_SC)
Initial value: 0080h (0.0 dB)
Use the following calculation expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: Approx. +40 dB (Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: Approx. 42 dB (Data: 0001h)
: MUTE
(Data: 0000h)
B-2: Internal data memory for adjustment of CODECA receive gain (RXGAINA)
Initial value: 0080h (0.0 dB)
Use the following calculation expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: Approx. +40 dB (Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: Approx. 42 dB (Data: 0001h)
: MUTE
(Data: 0000h)
B-3: Internal data memory for adjustment of CODECB receive gain (RXGAINB)
Initial value: 0080h (0.0 dB)
Use the following calculation expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: Approx. +40 dB (Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: Approx. 42 dB (Data: 0001h)
: MUTE
(Data: 0000h)
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C. Side tone gain
C-1: Internal data memory for adjustment of CODECA side tone gain (STGAINA)
Initial value: 0000h (MUTE)
Use the following calculation expression when changing the side tone gain amount.
Calculation expression: 1000hGAIN
<Example> Set the gain amount to 20 dB (0.1)
1000h0.1 = 019Ah
Upper limit: 0 dB
(Data: 1000h)
Lower limit: Approx. 72 dB (Data: 0001h)
: MUTE
(Data: 0000h)
C-2: Internal data memory adjustment for CODECB side tone gain (STGAINB)
Initial value: 0000h (MUTE)
Use the following calculation expression when changing the side tone gain amount.
Calculation expression: 1000hGAIN
<Example> Set the gain amount to 20 dB (0.1).
1000h0.1 = 019Ah
Upper limit: 0 dB
(Data: 1000h)
Lower limit: Approx. 72 dB (Data: 0001h)
: MUTE
(Data: 0000h)
D. PCM related gain
D-1: Internal data memory for adjustment of PCM transmit gain 0 (TXGAIN_PCM0)
Initial value: 0080h (0.0 dB)
Use the following expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: Approx. +40 dB (Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: Approx. 42 dB (Data: 0001h)
: MUTE
(Data: 0000h)
D-2: Internal data memory for adjustment of PCM transmit gain 1 (TXGAIN_PCM1)
Initial value: 0080h (0.0 dB)
Use the following expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: Approx. +40 dB (Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: Approx. 42 dB (Data: 0001h)
: MUTE
(Data: 0000h)
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D-3: Internal data memory for adjustment of PCM transmit gain 2 (TXGAIN_PCM2)
Initial value: 0080h (0.0 dB)
Use the following expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: Approx. +40 dB (Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: Approx. 42 dB (Data: 0001h)
: MUTE
(Data: 0000h)
D-4: Internal data memory for adjustment of PCM receive gain 0 (RXGAIN_PCM0)
Initial value: 0080h (0.0 dB)
Use the following expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: Approx. +40 dB (Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: Approx. 42 dB (Data: 0001h)
: MUTE
(Data: 0000h)
D-5: Internal data memory for adjustment of PCM receive gain 1 (RXGAIN_PCM1)
Initial value: 0080h (0.0 dB)
Use the following expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: Approx. +40 dB (Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: Approx. 42 dB (Data: 0001h)
: MUTE
(Data: 0000h)
D-6: Internal data memory for adjustment of PCM receive gain 2 (RXGAIN_PCM2)
Initial value: 0080h (0.0 dB)
Use the following expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: Approx. +40 dB (Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: Approx. 42 dB (Data: 0001h)
: MUTE
(Data: 0000h)
D-7: Internal data memory for adjustment of PCM input time slot selection 1 receive gain (RXGAIN_ITS1)
Initial value: 0080h (0.0 dB)
Use the following expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: Approx. +40 dB (Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: Approx. 42 dB (Data: 0001h)
: MUTE
(Data: 0000h)
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D-8: Internal data memory for adjustment of PCM input time slot selection 2 receive gain (RXGAIN_ITS2)
Initial value: 0080h (0.0 dB)
Use the following expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: Approx. +40 dB (Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: Approx. 42 dB (Data: 0001h)
: MUTE
(Data: 0000h)
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E. Gain related to three-way communication
E-1: Internal data memory for adjustment of CH1 receive gain (RXGAIN_CH1)
A receive gain at single channel operation (SC_EN = 1, DC_EN = 0) in Speech CODEC and a channel 1
receive gain at 2-channel operation (SC_EN-1, DC_EN = 1) can be set.
Initial value: 0080h (0.0 dB)
Use the following calculation expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: About +40 dB
(Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: About 42 dB
(Data: 0001h)
: MUTE
(Data: 0000h)
E-2: Internal data memory for adjustment of CH2 receive gain (RXGAIN_CH2)
A channel 2 receive gain at 2-channel operation (SC_EN-1, DC_EN = 1) in Speech CODEC can be set.
Initial value: 0080h (0.0 dB)
Use the following calculation expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: About +40 dB
(Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: About 42 dB
(Data: 0001h)
: MUTE
(Data: 0000h)
E-3: Internal data memory for adjustment of CH1 transmit gain (TXGAIN_CH1)
A transmit gain at single channel operation (SC_EN = 1, DC_EN = 0) in Speech CODEC and a channel 1
transmit gain at 2-channel operation (SC_EN-1, DC_EN = 1) can be set.
Initial value: 0080h (0.0 dB)
Use the following calculation expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: About +40 dB
(Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: About 42 dB
(Data: 0001h)
: MUTE
(Data: 0000h)
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E-4: Internal data memory for adjustment of CH2 transmit gain (TXGAIN_CH2)
A transmit gain of channel 2 at 2-channel operation (SC_EN = 1, DC_EN = 1) in Speech CODEC can be
set.
Initial value: 0080h (0.0 dB)
Use the following calculation expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: About +40 dB
(Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: About 42 dB
(Data: 0001h)
: MUTE
(Data: 0000h)
E-5: Internal data memory for adjustment of CH2 receiveCH1 transmit loop back gain (RX2TX1_GAIN)
Initial value: 0080h (0.0 dB)
Use the following calculation expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: About +40 dB
(Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: About 42 dB
(Data: 0001h)
: MUTE
(Data: 0000h)
E-6: Internal data memory for adjustment of CH1 receiveCH2 transmit loop back gain (RX1TX2_GAIN)
Initial value: 0080h (0.0 dB)
Use the following calculation expression when changing the gain amount.
Calculation expression: 0080hGAIN
<Example> Set the gain amount to +6 dB (2).
0080h2 = 0100h
Upper limit: About +40 dB
(Data: 3200h)
: 0 dB
(Data: 0080h)
Lower limit: About 42 dB
(Data: 0001h)
: MUTE
(Data: 0000h)
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F. Gain fade control internal data memory (GAIN_FADE_CONT0/GAIN_FADE_CONT1)
This LSI is equipped with the function for attenuating or amplifying (gain fade-in/fade-out function) signals to
the required gain when a gain amount is changed, except for STGAINA and STGAINB.
F-1: Gain fade control internal data memory 0 (GAIN_FADE_CONT0)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
RXGAIN_
ITS1_FC
RXGAIN_
PCM1_FC
RXGAIN_
PCM0_FC
TXGAIN_
PCM1_FC
TXGAIN_
PCM0_FC
Name
—
—
RXGAIN_
ITS2_FC
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name
OUT
BAND_FC
—
RXGAINB
_FC
RXGAINA
_FC
RXGAIN
_SC_FC
TXGAINB
_FC
TXGAINA
_FC
TXGAIN
_SC_FC
Initial value
0
0
0
0
0
0
0
0
B15-B14: Reserved bits Changing of the initial values is inhibited.
B13: RXGAIN_ITS2_FADECONT control
1: ON (Performs fade-in/fade-out processing when RXGAIN_ITS2 is modified)
0: OFF
B12: RXGAIN_ITS1_FADECONT control
1: ON (Performs fade-in/fade-out processing when RXGAIN_ITS1 is modified)
0: OFF
B11: RXGAIN_PCM1_FADECONT control
1: ON (Performs fade-in/fade-out processing when RXGAIN_PCM1 is modified)
0: OFF
B10: RXGAIN_PCM0_FADECONT control
1: ON (Performs fade-in/fade-out processing when RXGAIN_PCM0 is modified)
0: OFF
B9: TXGAIN_PCM1_FADECONT control
1: ON (Performs fade-in/fade-out processing when TXGAIN_PCM1 is modified)
0: OFF
B8: TXGAIN_PCM0_FADECONT control
1: ON (Performs fade-in/fade-out processing when TXGAIN_PCM0 is modified)
0: OFF
B7: OUTBAND_FADE_CONT control
1: ON (Performs fade-in/fade-out processing at transition to MUTE processing or returning to
MUTE processing)
0: OFF
B6: Reserved bit
Changing of the initial value is inhibited.
B5: RXGAINB _FADECONT control
1: ON (Performs fade-in/fade-out processing at modification of RXGAINB)
0: OFF
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B4: RXGAINA _FADECONT control
1: ON (Performs fade-in/fade-out processing at modification of RXGAINA)
0: OFF
B3: RXGAIN_SC_FADECONT control
1: ON (Performs fade-in/fade-out processing at modification of RXGAIN_SC)
0: OFF
B2: TXGAINB _FADECONT control
1: ON (Performs fade-in/fade-out processing at modification of TXGAINB)
0: OFF
B1: TXGAINA _FADECONT control
1: ON (Performs fade-in/fade-out processing at modification of TXGAINA)
0: OFF
B0: TXGAIN_SC_FADECONT control
1: ON (Performs fade-in/fade-out processing at modification of TXGAIN_SC)
0: OFF
F-2: Gain fade control internal data memory 1 (GAIN_FADE_CONT1)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name








Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name


RX1TX2_
GAIN_FC
RX2TX1_
GAIN_FC
RXGAIN_
CH2_FC
RXGAIN_
CH1_FC
TXGAIN_
CH2_FC
TXGAIN_
CH1_FC
Initial value
0
1
0
0
0
0
0
0
B15-B6: Reserved bits
Changing of the initial values is inhibited.
B5: RX1TX2_GAIN_FADECONT control
1: ON (Performs fade-in/fade-out processing at modification of RX1TX2_GAIN)
0: OFF
B4: RX2TX1_GAIN_FADECONT control
1: ON (Performs fade-in/fade-out processing at modification of RX2TX1_GAIN)
0: OFF
B3: RXGAIN_CH2_FADECONT control
1: ON (Performs fade-in/fade-out processing at modification of RXGAIN_CH2)
0: OFF
B2: RXGAIN_CH1_FADECONT control
1: ON (Performs fade-in/fade-out processing at modification of RXGAIN_CH1)
0: OFF
B1: TXGAIN_CH2_FADECONT control
1: ON (Performs fade-in/fade-out processing at modification of TXGAIN_CH2)
0: OFF
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B0: TXGAIN_CH1_FADECONT control
1: ON (Performs fade-in/fade-out processing at modification of TXGAIN_CH1)
0: OFF
F-3: Gain fade control internal data memory 2 (GAIN_FADE_CONT2)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name








Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
RXGAIN_
PCM2_FC
0
Name






TXGAIN_
PCM2_FC
Initial value
0
1
0
0
0
0
0
B15-B2: Reserved bits
Changing of the initial values is inhibited.
B1: TXGAIN_PCM2_FADECONT control
1: ON (Performs fade-in/fade-out processing at modification of TXGAIN_PCM2)
0: OFF
B0: RXGAIN_PCM2_FADECONT control
1: ON (Performs fade-in/fade-out processing at modification of RXGAIN_PCM2)
0: OFF
G. Gain fade-in step value control internal data memory (GAIN_FADE_IN_ST)
Initial value: 4C10h (+1.5 dB)
Use the following calculation expression when changing step amount X.
Calculation expression: 10(X/20)  16384
<Example> Set the step value to +3 dB.
10(3/20)  16384 = 23143d = 5A67h
Maximum step value: +6.0 dB (Data: 7FB2h)
Minimum step value: +0.1 dB (Data: 40BEh)
H. Gain fade-out step value control internal data memory (GAIN_FADE_OUT_ST)
Initial value: 35D9h (1.5 dB)
Use the following calculation expression when changing step amount X.
Calculation expression: 10(X/20)  16384
<Value> Set the step value to –3 dB.
10(3/20)  16384 = 11599d = 2D4Fh
Maximum step value: 6.0 dB (Data: 2013h)
Minimum step value: 0.1 dB (Data: 3F44h)
(Supplementary information) Step values of fade-in and fade-out can be set separately; however, the parameters
that are set are commonly used by all the gain controllers for which fade-in/fade-out processing is enabled.
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Tone Generator 0 (TONE_GEN0)
Various parameters of tone generator 0 can be set.
A. Tone frequency control internal data memory
TONE A frequency control (TGEN0_FREQ_A)
Initial value: 0CCDh (400 Hz)
TONE B frequency control (TGEN0_FREQ_B)
Initial value: 007Bh (15 Hz)
For the initial values, tone of 400 Hz is output as TONE A and tone of 15 Hz as TONE B. Use the
following calculation expression when changing the frequency.
Calculation expression: f  8.192 (f: Desired frequency)
<Example> Frequency = 2100 Hz
2100  8.192  4333h
Upper limit: 3 kHz
(Data: 6000h)
Lower limit: 15 Hz
(Data: 007Bh)
B. Tone gain control internal data memory
TONE A gain control (TGEN0_GAIN_A)
Initial value: 0080h
TONE B gain control (TGEN0_GAIN_B)
Initial value: 0080h
The initial value of the output level is -13.3 dBm0. Use the following calculation expression when
changing the output level.
Calculation expression: 0080h  GAIN
<Example> Reduce the gain amount by 6 dB (0.5).
0080h  0.5 = 0040h
Upper limit: +12 dB
(Data: 01FEh)
Lower limit: 12 dB
(Data: 0020h)
(Note)
The result of multiplication or addition of each tone must not exceed the maximum amplitude 3.17 dBm0.
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C. Tone output time control internal data memory (TGEN0_TIM_M0/TGEN0_TIM_M1)
TGEN0 output time control 0 (TGEN0_TIM_M0)
Initial value: 0FA0h (500 ms)
TGEN0 output time control 1 (TGEN0_TIM_M1)
Initial value: 0FA0h (500 ms)
Use the following calculation expression when changing the value.
Calculation expression: T/0.125 (T: Time in ms)
<Example> Time = 200 ms is set.
200/0.125 = 1600d = 0640h
Upper limit: 4095.875 ms
(Data: 7FFFh)
Lower limit: 0.125 ms
(Data: 0001h)
(Note)
The setting of 0000h (0 ms) is inhibited.
D. Tone total gain control internal data memory (TGEN0_RXABGAIN_TOTAL/TGEN0_RXGAIN_TOTAL)
TGEN0 RXAB side tone total gain control (TGEN0_RXABGAIN_TOTAL)
Initial value: 0080h
TGEN0 RX side tone total gain control (TGEN0_RXGAIN_TOTAL)
Initial value: 0080h
The initial value is 0 dB. Use the following calculation expression when changing the output level.
Calculation expression: 0080h  GAIN
<Example> Reduce the output level by 6 dB.
0080h  0.5 = 0040h
Upper limit: +40 dB
(Data: 3200h)
Lower limit: 40 dB
(Data: 0001h)
: MUTE
(Data: 0000h)
(Note)
The amplitude must not exceed the maximum amplitude 3.17 dBm0.
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E. TGEN0 fade control internal data memory (TGEN0_FADE_CONT)
Initial value: 0000h (Stop)
The fade-in/fade-out function of TGEN0 gain control can be activated by setting “0001h” in this data
memory.
0000h: Stops the fade-in/fade-out function.
0001h: Activates the fade-in/fade-out function
(Note)
When using this control function, set a correct fade-out time.
F. TGEN0 fade-in step value control internal data memory (TGEN0_FADE_IN_ST)
Initial value: 47CFh (+1.0 dB)
Use the following calculation expression when changing step amount X.
Calculation expression: 10(X/20)  16384
<Example> Set the step value to +3 dB.
10(3/20)  16384 = 23143d = 5A67h
Maximum step value: +6.0 dB (Data: 7FB2h)
Minimum step value: +0.1 dB (Data: 40BEh)
G. TGEN0 fade-out step value control internal data memory (TGEN0_FADE_OUT_ST)
Initial value: 390Ah (1.0 dB)
Use the following calculation expression when changing step amount X.
Calculation expression: 10(X/20)  16384
<Example> Set the step value to –3 dB.
10(3/20)  16384 = 11599d = 2D4Fh
Maximum step value: 6.0 dB (Data: 2013h)
Minimum step value: 0.1 dB (Data: 3F44h)
H. TGEN0 fade-out time control internal data memory (TGEN0_FADE_OUT_TIM)
Initial value: 002Bh (43 Sync)
Use the following calculation expression when changing the fade-out time.
Calculation expression: 43 dB/“fade-out step value” dB
<Example> The step value is 2 dB.
43/2 = 22d = 16h
Upper limit: 430 Sync
(Data: 01AEh)
Lower limit: 8 Sync
(Data: 0008h)
(Note)
Do not set 0000h since the value is inhibited.
The condition, fade-out time<TIM_M0,TIM_M1, must be observed.
(Supplementary information) Step values can be set individually; however, the parameters that are set
are commonly used for TONE_A and TONE_B. In addition, the operation control and stop time
parameters are commonly used for TONE_A and TONE_B.
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I. TGEN0 total gain fade control internal data memory (TGEN0_GAIN_TOTAL_FADE_CONT)
Initial value: 0000h (Stop)
The fade-in/fade-out function of the RXAB side/RX side total gain control can be activated by setting
“0001h” in this data memory.
0000h: Stops the fade-in/fade-out function.
0001h: Activates the fade-in/fade-out function.
J. TGEN0 total gain fade-in step value control internal data memory (TGEN0_GAIN_TOTAL_FADE_IN_ST)
Initial value: 4C10h (+1.5 dB)
Use the following calculation expression when changing step amount X.
Calculation expression: 10(X/20)  16384
<Example> Set the step value to +3 dB.
10(3/20)  16384 = 23143d = 5A67h
Maximum step value: +6.0 dB (Data: 7FB2h)
Minimum step value: +0.1 dB (Data: 40BEh)
K. TGEN0 total gain fade-output step value control internal data memory
(TGEN0_GAIN_TOTAL_FADE_OUT_ST)
Initial value: 35D9h (1.5 dB)
Use the following calculation expression when changing step amount X.
Calculation expression: 10(X/20)  16384
<Example> Set the step value to –3 dB.
10(3/20)  16384 = 11599d = 2D4Fh
Maximum step value: 6.0 dB (Data: 2013h)
Minimum step value: 0.1 dB (Data: 3F44h)
(Supplementary information) Step values can be set individually. However, the parameters that are set
are commonly used for TGEN0_RXABGAIN_TOTAL and TGEN0_RXGAIN_TOTAL.
The operation control is also commonly used for TGEN0_RXABGAIN_TOTAL and
TGEN0_RXGAIN_TOTAL.
L. TGEN0 execution flag display register (TGEN0_EXFLAG)
TGEN0_EXFLAG is set to “1” while the tone generator is active. (Initial value “0”: Inactive)
CR2="00h"
TGEN0 operation
Execution flag
(TGEN0_EXFLAG)
INTB
(Pin output)
Tone signal
TGEN0_FADE_CONT OFF
CR2="00h"
TGEN0 operation
Execution flag
(TGEN0_EXFLAG)
INTB
(Pin output)
Tone signal
TGEN0_FADE_CONT ON
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Tone Generator 1 (TONE_GEN1)
Various parameters of tone generator 1 can be set.
A. Tone frequency control internal data memory
TONE C frequency control (TGEN1_FREQ_C)
Initial value: 0CCDh (400 Hz)
TONE D frequency control (TGEN1_FREQ_D)
Initial value: 007Bh (15 Hz)
As the initial values, a tone of 400 Hz is output for TONE C and a tone of 15 Hz is output for TONE D.
Use the following calculation expression when changing the frequency.
Calculation expression: f  8.192 (f: Frequency to be set)
<Example> Frequency = 2100 Hz
2100  8.192  4333h
Upper limit: 3kHz
(Data: 6000h)
Lower limit: 15Hz
(Data: 007Bh)
B. Tone gain control internal data memory
TONE C gain control (TGEN1_GAIN_C)
Initial value: 0080h
TONE D gain control (TGEN1_GAIN_D)
Initial value: 0080h
The initial value of the output level is 13.3 dBm0. Use the following calculation expression when
changing the output level.
Calculation expression: 0080h  GAIN
<Example> Reduce the gain amount by 6 dB ( 0.5).
0080h  0.5 = 0040h
Upper limit: +12 dB
(Data: 01FEh)
Lower limit: 12 dB
(Data: 0020h)
(Note)
The result of multiplication or addition of each tone must not exceed the maximum amplitude 3.17 dBm0.
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C. Tone output time control internal data memory (TGEN1_TIM_M0/TGEN1_TIM_M1)
TGEN1 output time control 0 (TGEN1_TIM_M0)
Initial value: 0FA0h (500 ms)
TGEN1 output time control 1 (TGEN1_TIM_M1)
Initial value: 0FA0h (500 ms)
Use the following calculation expression when changing the value.
Calculation expression : T/0.125 (T: Time in ms)
<Example> Time = 200 ms is set.
200/0.125 = 1600d = 0640h
Upper limit: 4095.875 ms
(Data: 7FFFh)
Lower limit: 0.125 ms
(Data: 0001h)
(Note)
Do not set 0000h (0 ms) as the time since the value is inhibited.
D. Tone total gain control internal data memory (TGEN1_RXABGAIN_TOTAL/TGEN1_TXGAIN_TOTAL)
TGEN1 RXAB side tone total gain control (TGEN1_RXABGAIN_TOTAL)
Initial value: 0080h
TGEN TX side tone total gain control (TGEN1_TXGAIN_TOTAL)
Initial value: 0080h
The initial value is 0 dB. Use the following calculation expression when changing the output level.
Calculation expression: 0080h  GAIN
<Example> Reduce the output level by 6 dB.
0080h  0.5 = 0040h
Upper limit
: +40 dB
(Data: 3200h)
Lower limit
: –40 dB
(Data: 0001h)
: MUTE
(Data: 0000h)
(Note)
The amplitude must not exceed the maximum amplitude 3.17 dBm0.
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E. TGEN1 fade control internal data memory (TGEN1_FADE_CONT)
Initial value: 0000h (Stop)
By setting “0001h” in this data memory, the fade-in/fade-output function of TGEN1 gain control can be
activated.
0000h: Stops the fade-in/fade-out function.
0001h: Activates the fade-in/fade-out function.
(Note)
When using this control function, set a correct fade-out time.
F. TGEN1 fade-in step value control internal data memory (TGEN1_FADE_IN_ST)
Initial value: 47CFh (+1.0 dB)
Use the following calculation expression when changing step amount X.
Calculation expression: 10(X/20)  16384
<Example> Set the step value to +3 dB.
10(3/20)  16384 = 23143d = 5A67h
Maximum step value: +6.0 dB (Data: 7FB2h)
Minimum step value: +0.1 dB (Data: 40BEh)
G. TGEN1 fade-out step value control internal data memory (TGEN1_FADE_OUT_ST)
Initial value: 390Ah (–1.0 dB)
Use the following calculation expression when changing step amount X.
Calculation expression: 10(X/20)  16384
<Example> Set the step value to –3 dB.
10(3/20)  16384 = 11599d = 2D4Fh
Maximum step value: –6.0 dB (Data: 2013h)
Minimum step value: –0.1 dB (Data: 3F44h)
H. TGEN1 fade-out time control internal data memory (TGEN1_FADE_OUT_TIM)
Initial value: 002Bh (43 Sync)
Use the following calculation expression when changing the fade-out time.
Calculation expression: 43 dB/“fade-out step value” dB
<Example> The step value is 2 dB.
43/2 = 22d = 16h
Upper limit: 430 Sync
(Data: 01AEh)
Lower limit: 8 Sync
(Data: 0008h)
(Note)
Do not set 0000h since the value is inhibited.
The condition, fade-out timeTIM_M0, TIM_M1, must be observed.
(Supplementary information) Step values can be set individually. However, the parameters that are set
are commonly used for TONE_C and TONE_D. The operation control and stop time parameters are
also commonly used for TONE_C and TONE_D.
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I. TGEN1 total gain fade control internal data memory (TGEN1_GAIN_TOTAL_FADE_CONT)
Initial value: 0000h (Stop)
By setting “0001h” in this data memory, the fade-in/fade-out of RXAB side/TX side total gain control can
be activated.
0000h: Stops the fade-in/fade-out function.
0001h: Activates the fade-in/fade-out function.
J. TGEN1 total gain fade-in step value control internal data memory (TGEN1_GAIN_TOTAL_FADE_IN_ST)
Initial value: 4C10h (+1.5 dB)
Use the following calculation expression when changing step amount X.
Calculation expression: 10(X/20)  16384
<Example> Set the step value to +3 dB.
10(3/20)  16384 = 23143d = 5A67h
Maximum step value: +6.0 dB (Data: 7FB2h)
Minimum step value: +0.1 dB (Data: 40BEh)
K. TGEN1 total gain fade-out step value control internal data memory
(TGEN1_GAIN_TOTAL_FADE_OUT_ST)
Initial value: 35D9h (–1.5 dB)
Use the following calculation expression when changing step amount X.
Calculation expression: 10(X/20)  16384
<Example> Set the step value to –3 dB.
10(3/20)  16384 = 11599d = 2D4Fh
Maximum step value: -6.0 dB (Data: 2013h)
Minimum step value: -0.1 dB (Data: 3F44h)
(Supplementary information) Step values can be set individually. However, the parameters that are set are
commonly used for TGEN1_RXABGAIN_TOTAL and TGEN1_TXGAIN_TOTAL. The operation control
parameter is also commonly used for TGEN1_RXABGAIN_TOTAL and TGEN1_TXGAIN_TOTAL.
L. TGEN1 execution flag display register (TGEN1_EXFLAG)
TGEN1_EXFLAG is set to “1” while the tone generator is active. (Initial value “0”: Inactive)
CR3 = "00h"
TGEN1 operation
Execution flag
(TGEN1_EXFLAG)
INTB
(Pin output)
Tone signal
TGEN1_FADE_CONT OFF
CR3 = "00h"
TGEN1 operation
Execution flag
(TGEN1_EXFLAG)
INTB
(Pin output)
Tone signal
TGEN1_FADE_CONT ON
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FSK Generator (FSK_GEN)
The FSK generator (FSK_GEN) modulates the frequency of the data that was set in the control register and
outputs the result to VFRO0 and VFRO1. Table 15 shows the specification and Figure 55 shows the block
diagram of the FSK generator.
The FSK generator comprises a FSK signal generation section that can perform buffering of up to three words, a
data setting register, and a gain adjustment section. When FGEN_EN is set o “1”, the FSK generator starts
operation and transmits a mark bit (“1”) continuously. When transmitting data, set the first transmit data in
FGEN_D[7:0] and set FGEN_FLAG to “1”.
When FGEN_FLGA is set to “1”, the transmit data of
FGEN_D[7:0] is transferred to the internal buffer if there is free internal buffer space, and FGEN_FLAG is
cleared to “0”. ST (Start Bit ”0”) and SP (Stop Bit “1”) are added to the data that was transferred to the internal
buffer and is output in the transmit sequence shown in Figure 56. When setting the next transmit data, make
sure that FGEN_FLAG is set to “0”. A mark bit (“1”) is sent continuously while there is no data waiting to be
transmitted in the internal buffer of the FGEN signal generation section.
The internal buffer of the FSK signal generation section is structured in three levels and data of up to four words
can be buffered including the FSK output data setting register FGEN_D[7:0]. To terminate transmission, set
FGEN_EN to “0” while FGEN_FLAG is set to “0”. After transmission of the data that has been set in
FGEN_D[7:0] by the time that FGEN_EN is set to “0”, the FSK generator stops. When FGEN_EN is set to “0”
during consecutive transmission of a mark bit (“1”) and no data is waiting to be transmitted, the FSK generator
stops after output a mark bit (“1”) for a period of up to one bit. Figure 57 shows the transmission start and stop
timing and Figure 58 shows an example of control. The FSK generator output level can be changed using the
internal data memory (FGEN_GAIN).
Table 15 FSK Generator Specification
Modulation method
Synchronization mode
Transfer rate
Output frequency
Frequency modulation method
Start-stop synchronization mode
1200bps
1300 Hz (Data ”1” mark)
2100 Hz (Data “0” space)
Data setting register
Output level
8-bit (FGEN_D[7:0])
13.3 dBm0 (Initial value; gain adjustable)
FSKGEN
BUFF_OUT
FGEN_GAIN
BUFF0
BUFF1
FGEN_D<7:0>
Related CRs
FGEN_EN
FGEN_FLAG
FGEN_D[7:0]
Figure 55 FSK Generator Block
Transmission direction
S
S
0 1 2 3 4 5 6 7
T
P
FGEN_D
ST:StartBit("0")
SP:Stop Bit("1")
Figure 56 Data Transmission Sequence
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Figure 57 FSK Data Transmission Start and Stop Timing (50-bit Transmission)
(Remarks)
It is recommended to operate the FSK generator with detection circuits made inactive in order to avoid the
occurrence of interrupts due to some other factors.
Activate FGEN (FGEN_EN = “1”)
Mark (“1”) continuous
output?
YES
NO
FGEN_FLAG=0?
NO
YES
Set data to be transmitted
(FGEN_D]7:0])
FGEN_FLAG=1
NO
Last data?
YES
FGEN_FLAG=0?
NO
YES
Stop FGEN (FGEN_EN=”0”)
Figure 58 FSK Output Control Method
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A. FSK_GEN control register (FGEN_EN)
0: Stops FSK_GEN (Initial value)
1: Activates FSK_GEN
B. FSK output data setting completion flag display register (FGEN_FLAG)
After writing data in the FSK output data setting register (FGEN_D[7:0]), set this bit to “1”. When the
data is stored in the internal buffer of the FSK signal generation section, this bit is automatically cleared
to “0” and an interrupt is generated. Do not write data to this register while this bit is “1”.
C. FSK output data setting register (FGEN_D[7:0])
Initial value: 00h
D. FSK gain control internal data memory (FGEN_GAIN)
Initial value: 0080h
The initial value of the output level is –13.3 dBm0. Use the following calculation expression when
changing the output level.
Calculation expression: 0080h  GAIN
<Example> Reduce the output level by 6 dB.
0080h  0.5 = 0040h
Upper limit: +40 dB
(Data: 3200h)
Lower limit: –40 dB
(Data: 0001h)
(Note) The amplitude must not exceed the maximum amplitude 3.17 dBm0.
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FSK Receiver (FSK_DET)
Table 16 shows the specification of the FSK receiver and Figure 59 shows the operation outline.
Activation and receive operation
The FSK receiver is enabled when the FSK_DET control register (FDET_EN) is set to “1”.
When receiving FSK data (10 bits), the FSK receiver stores the data bit (8 bits) excluding ST (Start Bit “0”)
and SP (Stop Bit “1”) in the FSK receive data storage register FDET_D[7:0] and sets the FSK receive data read
request notification register (FDET_RQ) to “1”. When FDET_RQ is set to “1”, read the receive data from
FDET_D[7:0] and clear the read request by writing “0” to FDET_RQ.
Buffering function
The FSK receiver is equipped with an internal buffer that can buffer receive data of up to three words, or four
words if FDET_D[7:0] is included. When new FSK data is received while FDET_RQ = 1, the receive data is
transferred to the internal buffer.
Overrun error
When FSK data of 1 word is received while the internal buffer already contains receive data of three words, the
contents are updated by shifting 1 word of receive data in the internal buffer and the initial receive data is
deleted. The occurrence of an overrun error is notified to the MCU side at the next read request (FDET_RQ =
1) by setting the FSK receive overrun error notification register (FDET_OER) to “1”.
Framing error
When SP (Stop Bit “1”) is not detected correctly, the FSK receiver notifies an error when issuing the receive
data read request (FDET_RQ = 1), by setting the FSK receive framing error notification register (FDET_FER)
to “1”. Note that FDET_FER is not set to “1” when receive data from which SP (Stop Bit “1”) was not
detected is overwritten due to the occurrence of overrun while that data is stored in the internal buffer.
Clearing an error
Be sure to clear two error statuses (FDET_FER = 1 and FDET_OER = 1) by writing FDET_FER = 0 and
FDET_OER = 0 when clearing (writing FDET_RQ = 0) the FSK receive data read request notification register.
Stopping
The FSK receiver can be stopped by setting the FSK_DET control register (FDET_EN) to “0”.
An interval of 500usec or more is required before reactivating the FSK receiver after stopping it.
When the FSK receiver is stopped while FSK receive data read is being requested (FDET_RQ = 1), FDET_RQ,
FDET_FER, and FDET_OER are all cleared to “0”. When the FSK receiver is stopped, FDET_D[7:0] is
cleared to 00h.
Table 16 FSK Receiver Specification
Modulation method
Synchronization mode
Transfer rate
Detection frequency
Frequency modulation method
Start-stop synchronization mode
1200bps
1300Hz (Data “1” mark)
2100Hz (Data “0” space)
Receive data storage
register
Detection level
8-bit (FDET_D[7:0])
–39.3 dBm0 (Initial value, adjustable)
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Mark
Start bit
M
S
T
M
S
T
INTB
FDET_OER
FDET_FER
FDET_RQ
MCU receive data
read
FDET_D[7:0]
Internal buffer
FSK receiver input
FDET_EN
S
T
M
M
Start bit
Mark
S
T
(2) Abnormal reception
INTB
FDET_OER
FDET_FER
FDET_RQ
MCU receive data
read
FDET_D[7:0]
Internal buffer
FSK receiver input
FDET_EN
(1) Normal reception
A
0
A
0
?
S
P
A
1
S
P
A
1
A
4
Stop bit
A
3
A
7
A
2
A
4
A
5
Stop bit not
detected
Stop bit
A
3
S
P
B
0
[A7:A0]
Receive request
M
S
T

B
7
S
P
M

S
T
C
0
[A7:A0]

A
6
A
7
S
T
B
0
Framing error
[A7:A0]
Receive request
M

B
7
?
M
S
T
C
0

C
7
M
M
[B7:B0]
[A7:A0]
S
P

S
P
S
T
S
T
D
0
D
0
[B7:B0]

D S
7 P
S
T
[C7:C0]
M
S
T
[D7:D0]
M
Approx. 125 s
S
P

[C7:C0]

D
7


S
P
[D7:D0]

[D7:D0]
E
0
E
7
S
P

S
T
F
0
F
7
F
7
S
P
S
P
Overrun error
[F7:F0]
[F7:F0]
[F7:F0]
Receive request
[F7:F0]
Receive
request
About 125sec
[F7:F0]
[F7:F0]
[E7:E0]
[C7:C0] [D7:D0] [E7:E0]
Receive Receive Receive
request request request
[C7:C0] [D7:D0]
[C7:C0] [D7:D0] [E7:E0]


[E7:E0]


[E7:E0]
Receive
request
F
0
[D7:D0] [E7:E0]
[E7:E0]
M
S
T
[E7:E0]
M
[B7:B0] [C7:C0] [D7:D0]
Receive Receive Receive
request request request
[B7:B0] [C7:C0]
[C7:C0] [D7:D0]
E
7

[D7:D0]
E
0
(Note) FDET_RQ=1, FDET_FER = 1, and FDET_OER = 1 are cleared by writing FDET_RQ = 0, FDET_FER = 0, and FDET_OER = 0 from the MCU side.
?

C
7

(Note) FDET_RQ = 1 is cleared by writing FDET_RQ = 0 from the MCU side.
A A
5 6

A
2

Activation internal
500sec or more
Activation interval
500 s or more
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Figure 59 FSK Receive Timing
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A. FSK_DET control register (FDET_EN)
0: Stops FSK_DET (Initial value)
1: Activates FSK_DET
B. FSK receive data read request notification register (FDET_RQ)
0: No read request issued (Initial value)
1: Read request issued
C. FSK receive framing error notification register (FDET_FER)
0: No framing error occured (Initial value)
1: Framing error occured
D. FSK receive overrun error notification error (FDET_OER)
0: No overrun error occured (Initial value)
1: Overrun error occured
E. FSK receive data storage register (FDET_D[7:0])
Initial value: 00h
F. FSK receiver detection level control internal data memory (FDET_TH)
Initial value: 1000h
The initial value of the detection level is –39.3 dBm0. Use the following calculation expression when
changing the detection level.
Calculation expression: 4096  (1/10(X/20))
<Example> Increase the detection level by 6 dB.
4096  (1/10(6/20)) = 2053d = 0805h
Upper limit: +12 dB
(Data: 0405h)
Lower limit: 12dB
(Data: 3FB2h)
G. FSK receive mark guard time control internal data memory (FDET_MK_GT)
Initial value: 00F0h (30 ms)
After the FSK receiver makes a transition from an FSK signal non-detection state to a detection state, that
is, after activation of the FSK receiver for example, receive data fetching starts after a mark bit is detected
in succession for a specified period (mark guard time).
Use the following calculation expression when changing the mark guard time.
Calculation expression: (Mark guard time)/0.125 ms
<Example> Set the mark guard to 60 ms.
60/0.125 = 01E0h
Upper limit:
4095.875 ms
(Data: 7FFFh)
Lower limit:
0 ms
(Data: 0000h)
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TONE0 Detector (TONE_DET0)
The TONE0 detector comprises a main signal detection section that detects the signal of an appropriate
frequency, a noise detection section that detects signals other than an appropriate frequency, an ON guard timer,
and an OFF guard timer. The detector detects single-tone signals of 1650 Hz that are input from AIN.
The TONE0 detector is activated when the control register TDET0_EN is set to “1”. When a tone is detected
(main signal detection and noise non-detection state), the control register TONE0_DET is set to “1” and when a
tone is not detected or TDET0_EN is set to ”0”, TONE0_DET is set to “0”.
A detection time can be adjusted by the ON guard timer and OFF guard timer. In addition, main signal
detection and noise detection level adjustment are possible. Both guard timers are initially set to 5 ms. The
initial value of the detection levels is –5.3 dBm0 for both main signal detection level and noise detection level.
Figure 60 shows the tone detection timing.
TDET0_EN
AIN input
Voice
Tone signal
Main signal detection
Noise detection
Tone detection internal
signal
OFF guard timer
TONE0_DET
ON guard timer
INTB pin output
Figure 60 Tone Detection Timing
A. : TONE0 detection control register (TDET0_EN)
0: Stops TONE_DET0 (Initial value)
1: Activates TONE_DET0
B. : TONE0 detector detection status register (TONE0_DET)
0: Non-detection (Initial value)
1: Detection
C. TDET0 main signal detection level control internal data memory (TDET0_S_TH)
Initial value: 1EBBh (–5.3 dBm0)
Use the following calculation expression when setting detection level X.
Calculation expression: 10((X–3.17)/20)  2/PI  32768
<Example> Detection level –5.3 dBm0
10((–5.3 –3.17)/20)  2/PI  32768 = 7867d = 1EBBh
Upper limit: 3.17 dBm0
(Data: 517Dh)
: –5.3 dBm0
(Data: 1EBBh)
Lower limit: –35 dBm0
(Data: 0102h)
* PI = 3.14
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D. TDET0 noise detection level control internal data memory (TDET0_N_TH)
Initial value: 1EBBh (–5.3 dBm0)
Use the following calculation expression when setting detection level X.
Calculation expression: 10((X-3.17)/20)  2/PI  32768
<Example> Detection level -5.3 dBm0
10((–5.3 –3.17)/20)  2/PI  32768 = 7867d = 1EBBh
Upper limit: 3.17 dBm0
(Data: 517Dh)
: –5.3 dBm0
(Data: 1EBBh)
Lower limit: –30 dBm0
(Data: 01CAh)
When stopping the noise detection function, write 7FFFh in the internal data memory (TDET0_N_TH)
described above.
E. TDET0 detection ON guard timer internal data memory (TDET0_ON_TM)
Initial value: 0028h (5 ms)
Use the following calculation expression when changing the timer value.
Calculation expression: “Guard timer value” ms/0.125 ms
<Example> 5 ms
5/0.125 = 40d = 0028h
Upper limit: 4095.875 ms
(Data: 7FFFh)
: 5 ms
(Data: 0028h)
Lower limit: 0.125 ms
(Data: 0001h)
F. TDET0 detection OFF guard timer internal data memory (TDET0_OFF_TM)
Initial value: 0028h (5 ms)
Use the following calculation expression when changing the timer value.
Calculation expression: “Guard timer value” ms/0.125 ms
<Example> 5 ms
5/0.125 = 40d = 0028h
Upper limit: 4095.875 ms
(Data: 7FFFh)
: 5 ms
(Data: 0028h)
Lower limit: 0.125 ms
(Data: 0001h)
G. TDET0 detection frequency control internal data memory (TDET0_FREQ)
Initial value: –
A detection frequency can be changed. When changing the frequency, contact ROHM's responsible
sales person.
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TONE1 Detector (TONE_DET1)
The TONE1 detector comprises a main signal detection section that detects the signal of an appropriate
frequency, a noise detection section that detects signals other than an appropriate frequency, an ON guard timer,
and an OFF guard timer. The detector detects single-tone signals of 2100Hz that are input from AIN.
The TONE1 detector is activated when the control register TDET1_EN is set to “1”. When a tone is detected
(main signal detection and noise non-detection state), the control register TONE1_DET is set to “1” and when a
tone is not detected or TDET1_EN is set to ”0”, TONE1_DET is set to “0”.
A detection time can be adjusted by the ON guard timer and OFF guard timer. In addition, main signal
detection and noise detection level adjustment are possible Both guard timers are initially set to 5 ms. The
initial value of the detection levels is –5.3 dBm0 for both main signal detection level and noise detection level.
Figure 61 shows the tone detection timing.
TDET1_EN
AIN input
Voice
Tone signal
Main signal detection
Noise detection
Tone detection internal
signal
OFF guard timer
TONE1_DET
ON guard timer
INTB pin output
Figure 61 Tone Detection Timing
A. : TONE1 detection control register (TDET1_EN)
0: Stops TONE_DET1 (Initial value)
1: Activates TONE_DET1
B. : TONE1 detector detection status register (TONE1_DET)
0: Non-detection (Initial value)
1: Detection
C. TDET1 main signal detection level control internal data memory (TDET1_S_TH)
Initial value: 1EBBh (–5.3 dBm0)
Use the following calculation expression when setting detection level X.
Calculation expression: 10((X–3.17)/20)  2/PI  32768
<Example> Detection level –5.3 dBm0
10((–5.3–3.17)/20)  2/PI  32768 = 7867d = 1EBBh
Upper limit: 3.17 dBm0
(Data: 517Dh)
: –5.3 dBm0
(Data: 1EBBh)
Lower limit: –35 dBm0
(Data: 0102h)
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D. TDET1 noise detection level control internal data memory (TDET1_N_TH)
Initial value: 1EBBh (–5.3 dBm0)
Use the following calculation expression when setting the detection level to X.
Calculation expression: 10((X–3.17)/20)  2/PI  32768
<Example> Detection level –5.3 dBm0
10((–5.3 –3.17)/20)  2/PI  32768 = 7867d = 1EBBh
Upper limit: 3.17 dBm0
(Data: 517Dh)
: –5.3 dBm0
(Data: 1EBBh)
Lower limit: –30 dBm0
(Data: 01CAh)
When stopping the noise detection function, write 7FFFh in the internal data memory (TDET1_N_TH)
described above.
E. TDET1 detection ON guard timer internal data memory (TDET1_ON_TM)
Initial value: 0028h (5 ms)
Use the following calculation expression when changing the timer value.
Calculation expression: “Guard timer value” ms/0.125 ms
<Example> 5 ms
5/0.125 = 40d = 0028h
Upper limit: 4095.875 ms
(Data: 7FFFh)
: 5 ms
(Data: 0028h)
Lower limit: 0.125 ms
(Data: 0001h)
F. TDET1 detection OFF guard timer internal data memory (TDET1_OFF_TM)
Initial value: 0028h (5 ms)
Use the following calculation expression when changing the timer value.
Calculation expression: “Guard timer value” ms/0.125 ms
<Example> 5 ms
5/0.125 = 40d = 0028h
Upper limit: 4095.875 ms
(Data: 7FFFh)
: 5 ms
(Data: 0028h)
Lower limit: 0.125 ms
(Data: 0001h)
G. TDET1 detection frequency control internal data memory (TDET1_FREQ)
Initial value: –
A detection frequency can be changed. When changing the frequency, contact ROHM's responsible
sales person.
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DTMF Detector (DTMF_REC)
The DTMF detector detects DTMF signals that are input from AIN.
The DTMF detector comprises a DTMF section that detects DTMF signals, a noise detection section that detects
signals other than DTMF signals, an ON guard timer, and an OFF guard timer.
The DTMF detector is activated when the control register DTMF_EN is set to “1”. When a valid DTMF signal
is detected (detecting a DTMF signal without noise signal), DTMF_DET is set to “1” and the receive code is
stored in DTMF_CODE3–0. When a DTMF signal is not detected and DTMF_EN is “0”, DTMF_DET is set
to”0” and DTMF_CODE3– 0 are set to “0000”.
Figure 62 shows DTMF detection timing. The detection time and detection level can be adjusted by the ON
guard timer and the OFF guard timer. The initial values of both guard timers are 20 ms. The initial value of
the detection level is –37.0 dBm0.
DTMF_EN
AIN input
Voice
DTMF signal
DTMF detection section
Noise detection section
DTMF detection internal
signal
DTMF_DET
ON guard timer
DTMF code output
(DTMF_CODE[3:0])
"0000"
OFF guard timer
Detection code
"0000"
INTB pin output
Figure 62 DTMF Detection Timing
A. : DTMF detector control register (DTMF_EN)
0: Stops the DTMF detection function (Initial value)
1: Activates the DTMF detection function
B. : DTMF code display register (DTMF_CODE[3:0])
A valid code is stored in this register for the time period during which DTMF signals are detected (DTMF
detector detection status register DTMF_DET = “1”) when the DTMF detector control register
(DTMF_EN) is set to “1”. When DTMF signals are not detected (DTMF_DET = “0”), “0000” is
output. (Initial value:0000b)
C. : DTMF detector detection status register (DTMF_DET)
0: Non-detection (Initial value)
1: Detection
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D. DTMF detection level control internal data memory (DTMF_TH)
Initial value: 1000h (–37.0 dBm0)
Use the following calculation expression when changing the initial value of the detection level.
Calculation expression: 1000h  1/GAIN
<Example> Increase the detection level by 6 dB.
1000h  0.5 = 0800h
Upper limit: +12 dB (Data: 0405h)
Lower limit: –12 dB (Data: 3FB2h)
(Note)
The detection level that is set in the above data memory (DTMF_TH) is used as the common detection
level for both the DTMF detection section and the noise detection section.
E. DTMF detection ON guard timer internal data memory (DTMF_ON_TM)
Initial value: 00A0h (20 ms)
Use the following calculation expression when changing the timer value.
Calculation expression: “Guard timer value” ms/0.125 ms
<Example> 5 ms
5/0.125 = 40d = 0028h
Upper limit: 4095.875 ms
(Data: 7FFFh)
: 5 ms
(Data: 0028h)
Lower limit: 0.125 ms
(Data: 0001h)
F. DTMF detection OFF guard timer internal data memory (DTMF_OFF_TM)
Initial value: 00A0h (20 ms)
Use the following calculation expression when changing the timer value.
Calculation expression: “Guard timer value” ms/0.125 ms
<Example> 5 ms
5/0.125 = 40d = 0028h
Upper limit: 4095.875 ms
(Data: 7FFFh)
: 5 ms
(Data: 0028h)
Lower limit: 0.125 ms
(Data: 0001h)
G. DTMF noise detection function control internal data memory (DTMF_NDET_CONT)
Initial value: 0002h (noise detection function is enabled)
By writing 000h in this internal data memory, the noise detection function of the DTMF detector is
disabled.
(Note)
If DTMF signals are changed to other codes in succession during detection of DTMF signals, the receive
codes may change while DTMF_DET is “1”, causing an interrupt.
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Echo Canceler
Figure 63 shows an echo canceler block diagram.
The echo canceler, which has a delay time of 32 ms, is activated by setting the echo canceler control register
(EC_EN) to “1”. The operation of the echo canceler is specified mainly in the internal data memories EC_CR
and GLPAD_CR.
Echo Canceller
Sin
LPAD
+
-
ATTs
Center
Clip
Sout
GPAD
Adaptive
FIR Filter (AFF)
Power Calc
Howling Detector
Double Talk Det
Rout
GC
ATTr
Rin
Figure 63 Echo Canceler Block Diagram
A. Echo canceler control register (EC_EN)
0: Stops the echo canceler function: Passes through the echo canceler. (Initial value)
1: Activates the echo canceler function.
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B. Echo canceler control internal data memory (EC_CR)
Initial value: 0012h
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
CLP
—
ATTB
GC
0
0
1
0
Name
THR
—
HLD
HDB
Initial value
0
0
0
1
B15-B8: Reserved bits
Changing of the initial values is inhibited.
B7: Through mode control
1: Through mode
0: Normal mode (echo cancellation operation)
Rin data and Sin data are output to Rout and Sout in through mode, retaining the echo coefficients. In
through mode, the functions of HLD, HDB, CLP, ATTB, and GC are disabled.
B6: Reserved bit
Changing of the initial value is inhibited.
B5: Coefficient update control
1: Fixes the coefficient
0: Updates the coefficient
This bit specifies whether the coefficient of the echo canceler adaptive FIR filter (AFF) is updated. This
function is enabled when THR is set to a normal mode.
B4: Howling detector control
1: OFF
0: ON
This function detects howling that can occur in hands-free acoustic systems and eliminates howling.
This function is enabled when THR is set to a normal mode.
B3: Center clip control
1: ON
0: OFF
When Sout output of the echo canceler is 57 dBm0 or less, this center clip function fixes the Sout output
to the positive minimum value forcibly. This function is enabled when THR is set to a normal mode.
B2: Reserved bit
Changing of the initial value is inhibited.
B1: Attenuator control
1: ATT OFF
0: ATT ON
Use this function to select ON/OFF of the ATT function that prevents howling through the attenuators
(ATTs and ATTr) provided for Rin input and Sout output of the echo canceler. When a signal is input to
Rin only, ATT(ATTs) of Sout is inserted. When a signal is input to Sin only or input to both Sin and
Rin, ATT(ATTr) of Rin input is inserted. The ATT value is approx. 6 dB for both ATTs and ATTr.
This function is enabled when THR is set to a normal mode.
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B0: Gain controller control
1: OFF
0: ON
Use this function to select ON/OFF of the gain control function that uses the attenuator (GC) provided for
Rin input of the echo canceler. The gain control function is for suppressing overinput at an Rin input
level and howling.
When the peak of an input signal to the attenuator (GC) is 10 dBm0 or less, no output of the attenuator is
attenuated.
When the peak of an input signal to the attenuator (GC) is in the range of 10 dBm0 to approx. 1.5
dBm0, the output of the attenuator is attenuated to approx.10 dBm0.
When the peak of an input signal to the attenuator (GC) is 1.5 dBm0 or more, the output of the
attenuator is attenuated by approx.  dBm0. This function is enabled when THR is set to a normal
mode.
C. GLPAD control internal data memory (GLPAD_CR)
Initial value: 000Fh
GLPAD control memory in the echo canceler
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name
—
—
—
—
GPAD2
GPAD1
LPAD2
LPAD1
Initial value
0
0
0
0
1
1
1
1
B15-B4: Reserved bits
Changing of the initial values is inhibited.
B3 , 2: Output level control
GPAD level control of echo canceler output gain
(0,1): +18 dB
(0,0): +12 dB
(1,1): + 6 dB
(1,0): 0 dB
B1, 0: Input level control
LPAD level control of echo canceler input loss
(0,1): –18 dB
(0,0): –12 dB
(1,1): – 6 dB
(1,0): 0 dB
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D. Notes on using the echo canceler
D-1
Make sure that echo signal saturation or waveform distortion will not be caused by an external amplifier in
the echo path. Saturation or waveform distortion deteriorates echo attenuation.
D-2
The E.R.L. (Echo Return Loss) level should be more than 0dB. In particular, care must be taken when
TXGAINA, TXGAINB, RXGAINA, or RXGAINB is changed. When the E.R.L. level is 0dB or less, it is
recommended to use the GLPAD function. If the E.R.L. level is 0 dB or less, echo attenuation performance
can be degraded.
E.R.L. refers to an echo attenuation (loss) from echo canceler output (Rout) to echo canceler input (Sin).
D-3
When an echo path changes (upon re-calling), it is recommended to reset the echo canceler through EC_EN,
PDNB, or SPDN.
D-4
When using the echo canceler, it is recommended to output signals through RXGEN from various generators
to the receive side. If signals are output from RXGENA or RXGENB, echoes may not be eliminated.
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RC0 (Range Controller 0)
RC0 (Range Controller 0) is designed to improve the idle channel noise characteristics on the transmitting side
by attenuating an output signal by a certain level with respect to the level of an input signal.
Figure 64 shows the input/output characteristics of RC0. Setting RC0_EN of the RC0 control internal memory
(RC0_CR) to “1” will operate RC0. The settings for RC0 operation are configured using the internal data
memories descrbed below.
-40
-43
Output level [dBm0]
RC0_LOSS1 (3dB)
-48
-51
RC0_LOSS2 (6dB)
-56
-62
RC0_LOSS3 (12dB)
-72
RC0_LOSS4 (12dB)
-60
RC0_TH4
-50
-45
RC0_TH3 RC0_TH2
Input level [dBm0]
-40
RC0_TH1
* Each parameter indicates
its initial value.
Figure 64 RC0 Input/Output Characteristics
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A. Internal data memory for RC0 control (RC0_CR)
Initial value: 0000h
Internal data memory for RC0 control
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name








Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name







RC0_EN
Initial value
0
1
0
0
0
0
0
0
B15-B1: Reserved bits
Changing of the initial values is inhibited.
B0: RC0 control register (RC0_EN)
1: Disables the RC0 function. RC0 is passed undetected (Default)
0: Enables the RC0 function.
B-1: RC0 internal data memory for adjustment of threshold 1 for loss (RC0_TH1)
Initial value: 0090h (approx. –40 dBm0)
Use the following calculation expression when changing threshold 1 for loss to X:
Calculation expression: 10((X – 3.17)/20)  2/PI  32768
<Example> Set threshold 1 for loss to –40 dBm0.
10((–40 – 3.17)/20)  2/PI  32768  144d = 0090h
Upper limit: +3.17 dBm0
(Data: 517Ch)
: Approx. –40 dBm0
(Data: 0090h)
Lower limit: –
(Data: 0000h)
B-2: RC0 internal data memory for adjustment of threshold 2 for loss (RC0_TH2)
Initial value: 0051h (approx. –45 dBm0)
Use the following calculation expression when changing threshold 2 for loss to X:
Calculation expression: 10((X – 3.17)/20)  2/PI  32768
<Example> Set threshold 2 for loss to –45 dBm0.
10((–45 – 3.17)/20)  2/PI  32768  81d = 0051h
Upper limit: Less than RC0_TH1
: Approx. –45 dBm0
(Data: 0051h)
Lower limit: –
(Data: 0000h)
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B-3: RC0 internal data memory for adjustment of threshold 3 for loss (RC0_TH3)
Initial value: 002Dh (approx. –50 dBm0)
Use the following calculation expression when changing threshold 3 for loss to X:
Calculation expression: 10((X – 3.17)/20)  2/PI  32768
<Example> Set threshold 3 for loss to –50 dBm0.
10((–50 – 3.17)/20)  2/PI  32768  45d = 002Dh
Upper limit: Less than RC0_TH2
: Approx. –50 dBm0
(Data: 002Dh)
Lower limit: –
(Data: 0000h)
B-4: RC0 internal data memory for adjustment of threshold 4 for loss (RC0_TH4)
Initial value: 000Eh (approx. –60 dBm0)
Use the following calculation expression when changing threshold 4 for loss to X:
Calculation expression: 10((X – 3.17)/20)  2/PI  32768
<Example> Set threshold 4 for loss to –60 dBm0.
10((–60 – 3.17)/20)  2/PI  32768  14d = 000Eh
Upper limit: Less than RC0_TH3
: Approx. –60 dBm0
(Data: 000Eh)
Lower limit: –
(Data: 0000h)
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C-1: RC0 internal data memory for adjusting a loss value in the case of threshold 1 or 2 for loss
(RC0_LOSS1)
Initial value: 005Ah (approx. 3 dB)
Use the following calculation expression when changing the loss value to X:
Calculation expression: 128/10(X/20)
<Example> Set the loss value to 3 dB.
128/10(3/20)  90d = 005Ah
Upper limit: 0 dB
(Data: 0080h)
: Approx. 3 dB
(Data: 005Ah)
Lower limit: RC0_LOSS2
C-2: RC0 internal data memory for adjusting a loss value in the case of threshold 2 or 3 for loss
(RC0_LOSS2)
Initial value: 0040h (approx. 6 dB)
Use the following calculation expression when changing the loss value to X:
Calculation expression: 128/10(X/20)
<Example> Set the loss value to 6 dB.
128/10(6/20)  64d = 0040h
Upper limit: RC0_LOSS1
: Approx. 6 dB
(Data: 0040h)
Lower limit: RC0_LOSS3
C-3: RC0 internal data memory for adjusting a loss value in the case of threshold 3 or 4 for loss
(RC0_LOSS3)
Initial value: 0020h (approx. 12 dB)
Use the following calculation expression when changing the loss value to X:
Calculation expression: 128/10(X/20)
<Example> Set the loss value to 12 dB.
128/10(12/20)  32d = 0020h
Upper limit: RC0_LOSS2
: Approx. 12 dB
(Data: 0020h)
Lower limit: RC0_LOSS4
C-4: RC0 internal data memory for adjusting a loss value in the case of threshold 4 or less for loss
(RC0_LOSS4)
Initial value: 0020h (approx. 12 dB)
Use the following calculation expression when changing the loss value to X:
Calculation expression: 128/10(X/20)
<Example> Set the loss value to 12 dB.
128/10(12/20)  32d = 0020h
Upper limit: RC0_LOSS3
: Approx. 12 dB
(Data: 0020h)
Lower limit: MUTE
(Data: 0000h)
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D-1: RC0 internal data memory for adjusting a plus step value for loss (RC0_PL)
The loss value changes to the target loss value with the step value set in RC0_PL when the input level
becomes higher than each threshold level.
Initial value: 47CFh (approx. 1 dB)
Use the following calculation expression when changing the plus step value to X:
Calculation expression: 10(X/20)  16384
<Example> Set the plus step value to 1 dB.
10(1/20)  16384  18383d = 47CFh
Upper limit: +6 dB
(Data: 7FB2h)
: Approx. 1 dB
(Data: 47CFh)
Lower limit: Approx. +0.0005 dB
(Data: 4001h)
D-2: RC0 internal data memory for adjusting a minus step value for loss (RC0_MI)
The loss value changes to the target loss value with the step value set in RC0_MI when the input level
becomes lower than the threshold level that corresponds.
Initial value: 3F44h (approx. –0.1 dB)
Use the following calculation expression when changing the step value to X:
Calculation expression: 10(X/20)  16384
<Example> Set the step value to –0.1 dB.
10(–0.1/20)  16384  16196d = 3F44h
Upper limit: –6 dB
(Data: 2013h)
: Approx. –0.1 dB
(Data: 3F44h)
Lower limit: Approx. –0.0005 dB
(Data: 3FFFh)
E. RC0 internal data memory for adjusting the input signal level detecting sensitivity 1/2
(RC0_POW_C1/RC0_POW_C2)
Initial value: RC0_POW_C1: 3E00h
RC0_POW_C2: 0200h
This is an internal data memory for adjusting the input signal detecting sensitivity in RC0. By adjusting
this memory, the detecting sensitivity for a voice signal on the transmitting side that is input at a level
near threshold is decreased, so that fluctuations in output signal can be supressed.
Following shows the settings for decreasing the input signal detecting sensitivity.
- To decrease the detecting sensitivity to about one-half the initial value:
Setting value:
RC0_POW_C1: 3F00h
RC0_POW_C2: 0100h
- To decrease the detecting sensitivity to about one-fourth of the initial value:
Setting value:
RC0_POW_C1: 3F80h
RC0_POW_C2: 0080h
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RC1 (Range Controller 1)
RC1 (Range Controller 1) is designed to improve the idle channel noise characteristics on the transmitting side
by attenuating an output signal by a certain level with respect to the level of an input signal.
Figure 65 shows the input/output characteristics of RC1. Setting RC1_EN of the RC1 control internal memory
(RC1_CR) to “1” will operate RC1. The settings for RC1 operation are configured using the internal data
memories descrbed below.
-40
-43
Output level [dBm0]
RC0_LOSS1 (3dB)
-48
-51
RC0_LOSS2 (6dB)
-56
-62
RC0_LOSS3 (12dB)
-72
RC0_LOSS4 (12dB)
-60
RC0_TH4
-50
-45
RC0_TH3 RC0_TH2
Input level [dBm0]
-40
RC0_TH1
* Each parameter indicates
its initial value.
Figure 65 RC1 Input/Output Characteristics
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A. Internal data memory for RC1 control (RC1_CR)
Initial value: 0000h
Internal data memory for RC1 control
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name








Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name







RC1_EN
Initial value
0
1
0
0
0
0
0
0
B15-B1: Reserved bits
Changing of the initial values is inhibited.
B0: RC1 control register (RC1_EN)
1: Disables the RC1 function. RC1 is passed undetected (Default)
0: Enables the RC1 function.
B-1: RC1 internal data memory for adjustment of threshold 1 for loss (RC1_TH1)
Initial value: 0090h (approx. –40 dBm0)
Use the following calculation expression when changing threshold 1 for loss to X:
Calculation expression: 10((X – 3.17)/20)  2/PI  32768
<Example> Set threshold 1 for loss to –40 dBm0.
10((–40 – 3.17)/20)  2/PI  32768  144d = 0090h
Upper limit: +3.17 dBm0
(Data: 517Ch)
: Approx. –40 dBm0
(Data: 0090h)
Lower limit: –
(Data: 0000h)
B-2: RC1 internal data memory for adjustment of threshold 2 for loss (RC1_TH2)
Initial value: 0051h (approx. –45 dBm0)
Use the following calculation expression when changing threshold 2 for loss to X:
Calculation expression: 10((X – 3.17)/20)  2/PI  32768
<Example> Set threshold 2 for loss to –45 dBm0.
10((–45 – 3.17)/20)  2/PI  32768  81d = 0051h
Upper limit: Less than RC1_TH1
: Approx. –45 dBm0
(Data: 0051h)
Lower limit: –
(Data: 0000h)
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B-3: RC1 internal data memory for adjustment of threshold 3 for loss (RC1_TH3)
Initial value: 002Dh (approx. –50 dBm0)
Use the following calculation expression when changing threshold 3 for loss to X:
Calculation expression: 10((X – 3.17)/20)  2/PI  32768
<Example> Set threshold 3 for loss to –50 dBm0.
10((–50 – 3.17)/20)  2/PI  32768  45d = 002Dh
Upper limit: Less than RC1_TH2
: Approx. –50 dBm0
(Data: 002Dh)
Lower limit: –
(Data: 0000h)
B-4: RC1 internal data memory for adjustment of threshold 4 for loss (RC1_TH4)
Initial value: 000Eh (approx. –60 dBm0)
Use the following calculation expression when changing threshold 4 for loss to X:
Calculation expression: 10((X – 3.17)/20)  2/PI  32768
<Example> Set threshold 4 for loss to –60 dBm0.
10((–60 – 3.17)/20)  2/PI  32768  14d = 000Eh
Upper limit: Less than RC1_TH3
: Approx. –60 dBm0
(Data: 000Eh)
Lower limit: –
(Data: 0000h)
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C-1: RC1 internal data memory for adjusting a loss value in the case of threshold 1 or 2 for loss
(RC1_LOSS1)
Initial value: 005Ah (approx. 3 dB)
Use the following calculation expression when changing the loss value to X:
Calculation expression: 128/10(X/20)
<Example> Set the loss value to 3 dB.
128/10(3/20)  90d = 005Ah
Upper limit: 0 dB
(Data: 0080h)
: Approx. 3 dB
(Data: 005Ah)
Lower limit: RC1_LOSS2
C-2: RC1 internal data memory for adjusting a loss value in the case of threshold 2 or 3 for loss
(RC1_LOSS2)
Initial value: 0040h (approx. 6 dB)
Use the following calculation expression when changing the loss value to X:
Calculation expression: 128/10(X/20)
<Example> Set the loss value to 6 dB.
128/10(6/20)  64d = 0040h
Upper limit: RC1_LOSS1
: Approx. 6 dB
(Data: 0040h)
Lower limit: RC1_LOSS3
C-3: RC1 internal data memory for adjusting a loss value in the case of threshold 3 or 4 for loss
(RC1_LOSS3)
Initial value: 0020h (approx. 12 dB)
Use the following calculation expression when changing the loss value to X:
Calculation expression: 128/10(X/20)
<Example> Set the loss value to 12 dB.
128/10(12/20)  32d = 0020h
Upper limit: RC1_LOSS2
: Approx. 12 dB
(Data: 0020h)
Lower limit: RC1_LOSS4
C-4: RC1 internal data memory for adjusting a loss value in the case of threshold 4 or less for loss
(RC1_LOSS4)
Initial value: 0020h (approx. 12 dB)
Use the following calculation expression when changing the loss value to X:
Calculation expression: 128/10(X/20)
<Example> Set the loss value to 12 dB.
128/10(12/20)  32d = 0020h
Upper limit: RC1_LOSS3
: Approx. 12 dB
(Data: 0020h)
Lower limit: MUTE
(Data: 0000h)
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D-1: RC1 internal data memory for adjusting a plus step value for loss (RC1_PL)
The loss value changes to the target loss value with the step value set in RC1_PL when the input level
becomes higher than the threshold level that corresponds.
Initial value: 47CFh (approx. 1 dB)
Use the following calculation expression when changing the step value to X:
Calculation expression: 10(X/20)  16384
<Example> Set the step value to 1 dB.
10(1/20)  16384  18383d = 47CFh
Upper limit: +6 dB
(Data: 7FB2h)
: Approx. 1 dB
(Data: 47CFh)
Lower limit: Approx. +0.0005 dB
(Data: 4001h)
D-2: RC1 internal data memory for adjusting a minus step value for loss (RC1_MI)
The loss value changes to the target loss value with the step value set in RC1_MI when the input level
becomes lower than the shreshold level that corresponds.
Initial value: 3F44h (approx. –0.1 dB)
Use the following calculation expression when changing the step value to X:
Calculation expression: 10(X/20)  16384
<Example> Set the step value to –0.1 dB.
10(–0.1/20)  16384  16196d = 3F44h
Upper limit: –6 dB
(Data: 2013h)
: Approx. –0.1 dB
(Data: 3F44h)
Lower limit: Approx. –0.0005 dB
(Data: 3FFFh)
E. RC1 internal data memory for adjusting the input signal level detecting sensitivity 1/2
(RC1_POW_C1/RC1_POW_C2)
Initial value: RC1_POW_C1: 3E00h
RC1_POW_C2: 0200h
This is an internal data memory for adjusting the input signal detecting sensitivity in RC1. By adjusting
this memory, the detecting sensitivity for a voice signal on the transmitting side that is input at a level
near threshold is decreased, so that fluctuations in output signal can be supressed.
Following shows the settings for decreasing the input signal detecting sensitivity.
- To decrease the detecting sensitivity to about one-half the initial value:
Setting value:
RC1_POW_C1: 3F00h
RC1_POW_C2: 0100h
- To decrease the detecting sensitivity to about one-fourth of the initial value:
Setting value:
RC1_POW_C1: 3F80h
RC1_POW_C2: 0080h
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Dial Pulse Detector (DPDET)
When the general-purpose I/O port GPIOA[0] is configured as its secondary function (DPI: dial pulse input pin),
dial pulse signals can be detected.
The dial pulse detector is enabled when the control register (DPDET_EN) of the dial pulse detector is set to “1”.
When a dial pulse signal is detected, the dial pulse detector status register (DP_DET) is set to “1” and the
detected pulse count is stored in the detected dial pulse count display register (DPDET_DATA[7:0]). Read a
dial pulse count from DPDET_DATA[7:0] at the timing when DP_DET has changed from “1” to “0”. When a
dial pulse signal is not detected or DPDET_EN is “0”, DP_DET is set to “0”.
Figure 66 shows the dial pulse detection timing.
The dial pulse detector samples dial pulse signals that are input from GPIOA[0] at every 8kHz and detects dial
pulses according to the values set in the ON guard timer (DPDET_ON_TIM) and OFF guard timer
(DPDET_OFF_TIM). A detection termination time can be adjusted by setting a detection termination timer
(DPDET_DETOFF_TIM).
Figure 66 Dial Pulse Detection Timing
A. Dial pulse detector control register (DPDET_EN)
0: Stops the dial pulse detector (Initial value)
1: Activates the dial pulse detector
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B. Dial pulse detector detection status register (DP_DET)
0: Dial pulse non-detection (Initial value)
1: Dial pulse detection
An input edge of the DPI pin is detected after DPDET_EN and the register is set to “1”.
When no edge is detected within the period that is set in DPDET_DETOFF_TIM, the register is cleared to
“0”.
C. Dial pulse detection polarity control register (DPDET_POL)
Control the polarity that is input from the DPI pin.
0: No polarity inversion (Initial value)
1: Polarity inversion
D. Detected dial pulse count display register (DPDET_DATA[7:0])
Initial value: 00h (Non-detection state)
Displays the dial pulse count that was detected. This register is updated at edge detection.
E. Dial pulse detection ON guard timer internal data memory (DPDET_ON_TIM)
Initial value: 0028h (5 ms)
Use the following calculation expression when changing the timer value.
Calculation expression: Guard timer value ms/0.125 ms
<Example> 5 ms
5/0.125 = 40d = 0028h
Upper limit : 4095.875 ms (Data: 7FFFh)
: 5 ms
(Data: 0028h)
Lower limit : 0.125 ms
(Data: 0001h)
F. Dial pulse detection OFF guard timer internal data memory (DPDET_OFF_TIM)
Initial value: 0028h (5 ms)
Use the following calculation expression when changing the timer value.
Calculation expression: Guard timer value ms/0.125 ms
<Example> 5 ms
5/0.125 = 40d = 0028h
Upper limit : 4095.875 ms (Data: 7FFFh)
: 5 ms
(Data: 0028h)
Lower limit : 0.125 ms
(Data: 0001h)
G. Detection termination timer control internal data memory (DPDET_DETOFF_TIM)
Initial value: 03E8h (125 ms)
Use the following calculation expression when changing the timer value.
Calculation expression: Guard timer value ms/0.125 ms
<Example> 125 ms
125/0.125 = 1000d = 03E8h
Upper limit : 4095.875 ms (Data: 7FFFh)
: 125 ms
(Data: 03E8h)
Lower limit : 0.125 ms
(Data: 0001h)
(Note)
When activating DPDET, first set the primary function/secondary function selection register (GPFA[0]) of
GPIOA[0] to “1” to select the secondary function (dial pulse input pin), then activate DPDET. When
DPDET is activated under the following conditions, an interrupt occurs after the ON guard timer set time.
In this case, ignore the first interrupt.
 DPDET_POL = “0”, DPI = “1”
 DPDET_POL = “1”, DPI = “0”
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Dial Pulse Transmitter (DPGEN)
The dial pulse transmitter can output dial pulse signals when the general-purpose I/O port GPIOA[2] is set to the
secondary function (DPO: dial pulse output pin).
The dial pulse transmitter is enabled when the dial pulse transmit control register (DPGEN_EN) is set to ”1” and
outputs dial pulse signals of the pulse count that is set in dial pulse count setting register (DPGEN_DATA[3:0]).
Figure 67 shows the dial pulse output timing.
A dial pulse speed of 10 pps or 20 pps can be selected using the dial pulse speed control register (DPGEN_PPS).
A make rate can be adjusted through DPGEN_DUTY by setting a time of a break section. A dial pulse signal
output polarity can be changed by the dial pulse output polarity control register (DPGEN_POL).
 Setting output polarity and adjusting a make rate
Positive logic
GPIOA[2]
/DPO
Negative logic
GPIOA[2]
/DPO
Break
section
Make
section
Break
section
Make
section
The output polarity can be changed (DPGEN_POL).
The make rate can be adjusted by setting a time of the break section
(DPGEN_DUTY).
 10 pps/output polarity: Positive logic/output pulse count is 10
0.1 sec/10 pps (0.05 sec/20 pps)
GPIOA[2]
/DPO
DPGEN_EN
DPGEN_OFF_TIM
 10 pps/output polarity: Negative logic/output pulse count is 2
GPIOA[2]
/DPO
DPGEN_EN
DPGEN_OFF_TIM
Figure 67 Dial Pulse Output Timing
A. Dial pulse transmit control register (DPGEN_EN)
0: Stops dial pulse output (Initial value)
1: Activates dial pulse output
B. Dial pulse count setting register (DPGEN_DATA[3:0])
Initial value: 0h
Upper limit: 10
(Data: Ah)
Lower limit: 1
(Data: 1h)
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C. Dial pulse speed control register (DPGEN_PPS)
0: 10 pps (Initial value)
1: 20 pps
D. Dial pulse output polarity control register (DPGEN_POL)
Control the output polarity from GPIOA[2].
0: Positive logic (Low: Make section, High: Break section), initial value
1: Negative logic (Low: Break section, High: Make section)
E. Dial pulse make rate control internal data memory (DPGEN_DUTY)
Initial value: 0108h (33 ms/10 pps, 16.5 ms/20 pps)
Use the following calculation expression when setting a time of a break section.
When the pulse speed is set to 20 pps, the time will be 1/2 of the specified value.
Calculation expression: “Break section output time” ms/0.125 ms
<Example> 33 ms
33/0.125 = 264d = 0108h
Upper limit: 100 ms
(Data: 0320h)
: 33 ms
(Data: 0108h)
Lower limit: 0.125 ms
(Data: 0001h)
F. Dial pulse output termination control internal data memory (DPGEN_OFF_TIM)
Initial value: 03E8h (125 ms)
Use the following calculation expression when setting output termination control.
Calculation expression: “Output termination time” ms/0.125 ms
<Example> 125 ms
125/0.125 = 1000d = 03E8h
Upper limit: 4095.875 ms
(Data: 7FFFh)
: 125 ms
(Data: 03E8h)
Lower limit: 0 ms
(Data: 0001h)
(Note) Be sure to set the following before activating DPGEN (DPGEN_EN = 1).
 Set the dial pulse output polarity control register (DPGEN_POL).
The output level (initial value) of the dial pulse output pin is set as follows.
DPGEN_POL=0 (positive logic): GPOA[2]/DPO = “0”
DPGEN_POL=1 (negative logic): GPOA[2]/DPO = “1”
 After setting the above, set the primary function/secondary function selection register (GPFA[2]) of
GPIOA[2] to “1” to select the secondary function (dial pulse output pin).
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Timer (TIMER)
This is a 16-bit incremental timer. When the timer control register (TIM_EN) is set to “1”, this timer starts
incrementing the timer counter at every 125 s. When the timer counter value (TIM_COUNT) and the timer
data setting value (TIM_DATA) match, causing overflow, the timer counter value is reset to ”0000h” and the
counter is incremented again. When overflow occurs, the timer overflow display register (TMOVF) is set to
“1”, causing an INTB interrupt. The timer overflow interrupt can be cleared by writing “0” to TMOVF from
the MCU side.
A. Timer control register (TIM_EN)
When this bit is set to “1”, the timer starts incrementing the counter.
When “0” is set, the timer stops counting and clears the timer counter value.
0: Stops counting (Initial value)
1: Starts counting
B. Timer overflow display register (TMOVF)
When the timer counter value and the timer data setting value match, causing timer overflow, the timer
overflow display register (TMOVF) is set to “1”, causing an INTB interrupt.
When “0” is written either to TMOVF on the MCU side or to the timer control register (TIM_EN), the timer
stops and the timer overflow interrupt is cleared to “0”.
C. Timer counter value display internal data memory (TIM_COUNT)
Initial value: 0000h
D. Timer data setting internal data memory (TIM_DATA)
Initial value: FFFFh
Upper limit : 8192 ms
Lower limit : 0.250 ms
(Data: FFFFh)
(Data: 0001h)
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Outband Control (OUTBAND_CONTROL)
When the detection flag (DET) of tone detector 0, tone detector 1, or DTMF detector is set to “1”, MUTE
processing is performed automatically inside the LSI or silent data is written to the transmit buffer.
Processing contents in each Speech CODEC are shown below.
G.711(-law)
MUTE processing is performed for Speech CODEC input data.
G.711(A-law) MUTE processing is performed for Speech CODEC input data.
G.729.A
Fixed silent data is written to the transmit buffer (TX Buffer) and
Fixed silent data of 80 bits can be changed in initial mode.
Initial value: 0000h
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name
—
—
—
—
—
TDET1
_OB_EN
TDET0
_OB_EN
DTMFDE
T_OB_E
N
Initial value
0
0
0
0
0
0
0
0
B15-B3: Reserved bits Changing of the initial values is inhibited.
B2: TDET1_OUTBAND_EN control
1: ON (MUTE processing or silent data write processing is performed while TONE1_DET is “1”)
0: OFF
B1: TDET0_OUTBAND_EN control
1: ON (MUTE processing or silent data write processing is performed while TONE0_DET is “1”)
0: OFF
B0: DTMFDET_OUTBAND_EN control
1: ON (MUTE processing or silent data write processing is performed while DTMF_DET is “1”)
0: OFF
 Time of tone leakage to transmit buffer
Use the following expression as the reference for the transmit buffer tone leakage time in each Speech
CODEC.
G.711
G.729.A
0 ms + A + B
–10 ms to –20 ms + A + B
Note: –10 ms to –20 ms by prediction and framing process.
A : Detection delay time of each detector (ms)
Detection delay time A of each detector depends on the condition such as the input level
frequency.
B : ON guard timer time of each detector (ms)
<Example>
When the detection delay time of the detector is approx. 30 ms and the ON guard timer time is 20 ms, the
transmit buffer leakage time will be as follows.
G.711
G.729.A
30 ms(A) +20 ms(B) = Approx. 50 ms
–10 ms to –20 ms +30 ms(A) +20 ms(B) = Approx. 30 ms to 40 ms
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Outband G.729.A Data (OUTBAND_G729_DAT)
When G.729.A is selected as Speech CODEC at outband control and the detection flag (DET) of each detector is
set to “1”, the following fixed data is stored in the transmit buffer. The fixed data can be changed in initial
mode.
Address:
Initial value:
089Fh
7852h
08A0h
80A0h
08A1h
00FAh
08A2h
C200h
08A3h
07D6h
Interrupt Cause Mask Control
See Table 1 for the list of interrupt causes.
When an interrupt cause is changed, “L” is output to the INTB pin for about 1.0 s and when an interrupt cause
remains unchanged, “H” is output.
When “1” is written to an appropriate bit position of the internal memory, the INTB pin retains the “H” state
even if the interrupt cause is changed. (The change is reflected in the register that displays each interrupt factor
status.)
(Note)
As the default, an INTB interrupt occurs according to the interrupt cause that is indicated in Table 1 (mask
setting OFF). When an INTB interrupt is not required, set “1” in the related bit of the interrupt cause mask
control internal data memory during initial mode to set the mask setting to ON.
A. Rising edge interrupt mask control
A-1: CR16 rising edge interrupt mask control (CR16_INTP_MSKCNT)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
Name
—
—
—
—
—
Initial value
1
1
1
1
1
B15-B3: Reserved bits
FDET_OE FDET_FE
R_PMSK R_PMSK
0
0
B0
FDET_R
Q_PMSK
0
Changing of the initial values is inhibited.
B2: FSK receive overrun error rising edge mask setting (FDET_OER_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
B1: FSK receive framing error rising edge interrupt mask setting (FDET_FER_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
B0: FSK receive data read request rising edge interrupt mask setting (FDET_RQ_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
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A-2: CR18 rising edge interrupt mask control (CR18_INTP_MSKCNT)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name
—
—
—
—
—
—
—
TMOVF_
_PMSK
Initial value
1
1
1
1
1
1
1
0
B15-B1: Reserved bits
Changing of the initial values is inhibited.
B0: Timer overflow status rising edge interrupt mask setting (TMOVF_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
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A-3: CR19 rising edge interrupt mask control (CR19_INTP_MSKCNT)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name
—
—
—
TONE1_
DET_
PMSK
TONE0_
DET_
PMSK
TGEN1_
EXFLAG
_PMSK
TGEN0_
EXFLAG
_PMSK
—
Initial value
0
1
1
0
0
0
0
0
B15-B5: Reserved bits
Changing of the initial values is inhibited.
B4: TONE1 detector detection status rising edge interrupt mask setting (TONE1_DET_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
B3: TONE0 detector detection status rising edge interrupt mask setting (TONE0_DET_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
B2: TONE generator 1 execution flag rising edge interrupt mask setting (TGEN1_EXFLAG_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
B1: TONE generator 0 execution flag rising edge interrupt mask setting (TGEN0_EXFLAG_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
B0: Reserved bit. Changing the initial value is inhibited.
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A-4: CR20 rising edge interrupt mask control (CR20_INTP_MSKCNT)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name
—
DP_DET
_PMSK
—
DTMF
_DET
_PMSK
DTMF
_CODE3
_PMSK
DTMF
_CODE2
_PMSK
DTMF
_CODE1
_PMSK
DTMF
_CODE0
_PMSK
Initial value
0
0
1
0
0
0
0
0
B15-B7: Reserved bits
Changing of the initial values is inhibited.
B6: Dial pulse detector detection status rising edge interrupt mask setting (DP_DET_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
B5: Reserved bit
Changing of the initial value is inhibited.
B4: DTMF detector detection status rising edge interrupt mask setting (DTMF_DET_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
B3-B0: DTMF detection code rising edge interrupt mask setting (DTMF_CODE[3:0]_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
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A-5: CR21 rising edge interrupt mask control (CR21_INTP_MSKCNT)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name
—
—
—
—
TXERR
_CH2
_PMSK
TXERR
_CH1
_PMSK
FR0_CH
2
_PMSK
FR0_CH
1
_PMSK
Initial value
1
1
1
1
0
0
0
0
B15-B4: Reserved bits
Changing of the initial values is inhibited.
B3: CH2 transmit error status rising edge interrupt mask setting (TXERR_CH2_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
B2: CH1 transmit error status rising edge interrupt mask setting (TXERR_CH1_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
B1: CH2 transmit request rising edge interrupt mask setting (FR0_CH2_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
B0: CH1 transmit request rising edge interrupt mask setting (FR0_CH1_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
(Note) When stopping Speech CODEC, be sure to make the following settings in advance:
- Writing 00FFh to CR21 rising edge interrupt mask control (CR21_INTP_MSKCNT)
- Writing 00FFh to CR22 rising edge interrupt mask control (CR22_INTP_MSKCNT)
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A-6: CR22 rising edge interrupt mask control (CR22_INTP_MSKCNT)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name
—
—
—
—
RXERR
_CH2
_PMSK
RXERR
_CH1
_PMSK
RXBW
_ERR
_PMSK
FR1_
_PMSK
Initial value
1
1
1
1
0
0
0
0
B15-B4: Reserved bits
Changing of the initial values is inhibited.
B3: CH2 receive error status rising edge interrupt mask setting (RXERR_CH2_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
B2: CH1 receive error status rising edge interrupt mask setting (RXERR_CH1_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
B1: Receive invalid write error status rising edge interrupt mask setting (RXBW_ERR_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
B2-B1: Reserved bits Changing of the initial values is inhibited.
B0: Receive request rising edge interrupt mask setting (FR1_PMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the rising edge)
0: Mask setting OFF
(Note) When stopping Speech CODEC, be sure to make the following settings in advance:
- Writing 00FFh to CR21 rising edge interrupt mask control (CR21_INTP_MSKCNT)
- Writing 00FFh to CR22 rising edge interrupt mask control (CR22_INTP_MSKCNT)
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B. Falling edge interrupt mask control
B-1:CR17 falling edge interrupt mask control (CR17_INTN_MSKCNT)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name
—
—
—
—
—
—
—
FGEN
_FLAG
_NMSK
Initial value
1
1
1
1
1
1
1
0
B15-B1: Reserved bits
Changing of the initial values is inhibited.
B0: FSK output data setting completion flag falling edge interrupt mask setting (FGEN_FLAG_NMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the falling edge)
0: Mask setting OFF
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B-2: CR19 falling edge interrupt mask control (CR19_INTN_MSKCNT)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name
—
—
—
TONE1_
DET_
NMSK
TONE0_
DET_
NMSK
TGEN1_
EXFLAG
_NMSK
TGEN0_
EXFLAG
_NMSK
—
Initial value
0
1
1
0
0
0
0
0
B15-B5: Reserved bits
Changing of the initial values is inhibited.
B4: TONE1 detector detection status falling edge interrupt mask setting (TONE1_DET_NMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the falling edge)
0: Mask setting OFF
B3: TONE0 detector detection status falling edge interrupt mask setting (TONE0_DET_NMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the falling edge)
0: Mask setting OFF
B2: TONE generator 1 execution flag falling edge interrupt mask setting (TGEN1_EXFLAG_NMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the falling edge)
0: Mask setting OFF
B1: TONE generator 0 execution flag falling edge interrupt mask setting (TGEN0_EXFLAG_NMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the falling edge)
0: Mask setting OFF
B0: Reserved bit
Changing of the initial value is inhibited.
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B-3: CR20 falling edge interrupt mask control (CR20_INTN_MSKCNT)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name
—
DP_DET
_NMSK
—
DTMF
_DET
_NMSK
DTMF
_CODE3
_NMSK
DTMF
_CODE2
_NMSK
DTMF
_CODE1
_NMSK
DTMF
_CODE0
_NMSK
Initial value
0
0
1
0
0
0
0
0
B15-B7: Reserved bits
Changing of the initial values is inhibited.
B6: Dial pulse detector detection status falling edge interrupt mask setting (DP_DET_NMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the falling edge)
0: Mask setting OFF
B5: Reserved bit
Changing of the initial value is inhibited.
B4: DTMF detector detection status falling edge interrupt mask setting (DTMF_DET_NMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the falling edge)
0: Mask setting OFF
B3-B0: DTMF detection code falling edge interrupt mask setting (DTMF_CODE[3:0]_NMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the falling edge)
0: Mask setting OFF
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B-4: CR21 falling edge interrupt mask control (CR21_INTN_MSKCNT)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name
—
—
—
—
TXERR
_CH2
_NMSK
TXERR
_CH1
_NMSK
—
—
Initial value
1
1
1
1
0
0
1
1
B15-B4: Reserved bits
Changing of the initial values is inhibited.
B3: CH2 transmit error status falling edge interrupt mask setting (TXERR_CH2_NMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the falling edge)
0: Mask setting OFF
B2: CH1 transmit error status falling edge interrupt mask setting (TXERR_CH1_NMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the falling edge)
0: Mask setting OFF
B1-B0: Reserved bits Changing of the initial values is inhibited.
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B-5: CR22 falling edge interrupt mask control (CR22_INTN_MSKCNT)
Bit
B15
B14
B13
B12
B11
B10
B9
B8
Name
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name
—
—
—
—
RXERR
_CH2
_NMSK
RXERR
_CH1
_NMSK
RXBW
_ERR
_NMSK
—
Initial value
1
1
1
1
0
0
0
1
B15-B4: Reserved bits
Changing of the initial values is inhibited.
B3: CH2 receive error status falling edge interrupt mask setting (RXERR_CH2_NMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the falling edge)
0: Mask setting OFF
B2: CH1 receive error status falling edge interrupt mask setting (RXERR_CH1_NMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the falling edge)
0: Mask setting OFF
B1: Receive invalid write error status falling edge interrupt mask setting (RXBW_ERR_NMSK)
1: Mask setting ON (Masks the interrupt request signal INTB that occurs at the falling edge)
0: Mask setting OFF
B0: Reserved bit
Changing of the initial value is inhibited.
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Decoded Output Starting Offset Time Control (DEC_ONTIM)
Initial value: 0000h (0 ms)
Use the following calculation expression when changing the decoded output starting offset time (tDECON).
For tDECON, see the receive buffer control timing of Figures 18 to 21.
Calculation expression: Decoded output starting offset time ms/0.125 ms
<Example> 5 ms
5/0.125 = 0040d = 0028h
Upper limit: 32 ms (Data: 0100h)
Lower limit: 0 ms (Data: 0000h)
(Note)
Regardless of decoded output starting offset time value, in G.711 (PLC function enabled), decoded output starts
after the decoded output control register (DEC_OUTON) is set to “1” and silent data of approx. 3.75 ms is
output. (Due to the delay of the G.711 PLC algorithm)
Note that the time required up to the actual start of the decoded output is calculated by adding approx. 3.75 ms to
the value set for the decoded output starting offset time. In G.711 (PLC function disabled), decoded output
starts after the decoded output starting offset time that is set in the data memory.
In G.729.A, note that a time of approx. 15 ms is added to the setting value of the decoded output starting offset
time that is set in the internal data memory for the time required up to the actual start of decoded output.
(Note)
Though the initial value of the decoded output starting offset time control (DEC_ONTIM) is defined as 0000h (0
ms), be sure to set the offset time to 0001h (0.125 ms) to 0100h (32 ms).
Multiple Word Write Starting Address Setting Internal Data Memory (START_ADDRESS)
Set an internal data memory starting address when writing to consecutive addresses in the internal data memory
according to the procedure that is shown in Figure 53. (Initial value: 0000h)
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CONFIGURATION EXAMPLES
Configuration Example 1 (Basic Call, CODEC_A)
GSX1
TXGAIN_PCM1 PCM_TXEN1
TXDETB
10k
AIN1N
A/D1
PCM I/F
LPEN0
G.711
Encoder
RC1
TXGAINB CODECB_TXEN
AMP1
PCM Codec
RX_SIG
BPF
TXGAIN_PCM0
PCM_TXEN0
STGAINB
OTS2
CONT
ITS3
CONT
PCM_RXEN2 RXGAIN_PCM2
RXGAIN_ITS1
RXGAINB CODECB_RXEN
D/A1
G.711
Decoder
LPEN1
LPF
AMP3
RXGAIN_PCM0
GSX0
G.729.A
TXGAIN_SC
A/D0
BPF
RC0
TXGAINA CODECA_TXEN
AMP0
AIN0P
PCM_RXEN1
TXGEN
TXDETA
10k
Sin
LPAD
+
- ATTs
Center
Clip
CH1
SC_TXEN
GPAD Sout
TXGAIN Encoder
_CH1
G.711
Echo Canceller
AFF
STGAINA
RX1TX2
_GAIN
D/A0
VFRO0
LPF
GC
Rin
ATTr
RXGAIN_SC
CODECA_RXEN
RXGAIN
_CH1
Bus Control
Unit
G.729.A
RDB
CSB
RXGEN
RXGENA
RXGAIN
_CH2
RXDET
DVDD2
TXDETA
DVDD1
TXDETB
DVDD0
FSK_DET
FDET_RQ
FDET_FER/FDET_OER
FDET_D[7:0]
DTMF_DET
TGEN1_EXFLAG
TONE_GEN1
(TONEC/D)
TGEN0_EXFLAG
TONE_GEN0
(TONEA/B)
POWER
PLL
MCK
CKGN
RXDET_PCM
TONE_DET0
TONE0_DET
TONE_DET1
TONE1_DET
RXGENB_EN
FGEN_FLAG
SYNC(8kHz)
TXGEN
DPGEN
RXGENA
DPDET
RXGENA_EN
DTMF_CODE[3:0]
DGND2
DGND1
TIMER
Generator path setting
DTMF_REC
RXDET
RX
Buffer1
CH2
TIMOVF
Frame/DMA
Controller
GPIO2
Control
Register
GPIO0
DP_DET
DTMF_DET
RXGENB
DTMF_CODE[3:0]
TONE0_DET
RXGEN
TONE1_DET
DP_DET
FSK_GEN
AGND
A0-A7
8b
DC_EN
RX_SIG
VREF
Detector path setting
G.711
16b
RX
Buffer0
T
CH1 S
W
Decoder
SC_RXEN
AMP2
VREGOUT
FR0B
WRB
Speech Codec
D0-D15
Rout
RXGAINA
AVDD
TX
Buffer1
CH2
RX2TX1
_GAIN
10k
DGND0
ACK1B/
GPIOA[5]
ACK0B/
GPIOA[4]
FR1B
TX
Buffer0
T
S
W
DC_EN
TXGAIN
_CH2
Linear PCM
Codec
(CODEC_A)
AVREF
PCMI
RXGAIN_PCM1
PCM_RXEN0
AIN0N
S/P
ITS2
CONT
RXGAIN_ITS2
RXGENB
CLKSEL
ITS1
CONT
RXDET_PCM
VFRO1
SYNC
BCLK
G.711
Decoder
10k
PCMO
P/S
G.711
Encoder
TXGAIN_PCM2 PCM_TXEN2
Linear PCM
Codec
(CODEC_B)
OTS1
CONT
INT
INTB/
GPIOA[6]
FDET_RQ
FDET_FER/FDET_OER
OSC
12.288MHz
FGEN_FLAG
TIMOVF
VGB
Note: Restrictions on I/O pins
: can be used in 100-pin packages only.
8
6
4
GPIOA
[3:0]
GPIOB
[5:0]
GPIOC
[7:0]
PDNB
TST1
TST0
CLKOUT
XI
XO
This example shows the configuration for making calls with an analog telephone set (A-TEL) on the NW side by
connecting the analog telephone interface on the Linear PCM CODEC_A side.
RX_SIG
Linear
PCM
Codec
(CODEC
_B)
A-TEL
Linear
PCM
Codec
(CODEC
_A)
EC
PCM
Codec
PCM
I/F
Speech
Codec
MCU
I/F
VoIP-NW
RX_SIG
ML7204 (Configuration Example 1)
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Configuration Example 2 (Basic Call, CODEC_B)
GPIOA
[3:0]
GPIOB
[5:0]
GPIOC
[7:0]
TST1
TST0
PDNB
CLKOUT
XI
XO
This example shows the configuration for making calls with an analog telephone set (A-TEL) on the NW side by
connecting the analog telephone interface on the Linear PCM CODEC_B side.
RX_SIG
A-TEL
Linear
PCM
Codec
(CODEC
_B)
Linear
PCM
Codec
(CODEC
_A)
EC
PCM
Codec
PCM
I/F
Speech
Codec
MCU
I/F
VoIP-NW
RX_SIG
ML7204 (Configuration Example 2)
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Configuration Example 3 (Calling Using Extension with PCM)
GSX1
TXGAIN_PCM1 PCM_TXEN1
TXDETB
10k
AIN1N
A/D1
PCM I/F
LPEN0
G.711
Encoder
RC1
TXGAINB CODECB_TXEN
AMP1
PCM Codec
RX_SIG
BPF
TXGAIN_PCM0
PCM_TXEN0
STGAINB
OTS2
CONT
ITS3
CONT
RXGAIN_PCM2
RXGAIN_ITS1
RXGAINB CODECB_RXEN
D/A1
VFRO1
G.711
Decoder
LPEN1
LPF
AMP3
RXGAIN_PCM0
GSX0
A/D0
G.729.A
TXGAIN_SC
RC0
BPF
TXGAINA
AMP0
AIN0P
PCM_RXEN1
TXGEN
TXDETA
10k
CODECA_TXEN
Sin
LPAD
+
- ATTs
Center
Clip
CH1
TXGAIN
_CH1
SC_TXEN
GPAD Sout
Echo Canceller
AFF
STGAINA
Encoder
G.711
VFRO0
LPF
GC
Rout
ATTr
RXGAIN_SC
Rin
CODECA_RXEN
RXGAIN
_CH1
RXGEN
RXGENA
RXDET
CSB
DVDD2
TXDETA
DVDD1
TXDETB
DVDD0
FSK_DET
FDET_RQ
FDET_FER/FDET_OER
FDET_D[7:0]
DTMF_DET
TGEN1_EXFLAG
TONE_GEN1
(TONEC/D)
TGEN0_EXFLAG
TONE_GEN0
(TONEA/B)
MCK
CKGN
RXDET_PCM
TONE_DET0
TONE0_DET
TONE_DET1
TONE1_DET
SYNC(8kHz)
RXGENB_EN
FGEN_FLAG
TXGEN
DPGEN
RXGENA
DPDET
RXGENA_EN
DTMF_CODE[3:0]
DGND2
PLL
TIMER
Generator path setting
DTMF_REC
RXGENB
RXGEN
RXDET
A0-A7
8b
RX
Buffer1
CH2
TIMOVF
Frame/DMA
Controller
GPIO2
Control
Register
GPIO0
DP_DET
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
FSK_GEN
AGND
G.711
16b
DC_EN
VREF
Detector path setting
VREGOUT
RDB
RX
Buffer0
T
CH1 S
W
Decoder
RXGAIN
_CH2
RX_SIG
AVDD
Bus Control
Unit
G.729.A
SC_RXEN
AMP2
DGND0
FR0B
WRB
Speech Codec
D0-D15
RXGAINA
D/A0
POWER
TX
Buffer1
CH2
RX2TX1
_GAIN
RX1TX2
_GAIN
10k
DGND1
ACK1B/
GPIOA[5]
ACK0B/
GPIOA[4]
FR1B
TX
Buffer0
T
S
W
DC_EN
TXGAIN
_CH2
Linear PCM
Codec
(CODEC_A)
AVREF
PCMI
RXGAIN_PCM1
PCM_RXEN0
AIN0N
S/P
ITS2
CONT
RXGAIN_ITS2
RXGENB
CLKSEL
ITS1
CONT
RXDET_PCM
10k
SYNC
BCLK
G.711
Decoder
PCM_RXEN2
PCMO
P/S
G.711
Encoder
TXGAIN_PCM2 PCM_TXEN2
Linear PCM
Codec
(CODEC_B)
OTS1
CONT
INT
INTB/
GPIOA[6]
FDET_RQ
FDET_FER/FDET_OER
OSC
12.288MHz
FGEN_FLAG
TIMOVF
VGB
Note: Restrictions on I/O pins
: can be used in 100-pin packages only.
8
6
4
GPIOA
[3:0]
GPIOB
[5:0]
GPIOC
[7:0]
TST1
TST0
CLKOUT
PDNB
XI
XO
This example shows the configuration for making calls using extension between two analog telephone sets
(A-TEL1 and A-TEL2) on the equipment that has two or more analog telephone interface ports.
ML7204
(Configuration Example 3)
A-TEL1
ML7204
(Configuration Example 3)
A-TEL2
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Configuration Example 4 (Three-Way Calling: Terminal Side [Two Parties] – NW Side [One Party])
GPIOA
[3:0]
GPIOB
[5:0]
GPIOC
[7:0]
TST1
TST0
CLKOUT
PDNB
XI
XO
This example shows the configuration for making three-way calling between the terminal side (two parties) and
the VoIP NW side (one party).
ML7204
(Configuration Example 3)
A-TEL2
VoIP-NW
ML7204
(Configuration
Example 4)
A-TEL1
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Configuration Example 5 (Three-Way Calling: Terminal Side [One Party] – NW Side [Two Parties])
GSX1
TXGAIN_PCM1 PCM_TXEN1
TXDETB
10k
AIN1N
A/D1
PCM I/F
LPEN0
G.711
Encoder
RC1
TXGAINB CODECB_TXEN
AMP1
PCM Codec
RX_SIG
BPF
TXGAIN_PCM0
PCM_TXEN0
STGAINB
OTS2
CONT
ITS3
CONT
RXGAIN_PCM2
RXGAIN_ITS1
RXGAINB CODECB_RXEN
D/A1
VFRO1
G.711
Decoder
LPEN1
LPF
AMP3
GSX0
G.729.A
TXGAIN_SC
A/D0
BPF
RC0
TXGAINA CODECA_TXEN
AMP0
AIN0P
PCM_RXEN1
TXGEN
TXDETA
10k
Sin
LPAD
+
- ATTs
Center
Clip
CH1
TXGAIN Encoder
_CH1
SC_TXEN
GPAD Sout
G.711
Echo Canceller
AFF
STGAINA
RX1TX2
_GAIN
VFRO0
LPF
GC
Rout
ATTr
RXGAIN_SC
Rin
CODECA_RXEN
RXGAIN
_CH1
RXGEN
RXGENA
Decoder
RXDET
RXGAIN
_CH2
VREF
DVDD2
TXDETA
DVDD1
TXDETB
FSK_DET
DTMF_REC
DVDD0
FDET_RQ
FDET_FER/FDET_OER
FDET_D[7:0]
DTMF_DET
TGEN1_EXFLAG
TONE_GEN1
(TONEC/D)
TGEN0_EXFLAG
TONE_GEN0
(TONEA/B)
MCK
CKGN
RXDET_PCM
TONE_DET0
TONE0_DET
TONE_DET1
TONE1_DET
SYNC(8kHz)
FGEN_FLAG
TXGEN
DPGEN
RXGENA
DPDET
RXGENA_EN
DTMF_CODE[3:0]
DGND2
PLL
TIMER
Generator path setting
Detector path setting
RXGENB_EN
RXGENB
RXGEN
CSB
RXDET
CH1
G.711
16b
RX
Buffer0
T
S
W
A0-A7
8b
RX
Buffer1
CH2
TIMOVF
Frame/DMA
Controller
GPIO2
Control
Register
GPIO0
DP_DET
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
FSK_GEN
AGND
VREGOUT
RDB
DC_EN
RX_SIG
AVDD
WRB
G.729.A
SC_RXEN
AMP2
DGND0
FR0B
Bus Control
Unit
Speech Codec
D0-D15
RXGAINA
D/A0
POWER
TX
Buffer1
CH2
RX2TX1
_GAIN
10k
DGND1
ACK1B/
GPIOA[5]
ACK0B/
GPIOA[4]
FR1B
TX
Buffer0
T
S
W
DC_EN
TXGAIN
_CH2
Linear PCM
Codec
(CODEC_A)
AVREF
PCMI
RXGAIN_PCM1
RXGAIN_PCM0
PCM_RXEN0
AIN0N
S/P
ITS2
CONT
RXGAIN_ITS2
RXGENB
CLKSEL
ITS1
CONT
RXDET_PCM
10k
SYNC
BCLK
G.711
Decoder
PCM_RXEN2
PCMO
P/S
G.711
Encoder
TXGAIN_PCM2 PCM_TXEN2
Linear PCM
Codec
(CODEC_B)
OTS1
CONT
INT
INTB/
GPIOA[6]
FDET_RQ
FDET_FER/FDET_OER
OSC
12.288MHz
FGEN_FLAG
TIMOVF
VGB
Note: Restrictions on I/O pins
: can be used in 100-pin packages only.
8
6
4
GPIOA
[3:0]
GPIOB
[5:0]
GPIOC
[7:0]
TST1
TST0
CLKOUT
PDNB
XI
XO
This example shows the configuration for making three-way calling between the terminal side (one party) and
VoIP NW side (two parties).
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Configuration Example 6 (Three-Way Calling: Terminal Side [Three Parties])
GSX1
TXGAIN_PCM1
TXDETB
10k
AIN1N
A/D1
PCM Codec
PCM I/F
LPEN0
G.711
Encoder
RC1
TXGAINB CODECB_TXEN
AMP1
PCM_TXEN1
RX_SIG
BPF
TXGAIN_PCM0
PCM_TXEN0
STGAINB
OTS2
CONT
ITS3
CONT
PCM_RXEN2 RXGAIN_PCM2
RXGAIN_ITS1
RXGAINB CODECB_RXEN
D/A1
G.711
Decoder
LPEN1
LPF
AMP3
RXGAIN_PCM0
GSX0
A/D0
G.729.A
TXGAIN_SC
RC0
BPF
TXGAINA CODECA_TXEN
AMP0
AIN0P
PCM_RXEN1
TXGEN
TXDETA
10k
Sin
LPAD
+
- ATTs
Center
Clip
CH1
TXGAIN
_CH1
SC_TXEN
GPAD Sout
Echo Canceller
AFF
STGAINA
Encoder
G.711
RX1TX2
_GAIN
VFRO0
LPF
GC
Rout
ATTr
RXGAIN_SC
Rin
CODECA_RXEN
RXGAIN
_CH1
RXGEN
RXGENA
Decoder
RXDET
RXGAIN
_CH2
VREF
DVDD2
TXDETA
DVDD1
TXDETB
FSK_DET
DTMF_REC
DVDD0
FDET_RQ
FDET_FER/FDET_OER
FDET_D[7:0]
DTMF_DET
TGEN1_EXFLAG
TONE_GEN1
(TONEC/D)
TGEN0_EXFLAG
TONE_GEN0
(TONEA/B)
MCK
CKGN
RXDET_PCM
TONE_DET0
TONE0_DET
TONE_DET1
TONE1_DET
SYNC(8kHz)
FGEN_FLAG
TXGEN
DPGEN
RXGENA
DPDET
RXGENA_EN
DTMF_CODE[3:0]
DGND2
PLL
TIMER
Generator path setting
Detector path setting
RXGENB_EN
RXGENB
RXGEN
CSB
RXDET
CH1
G.711
16b
RX
Buffer0
T
S
W
A0-A7
8b
RX
Buffer1
CH2
TIMOVF
Frame/DMA
Controller
GPIO2
Control
Register
GPIO0
DP_DET
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
FSK_GEN
AGND
VREGOUT
RDB
DC_EN
RX_SIG
AVDD
WRB
G.729.A
SC_RXEN
AMP2
DGND0
FR0B
Bus Control
Unit
Speech Codec
D0-D15
RXGAINA
D/A0
POWER
TX
Buffer1
CH2
RX2TX1
_GAIN
10k
DGND1
ACK1B/
GPIOA[5]
ACK0B/
GPIOA[4]
FR1B
TX
Buffer0
T
S
W
DC_EN
TXGAIN
_CH2
Linear PCM
Codec
(CODEC_A)
AVREF
PCMI
RXGAIN_PCM1
PCM_RXEN0
AIN0N
S/P
ITS2
CONT
RXGAIN_ITS2
RXGENB
CLKSEL
ITS1
CONT
RXDET_PCM
VFRO1
SYNC
BCLK
G.711
Decoder
10k
PCMO
P/S
G.711
Encoder
TXGAIN_PCM2 PCM_TXEN2
Linear PCM
Codec
(CODEC_B)
OTS1
CONT
INT
INTB/
GPIOA[6]
FDET_RQ
FDET_FER/FDET_OER
OSC
12.288MHz
FGEN_FLAG
TIMOVF
VGB
Note: Restrictions on I/O pins
: can be used in 100-pin packages only.
8
6
4
GPIOA
[3:0]
GPIOB
[5:0]
GPIOC
[7:0]
TST1
TST0
CLKOUT
PDNB
XI
XO
This example shows the configuration for making three-way calling between analog telephones (A-TEL1,
A-TEL2, and A-TEL3) on the equipment with multiple analog telephone interface ports.
208/214
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Configuration Example 7 (CODEC-A-CODEC-B Loop Back Mode)
GSX1
TXGAIN_PCM1 PCM_TXEN1
TXDETB
10k
AIN1N
A/D1
PCM I/F
LPEN0
G.711
Encoder
RC1
TXGAINB CODECB_TXEN
AMP1
PCM Codec
RX_SIG
BPF
TXGAIN_PCM0
PCM_TXEN0
STGAINB
OTS2
CONT
ITS3
CONT
PCM_RXEN2 RXGAIN_PCM2
RXGAIN_ITS1
RXGAINB CODECB_RXEN
D/A1
G.711
Decoder
LPEN1
LPF
AMP3
RXGAIN_PCM0
GSX0
A/D0
G.729.A
TXGAIN_SC
RC0
BPF
TXGAINA CODECA_TXEN
AMP0
AIN0P
PCM_RXEN1
TXGEN
TXDETA
10k
Sin
LPAD
+
- ATTs
Center
Clip
CH1
TXGAIN Encoder
_CH1
SC_TXEN
GPAD Sout
G.711
Echo Canceller
AFF
STGAINA
RX1TX2
_GAIN
VFRO0
LPF
GC
Rout
ATTr
RXGAIN_SC
Rin
CODECA_RXEN
RXGAIN
_CH1
RXGEN
RXGENA
RXDET
VREF
CSB
DVDD2
TXDETA
DVDD1
TXDETB
FSK_DET
DTMF_REC
DVDD0
FDET_RQ
FDET_FER/FDET_OER
FDET_D[7:0]
DTMF_DET
TGEN1_EXFLAG
TONE_GEN1
(TONEC/D)
TGEN0_EXFLAG
DTMF_CODE[3:0]
TONE_GEN0
(TONEA/B)
DGND2
PLL
MCK
CKGN
RXDET_PCM
TONE_DET0
TONE0_DET
TONE_DET1
TONE1_DET
SYNC(8kHz)
FGEN_FLAG
TXGEN
DPGEN
RXGENA
DPDET
RXGENA_EN
RXGENB_EN
RXGENB
RXGEN
RXDET
A0-A7
8b
RX
Buffer1
CH2
TIMOVF
Frame/DMA
Controller
GPIO2
Control
Register
GPIO0
DP_DET
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
FSK_GEN
AGND
G.711
16b
DC_EN
TIMER
Generator path setting
Detector path setting
VREGOUT
RDB
RX
Buffer0
T
CH1 S
W
Decoder
RXGAIN
_CH2
RX_SIG
AVDD
Bus Control
Unit
G.729.A
SC_RXEN
AMP2
DGND0
FR0B
WRB
Speech Codec
D0-D15
RXGAINA
D/A0
POWER
TX
Buffer1
CH2
RX2TX1
_GAIN
10k
DGND1
ACK1B/
GPIOA[5]
ACK0B/
GPIOA[4]
FR1B
TX
Buffer0
T
S
W
DC_EN
TXGAIN
_CH2
Linear PCM
Codec
(CODEC_A)
AVREF
PCMI
RXGAIN_PCM1
PCM_RXEN0
AIN0N
S/P
ITS2
CONT
RXGAIN_ITS2
RXGENB
CLKSEL
ITS1
CONT
RXDET_PCM
VFRO1
SYNC
BCLK
G.711
Decoder
10k
PCMO
P/S
G.711
Encoder
TXGAIN_PCM2 PCM_TXEN2
Linear PCM
Codec
(CODEC_B)
OTS1
CONT
INT
INTB/
GPIOA[6]
FDET_RQ
FDET_FER/FDET_OER
OSC
12.288MHz
FGEN_FLAG
TIMOVF
VGB
Note: Restrictions on I/O pins
: can be used in 100-pin packages only.
8
6
4
GPIOA
[3:0]
GPIOB
[5:0]
GPIOC
[7:0]
TST1
TST0
CLKOUT
PDNB
XI
XO
This example shows the configuration where CODEC_A and CODEC_B are connected in loopback mode
according to the internal path settings.
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Configuration Example 8 (Calling Using Extension with PCM + Extended Call Functions)
GPIO
B[5:0]
GPIO
A[3:0]
GPIO
C[7:0]
TST1
TST0
PDNB
CLKOUT
XI
XO
MCU
I/F
RX_SIG
PCM
Codec
Linear
PCM
Codec
(CODEC
_A)
EC
RX_SIG
Linear
PCM
Codec
(CODEC
_B)
Linear
PCM
Codec
(CODEC
_A)
Linear
PCM
Codec
(CODEC
_B)
EC
RX_SIG
RX_SIG
Speech
Codec
PCM
I/F
MCU
I/F
Speech
Codec
PCM
Codec
PCM
I/F
This example shows the configuration for making calls using extension between two analog telephone sets
(A-TEL1 and A-TEL2) on the equipment that has two or more analog telephone interface ports. This
configuration also supports various functions of extended calling between the Mike/Speaker of A-TEL2 and an
MCU.
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APPLICATION CIRCUITS
ML7204-003GA
1.4 V
50
52
51
Analog input
53
54
55
2.2uF
AIN0P
GSX0
AIN0N
GSX1
AIN1N
AVREF
0.1uF
56
Analog output
57
45
46
47
48
General-purpose
I/O pins
VFRO0
VFRO1
GPIOA[0]
GPIOA[1]
GPIOA[2]
GPIOA[3]
+3.3 V +3.3 V
43
3
4
500Ω
PCM
I/F
5
6
Power-down control
12.288 MHz
crystal
42
60
61
CLKSEL
PCMO
PCMI
BCLK
SYNC
PDNB
XI
XO
1MΩ
8pF
8pF
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
41
40
39
38
37
36
35
34
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MCU
I/F
+3.3 V
ACK0B
ACK1B
FR0B
FR1B
INTB
CSB
RDB
WRB
VBG
8
9
10
11
12
13
14
15
64
150pF
+3.3 V
+
7
33
62
49
10uF 0.1uF
16
44
59
58
DVDD0
DVDD1
DVDD2
AVDD
DGND0
DGND1
DGND2
AGND
VREGOUT
63
0.1uF 10uF
TST1
TST0
1
2
+
Conditions
 Frame mode
 SYNC and BCLK:
Configured to be
output
(CLKSEL = "1")
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PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact ROHM's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
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REVISION HISTORY
Document
No.
Date
FEDL7204-003-01
June 14, 2006
FEDL7204-003-02
Oct 14, 2011
Page
Previous Current
Edition
Edition
–
–
1 - 224
1 - 214
Description
First Edition
Deletions of 100 pin package type.
(ML7204V-003TB)
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ML7204-003
NOTICE
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"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be
obtained from LAPIS Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
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