NTD4810N Power MOSFET 30 V, 54 A, Single N--Channel, DPAK/IPAK Features • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb--Free Devices http://onsemi.com V(BR)DSS Applications RDS(on) MAX 10 mΩ @ 10 V 30 V • CPU Power Delivery • DC--DC Converters ID MAX 54 A 15.7 mΩ @ 4.5 V D MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) 30 V VGS 20 V ID 10.8 A Continuous Drain Current (RθJA) (Note 1) TA = 25°C Power Dissipation (RθJA) (Note 1) TA = 25°C PD 2.0 W Continuous Drain Current (RθJA) (Note 2) TA = 25°C ID 8.6 A Steady State 8.4 TA = 85°C 6.7 TA = 25°C PD 1.28 W Continuous Drain Current (RθJC) (Note 1) TC = 25°C ID 54 A Power Dissipation (RθJC) (Note 1) TC = 25°C PD 50 W TA = 25°C IDM 120 A TA = 25°C IDmaxPkg 45 A TJ, Tstg -- 55 to 175 °C Pulsed Drain Current TC = 85°C tp=10ms Current Limited by Package Operating Junction and Storage Temperature Source Current (Body Diode) S 42 IS 41 A Drain to Source dV/dt dV/dt 6.0 V/ns Single Pulse Drain--to--Source Avalanche Energy (VDD = 24 V, VGS = 10 V, L = 1.0 mH, IL(pk) = 14 A, RG = 25 Ω) EAS 98 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4 4 4 1 2 1 3 CASE 369AA DPAK (Bent Lead) STYLE 2 2 3 1 2 3 CASE 369AC CASE 369D 3 IPAK IPAK (Straight Lead) (Straight Lead DPAK) MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain 4810NG Power Dissipation (RθJA) (Note 2) TA = 85°C N--Channel G 4 Drain 4810NG VDSS YWW Unit YWW Gate--to--Source Voltage Value 4810NG Drain--to--Source Voltage Symbol YWW Parameter 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y WW 4810N G = Year = Work Week = Device Code = Pb--Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2010 June, 2010 -- Rev. 8 1 Publication Order Number: NTD4810N/D NTD4810N THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction--to--Case (Drain) Parameter RθJC 3.0 °C/W Junction--to--TAB (Drain) RθJC--TAB 3.5 Junction--to--Ambient -- Steady State (Note 1) RθJA 75 Junction--to--Ambient -- Steady State (Note 2) RθJA 117 1. Surface--mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface--mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Drain--to--Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain--to--Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate--to--Source Leakage Current IDSS V 27 VGS = 0 V, VDS = 24 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = 20 V VGS(TH) VGS = VDS, ID = 250 mA mA 100 nA 2.5 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain--to--Source On Resistance VGS(TH)/TJ RDS(on) 5.2 VGS = 10 to 11.5 V ID = 30 A 8.0 ID = 15 A 7.8 VGS = 4.5 V ID = 30 A 12 ID = 15 A Forward Transconductance gFS 1.5 VDS = 15 V, ID = 10 A mV/°C 10 mΩ 15.7 11 9.0 S CHARGES AND CAPACITANCES Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate--to--Source Charge QGS Gate--to--Drain Charge QGD Total Gate Charge QG(TOT) VGS = 0 V, f = 1.0 MHz, VDS = 12 V VGS = 4.5 V, VDS = 15 V, ID = 30 A 1165 1350 284 330 154 200 9.2 11 pF nC 1.3 3.3 4.4 VGS = 11.5 V, VDS = 15 V, ID = 30 A 21 nC 11.5 ns SWITCHING CHARACTERISTICS (Note 4) Turn--On Delay Time Rise Time Turn--Off Delay Time Fall Time Turn--On Delay Time Rise Time Turn--Off Delay Time Fall Time td(on) tr td(off) VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 Ω 20.7 13.8 tf 3.8 td(on) 7.2 tr td(off) VGS = 11.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 Ω tf 20.7 21.8 2.6 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns NTD4810N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit TJ = 25°C 0.92 1.2 V TJ = 125°C 0.79 DRAIN--SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD tRR Charge Time ta Discharge Time tb Reverse Recovery Time VGS = 0 V, IS = 30 A 18.2 VGS = 0 V, dIs/dt = 100 A/ms, IS = 30 A ns 10.6 7.6 QRR 8.8 nC Source Inductance LS 2.49 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK LD Gate Inductance LG 3.46 Gate Resistance RG 2.4 PACKAGE PARASITIC VALUES TA = 25°C http://onsemi.com 3 1.88 Ω NTD4810N TYPICAL PERFORMANCE CURVES 40 3.6 V 30 3.4 V 20 3.2 V 3V 10 0 2.8 V 0 1 2 3 5 4 40 30 20 TJ = 125°C TJ = 25°C 10 TJ = --55°C 0 1 2 4 3 5 VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS) VGS, GATE--TO--SOURCE VOLTAGE (VOLTS) Figure 1. On--Region Characteristics Figure 2. Transfer Characteristics ID = 30 A TJ = 25°C 0.043 0.038 0.033 0.028 0.023 0.018 0.013 0.008 0.003 VDS ≥ 10 V 50 0 0.048 3 4 6 5 7 8 9 10 0.020 TJ = 25°C 0.015 VGS = 4.5 V 0.010 VGS = 11.5 V 0.005 0 10 15 20 25 30 35 40 45 50 55 VGS, GATE--TO--SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On--Resistance vs. Gate--to--Source Voltage Figure 4. On--Resistance vs. Drain Current and Gate Voltage 100,000 2.0 VGS = 0 V ID = 30 A VGS = 10 V TJ = 175°C 10,000 1.5 IDSS, LEAKAGE (nA) RDS(on), DRAIN--TO--SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN--TO--SOURCE RESISTANCE (Ω) 3.8 V TJ = 25°C ID, DRAIN CURRENT (AMPS) 50 60 4V 10 V 6V 5V 4.5 V RDS(on), DRAIN--TO--SOURCE RESISTANCE (Ω) ID, DRAIN CURRENT (AMPS) 60 1.0 0.5 0 --50 --25 1000 TJ = 125°C 100 10 0 25 50 75 100 125 150 175 5 10 15 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS) Figure 5. On--Resistance Variation with Temperature Figure 6. Drain--to--Source Leakage Current vs. Drain Voltage http://onsemi.com 4 25 NTD4810N TYPICAL PERFORMANCE CURVES VDS = 0 V VGS = 0 V TJ = 25°C C, CAPACITANCE (pF) Ciss 1500 Ciss 1000 Crss 500 Coss 0 10 Crss 5 VGS 0 VDS 5 10 15 20 12 VGS , GATE--TO--SOURCE VOLTAGE (VOLTS) 2000 25 9 8 7 6 5 3 2 ID = 30 A 0 V < VGS < 11.5 V 1 TJ = 25°C 0 0 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 QG, TOTAL GATE CHARGE (nC) Figure 8. Gate--To--Source and Drain--To--Source Voltage vs. Total Charge Figure 7. Capacitance Variation IS, SOURCE CURRENT (AMPS) t, TIME (ns) 30 VDD = 15 V ID = 30 A VGS = 11.5 V 100 td(off) tr 10 td(on) tf 1 1 10 RG, GATE RESISTANCE (OHMS) VGS = 0 V 25 15 10 5 0 0.5 100 0.1 1 ms 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS) 100 EAS, SINGLE PULSE DRAIN--TO--SOURCE AVALANCHE ENERGY (mJ) I D, DRAIN CURRENT (AMPS) 100 ms 1 0.7 0.8 0.9 1.0 Figure 10. Diode Forward Voltage vs. Current 10 ms VGS = 20 V SINGLE PULSE TC = 25°C 0.6 VSD, SOURCE--TO--DRAIN VOLTAGE (VOLTS) 1000 10 TJ = 25°C 20 Figure 9. Resistive Switching Time Variation vs. Gate Resistance 100 Q2 Q1 4 GATE--TO--SOURCE OR DRAIN--TO--SOURCE VOLTAGE (VOLTS) 1000 QT 11 10 110 100 ID = 14 A 90 80 70 60 50 40 30 20 10 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTD4810N TYPICAL PERFORMANCE CURVES I D, DRAIN CURRENT (AMPS) 100 25°C 100°C 125°C 10 1 0.1 10 100 PULSE WIDTH (ms) 1 1000 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Figure 13. Avalanche Characteristics 1.0 D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE 0.01 1.0E--05 1.0E--04 t1 t2 DUTY CYCLE, D = t1/t2 1.0E--03 1.0E--02 t, TIME (ms) RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) -- TC = P(pk) RθJC(t) 1.0E--01 1.0E+00 1.0E+01 Figure 14. Thermal Response ORDERING INFORMATION Package Shipping† NTD4810NT4G DPAK (Pb--Free) 2500 Tape & Reel NTD4810N--1G IPAK (Pb--Free) 75 Units/Rail NTD4810N--35G IPAK Trimmed Lead (3.5 0.15 mm) (Pb--Free) 75 Units/Rail Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD4810N PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA--01 ISSUE B A E b3 c2 B Z D 1 L4 A 4 L3 b2 e 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C H DETAIL A 3 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z c b 0.005 (0.13) M C H L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 90° CW STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 ------ 0.040 0.155 ------ 6.17 0.243 SCALE 3:1 mm inches *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 -----1.01 3.93 ------ NTD4810N PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC--01 ISSUE O B V NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. C E R DIM A B C D E F G H J K R V W A SEATING PLANE K W F J G D H 3 PL 0.13 (0.005) W INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25 IPAK (STRAIGHT LEAD DPAK) CASE 369D--01 ISSUE B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. C B E R 4 Z A S 1 2 3 --T-SEATING PLANE K J F D G H M INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 ------ MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 ------ STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 3 PL 0.13 (0.005) DIM A B C D E F G H J K R S V Z T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303--675--2175 or 800--344--3860 Toll Free USA/Canada Fax: 303--675--2176 or 800--344--3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800--282--9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81--3--5773--3850 http://onsemi.com 8 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTD4810N/D