TI1 LF398H Monolithic sample-and-hold circuit Datasheet

Product
Folder
Sample &
Buy
Technical
Documents
Support &
Community
Tools &
Software
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
LF298, LFx98x Monolithic Sample-and-Hold Circuits
1 Features
3 Description
•
•
•
•
•
•
•
•
The LF298 and LFx98x devices are monolithic
sample-and-hold circuits that use BI-FET technology
to obtain ultrahigh DC accuracy with fast acquisition
of signal and low droop rate. Operating as a unitygain follower, DC gain accuracy is 0.002% typical and
acquisition time is as low as 6 µs to 0.01%. A bipolar
input stage is used to achieve low offset voltage and
wide bandwidth. Input offset adjust is accomplished
with a single pin and does not degrade input offset
drift. The wide bandwidth allows the LF198-N to be
included inside the feedback loop of 1-MHz
operational amplifiers without having stability
problems. Input impedance of 1010 Ω allows highsource impedances to be used without degrading
accuracy.
1
•
•
•
Operates from ±5-V to ±18-V Supplies
Less than 10-μs Acquisition Time
Logic Input Compatible With TTL, PMOS, CMOS
0.5-mV Typical Hold Step at Ch = 0.01 µF
Low Input Offset
0.002% Gain Accuracy
Low Output Noise in Hold Mode
Input Characteristics Do Not Change During Hold
Mode
High Supply Rejection Ratio in Sample or Hold
Wide Bandwidth
Space Qualified, JM38510
2 Applications
•
•
•
•
•
•
Ramp Generators With Variable Reset Level
Integrators With Programmable Reset Level
Synchronous Correlators
2-Channel Switches
DC and AC Zeroing
Staircase Generators
P-channel junction FETs are combined with bipolar
devices in the output amplifier to give droop rates as
low as 5 mV/min with a 1-µF hold capacitor. The
JFETs have much lower noise than MOS devices
used in previous designs and do not exhibit high
temperature instabilities. The overall design ensures
no feedthrough from input to output in the hold mode,
even for input signals equal to the supply voltages.
Logic inputs on the LF198-N are fully differential with
low input current, allowing for direct connection to
TTL, PMOS, and CMOS. Differential threshold is
1.4 V. The LF198-N will operate from ±5-V to ±18-V
supplies.
An A version is available with tightened electrical
specifications.
Device Information(1)
PART NUMBER
LF298, LFx98x
PACKAGE
BODY SIZE (NOM)
SOIC (14)
8.65 mm × 3.91 mm
TO-99 (8)
9.08 mm × 9.08 mm
PDIP (8)
9.81 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Connection
Acquisition Time
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics, LF198-N and LF298 ........
Electrical Characteristics, LF398-N...........................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
7.1 TTL and CMOS 3 V ≤ VLOGIC (Hi State) ≤ 7 V ....... 10
7.2 CMOS 7 V ≤ VLOGIC (Hi State) ≤ 15 V .................... 10
7.3 Operational Amplifier Drive ..................................... 11
8
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Applications ................................................ 15
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2000) to Revision B
•
2
Page
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
www.ti.com
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
5 Pin Configuration and Functions
P Package
8-Pin PDIP
Top View
D Package
14-Pin SOIC
Top View
LMC Package
8-Pin TO-99
Top View
A military RETS electrical test specification is available on request. The LF198-N may also be procured to Standard
Military Drawing #5962-8760801GA or to MIL-STD-38510 part ID JM38510/12501SGA.
Pin Functions
PIN
NAME
TYPE (1)
DESCRIPTION
SOIC
TO-99
PDIP
V+
12
1
1
P
Positive supply
OFFSET ADJUST
14
2
2
A
DC offset compensation pin
INPUT
1
3
3
A
Analog Input
V
3
4
4
P
Negative supply
OUTPUT
7
5
5
O
Output
Ch
8
6
6
A
Hold capacitor
LOGIC REFERENCE
10
7
7
I
Reference for LOGIC input
LOGIC
11
8
8
I
Logic input for Sample and Hold modes
2, 4, 5, 6, 9, 13
—
—
NA
–
NC
(1)
No connect
P = Power, G = Ground, I = Input, O = Output, A = Analog
Copyright © 2000–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
3
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
Supply voltage
Power dissipation
(Package limitation, see
Operating ambient temperature
(3)
)
UNIT
±18
V
500
mW
LF198-N, LF198A-N
–55
125
°C
LF298
–25
85
°C
LF398-N, LF398A-N
0
Input voltage
Logic-to-logic reference differential voltage (see
MAX
(4)
)
7
Output short circuit duration
70
°C
±18
V
−30
V
Indefinite
Hold capacitor short circuit duration
Lead temperature
10
sec
H package (soldering, 10 sec.)
260
°C
N package (soldering, 10 sec.)
260
°C
M package: vapor phase (60 sec.)
215
°C
Infrared (15 sec.)
220
°C
150
°C
Storage temperature, Tstg
(1)
(2)
(3)
(4)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, RθJA, and the ambient
temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA) / RθJA, or the number given in the
Absolute Maximum Ratings, whichever is lower. The maximum junction temperature, TJMAX, for the LF198-N and LF198A-N is 150°C;
for the LF298, 115°C; and for the LF398-N and LF398A-N, 100°C.
Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the
supply voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least
2 V below the positive supply and 3 V above the negative supply.
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
TJ
Ambient temperature
NOM
MAX
±15
V
LF198-N, LF198A-N
–55
125
LF298
–25
85
0
70
LF398-N, LF398A-N
UNIT
°C
6.3 Thermal Information
THERMAL METRIC (1)
LF398-N
LF298, LF398-N
LFx98x
P (PDIP)
D (SOIC)
LMC (TO-99)
8 PINS
14 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
48.9
80.6
85 (2)
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
37.3
38.1
20
°C/W
RθJB
Junction-to-board thermal resistance
26.2
35.4
—
°C/W
ψJT
Junction-to-top characterization parameter
14.3
5.8
—
°C/W
ψJB
Junction-to-board characterization parameter
26.0
35.1
—
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Board mount in 400 LF/min air flow.
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
www.ti.com
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
6.4 Electrical Characteristics, LF198-N and LF298
The following specifications apply for –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V, +VS = +15 V, –VS = –15 V, TA = TJ = 25°C, Ch = 0.01
µF, RL = 10 kΩ, LOGIC REFERENCE = 0 V, LOGIC HIGH = 2.5 V, LOGIC LOW = 0 V unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TJ = 25°C
Input offset voltage (1)
TYP
MAX
1
3
mV
5
mV
5
25
nA
Full temperature range
TJ = 25°C
Input bias current (1)
Full temperature range
Input impedance
75
TJ = 25°C
10
TJ = 25°C, RL= 10k
Gain error
0.002%
Full temperature range
Feedthrough attenuation ratio at 1 kHz
TJ = 25°C, Ch = 0.01 µF
nA
GΩ
0.005%
0.02%
86
Tj = 25°C, “HOLD” mode
Output impedance
UNIT
96
0.5
Full temperature range
dB
2
Ω
4
Ω
HOLD step (2)
TJ = 25°C, Ch = 0.01 µF, VOUT = 0
0.5
2
mV
Supply current (1)
TJ ≥ 25°C
4.5
5.5
mA
Logic and logic reference input current
TJ = 25°C
2
10
µA
Leakage current into hold capacitor (1)
TJ = 25°C (3), hold mode
30
100
pA
ΔVOUT = 10 V, Ch = 1000 pF
Acquisition time to 0.1%
4
CH = 0.01 µF
Hold capacitor charging current
VIN – VOUT = 2 V
Supply voltage rejection ratio
VOUT = 0
Differential logic threshold
TJ = 25°C
20
µs
5
mA
80
110
dB
0.8
1.4
2.4
1
1
mV
2
mV
25
nA
TJ = 25°C
Input offset voltage (1)
Full temperature range
TJ = 25°C
Input bias current (1)
5
Full temperature range
Input impedance
75
TJ = 25°C
10
TJ = 25°C, RL = 10 k
Gain error
0.002%
Full temperature range
Feedthrough attenuation ratio at 1 kHz
TJ = 25°C, Ch = 0.01 µF
V
nA
GΩ
0.005%
0.01%
86
TJ = 25°C, “HOLD” mode
Output impedance
µs
96
0.5
dB
1
Ω
4
Ω
HOLD step (2)
TJ = 25°C, Ch = 0.01 µF, VOUT = 0
0.5
1
mV
Supply current (1)
TJ ≥ 25°C
4.5
5.5
mA
Logic and logic reference input current
TJ = 25°C
Leakage current into hold capacitor (1)
TJ = 25°C (3), hold mode
Full temperature range
ΔVOUT = 10 V, Ch = 1000 pF
Acquisition time to 0.1%
CH = 0.01 µF
2
10
µA
30
100
pA
4
6
µs
20
25
µs
Hold capacitor charging current
VIN – VOUT = 2 V
Supply voltage rejection ratio
VOUT = 0
90
110
Differential logic threshold
TJ = 25°C
0.8
1.4
(1)
(2)
(3)
5
mA
dB
2.4
V
These parameters ensured over a supply voltage range of ±5 to ±18 V, and an input range of –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V.
Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an
additional 0.5-mV step with a 5-V logic swing and a 0.01-µF hold capacitor. Magnitude of the hold step is inversely proportional to hold
capacitor value.
Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or
elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over
full input signal range.
Copyright © 2000–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
5
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
www.ti.com
6.5 Electrical Characteristics, LF398-N
The following specifications apply for –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V, +VS = +15 V, –VS = –15 V, TA = TJ = 25°C, Ch = 0.01
µF, RL = 10 kΩ, LOGIC REFERENCE = 0 V, LOGIC HIGH = 2.5 V, LOGIC LOW = 0 V unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TJ = 25°C
Input offset voltage (1)
TYP
MAX
2
7
mV
10
mV
50
nA
Full temperature range
TJ = 25°C
Input bias current (1)
10
Full temperature range
Input impedance
100
TJ = 25°C
10
TJ = 25°C, RL= 10 k
Gain error
0.004%
Full temperature range
Feedthrough attenuation ratio at 1 kHz
TJ = 25°C, Ch = 0.01 µF
TJ = 25°C, Ch = 0.01 µF, VOUT = 0
Supply current (1)
Logic and logic reference input current
Leakage current into hold capacitor (1)
TJ = 25°C (3), hold mode
0.5
TJ ≥ 25°C
4.5
6.5
mA
TJ = 25°C
2
10
µA
30
200
pA
Supply voltage rejection ratio
VOUT = 0
Differential logic threshold
TJ = 25°C
4
µs
5
mA
80
110
dB
0.8
1.4
2.4
2
2
mV
3
mV
25
nA
Full temperature range
TJ = 25°C
10
Full temperature range
50
TJ = 25°C
10
TJ = 25°C, RL = 10 k
0.004%
Full temperature range
Feedthrough attenuation ratio at 1 kHz
TJ = 25°C, Ch = 0.01 µF
TJ = 25°C, Ch = 0.01 µF, VOUT = 0
Supply current (1)
TJ ≥ 25°C
Logic and logic reference input current
TJ = 25°C
Leakage current into hold capacitor (1)
TJ = 25°C (3), hold mode
0.5
ΔVOUT = 10 V, Ch = 1000 pF
Acquisition time to 0.1%
CH = 0.01 µF
Ω
Ω
1
mV
4.5
6.5
mA
2
10
µA
30
100
pA
4
6
µs
20
25
µs
VIN – VOUT = 2 V
VOUT = 0
90
110
Differential logic threshold
TJ = 25°C
0.8
1.4
6
dB
1
6
Supply voltage rejection ratio
(3)
0.005%
1
Hold capacitor charging current
(1)
(2)
nA
GΩ
90
Full temperature range
HOLD step (2)
V
0.01%
86
TJ = 25°C, “HOLD” mode
Output impedance
µs
20
TJ = 25°C
Gain error
Ω
mV
VIN – VOUT = 2 V
Input impedance
Ω
2.5
CH = 0.01 µF
Input bias current (1)
4
1
Hold capacitor charging current
Input offset voltage (1)
dB
6
ΔVOUT = 10 V, Ch = 1000 pF
Acquisition time to 0.1%
0.01%
90
Full temperature range
HOLD step (2)
nA
GΩ
0.02%
80
TJ = 25°C, “HOLD” mode
Output impedance
UNIT
5
mA
dB
2.4
V
These parameters ensured over a supply voltage range of ±5 to ±18 V, and an input range of –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V.
Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an
additional 0.5-mV step with a 5-V logic swing and a 0.01-µF hold capacitor. Magnitude of the hold step is inversely proportional to hold
capacitor value.
Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or
elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over
full input signal range.
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
www.ti.com
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
6.6 Typical Characteristics
Figure 1. Aperture Time
Figure 2. Dielectric Absorption Error in Hold Capacitor
Figure 3. Dynamic Sampling Error
Figure 4. Output Droop Rate
Figure 5. Hold Step
Figure 6. Hold Settling Time
Copyright © 2000–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
7
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
www.ti.com
Typical Characteristics (continued)
8
Figure 7. Leakage Current into Hold Capacitor
Figure 8. Phase and Gain (Input to Output, Small Signal)
Figure 9. Gain Error
Figure 10. Power Supply Rejection
Figure 11. Output Short Circuit Current
Figure 12. Output Noise
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
www.ti.com
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
Typical Characteristics (continued)
Figure 13. Input Bias Current
Figure 14. Feedthrough Rejection Ratio (Hold Mode)
Figure 15. Hold Step vs Input Voltage
Figure 16. Output Transient at Start of Sample Mode
Figure 17. Output Transient at Start of Hold Mode
Copyright © 2000–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
9
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
www.ti.com
7 Parameter Measurement Information
7.1 TTL and CMOS 3 V ≤ VLOGIC (Hi State) ≤ 7 V
Threshold = 1.4 V
Figure 18. Sample When Logic High With TTL and CMOS Biasing
Threshold = 1.4 V
Select for 2.8 V at pin 8
Figure 19. Sample When Logic Low With TTL and CMOS Biasing
7.2 CMOS 7 V ≤ VLOGIC (Hi State) ≤ 15 V
Threshold = 0.6 (V+) + 1.4 V
Figure 20. Sample When Logic High With CMOS Biasing
10
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
www.ti.com
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
CMOS 7 V ≤ VLOGIC (Hi State) ≤ 15 V (continued)
Threshold = 0.6 (V+) –1.4V
Figure 21. Sample When Logic Low With CMOS Biasing
7.3 Operational Amplifier Drive
Threshold ≈ +4 V
Figure 22. Sample When Logic High With Operational Amplifier Biasing
Threshold = −4 V
Figure 23. Sample When Logic Low With Operational Amplifier Biasing
Copyright © 2000–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
11
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
www.ti.com
8 Detailed Description
8.1 Overview
The LF298 and LFx98x devices are monolithic sample-and-hold circuits that utilize BI-FET technology to obtain
ultrahigh DC accuracy with fast acquisition of signal and low droop rate. Operating as a unity-gain follower, DC
gain accuracy is 0.002% typical and acquisition time is as low as 6 µs to 0.01%. A bipolar input stage is used to
achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin, and does
not degrade input offset drift. The wide bandwidth allows the LF198-N to be included inside the feedback loop of
1-MHz operational amplifier without having stability problems. Input impedance of 1010 Ω allows high-source
impedances to be used without degrading accuracy.
8.2 Functional Block Diagram
8.3 Feature Description
The LF298 and LFx98x OUTPUT tracks the INPUT signal by charging and discharging the hold capacitor. The
OUTPUT can be held at any given time by pulling the LOGIC input low relative to the LOGIC REFERENCE
voltage and resume sampling when LOGIC returns high. Additionally, the OFFSET pin can be used to zero the
offset voltage present at the INPUT.
8.4 Device Functional Modes
The LF298 and LFx98x devices have a sample mode and hold mode controlled by the LOGIC voltage relative to
the LOGIC REFERENCE voltage. The device is in sample mode when the LOGIC input is pulled high relative to
the LOGIC REFERENCE voltage and in hold mode when the LOGIC input is pulled low relative to the LOGIC
REFERENCE. In sample mode, the output is tracking the input signal by charging and discharging the hold
capacitor. Smaller values of hold capacitance will allow the output to track faster signals. In hold mode the input
signal is disconnected from the signal path and the output retains the value on the hold capacitor. Larger values
of capacitance will have a smaller droop rate as shown in Figure 4.
12
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
www.ti.com
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Hold Capacitor
Hold step, acquisition time, and droop rate are the major trade-offs in the selection of a hold capacitor value. Size
and cost may also become important for larger values. Use of the curves included with this data sheet should be
helpful in selecting a reasonable value of capacitance. Keep in mind that for fast repetition rates or tracking fast
signals, the capacitor drive currents may cause a significant temperature rise in the LF198-N.
A significant source of error in an accurate sample and hold circuit is dielectric absorption in the hold capacitor. A
mylar cap, for instance, may sag back up to 0.2% after a quick change in voltage. A long sample time is required
before the circuit can be put back into the hold mode with this type of capacitor. Dielectrics with very low
hysteresis are polystyrene, polypropylene, and Teflon. Other types such as mica and polycarbonate are not
nearly as good. The advantage of polypropylene over polystyrene is that it extends the maximum ambient
temperature from 85°C to 100°C. Most ceramic capacitors are unusable with > 1% hysteresis. Ceramic NPO or
COG capacitors are now available for 125°C operation and also have low dielectric absorption. For more exact
data, see Figure 2. The hysteresis numbers on the curve are final values, taken after full relaxation. The
hysteresis error can be significantly reduced if the output of the LF198-N is digitized quickly after the hold mode
is initiated. The hysteresis relaxation time constant in polypropylene, for instance, is 10 to 50 ms. If A-to-D
conversion can be made within 1 ms, hysteresis error will be reduced by a factor of ten.
9.1.2 DC and AC Zeroing
DC zeroing is accomplished by connecting the offset adjust pin to the wiper of a 1-kΩ potentiometer, which has
one end tied to V+ and the other end tied through a resistor to ground. The resistor should be selected to give
approximately 0.6 mA through the 1-kΩ potentiometer.
AC zeroing (hold step zeroing) can be obtained by adding an inverter with the adjustment pot tied input to output.
A 10-pF capacitor from the wiper to the hold capacitor will give ±4-mV hold step adjustment with a 0.01-µF hold
capacitor and 5-V logic supply. For larger logic swings, a smaller capacitor (< 10 pF) may be used.
9.1.3 Logic Rise Time
For proper operation, logic signals into the LF198-N must have a minimum dV/dt of 1.0 V/µs. Slower signals will
cause excessive hold step. If a R/C network is used in front of the logic input for signal delay, calculate the slope
of the waveform at the threshold point to ensure that it is at least 1.0 V/µs.
9.1.4 Sampling Dynamic Signals
Sample error to moving input signals probably causes more confusion among sample-and-hold users than any
other parameter. The primary reason for this is that many users make the assumption that the sample and hold
amplifier is truly locked on to the input signal while in the sample mode. In actuality, there are finite phase delays
through the circuit creating an input-output differential for fast moving signals. In addition, although the output
may have settled, the hold capacitor has an additional lag due to the 300-Ω series resistor on the chip. This
means that at the moment the hold command arrives, the hold capacitor voltage may be somewhat different than
the actual analog input. The effect of these delays is opposite to the effect created by delays in the logic which
switches the circuit from sample to hold. For example, consider an analog input of 20 Vp–p at 10 kHz. Maximum
dV/dt is 0.6 V/µs. With no analog phase delay and 100-ns logic delay, one could expect up to (0.1 µs) (0.6V/µs)
= 60 mVerror if the hold signal arrived near maximum dV/dt of the input. A positive-going input would give a
Copyright © 2000–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
13
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
www.ti.com
Application Information (continued)
60-mV error. Now assume a 1-MHz (3-dB) bandwidth for the overall analog loop. This generates a phase delay
of 160 ns. If the hold capacitor sees this exact delay, then error due to analog delay will be (0.16 µs) (0.6 V/µs) =
–96 mV. Total output error is 60 mV (digital) –96 mV (analog) for a total of –36 mV. To add to the confusion,
analog delay is proportioned to hold capacitor value while digital delay remains constant. A family of curves
(dynamic sampling error) is included to help estimate errors.
Figure 1 has been included for sampling conditions where the input is steady during the sampling period, but
may experience a sudden change nearly coincident with the hold command. This curve is based on a 1-mV error
fed into the output.
Figure 6 indicates the time required for the output to settle to 1 mV after the hold command.
9.1.5 Digital Feedthrough
Fast rise time logic signals can cause hold errors by feeding externally into the analog input at the same time the
amplifier is put into the hold mode. To minimize this problem, board layout should keep logic lines as far as
possible from the analog input and the Ch pin. Grounded guarding traces may also be used around the input line,
especially if it is driven from a high impedance source. Reducing high amplitude logic signals to 2.5 V will also
help.
Use 10-pin layout. Guard around CH is tied to output.
Figure 24. Guarding Technique
14
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
www.ti.com
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
9.2 Typical Applications
9.2.1 X1000 Sample and Hold
The circuit configuration in Figure 25 shows how to incorporate an amplification factor of 1000 into the sample
and hold stage. This may be particularly useful if the input signal has a very low amplitude. Equation 1 provides
the appropriate value of capacitance for the COMP 2 pin capacitance of the LM108.
*For lower gains, the LM108 must be frequency compensated
Figure 25. X1000 Sample and Hold
Use »
100
pF from comp 2 to ground
AV
(1)
9.2.1.1 Design Requirements
Assume an unbuffered analog to digital converter with 1-Vpp dynamic range is used in a system which needs to
sample an input signal with only 1-mVpp amplitude. Using the LF198-N and LM108 connect the input signal so
that the maximum dynamic range is used by the 1-Vpp data converter.
9.2.1.2 Detailed Design Procedure
Connect the LF198-N and LM108 as shown in Figure 25. To maximize the dynamic range of 1 Vpp a gain factor
of 1000x is needed. Set R3 to 1 MΩ and R4 to 1 kΩ to give a noninverting gain of 1001. The calculated value of
C1 is 0.1 pF according to Equation 1, which is negligibly small and may be left off of the design.
Copyright © 2000–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
15
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
www.ti.com
Typical Applications (continued)
9.2.1.3 Application Curves
The feedthrough rejection ratio of the LF198-N is extremely good and provides good isolation for a wide variety
of hold capacitors as Figure 26 shows. Additionally, the output transient settles almost completely after 0.8 µs
and would be ready to sample as shown in Figure 27.
Figure 26. Feedthrough Rejection Ratio (Hold Mode)
Figure 27. Output Transient at Start of Hold Mode
9.2.2 Sample and Difference Circuit
The LF198-N may be used as a sample and difference circuit as shown in Figure 28 where the output follows the
input in hold mode.
VOUT = VB + ∆VIN (HOLD MODE)
Figure 28. Sample and Difference Circuit
16
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
www.ti.com
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
Typical Applications (continued)
9.2.3 Ramp Generator With Variable Reset Level
The circuit configuration shown in Figure 29 generates a ramp signal with variable reset level. The rise or fall
time may be computed by Equation 2.
Figure 29. Ramp Generator With Variable Reset Level
DV
1.2V
=
DT (R2) (Ch )
(2)
9.2.4 Integrator With Programmable Reset Level
The LF398-N may be used with LM308 to create an integrator circuit with programmable reset level as shown in
Figure 30. The integrated output voltage in hold mode is computed with Equation 3.
Figure 30. Integrator With Programmable Reset Level
é
1
VOUT (Hold Mode) = ê
(R1)
(Ch )
ë
ù
VIN dt ú + éë VR ùû
0
û
ò
t
Copyright © 2000–2015, Texas Instruments Incorporated
(3)
Submit Documentation Feedback
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
17
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
www.ti.com
Typical Applications (continued)
9.2.5 Output Holds at Average of Sampled Input
The LF198-N can be used to identify the average value of the input signal and hold the corresponding voltage on
the output. Connect Rh and Ch as shown in Figure 31. The corresponding values may be calculated with
Equation 4.
Figure 31. Output Holds at Average of Sampled Input
Select (Rh ) (Ch ) ?
1
2pfIN (Min)
(4)
9.2.6 Increased Slew Current
The slew current can be increased by connecting opposing diodes from the OUTPUT to the HOLD CAPACITOR
pins as shown in Figure 32.
Figure 32. Increased Slew Current
18
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
www.ti.com
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
Typical Applications (continued)
9.2.7 Reset Stabilized Amplifier
The LF398-N may be used with LH0042H to create a reset stabilized amplifier with a gain of 1000 as shown in
Figure 33.
VOS ≤ 20 µV (No trim)
ZIN ≈ 1 MΩ
Figure 33. Reset Stabilized Amplifier
DVOS
» 30mV / sec
Dt
DVOS
» 0.1mV/º C
DT
(5)
(6)
Copyright © 2000–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
19
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
www.ti.com
Typical Applications (continued)
9.2.8 Fast Acquisition, Low Droop Sample and Hold
Two LF398-N devices may be used along with LM3905 TIMER to create a fast acquisition, low droop sample
and hold circuit as shown in Figure 34.
Figure 34. Fast Acquisition, Low Droop Sample and Hold
20
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
www.ti.com
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
Typical Applications (continued)
9.2.9 Synchronous Correlator for Recovering Signals Below Noise Level
The LF198-N may be used with two LM122H TIMER devices to create a synchronous correlator for recovering
signals below noise level as shown in Figure 35.
Figure 35. Synchronous Correlator for Recovering Signals Below Noise Level
9.2.10 2-Channel Switch
The HOLD CAPACITOR pin could be alternatively used as a second input to create a 2-channel switch shown
Figure 36
Figure 36. 2-Channel Switch
In the configuration of Figure 36, input signal A and input signal B have the characteristics listed in Table 1.
Copyright © 2000–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
21
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
www.ti.com
Typical Applications (continued)
Table 1. 2-Channel Switch Characteristics
A
B
Gain
1 ± 0.02%
1 ± 0.2%
ZIN
1010 Ω
47 kΩ
BW
≈1 MHz
≈400 kHz
Crosstalk @ 1 kHz
–90 dB
–90 dB
Offset
≤ 6 mV
≤ 75 mV
9.2.11 DC and AC Zeroing
The LF198-N features an OFFSET ADJUST pin which can be connected to a potentiometer to zero the DC
offset. Additionally, an inverter may be connected with an AC-coupled potentiometer to the HOLD CAPACITOR
pin to create a DC- and AC-zeroing circuit as shown in Figure 37.
Figure 37. DC and AC Zeroing
22
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
www.ti.com
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
9.2.12 Staircase Generator
The LF368 can be connected as shown in Figure 38 to create a staircase generator.
*Select for step height: 50 kΩ → 1-V Step.
Figure 38. Staircase Generator
9.2.13 Differential Hold
Two LF198-N devices may be connected as shown in Figure 39 to create a differential hold circuit.
Figure 39. Differential Hold
Copyright © 2000–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
23
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
www.ti.com
9.2.14 Capacitor Hysteresis Compensation
The LF298 and LFx98x devices may be used for capacitor hysteresis compensation as shown in Figure 40.
*Select for time constant C1 = τ/100 kΩ
**Adjust for amplitude
Figure 40. Capacitor Hysteresis Compensation
10 Power Supply Recommendations
The LF298 and LFx98x devices are rated for a typical supply voltage of ±15 V. To achieve noise immunity as
appropriate to the application, it is important to use good printed-circuit-board layout practices for power supply
rails and planes, as well as using bypass capacitors connected between the power supply pins and ground. All
bypass capacitors must be rated to handle the supply voltage and be decoupled to ground. TI recommends to
decouple each supply with two capacitors; a small value ceramic capacitor (approximately 0.1 μF) placed close
to the supply pin in addition to a large value Tantalum or Ceramic (≥ 10 μF). The large capacitor can be shared
by more than one device if necessary. The small ceramic capacitor maintains low supply impedance at higher
frequencies while the large capacitor will act as the charge bucket for fast load current spikes at the op amp
output. The combination of these capacitors will provide supply decoupling and will help maintain stable
operation for most loading conditions.
24
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
www.ti.com
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
11 Layout
11.1 Layout Guidelines
Take care to minimize the loop area formed by the bypass capacitor connection between supply pins and
ground. A ground plane underneath the device is recommended; any bypass components to ground should have
a nearby via to the ground plane. The optimum bypass capacitor placement is closest to the corresponding
supply pin. Use of thicker traces from the bypass capacitors to the corresponding supply pins will lower the
power supply inductance and provide a more stable power supply. The feedback components should be placed
as close to the device as possible to minimize stray parasitics.
11.2 Layout Example
Figure 41 shows an example schematic and layout for the LFx98x 8-pin PDIP package.
U1
1
INPUT
2
3
V±
C1
10 µF
C2
0.1 µF
4
5
6
7
OUTPUT
LFx98M
INPUT
NC
VV±
OFFSET
ADJUST
NC
V+
NC
LOGIC
NC
LOGIC
REFERENCE
NC
NC
OUTPUT
CH
14
OFF ADJ
13
12
V+
C3
0.1 µF
11
C4
10 µF
LOGIC
10
LOG REF
9
8
Ch
CH
Figure 41. Schematic Example
Figure 42. Layout Example
Copyright © 2000–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
25
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
• Hold Step: The voltage step at the output of the sample and hold when switching from sample mode to hold
mode with a steady (DC) analog input voltage. Logic swing is 5 V.
• Acquisition Time: The time required to acquire a new analog input voltage with an output step of 10 V.
Acquisition time is not just the time required for the output to settle, but also includes the time required for all
internal nodes to settle so that the output assumes the proper value when switched to the hold mode.
• Gain Error: The ratio of output voltage swing to input voltage swing in the sample mode expressed as a per
cent difference.
• Hold Settling Time: The time required for the output to settle within 1 mV of final value after the hold logic
command.
• Dynamic Sampling Error: The error introduced into the held output due to a changing analog input at the
time the hold command is given. Error is expressed in mV with a given hold capacitor value and input slew
rate. This error term occurs even for long sample times.
• Aperture Time: The delay required between hold command and an input analog transition, so that the
transition does not affect the held output.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LF198-N
Click here
Click here
Click here
Click here
Click here
LF298
Click here
Click here
Click here
Click here
Click here
LF398-N
Click here
Click here
Click here
Click here
Click here
LF198A-N
Click here
Click here
Click here
Click here
Click here
LF398A-N
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
26
Submit Documentation Feedback
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
LF198-N, LF298, LF398-N
LF198A-N, LF398A-N
www.ti.com
SNOSBI3B – JULY 2000 – REVISED NOVEMBER 2015
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2000–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: LF198-N LF298 LF398-N LF198A-N LF398A-N
27
PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LF198AH
ACTIVE
TO-99
LMC
8
500
TBD
Call TI
Call TI
-55 to 125
( LF198AH ~
LF198AH)
LF198AH/NOPB
ACTIVE
TO-99
LMC
8
500
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
-55 to 125
( LF198AH ~
LF198AH)
LF198H
ACTIVE
TO-99
LMC
8
500
TBD
Call TI
Call TI
-55 to 125
( LF198H ~ LF198H)
LF198H/NOPB
ACTIVE
TO-99
LMC
8
500
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
-55 to 125
( LF198H ~ LF198H)
LF298H
ACTIVE
TO-99
LMC
8
500
TBD
Call TI
Call TI
-25 to 85
( LF298H ~ LF298H)
LF298H/NOPB
ACTIVE
TO-99
LMC
8
500
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
-25 to 85
( LF298H ~ LF298H)
LF298M
NRND
SOIC
D
14
55
TBD
Call TI
Call TI
-25 to 85
LF298M
LF298M/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-25 to 85
LF298M
LF298MX
NRND
SOIC
D
14
2500
TBD
Call TI
Call TI
-25 to 85
LF298M
LF298MX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-25 to 85
LF298M
LF398AN/NOPB
ACTIVE
PDIP
P
8
40
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
0 to 70
LF
398AN
LF398H
ACTIVE
TO-99
LMC
8
500
TBD
Call TI
Call TI
0 to 70
LF398H
LF398H/NOPB
ACTIVE
TO-99
LMC
8
500
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
0 to 70
( LF398H ~ LF398H)
LF398M
NRND
SOIC
D
14
55
TBD
Call TI
Call TI
0 to 70
LF398M
LF398M/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LF398M
LF398MX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LF398M
LF398N/NOPB
ACTIVE
PDIP
P
8
40
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
0 to 70
LF
398N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2016
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated