NXP ISP1507ABS Ulpi hi-speed universal serial bus on-the-go transceiver Datasheet

ISP1507A; ISP1507B
ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver
Rev. 01 — 19 May 2008
Product data sheet
1. General description
The ISP1507 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully
compliant with Universal Serial Bus Specification Rev. 2.0, On-The-Go Supplement to the
USB 2.0 Specification Rev. 1.3 and UTMI+ Low Pin Interface (ULPI) Specification
Rev. 1.1.
The ISP1507 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer
front-end attachment to USB host, peripheral and OTG devices.
It is ideal for use in portable electronic devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) and any system chip set to interface with the physical layer of the
USB through a 12-pin interface.
The ISP1507 can interface to the link with digital I/O voltages in the range of 1.65 V to
3.6 V.
The ISP1507 is available in HVQFN32 package.
2. Features
n Fully complies with:
u Universal Serial Bus Specification Rev. 2.0
u On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3
u UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
n Interfaces to host, peripheral and OTG device cores; optimized for portable devices or
system ASICs with built-in USB OTG device core
n Complete Hi-Speed USB physical front-end solution that supports high-speed
(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
u Integrated 45 Ω ± 10 % high-speed termination resistors, 1.5 kΩ ± 5 % full-speed
device pull-up resistor, and 15 kΩ ± 5 % host termination resistors
u Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
u USB clock and data recovery to receive USB data up to ±500 ppm
u Insertion of stuff bits during transmit and discarding of stuff bits during receive
u Non-Return-to-Zero Inverted (NRZI) encoding and decoding
u Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
n Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP)
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
n
n
n
n
n
u Integrated 5 V charge pump; also supports external charge pump or 5 V VBUS
switch
u Complete control over bus resistors
u Data line and VBUS pulsing session request methods
u Integrated VBUS voltage comparators
u Integrated cable (ID) detector
Highly optimized ULPI-compliant
u 60 MHz, 8-bit interface between the core and the transceiver
u Supports 60 MHz output clock configuration
u Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency:
19.2 MHz (ISP1507ABS) and 26 MHz (ISP1507BBS)
u Fully programmable ULPI-compliant register set
u Internal Power-On Reset (POR) circuit
Flexible system integration and very low current consumption, optimized for portable
devices
u Power-supply input range is 3.0 V to 3.6 V
u Internal voltage regulator supplies 3.3 V and 1.8 V
u Charge pump regulator outputs 4.75 V to 5.25 V at a current of up to 50 mA,
tunable using an external capacitor
u Supports external VBUS charge pump or 5 V VBUS switch:
External VBUS source is controlled using the PSW_N pin; open-drain PSW_N
allows per-port or ganged power control
Digital FAULT input to monitor the external VBUS supply status
u Pin CHIP_SELECT_N 3-states the ULPI interface, allowing bus reuse for other
applications
u Supports wide range interfacing I/O voltage of 1.65 V to 3.6 V; separate I/O voltage
pins minimize crosstalk
u Typical operating current of 10 mA to 48 mA, depending on the USB speed and
bus utilization; not including the charge pump
u Typical suspend current of 35 µA
Full industrial grade operating temperature range from −40 °C to +85 °C
4 kV ElectroStatic Discharge (ESD) protection at pins DP, DM, ID, VBUS and GND
Available in a small HVQFN32 (5 mm × 5 mm) Restriction of Hazardous Substances
(RoHS) compliant, halogen-free and lead-free package
3. Applications
n
n
n
n
Digital still camera
Digital TV
Digital Video Disc (DVD) recorder
External storage device, for example:
u Magneto-Optical (MO) drive
u Optical drive: CD-ROM, CD-RW, DVD
u Zip drive
n Mobile phone
n MP3 player
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
2 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
n
n
n
n
n
PDA
Printer
Scanner
Set-Top Box (STB)
Video camera
4. Ordering information
Table 1.
Ordering information
Part
Package
Type number
Marking
Crystal or Name
clock
frequency
Description
Version
ISP1507ABS
507A[1]
19.2 MHz
HVQFN32
plastic thermal enhanced very thin quad flat package;
no leads; 32 terminals; body 5 × 5 × 0.85 mm
SOT617-1
ISP1507BBS
507B[1]
26 MHz
HVQFN32
plastic thermal enhanced very thin quad flat package;
no leads; 32 terminals; body 5 × 5 × 0.85 mm
SOT617-1
[1]
The package marking is the first line of text on the IC package and can be used for IC identification.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
3 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
5. Block diagram
27
CLOCK
ULPI
INTERFACE
DATA
[7:0]
5
USB DATA
SERIALIZER
8
DIR
STP
NXT
CHIP_SELECT_N
RESET_N
1, 23 to 26,
28, 31, 32
ULPI
INTERFACE
CONTROLLER
19
DRV VBUS
21
VBUS VALID
EXTERNAL
REGISTER
MAP
29
VCC(I/O)
TERMINATION
RESISTORS
REG1V8
VCC
DM
USB
CABLE
ON-THE-GO MODULE
DRV VBUS
EXTERNAL
ID
DETECTOR
7
ID
VBUS
COMPARATORS
13
GLOBAL
RESET
PLL
15
16
5 V CHARGE
PUMP SUPPLY
CRYSTAL
OSCILLATOR
10
C_A
9
C_B
8
CPGND
ISP1507
2, 22, 30 interface voltage
6
14
12
18
11
VBUS
SRP CHARGE
AND DISCHARGE
RESISTORS
internal power
REG3V3
4
17
GLOBAL
CLOCKS
XTAL2
USB DATA
DESERIALIZER
20
POWER-ON
RESET
XTAL1
DP
HI-SPEED USB ATX
VOLTAGE
REGULATOR
VREF
BAND GAP
REFERENCE
VOLTAGE
3
FAULT
PSW_N
RREF
004aab035
Fig 1.
Block diagram
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
4 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
6. Pinning information
25 DATA5
26 DATA4
27 CLOCK
28 DATA3
29 CHIP_SELECT_N
30 VCC(I/O)
terminal 1
index area
31 DATA2
32 DATA1
6.1 Pinning
DATA0
1
24 DATA6
VCC(I/O)
2
23 DATA7
RREF
3
22 VCC(I/O)
DM
4
DP
5
FAULT
6
19 DIR
ID
7
18 REG1V8
CPGND
8
17 RESET_N
21 NXT
XTAL2 16
XTAL1 15
20 STP
REG3V3 14
VBUS 13
PSW_N 12
VCC 11
9
C_B
C_A 10
ISP1507
004aab036
Transparent top view
Fig 2.
Pin configuration HVQFN32; top view
6.2 Pin description
Table 2.
Pin description
Symbol[1][2]
Pin
Type[3]
Description[4]
DATA0
1
I/O
pin 0 of the bidirectional ULPI data bus
VCC(I/O)
2
P
I/O supply rail
RREF
3
AI/O
resistor reference
DM
4
AI/O
data minus (D−) pin of the USB cable
DP
5
AI/O
data plus (D+) pin of the USB cable
FAULT
6
I
input pin for the external VBUS digital overcurrent or fault detector signal
slew-rate controlled output (1 ns); plain input; programmable pull down
plain input; 5 V tolerant
ID
7
I
identification (ID) pin of the micro-USB cable
If this pin is not used, it is recommended to connect to REG3V3.
plain input; TTL level
CPGND
8
P
charge pump ground
C_B
9
AI/O
flying capacitor pin connection for the charge pump
C_A
10
AI/O
flying capacitor pin connection for the charge pump
VCC
11
P
input supply voltage or battery source
PSW_N
12
OD
active LOW external VBUS power switch or external charge pump enable
open-drain; 5 V tolerant
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
5 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 2.
Pin description …continued
Symbol[1][2]
Pin
Type[3]
Description[4]
VBUS
13
AI/O
VBUS pin of the USB cable
5 V tolerant
REG3V3
14
P
3.3 V regulator output
XTAL1
15
AI
crystal oscillator or clock input
XTAL2
16
AO
crystal oscillator output
RESET_N
17
I
active LOW, asynchronous reset input
plain input
REG1V8
18
P
1.8 V regulator output
DIR
19
O
ULPI direction signal
slew-rate controlled output (1 ns)
STP
20
I
NXT
21
O
ULPI stop signal
plain input; programmable pull up
ULPI next signal
slew-rate controlled output (1 ns)
VCC(I/O)
22
P
I/O supply rail
DATA7
23
I/O
pin 7 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); plain input; programmable pull down
DATA6
24
I/O
pin 6 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); plain input; programmable pull down
DATA5
25
I/O
pin 5 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); plain input; programmable pull down
DATA4
26
I/O
CLOCK
27
O
pin 4 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); plain input; programmable pull down
60 MHz clock output
slew-rate controlled output (1 ns); plain input
DATA3
28
I/O
pin 3 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); plain input; programmable pull down
CHIP_SELECT_ 29
N
I
active LOW chip select
plain input
VCC(I/O)
30
P
I/O supply rail
DATA2
31
I/O
pin 2 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); plain input; programmable pull down
DATA1
32
I/O
GND
die
pad
P
pin 1 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); plain input; programmable pull down
[1]
ground supply; down bonded to the exposed die pad (heat sink); to be connected to
the PCB ground
Symbol names ending with underscore N, for example, NAME_N, indicate active LOW signals.
[2]
For details on external components required on each pin, see bill of materials and application diagrams in Section 16.
[3]
I = input; O = output; I/O = digital input/output; OD = open-drain output; AI = analog input; AO = analog output; AI/O = analog
input/output; P = power or ground pin.
[4]
A detailed description of these pins can be found in Section 7.9.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
6 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
7. Functional description
7.1 ULPI interface controller
The ISP1507 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface
(ULPI) Specification Rev. 1.1. This interface must be connected to the USB link.
The ULPI interface controller provides the following functions:
•
•
•
•
•
•
•
•
•
•
•
ULPI-compliant and register set
Allows full control over the USB peripheral, host and OTG functionality
Parses USB transmit and receive data
Prioritizes USB receive data, USB transmit data, interrupts and register operations
Low-power mode
Control of the VBUS charge pump or external source
VBUS monitoring, charging and discharging
6-pin serial mode and 3-pin serial mode
Generates RXCMDs; status updates
Maskable interrupts
Control over the ULPI bus state, allowing pins to 3-state or attach active weak
pull-down resistors
For more information on the ULPI protocol, see Section 9.
7.2 USB data serializer and deserializer
The USB data serializer prepares data to transmit on the USB bus. To transmit data, the
USB link sends a transmit command and data on the ULPI bus. The serializer performs
parallel-to-serial conversion, bit stuffing and NRZI encoding. For packets with a PID, the
serializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the end
of the packet. When the serializer is busy and cannot accept any more data, the ULPI
interface controller deasserts NXT.
The USB data deserializer decodes data received from the USB bus. When data is
received, the deserializer strips the SYNC and EOP patterns, and then performs
serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data
payload. The ULPI interface controller sends data to the USB link by asserting DIR, and
then asserting NXT whenever a byte is ready. The deserializer also detects various
receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and
byte-alignment errors.
7.3 Hi-Speed USB (USB 2.0) ATX
The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to
transmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, for
USB peripheral, host and OTG implementations. The following circuitry is included:
• Differential drivers to transmit data at high-speed, full-speed and low-speed
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
7 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
• Differential and single-ended receivers to receive data at high-speed, full-speed and
low-speed
•
•
•
•
•
Squelch circuit to detect high-speed bus activity
High-speed disconnect detector
45 Ω high-speed bus terminations on DP and DM for peripheral and host modes
1.5 kΩ pull-up resistor on DP for full-speed peripheral mode
15 kΩ bus terminations on DP and DM for host and OTG modes
For details on controlling resistor settings, see Table 8.
7.4 Voltage regulator
The ISP1507 contains a built-in voltage regulator that conditions the VCC supply for use
inside the ISP1507. The voltage regulator:
• Supports input supply range of 3.0 V < VCC < 3.6 V
• Supplies internal circuitry with 1.8 V and 3.3 V
Remark: The REG1V8 and REG3V3 pins require external decoupling capacitors. For
details, see Section 16.
7.5 Crystal oscillator and PLL
The ISP1507 has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock
generation.
The crystal oscillator takes a sine-wave input from an external crystal on the XTAL1 pin,
and converts it to a square wave clock for internal use. Alternatively, a square wave clock
of the same frequency can also be directly driven into the XTAL1 pin. Using an existing
square wave clock can save the cost of a crystal and also reduce the board size.
The PLL takes the square wave clock from the crystal oscillator and multiplies or divides it
into various frequencies for internal use.
The PLL produces the following frequencies, irrespective of the clock source:
•
•
•
•
•
60 MHz clock for the ULPI interface controller
1.5 MHz for the low-speed USB data
12 MHz for the full-speed USB data
480 MHz for the high-speed USB data
Other internal frequencies for data conversion and data recovery
7.6 OTG module
This module contains several sub-blocks that provide all the functionality required by the
USB OTG specification. Specifically, it provides the following circuits:
• The ID detector to sense the ID pin of the micro-USB cable. The ID pin dictates which
device is initially configured as the host and which as the peripheral.
• VBUS comparators to determine the VBUS voltage level. This is required for the VBUS
detection, SRP and HNP.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
8 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
• Resistors to temporarily charge and discharge VBUS. This is required for SRP.
• Charge pump to provide 5 V power on VBUS. The downstream peripheral can draw its
power from the ISP1507 VBUS.
7.6.1 ID detector
The ID detector detects which end of the micro-USB cable is plugged in. The detector
must first be enabled by setting the ID_PULLUP register bit to logic 1. If the ISP1507
senses a value on ID that is different from the previously reported value, an RXCMD
status update will be sent to the USB link, or an interrupt will be asserted.
• If the micro-B end of the cable is plugged in, the ISP1507 will report that ID_GND is
logic 1. The USB link must change to peripheral mode.
• If the micro-A end of the cable is plugged in, the ISP1507 will report that ID_GND is
logic 0. The USB link must change to host mode.
7.6.2 VBUS comparators
The ISP1507 provides three comparators, VBUS valid comparator, session valid
comparator and session end comparator, to detect the VBUS voltage level.
7.6.2.1
VBUS valid comparator
This comparator is used by hosts and A-devices to determine whether the voltage on
VBUS is at a valid level for operation. The ISP1507 minimum threshold for the VBUS valid
comparator is VA_VBUS_VLD. Any voltage on VBUS below VA_VBUS_VLD is considered a fault.
During power-up, it is expected that the comparator output will be ignored.
7.6.2.2
Session valid comparator
The session valid comparator is a TTL-level input that determines when VBUS is high
enough for a session to start. Peripherals, A-devices and B-devices use this comparator to
detect when a session is started. The A-device also uses this comparator to determine
when a session is completed. The session valid threshold of the ISP1507 is VB_SESS_VLD,
with a hysteresis of Vhys(B_SESS_VLD).
7.6.2.3
Session end comparator
The ISP1507 session end comparator determines when VBUS is below the B-device
session end threshold. The B-device uses this threshold to determine when a session has
ended. The session end threshold of the ISP1507 is VB_SESS_END.
7.6.3 SRP charge and discharge resistors
The ISP1507 provides on-chip resistors for short-term charging and discharging of VBUS.
These are used by the B-device to request a session, prompting the A-device to restore
the VBUS power. First, the B-device makes sure that VBUS is fully discharged from the
previous session by setting the DISCHRG_VBUS register bit to logic 1 and waiting for
SESS_END to be logic 1. Then the B-device charges VBUS by setting the CHRG_VBUS
register bit to logic 1. The A-device sees that VBUS is charged above the session valid
threshold and starts a session by turning on the VBUS power.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
9 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
7.6.4 Charge pump
The ISP1507 uses a built-in charge pump to supply current to VBUS at a nominal voltage
of 5 V. The charge pump works as a capacitive DC-DC converter. An external holding
capacitor, Ccp(C_A)-(C_B), is required between the C_A and C_B pins as shown in Figure 3,
which also shows a typical OTG VBUS load. The value of Ccp(C_A)-(C_B) depends on the
amount of current drive required. If the internal charge pump is not used, the Ccp(C_A)-(C_B)
capacitor is not required.
For details on the C_A and C_B pins, see Section 7.9.8.
VBUS
OTG VBUS
0.1 µF
4.7 µF
ISP1507
C_B
Ccp(C_A)-(C_B)
C_A
004aab037
Fig 3.
External capacitors connection
7.7 Band gap reference voltage
The band gap circuit provides a stable internal voltage reference to bias the analog
circuitry. The band gap requires an accurate external reference, RRREF, resistor
connected between the RREF pin and GND. For details, see Section 16.
7.8 Power-On Reset (POR)
The ISP1507 has an internal power-on reset circuit that resets all internal logic on
power-up. The ULPI interface is also reset on power-up.
Remark: When CLOCK starts toggling after power-up, the USB link must issue a reset
command over the ULPI bus to ensure correct operation of the ISP1507.
7.9 Detailed description of pins
7.9.1 DATA[7:0]
The ISP1507 is a Physical layer (PHY) containing a USB transceiver. DATA[7:0] is the
bidirectional data bus. The USB link must drive DATA[7:0] to LOW when the ULPI bus is
idle. When the link has data to transmit to the PHY, it drives a nonzero value.
The data bus can be reconfigured to carry various data types, as given in Section 8 and
Section 9.
The DATA[7:0] pins can be 3-stated by driving pin CHIP_SELECT_N to HIGH. Weak
pull-down resistors are incorporated into the DATA[7:0] pins as part of the interface protect
feature. For details, see Section 9.3.1.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
10 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
7.9.2 VCC(I/O)
The input power pin that sets the I/O voltage level. For details, see Section 12, Section 13
and Section 16. VCC(I/O) provides power to on-chip pads of the following pins:
•
•
•
•
•
•
•
CHIP_SELECT_N
CLOCK
DATA[7:0]
DIR
NXT
RESET_N
STP
7.9.3 RREF
Resistor reference analog I/O pin. A resistor, RRREF, must be connected between RREF
and GND, as shown in Section 16. This provides an accurate voltage reference that
biases internal analog circuitry. Less accurate resistors cannot be used and will render the
ISP1507 unusable.
7.9.4 DP and DM
The DP (data plus) and DM (data minus) are USB differential data pins. These must be
connected to the D+ and D− pins of the USB receptacle.
7.9.5 FAULT
If an external VBUS overcurrent or fault circuit is used, the output fault indicator of that
circuit can be connected to the ISP1507 FAULT input pin. The ISP1507 will inform the link
of VBUS fault events by sending RXCMDs on the ULPI bus. To use the FAULT pin, the link
must:
• Set the USE_EXT_VBUS_IND register bit to logic 1.
• Set the polarity of the external fault signal using the IND_COMPL register bit.
• Set the IND_PASSTHRU register bit to logic 1.
If the FAULT pin is not used, it is recommended to connect to GND.
7.9.6 ID
For OTG implementations, the ID (identification) pin is connected to the ID pin of the
micro-USB receptacle. As defined in On-The-Go Supplement to the USB 2.0 Specification
Rev. 1.3, the ID pin dictates the initial role of the link. If ID is detected as HIGH, the link
must assume the role of a peripheral. If ID is detected as LOW, the link must assume a
host role. Roles can be swapped at a later time by using HNP.
If the ISP1507 is not used as an OTG PHY, but as a standard USB host or peripheral PHY,
the ID pin must be connected to REG3V3.
7.9.7 CPGND
CPGND indicates the analog ground for the on-board charge pump. CPGND must always
be connected to ground, even when the charge pump is not used.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
11 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
7.9.8 C_A and C_B
The C_A and C_B pins are to connect the flying capacitor of the charge pump. The output
current capability of the charge pump depends on the value of the capacitor used, as
shown in Table 3. For maximum efficiency, place capacitors as close as possible to pins.
For details, see Section 16.
If the charge pump is not used, C_A and C_B must be left floating (not connected).
C_A
Ccp(C_A)-(C_B)
C_B
ISP1507
VBUS
IL
004aab038
Fig 4.
Table 3.
Charge pump capacitor
Recommended charge pump capacitor value
Ccp(C_A)-(C_B)
IL (max)
22 nF
8 mA
270 nF
50 mA
7.9.9 VCC
VCC is the main input supply voltage for the ISP1507. Decoupling capacitors are
recommended. For details, see Section 16.
7.9.10 PSW_N
PSW_N is an active LOW, open-drain output pin. This pin can be connected to an active
LOW, external VBUS switch or charge pump enable circuit to control the external VBUS
power source. An external pull-up resistor, Rpullup, is required when PSW_N is used. This
pin is open-drain, allowing ganged-mode power control for multiple USB ports. For
application details, see Section 16.
If the link is in host mode, it can enable the external VBUS power source by setting the
DRV_VBUS_EXT bit in the OTG_CTRL register (see Section 10.1.4) to logic 1. The
ISP1507 will drive PSW_N to LOW to enable the external VBUS power source. If the link
detects an overcurrent condition (the VBUS state in RXCMD is not 11b), it must disable the
external VBUS power source by setting DRV_VBUS_EXT to logic 0.
7.9.11 VBUS
This pin acts as an input to VBUS comparators, and also as a power pin for the charge
pump, and SRP charge and discharge resistors.
When the DRV_VBUS bit in the OTG_CTRL register (see Section 10.1.4) is set to logic 1,
the ISP1507 drives VBUS to a voltage of 4.4 V to 5.25 V, with a minimum output current
capability of 8 mA.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
12 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
The VBUS pin requires a capacitive load as shown in Section 16.
To prevent electrical overstress, it is strongly recommended that you attach a series
resistor on the VBUS pin (RVBUS). RVBUS must not be attached when using the ISP1507
internal charge pump. For details, see Section 16.
7.9.12 REG3V3 and REG1V8
Regulator output voltage. These supplies are used to power the ISP1507 internal digital
and analog circuits, and must not be used to power external circuits.
For correct operation of the regulator, it is recommended that you connect REG3V3 and
REG1V8 to decoupling capacitors. For examples, see Section 16.
7.9.13 XTAL1 and XTAL2
XTAL1 is the crystal input, and XTAL2 is the crystal output. The allowed frequency on the
XTAL1 pin depends on the ISP1507 product version.
If the link requires a 60 MHz clock from the ISP1507, then either a crystal must be
attached, or a clock of the same frequency must be driven into XTAL1, with XTAL2 left
floating.
If a crystal is attached, it requires external load capacitors to GND on each terminal of the
crystal. For details, see Section 16.
If at any time the system wants to stop the clock on XTAL1, the link must first put the
ISP1507 into low-power mode. The clock on XTAL1 must be restarted before low-power
mode is exited.
7.9.14 RESET_N
An active LOW asynchronous reset pin that resets all circuits in the ISP1507. The
ISP1507 contains an internal power-on reset circuit, and therefore using the RESET_N
pin is optional. If RESET_N is not used, it must be connected to VCC(I/O).
For details on using RESET_N, see Section 9.3.2.
7.9.15 DIR
ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1507
holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the ISP1507
listens for data from the link. The ISP1507 pulls DIR to HIGH only when it has data to
send to the link, which is for one of two reasons:
• To send USB receive data, RXCMD status updates and register read data to the link.
• To block the link from driving the data bus during power-up, reset and low-power
(suspend) mode.
The DIR pin can also be 3-stated by driving CHIP_SELECT_N to HIGH.
For details on DIR usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
13 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
7.9.16 STP
ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet
or a register write operation. When DIR is asserted, the link can optionally assert STP to
abort the ISP1507, causing it to deassert DIR in the next clock cycle. A weak pull-up
resistor is incorporated into the STP pin as part of the interface protect feature. For details,
see Section 9.3.1.
The STP input will be ignored when CHIP_SELECT_N is driven to HIGH.
For details on STP usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
7.9.17 NXT
ULPI next data output pin. The ISP1507 holds NXT at LOW, by default. When DIR is LOW
and the link is sending data to the ISP1507, NXT will be asserted to notify the link to
provide the next data byte. When DIR is at HIGH and the ISP1507 is sending data to the
link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is not
used for register read data or the RXCMD status update.
The NXT pin can also be 3-stated by driving CHIP_SELECT_N to HIGH.
For details on NXT usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
7.9.18 CLOCK
A 60 MHz interface clock to synchronize the ULPI bus. The ISP1507 provides two
clocking options:
• A crystal attached between the XTAL1 and XTAL2 pins.
• A clock driven into the XTAL1 pin, with the XTAL2 pin left floating.
For details on CLOCK usage, refer to UTMI+ Low Pin Interface (ULPI) Specification
Rev. 1.1.
7.9.19 CHIP_SELECT_N
Active LOW chip select pin. If CHIP_SELECT_N is not used, it must be connected to
GND. For more information on using CHIP_SELECT_N, see Section 9.3.3.
7.9.20 GND (die pad)
Global ground signal, except for the charge pump that uses CPGND. The die pad is
exposed on the underside of the package as a ground plate. This acts as a ground to all
circuits in the ISP1507, except the charge pump. To ensure correct operation of the
ISP1507, GND must be soldered to the cleanest ground available.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
14 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
8. Modes of operation
8.1 ULPI modes
The ISP1507 ULPI bus can be programmed to operate in four modes. Each mode
reconfigures the signals on the data bus as described in the following subsections. Setting
more than one mode will lead to undefined behavior.
8.1.1 Synchronous mode
This is default mode. At power-up, and when CLOCK is stable, the ISP1507 will enter
synchronous mode. The link must synchronize all ULPI signals to CLOCK, meeting the
set-up time and the hold time as defined in Section 15. A description of the ULPI pin
behavior in synchronous mode is given in Table 4.
This mode is used by the link to perform the following tasks:
•
•
•
•
High-speed detection handshake (chirp)
Transmit and receive USB packets
Read and write to registers
Receive USB status updates (RXCMDs)
For more information on various synchronous mode protocols, see Section 9.
Table 4.
ULPI signal description
Signal
name
Direction
on ISP1507
Signal description
CLOCK
O
60 MHz interface clock. If a crystal is attached or a clock is driven into
the XTAL1 pin, the ISP1507 will drive a 60 MHz output clock.
DATA[7:0] I/O
8-bit data bus. In synchronous mode, the link drives DATA[7:0] to LOW
by default. The link initiates transfers by sending a nonzero data pattern
called TXCMD (transmit command). In synchronous mode, the direction
of DATA[7:0] is controlled by DIR. Contents of DATA[7:0] lines must be
ignored for exactly one clock cycle whenever DIR changes value. This is
called the turnaround cycle.
Data lines have fixed direction and different meaning in low-power and
serial modes.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
15 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 4.
ULPI signal description …continued
Signal
name
Direction
on ISP1507
Signal description
DIR
O
Direction: Controls the direction of data bus DATA[7:0]. In synchronous
mode, the ISP1507 drives DIR to LOW by default, making the data bus
an input so that the ISP1507 can listen for TXCMDs from the link. The
ISP1507 drives DIR to HIGH only when it has data for the link. When
DIR and NXT are HIGH, the byte on the data bus contains decoded
USB data. When DIR is HIGH and NXT is LOW, the byte contains status
information called RXCMD (receive command). The only exception to
this rule is when the PHY returns register read data, where NXT is also
LOW, replacing the usual RXCMD byte. Every change in DIR causes a
turnaround cycle on the data bus, during which DATA[7:0] is not valid
and must be ignored by the link.
DIR is always asserted during low-power and serial modes.
STP
I
Stop: In synchronous mode, the link drives STP to HIGH for one cycle
after the last byte of data is sent to the ISP1507. The link can optionally
assert STP to force DIR to be deasserted.
In low-power and serial modes, the link holds STP at HIGH to wake up
the ISP1507, causing the ULPI bus to return to synchronous mode.
NXT
O
Next: In synchronous mode, the ISP1507 drives NXT to HIGH to throttle
data. If DIR is LOW, the ISP1507 asserts NXT to notify the link to place
the next data byte on DATA[7:0] in the following clock cycle. If DIR is
HIGH, the ISP1507 asserts NXT to notify the link that a valid USB data
byte is on DATA[7:0] in the current cycle. The ISP1507 always drives an
RXCMD when DIR is HIGH and NXT is LOW, unless register read data
is to be returned to the link in the current cycle.
NXT is not used in low-power or serial mode.
8.1.2 Low-power mode
When the USB is idle, the link can place the ISP1507 into low-power mode (also called
suspend mode). In low-power mode, the data bus definition changes to that shown in
Table 5. To enter low-power mode, the link sets the SUSPENDM bit in the FUNC_CTRL
register (see Section 10.1.2) to logic 0. To exit low-power mode, the link asserts the STP
signal. The ISP1507 will draw only suspend current from the VCC supply (see Table 46).
During low-power mode, the clock on XTAL1 may be stopped. The clock must be started
again before asserting STP to exit low-power mode. After exiting low-power mode, the
ISP1507 will send an RXCMD to the link if a change was detected in any interrupt source,
and the change still exists. An RXCMD may not be sent if the interrupt condition is
removed before exiting.
For more information on low-power mode enter and exit protocols, refer to UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1.
Table 5.
Signal mapping during low-power mode
Signal
Maps to
Direction
Description
LINESTATE0
DATA0
O
combinatorial LINESTATE0 directly driven by analog receiver
LINESTATE1
DATA1
O
combinatorial LINESTATE1 directly driven by analog receiver
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
16 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 5.
Signal mapping during low-power mode …continued
Signal
Maps to
Direction
Description
Reserved
DATA2
O
reserved; the ISP1507 will drive this pin to LOW
INT
DATA3
O
active HIGH interrupt indication; will be asserted whenever any unmasked
interrupt occurs
Reserved
DATA[7:4]
O
reserved; the ISP1507 will drive these pins to LOW
8.1.3 6-pin full-speed or low-speed serial mode
If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed
USB data, it can set the ISP1507 to 6-pin serial mode. In 6-pin serial mode, the DATA[7:0]
bus definition changes to that shown in Table 6. To enter 6-pin serial mode, the link sets
the 6PIN_FSLS_SERIAL bit in the INTF_CTRL register (see Section 10.1.3) to logic 1. To
exit 6-pin serial mode, the link asserts STP. This is provided primarily for links that contain
legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path
to high-speed. An interrupt pin is also provided to inform the link of USB events. If the link
requires CLOCK to be running during 6-pin serial mode, the CLOCK_SUSPENDM
register bit must be set to logic 1.
For more information on 6-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1.
Table 6.
Signal mapping for 6-pin serial mode
Signal
Maps to
Direction
Description
TX_ENABLE
DATA0
I
active HIGH transmit enable
TX_DAT
DATA1
I
transmit differential data on DP and DM
TX_SE0
DATA2
I
transmit single-ended zero on DP and DM
INT
DATA3
O
active HIGH interrupt indication; will be asserted whenever any
unmasked interrupt occurs
RX_DP
DATA4
O
single-ended receive data from DP
RX_DM
DATA5
O
single-ended receive data from DM
RX_RCV
DATA6
O
differential receive data from DP and DM
Reserved
DATA7
O
reserved; the ISP1507 will drive this pin to LOW
8.1.4 3-pin full-speed or low-speed serial mode
If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed
USB data, it can set the ISP1507 to 3-pin serial mode. In 3-pin serial mode, the data bus
definition changes to that shown in Table 7. To enter 3-pin serial mode, the link sets the
3PIN_FSLS_SERIAL bit in the INTF_CTRL register (see Section 10.1.3) to logic 1. To exit
3-pin serial mode, the link asserts STP. This is primarily provided for links that contain
legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path
to high-speed. An interrupt pin is also provided to inform the link of USB events. If the link
requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM
register bit must be set to logic 1.
For more information on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
17 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 7.
Signal mapping for 3-pin serial mode
Signal
Maps to
Direction
Description
TX_ENABLE
DATA0
I
active HIGH transmit enable
DAT
DATA1
I/O
transmit differential data on DP and DM when TX_ENABLE is HIGH
receive differential data from DP and DM when TX_ENABLE is LOW
SE0
DATA2
I/O
transmit single-ended zero on DP and DM when TX_ENABLE is HIGH
receive single-ended zero from DP and DM when TX_ENABLE is LOW
INT
DATA3
O
active HIGH interrupt indication; will be asserted whenever any
unmasked interrupt occurs
Reserved
DATA[7:4]
O
reserved; the ISP1507 will drive these pins to LOW
8.2 USB and OTG state transitions
A Hi-Speed USB peripheral, host or OTG device handles more than one electrical state as
defined in Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the
USB 2.0 Specification Rev. 1.3. The ISP1507 accommodates various states through
register bit settings of XCVRSELECT[1:0], TERMSELECT, OPMODE[1:0],
DP_PULLDOWN and DM_PULLDOWN.
Table 8 summarizes operating states. The values of register settings in Table 8 will force
resistor settings as also given in Table 8. Resistor setting signals are defined as follows:
•
•
•
•
RPU_DP_EN enables the 1.5 kΩ pull-up resistor on DP
RPD_DP_EN enables the 15 kΩ pull-down resistor on DP
RPD_DM_EN enables the 15 kΩ pull-down resistor on DM
HSTERM_EN enables the 45 Ω termination resistors on DP and DM
It is up to the link to set the desired register settings.
Table 8.
Operating states and their corresponding resistor settings
Signaling mode
Register settings
Internal resistor settings
XCVR
SELECT
[1:0]
TERM
SELECT
OPMODE
[1:0]
DP_PULL DM_PULL RPU_
DOWN
DOWN
DP_EN
RPD_
DP_EN
RPD_
HSTERM
DM_EN _EN
3-state drivers
XXb
Xb
01b
Xb
Xb
0b
0b
0b
0b
Power-up or
VBUS < VB_SESS_END
01b
0b
00b
1b
1b
0b
1b
1b
0b
00b
0b
10b
1b
1b
0b
1b
1b
1b
General settings
Host settings
Host chirp
Host high-speed
00b
0b
00b
1b
1b
0b
1b
1b
1b
Host full-speed
X1b
1b
00b
1b
1b
0b
1b
1b
0b
Host high-speed or
full-speed suspend
01b
1b
00b
1b
1b
0b
1b
1b
0b
Host high-speed or
full-speed resume
01b
1b
10b
1b
1b
0b
1b
1b
0b
Host low-speed
10b
1b
00b
1b
1b
0b
1b
1b
0b
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
18 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 8.
Operating states and their corresponding resistor settings …continued
Signaling mode
Register settings
Internal resistor settings
XCVR
SELECT
[1:0]
TERM
SELECT
OPMODE
[1:0]
DP_PULL DM_PULL RPU_
DOWN
DOWN
DP_EN
RPD_
DP_EN
RPD_
HSTERM
DM_EN _EN
Host low-speed
suspend
10b
1b
00b
1b
1b
0b
1b
1b
0b
Host low-speed
resume
10b
1b
10b
1b
1b
0b
1b
1b
0b
Host Test J or Test K 00b
0b
10b
1b
1b
0b
1b
1b
1b
Peripheral settings
Peripheral chirp
00b
1b
10b
0b
0b
1b
0b
0b
0b
Peripheral
high-speed
00b
0b
00b
0b
0b
0b
0b
0b
1b
Peripheral full-speed 01b
1b
00b
0b
0b
1b
0b
0b
0b
Peripheral
high-speed or
full-speed suspend
01b
1b
00b
0b
0b
1b
0b
0b
0b
Peripheral
high-speed or
full-speed resume
01b
1b
10b
0b
0b
1b
0b
0b
0b
Peripheral Test J or
Test K
00b
0b
10b
0b
0b
0b
0b
0b
1b
OTG device
peripheral chirp
00b
1b
10b
0b
1b
1b
0b
1b
0b
OTG device
peripheral
high-speed
00b
0b
00b
0b
1b
0b
0b
1b
1b
OTG device
01b
peripheral full-speed
1b
00b
0b
1b
1b
0b
1b
0b
OTG device
peripheral
high-speed and
full-speed suspend
01b
1b
00b
0b
1b
1b
0b
1b
0b
OTG device
peripheral
high-speed and
full-speed resume
01b
1b
10b
0b
1b
1b
0b
1b
0b
OTG device
peripheral Test J or
Test K
00b
0b
10b
0b
1b
0b
0b
1b
1b
OTG settings
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
19 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
9. Protocol description
The following subsections describe the protocol for using the ISP1507.
9.1 ULPI references
The ISP1507 provides a 12-pin ULPI interface to communicate with the link. It is highly
recommended that you read UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 and
UTMI+ Specification Rev. 1.0.
9.2 Power-On Reset (POR)
An internal POR is generated when REG1V8 rises above VPOR(trip), for at least
tw(REG1V8_H). The internal POR pulse will also be generated whenever REG1V8 drops
below VPOR(trip) for more than tw(REG1V8_L), and then rises above VPOR(trip) again. The
voltage on REG1V8 is generated from VCC.
To give a better view of the functionality, Figure 5 shows a possible curve of REG1V8. The
internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip
level so that POR turns to logic 1 and a delay element will add another tPORP before it
drops to logic 0. If REG1V8 dips from t2 to t3 for > tw(REG1V8_L), another POR pulse is
generated. If the dip at t4 to t5 is too short, that is, < tw(REG1V8_L), the internal POR pulse
will not react and will remain LOW.
REG1V8
VPOR(trip)
t0
t1
t2
t3
tPORP
tPORP
t4
t5
POR
004aaa751
Fig 5.
Internal power-on reset timing
9.3 Power-up, reset and bus idle sequence
Figure 6 shows a typical start-up sequence.
On power-up, the ISP1507 performs an internal power-on reset and asserts DIR to
indicate to the link that the ULPI bus cannot be used. When the internal PLL is stable, the
ISP1507 deasserts DIR. The power-up time depends on the VCC supply rise time, the
crystal start-up time, and PLL start-up time tstartup(o)(CLOCK). Whenever DIR is asserted,
the ISP1507 drives the NXT pin to LOW and drives DATA[7:0] with RXCMD values. When
DIR is deasserted, the link must drive the data bus to a valid level. By default, the link
must drive data to LOW. When the ISP1507 initially deasserts DIR on power-up, the link
must ignore all RXCMDs until it resets the ISP1507. Before beginning USB packets, the
link must set the RESET bit in the FUNC_CTRL register (see Section 10.1.2) to reset the
ISP1507. After the RESET bit is set, the ISP1507 will assert DIR until the internal reset
completes. The ISP1507 will automatically deassert DIR and clear the RESET bit when
reset has completed. After every reset, an RXCMD is sent to the link to update USB status
information. After this sequence, the ULPI bus is ready for use and the link can start USB
operations.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
20 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1507 will drive a
60 MHz clock out from the CLOCK pin when DIR deasserts. This is shown as CLOCK in
Figure 6.
The recommended power-up sequence for the link is as follows:
1. The link waits for 1 ms, ignoring all the ULPI pin status.
2. The link may start to detect DIR status level. If DIR is detected as LOW for three clock
cycles, the link may send a RESET command.
The ULPI interface is ready for use.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
21 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
VCC
VCC(I/O)
REG1V8
tPWRUP
internal
REG1V8
detector
internal
POR
XTAL1
bus idle
internal clocks stable
tstartup(PLL)
CLOCK
RESET command
DATA[7:0]
TXCMD D
internal reset
RXCMD
update
DIR
STP
NXT
t1
t2
t3
t4
t5
004aaa885
t1 = VCC and VCC(I/O) are applied to the ISP1507. The ISP1507 regulator starts to turn on.
t2 = ULPI pads detect REG1V8 rising above the REG1V8 regulator threshold and are not in 3-state. These pads may drive
either LOW or HIGH. It is recommended that the link ignores the ULPI pins status during tPWRUP.
t3 = The POR threshold is reached and a POR pulse is generated. After the POR pulse, ULPI pins are driven to a defined level.
DIR is driven to HIGH and the other pins are driven to LOW.
t4 = The internal PLL is stabilized after tstartup(PLL). If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL will
be stabilized after tstartup(PLL) from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH to LOW.
The DIR pin will remain LOW before the link issues a RESET command to the ISP1507.
t5 = The power-up sequence is completed and the ULPI bus interface is ready for use.
Fig 6.
Power-up and reset sequence required before the ULPI bus is ready for use
9.3.1 Interface protection
By default, the ISP1507 enables a weak pull-up resistor on STP. If the STP pin is
unexpectedly HIGH at any time, the ISP1507 will protect the ULPI interface by enabling
weak pull-down resistors on DATA[7:0].
The interface protect feature prevents unwanted activity of the ISP1507 whenever the
ULPI interface is not correctly driven by the link. For example, when the link powers up
more slowly than the ISP1507.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
22 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.
9.3.2 Interface behavior with respect to RESET_N
The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the
ISP1507 will assert DIR. All logic in the ISP1507 will be reset, including the analog
circuitry and ULPI registers. During reset, the link must drive DATA[7:0] and STP to LOW;
otherwise undefined behavior may result. When RESET_N is deasserted (HIGH), the DIR
output will deassert (LOW) four or five clock cycles later. Figure 7 shows the ULPI
interface behavior when RESET_N is asserted (LOW), and subsequently deasserted
(HIGH). The behavior of Figure 7 applies only when CHIP_SELECT_N is asserted
(LOW). If RESET_N is not used, it must be connected to VCC(I/O).
CLOCK
RESET_N
DATA[7:0]
Hi-Z (input)
Hi-Z (link must drive)
Hi-Z (input)
Hi-Z (link must drive)
Hi-Z (input)
DIR
STP
Hi-Z (input)
NXT
004aaa720
Fig 7.
Interface behavior with respect to RESET_N
9.3.3 Interface behavior with respect to CHIP_SELECT_N
At any time that CHIP_SELECT_N is HIGH, the ISP1507 will 3-state DATA[7:0], NXT and
DIR. STP input will be ignored. The link can reuse these pins for other purposes.
When CHIP_SELECT_N is LOW, ULPI output pins operate normally. During normal
operation, the PLL is always powered, regardless of the level of CHIP_SELECT_N.
During power-up, if CHIP_SELECT_N is HIGH, the PLL is not powered up to reduce
power consumption. During power-up, if CHIP_SELECT_N is LOW, the PLL is powered
and the ISP1507 operates normally.
If CHIP_SELECT_N is HIGH:
• The DATA[7:0], NXT and DIR pins are 3-stated and ignored.
• If the ISP1507 was previously in synchronous mode, the STP pin is ignored. If the
ISP1507 was previously in serial or suspend mode, STP is used to exit.
• The pull-down resistors on DATA[7:0] are disabled.
• The ULPI controller is forced into an idle state and any ULPI command is ignored.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
23 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
entering 3-state mode
exiting 3-state mode
CLOCK
CHIP_
SELECT_N
3-stated pins
DATA[7:0]
DIR
NXT
input ignored
STP
004aaa690
Fig 8.
Entering and exiting 3-state in normal mode
entering
3-state mode
exiting
3-state mode
CLOCK
CHIP_
SELECT_N
3-stated pins
DATA[7:0]
TXCMD
DATA
DIR
NXT
input ignored
STP
exiting
suspend mode
entering
suspend mode
SUSPENDM
004aaa691
Remark: Clock timing is not to scale.
Fig 9.
Entering and exiting 3-state in suspend mode
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
24 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
9.4 VBUS power and fault detection
9.4.1 Driving 5 V on VBUS
The ISP1507 provides a built-in charge pump. To enable the charge pump, the link must
set the DRV_VBUS bit in the OTG_CTRL register (see Section 10.1.4).
The ISP1507 also supports external 5 V supplies. The ISP1507 can control the external
supply using the active-LOW PSW_N open-drain output pin. To enable the external supply
by driving PSW_N to LOW, the link must set the DRV_VBUS_EXT bit in the OTG_CTRL
register to logic 1. The link can optionally set both the DRV_VBUS and DRV_VBUS_EXT
bits to logic 1 to enable the external supply.
Table 9 summarizes settings to drive 5 V on VBUS.
Table 9.
OTG_CTRL register power control bits
DRV_VBUS
DRV_VBUS_EXT
Power source used
0
0
internal and external VBUS power sources are disabled
1
0
internal VBUS charge pump is enabled
X
1
external 5 V VBUS supply is enabled
9.4.2 Fault detection
The ISP1507 supports external VBUS fault detector circuits that output a digital fault
indicator signal. The indicator signal must be connected to the FAULT pin. To enable the
ISP1507 to monitor the digital fault input, the link must set the USE_EXT_VBUS_IND bit
in the OTG_CTRL register (see Section 10.1.4) and the IND_PASSTHRU bit in the
INTF_CTRL register (see Section 10.1.3) to logic 1. For details, see Figure 11.
The FAULT input pin is mapped to the A_VBUS_VLD bit in RXCMD. Any changes for the
FAULT input will trigger RXCMD carrying the FAULT condition with A_VBUS_VLD.
9.5 TXCMD and RXCMD
Commands between the ISP1507 and the link are described in the following subsections.
9.5.1 TXCMD
By default, the link must drive the ULPI bus to its idle state of 00h. To send commands and
USB packets, the link drives a nonzero value on DATA[7:0] to the ISP1507 by sending a
byte called TXCMD. Commands include USB packet transmissions, and register reads
and writes. Once the TXCMD is interpreted and accepted by the ISP1507, the NXT signal
is asserted and the link can follow up with the required number of data bytes. The TXCMD
byte format is given in Table 10. Any values other than those in Table 10 are illegal and
may result in undefined behavior.
Various TXCMD packet and register sequences are shown in later sections.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
25 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 10.
TXCMD byte format
Command
type name
Command code Command payload
DATA[7:6]
DATA[5:0]
Command
name
Command description
Idle
00b
00 0000b
NOOP
No operation. 00h is the idle value of the data bus.
The link must drive NOOP by default.
Packet
transmit
01b
00 0000b
NOPID
Transmit USB data that does not have a PID, such as
chirp and resume signaling. The ISP1507 starts
transmitting only after accepting the next data byte.
00 XXXXb
PID
Transmit USB packet. DATA[3:0] indicates USB
packet identifier PID[3:0].
10 1111b
EXTW
Extended register write command (optional). The
8-bit address must be provided after the command is
accepted.
XX XXXXb
REGW
Register write command with 6-bit immediate
address.
10 1111b
EXTR
Extended register read command (optional). The
8-bit address must be provided after the command is
accepted.
XX XXXXb
REGR
Register read command with 6-bit immediate
address.
10b
Register
write
Register read 11b
9.5.2 RXCMD
The ISP1507 communicates status information to the link by asserting DIR and sending
an RXCMD byte on the data bus. The RXCMD data byte format is given in Table 11.
The ISP1507 will automatically send an RXCMD whenever there is a change in any of the
RXCMD data fields. The link must be able to accept an RXCMD at any time; including
single RXCMDs, back-to-back RXCMDs, and RXCMDs at any time during USB receive
packets when NXT is LOW. An example is shown in Figure 10. For details and diagrams,
refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
An RXCMD may not be sent when exiting low-power mode or serial mode, if the interrupt
condition is removed before exiting.
Table 11.
RXCMD byte format
DATA
Name
Description and value
1 to 0
LINESTATE LINESTATE signals: For a definition of LINESTATE, see Section 9.5.2.1.
DATA0 — LINESTATE[0]
DATA1 — LINESTATE[1]
3 to 2
VBUS state
Encoded VBUS voltage state: For an explanation of the VBUS state, see Section 9.5.2.2.
5 to 4
RxEvent
Encoded USB event signals: For an explanation of RxEvent, see Section 9.5.2.4.
6
ID
Set to the value of the ID pin.
7
ALT_INT
By default, this signal is not used and is not needed in typical designs. Optionally, the link can enable
the BVALID_RISE and/or BVALID_FALL bits in the PWR_CTRL register (see Section 10.1.14).
Corresponding changes in BVALID will cause an RXCMD to be sent to the link with the ALT_INT bit
asserted.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
26 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
CLOCK
Single RXCMD
turnaround
DATA[ 7:0]
Back-to-back RXCMDs
turnaround
RXCMD
turnaround
RXCMD
RXCMD
turnaround
DIR
STP
NXT
004aaa695
Fig 10. Single and back-to-back RXCMDs from the ISP1507 to the link
9.5.2.1
Linestate encoding
LINESTATE[1:0] reflects the current state of DP and DM. Whenever the ISP1507 detects
a change in DP or DM, an RXCMD will be sent to the link with the new LINESTATE[1:0]
value. The value given on LINESTATE[1:0] depends on the setting of various registers.
Table 12 shows the LINESTATE[1:0] encoding for upstream facing ports, which applies to
peripherals. Table 13 shows the LINESTATE[1:0] encoding for downstream facing ports,
which applies to host controllers. Dual-role devices must choose the correct table,
depending on whether it is in peripheral or host mode.
Table 12. LINESTATE[1:0] encoding for upstream facing ports: peripheral
DP_PULLDOWN = 0.[1]
Mode
Full-speed
High-speed
Chirp
XCVRSELECT[1:0]
01, 11
00
00
TERMSELECT
1
0
1
00
SE0
squelch
squelch
01
FS-J
!squelch
!squelch and HS_Differential_Receiver_Output
10
FS-K
invalid
!squelch and !HS_Differential_Receiver_Output
11
SE1
invalid
invalid
LINESTATE[1:0]
[1]
!squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
27 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 13. LINESTATE[1:0] encoding for downstream facing ports: host
DP_PULLDOWN and DM_PULLDOWN = 1.[1]
Mode
Low-speed
Full-speed
High-speed
Chirp
XCVRSELECT[1:0]
10
01, 11
00
00
TERMSELECT
1
1
0
0
OPMODE[1:0]
X
X
00, 01 or 11
10
00
SE0
SE0
squelch
squelch
01
LS-K
FS-J
!squelch
!squelch and HS_Differential_Receiver_Output
10
LS-J
FS-K
invalid
!squelch and !HS_Differential_Receiver_Output
11
SE1
SE1
invalid
invalid
LINESTATE[1:0]
[1]
!squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output.
9.5.2.2
VBUS state encoding
USB devices must monitor the VBUS voltage for purposes such as overcurrent detection,
starting a session and SRP. The VBUS state field in the RXCMD is an encoding of the
voltage level on VBUS.
The SESS_END and SESS_VLD indicators in the VBUS state are directly taken from
internal comparators built-in to the ISP1507, and encoded as shown in Table 11 and
Table 14.
Table 14.
Encoded VBUS voltage state
Value
VBUS voltage
SESS_END
SESS_VLD
A_VBUS_VLD
00
VBUS < VB_SESS_END
1
0
0
01
VB_SESS_END ≤ VBUS < VB_SESS_VLD
0
0
0
10
VB_SESS_VLD ≤ VBUS < VA_VBUS_VLD
X
1
0
11
VBUS ≥ VA_VBUS_VLD
X
X
1
The A_VBUS_VLD indicator in the VBUS state provides several options and must be
configured based on current draw requirements. A_VBUS_VLD can input from one or
more VBUS voltage indicators, as shown in Figure 11.
A description on how to use and select the VBUS state encoding is given in
Section 9.5.2.3.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
28 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
A_VBUS_VLD comparator
internal A_VBUS_VLD
VBUS
(0, X)
(1, 0)
FAULT
complement
output
FAULT indicator
RXCMD
A_VBUS_VLD
(1, 1)
IND_COMPL
USE_EXT_VBUS_IND,
IND_PASSTHRU
004aaa698
Fig 11. RXCMD A_VBUS_VLD indicator source
9.5.2.3
Using and selecting the VBUS state encoding
The VBUS state encoding is shown in Table 11. The ISP1507 will send an RXCMD to the
link whenever there is a change in the VBUS state. To receive VBUS state updates, the link
must first enable the corresponding interrupts in the USB_INTR_EN_R_E and
USB_INTR_EN_F_E registers.
The link can use the VBUS state to monitor VBUS and take appropriate action. Table 15
shows the recommended usage for typical applications.
Table 15.
VBUS indicators in RXCMD required for typical applications
Application
A_VBUS_VLD
SESS_VLD
SESS_END
Standard host
yes
no
no
Standard peripheral
no
yes
no
OTG A-device
yes
yes
no
OTG B-device
no
yes
yes
Standard USB host controllers: For standard hosts, the system must be able to provide
500 mA on VBUS in the range of 4.75 V to 5.25 V. An external circuit must be used to
detect overcurrent conditions. If the external overcurrent detector provides a digital fault
signal, then the fault signal must be connected to the ISP1507 FAULT input pin, and the
link must do the following:
1. Set the IND_COMPL bit in the INTF_CTRL register (see Section 10.1.3) to logic 0 or
logic 1, depending on the polarity of the external fault signal.
2. Set the USE_EXT_VBUS_IND bit in the OTG_CTRL register (see Section 10.1.4) to
logic 1.
3. If it is not necessary to qualify the fault indicator with the internal A_VBUS_VLD
comparator, set the IND_PASSTHRU bit in the INTF_CTRL register to logic 1.
Standard USB peripheral controllers: Standard peripherals must be able to detect
when VBUS is at a sufficient level for operation. SESS_VLD must be enabled to detect the
start and end of USB peripheral operations. Detection of A_VBUS_VLD and SESS_END
thresholds is not needed for standard peripherals.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
29 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
OTG devices: When an OTG device is configured as an OTG A-device, it must be able to
provide a minimum of 8 mA on VBUS. If the OTG A-device provides less than 100 mA, then
there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD
comparator is sufficient. If the OTG A-device provides more than 100 mA on VBUS, an
overcurrent detector must be used and Section “Standard USB host controllers” applies.
The OTG A-device also uses SESS_VLD to detect when an OTG B-device is initiating
VBUS pulsing SRP.
When an OTG device is configured as an OTG B-device, SESS_VLD must be used to
detect when VBUS is at a sufficient level for operation. SESS_END must be used to detect
when VBUS has dropped to a LOW level, allowing the B-device to safely initiate VBUS
pulsing SRP.
9.5.2.4
RxEvent encoding
The RxEvent field (see Table 16) of the RXCMD informs the link of information related
packets received on the USB bus. RxActive and RxError are defined in USB 2.0
Transceiver Macrocell Interface (UTMI) Specification Ver. 1.05. HostDisconnect is defined
in UTMI+ Specification Rev. 1.0. A short definition is also given in the following
subsections.
Table 16.
Encoded USB event signals
Value
RxActive
RxError
HostDisconnect
00
0
0
0
01
1
0
0
11
1
1
0
10
X
X
1
RxActive: When the ISP1507 has detected a SYNC pattern on the USB bus, it signals an
RxActive event to the link. An RxActive event can be communicated using two methods.
The first method is for the ISP1507 to simultaneously assert DIR and NXT. The second
method is for the ISP1507 to send an RXCMD to the link with the RxActive field in
RxEvent bits set to logic 1. The link must be able to detect both methods. RxActive frames
the receive packet from the first byte to the last byte.
The link must assume that RxActive is set to logic 0 when indicated in an RXCMD or when
DIR is deasserted, whichever occurs first.
The link uses RxActive to time high-speed packets and ensure that bus turnaround times
are met. For more information on the USB packet timing, see Section 9.8.1.
RxError: When the ISP1507 has detected an error while receiving a USB packet, it
deasserts NXT and sends an RXCMD with the RxError field set to logic 1. The received
packet is no longer valid and must be dropped by the link.
HostDisconnect: HostDisconnect is encoded into the RxEvent field of the RXCMD.
HostDisconnect is valid only when the ISP1507 is configured as a host (both
DP_PULLDOWN and DM_PULLDOWN are set to logic 1), and indicates to the host
controller when a peripheral is connected or disconnected. The host controller must
enable HostDisconnect by setting the HOST_DISCON_R and HOST_DISCON_F bits in
the USB_INTR_EN_R_E and USB_INTR_EN_F_E registers, respectively. Changes in
HostDisconnect will cause the PHY to send an RXCMD to the link with the updated value.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
30 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
9.6 Register read and write operations
Figure 12 shows register read and write sequences. The ISP1507 supports immediate
addressing and extended addressing register operations. Extended register addressing is
optional for links. Note that register operations will be aborted if the ISP1507 unexpectedly
asserts DIR during the operation. When a register operation is aborted, the link must retry
until successful. For more information on register operations, refer to UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1.
CLOCK
TXCMD
(REGW) D
TXCMD
(EXTW) AD D
TXCMD
(REGR)
D
TXCMD
(EXTW) AD
D
DATA[7:0]
immediate
register write
extended
register write
immediate
register read
extended
register read
DIR
STP
NXT
004aaa710
AD indicates the address byte, and D indicates the data byte.
Fig 12. Example of register write, register read, extended register write and extended register read
9.7 USB reset and high-speed detection handshake (chirp)
Figure 13 shows the sequence of events for USB reset and high-speed detection
handshake (chirp). The sequence is shown for hosts and peripherals. Figure 13 does not
show all RXCMD updates and timing is not to scale. The sequence is as follows:
1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and
as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow
the remainder of this protocol. If a host detects a full-speed peripheral, it resets the
peripheral by writing to the Function Control register (see Section 10.1.2).
XCVRSELECT[1:0] = 00b (high-speed) and TERMSELECT = 0b are then set which
drives SE0 on the bus (DP and DM are connected to ground through 45 Ω). The host
also sets OPMODE[1:0] = 10b for correct chirp transmit and receive. The start of SE0
is labeled T0.
Remark: To receive chirp signaling, the host must also consider the high-speed
differential receiver output. The host controller must interpret LINESTATE[1:0] as
shown in Table 13.
2. High-speed detection handshake (chirp)
a. Peripheral chirp: After detecting SE0 for no less than 2.5 µs, if the peripheral is
capable of high-speed, it sets XCVRSELECT[1:0] = 00b (high-speed) and
OPMODE[1:0] = 10b (chirp). The peripheral immediately follows this with a
TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
31 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
than 7 ms after reset time T0. If the peripheral is in low-power mode, it must wake
up its clock within 5.6 ms, leaving 200 µs for the link to start transmitting the
Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock).
b. Host chirp: If the host does not detect the peripheral chirp, it must continue
asserting SE0 until the end of reset. If the host detects the peripheral Chirp K for
no less than 2.5 µs, then no more than 100 µs after the bus leaves the Chirp K
state, the host sends a TXCMD (NOPID) with an alternating sequence of Chirp Ks
and Js. Each Chirp K or Chirp J must last no less than 40 µs and no longer than
60 µs.
c. High-speed idle: The peripheral must detect a minimum of Chirp K-J-K-J-K-J. Each
Chirp K and Chirp J must be detected for at least 2.5 µs. The peripheral sets
TERMSELECT = 0b and OPMODE[1:0] = 00b after seeing the minimum Chirp
sequence. The peripheral is now in high-speed mode and sees !squelch (01b on
LINESTATE). When the peripheral sees squelch (10b on LINESTATE), it knows
that the host has completed chirp and waits for Hi-Speed USB traffic to begin. After
transmitting the chirp sequence, the host changes OPMODE[1:0] to 00b and
begins sending USB packets.
For more information, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
32 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
USB reset
high-speed detection handshake (chirp)
T0
TXCMD
(REGW) SE0
K
HS idle
host chirp
peripheral chirp
00
TXCMD
NOPID K
...
J
K
J
TXCMD
(REGW)
DATA
[ 7:0]
DIR
ULPI host
STP
NXT
00 (HS)
01 (FS)
XCVR
SELECT
TERM
SELECT
00 (normal)
00 (normal)
01 (chirp)
OP
MODE
J (01b)
SE0 (00b)
peripheral chirp K (10b)
squelch
(00b)
host chirp K (10b) or chirp J (01b)
squelch (00b)
LINE
STATE
TXCMD
SE0 (REGW)
TXCMD
NOPID K
RXCMDs
K
...
K
00
K
J
K
J
K
TXCMD
J (REGW)
00
DATA
[ 7:0]
DIR
ULPI peripheral
STP
NXT
00 (HS)
01 (FS)
XCVR
SELECT
TERM
SELECT
00 (normal)
10 (chirp)
00 (normal)
OP
MODE
J (01b)
SE0 (00b)
peripheral chirp K (10b)
squelch
(00b)
host chirp K or J (10b or 01b)
!squelch
(01b) squelch (00b)
USB signals
LINE
STATE
DP
DM
004aaa711
Timing is not to scale.
Fig 13. USB reset and high-speed detection handshake (chirp) sequence
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
33 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
9.8 USB packet transmit and receive
An example of a packet transmit and receive is shown in Figure 14. For details on USB
packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
ISP1507
accepts
TXCMD
link sends
TXCMD
link sends
the next data;
ISP1507 link signals
accepts end of data
ISP1507
ISP1507
asserts DIR, ISP1507
ISP1507
deasserts
sends
causing
sends
DIR, causing
ULPI bus turnaround
RXCMD
USB data turnaround
is idle
(NXT LOW) (NXT HIGH)
cycle
cycle
CLOCK
TXCMD
DATA[7:0]
DATA
turnaround
RXCMD
turnaround
DATA
DIR
STP
NXT
004aab039
Fig 14. Example of using the ISP1507 to transmit and receive USB data
9.8.1 USB packet timing
9.8.1.1
ISP1507 pipeline delays
The ISP1507 delays are shown in Table 17. For a detailed description, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.2.6.2.
Table 17.
PHY pipeline delays
Parameter name
High-speed PHY delay
Full-speed PHY delay
Low-speed PHY delay
RXCMD delay (J and K)
4
4
4
RXCMD delay (SE0)
4
4 to 6
16 to 18
TX start delay
1 to 2
6 to 10
74 to 75
TX end delay (packets)
3 to 4
not applicable
not applicable
TX end delay (SOF)
6 to 9
not applicable
not applicable
RX start delay
5 to 6
not applicable
not applicable
RX end delay
5 to 6
17 to 18
122 to 123
9.8.1.2
Allowed link decision time
The amount of clock cycles allocated to the link to respond to a received packet and
correctly receive back-to-back packets is given in Table 18. Link designs must follow
values given in Table 18 for correct USB system operation. Examples of high-speed
packet sequences and timing are shown in Figure 15 and Figure 16. For details, refer to
UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.2.6.3.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
34 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 18.
Link decision times
Packet sequence High-speed Full-speed
link delay
link delay
Low-speed Definition
link delay
Transmit-Transmit
(host only)
77 to 247
15 to 24
7 to 18
Number of clock cycles a host link must wait before driving
the TXCMD for the second packet.
In high-speed, the link starts counting from the assertion of
STP for the first packet.
In full-speed, the link starts counting from the RXCMD,
indicating LINESTATE has changed from SE0 to J for the first
packet. The timing given ensures inter-packet delays of 2 bit
times to 6.5 bit times.
Receive-Transmit
(host or
peripheral)
1 to 14
7 to 18
77 to 247
Number of clock cycles the link must wait before driving the
TXCMD for the transmit packet.
In high-speed, the link starts counting from the end of the
receive packet; deassertion of DIR or an RXCMD, indicating
RxActive is LOW.
In full-speed or low-speed, the link starts counting from the
RXCMD, indicating LINESTATE has changed from SE0 to J
for the receive packet. The timing given ensures inter-packet
delays of 2 bit times to 6.5 bit times.
Receive-Receive
(peripheral only)
1
1
1
Minimum number of clock cycles between consecutive
receive packets. The link must be able to receive both
packets.
Transmit-Receive
(host or
peripheral)
92
80
718
Host or peripheral transmits a packet and will time-out after
this number of clock cycles if a response is not received. Any
subsequent transmission can occur after this time.
USB interpacket delay (88 to 192 high-speed bit times)
DP or
DM
DATA
IDLE
EOP
SYNC
CLOCK
DN−1
DN
TXCMD
D0
D1
DATA
[7:0]
DIR
STP
NXT
link decision time (15 to 24 clocks)
TX end delay (two to five clocks)
TX start delay
(one to two clocks)
004aaa712
Fig 15. High-speed transmit-to-transmit packet timing
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
35 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
USB interpacket delay (8 to 192 high-speed bit times)
DP or
DM
IDLE
EOP
DATA
SYNC
CLOCK
DN
DN−2
DN−4
TXCMD
D0
D1
DATA
[7:0]
DN−3
DN−1
turnaround
DIR
STP
NXT
RX end delay
(three to eight clocks)
link decision time (1 to 14 clocks)
TX start delay
(one to two clocks)
004aaa713
Fig 16. High-speed receive-to-transmit packet timing
9.9 Preamble
Preamble packets are headers to low-speed packets that must travel over a full-speed
bus, between a host and a hub. To enter preamble mode, the link sets
XCVRSELECT[1:0] = 11b in the FUNC_CTRL register (see Section 10.1.2). When in
preamble mode, the ISP1507 operates just as in full-speed mode, and sends all data with
the full-speed rise time and fall time. Whenever the link transmits a USB packet in
preamble mode, the ISP1507 will automatically send a preamble header at full-speed bit
rate before sending the link packet at low-speed bit rate. The ISP1507 will ensure a
minimum gap of four full-speed bit times between the last bit of the full-speed PRE PID
and the first bit of the low-speed packet SYNC. The ISP1507 will drive a J for at least one
full-speed bit time after sending the PRE PID, after which the pull-up resistor can hold the
J state on the bus. An example transmit packet is shown in Figure 17.
In preamble mode, the ISP1507 can also receive low-speed packets from the full-speed
bus.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
36 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
CLOCK
DATA[7:0]
TXCMD (low-speed packet ID)
D0
D1
DIR
STP
NXT
DP or DM
FS SYNC
FS
PRE ID
IDLE (min
4 FS bits)
LS SYNC
LS PID
LS D0
LS D1
004aaa714
DP and DM timing is not to scale.
Fig 17. Preamble sequence
9.10 USB suspend and resume
9.10.1 Full-speed or low-speed host-initiated suspend and resume
Figure 18 illustrates how a host or a hub places a full-speed or low-speed peripheral into
suspend and sometime later initiates resume signaling to wake up the downstream
peripheral. Note that Figure 18 timing is not to scale, and does not show all RXCMD
LINESTATE updates.
The sequence of events for a host and a peripheral, both with ISP1507, is as follows:
1. Idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ pull-down
resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and 45 Ω
terminations disabled (TERMSELECT is set to 1b). The peripheral has the 1.5 kΩ
pull-up resistor connected to DP for full-speed or DM for low-speed (TERMSELECT is
set to 1b).
2. Suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend
state. The peripheral link places the PHY into low-power mode by clearing the
SUSPENDM bit in the FUNC_CTRL register (see Section 10.1.2), causing the PHY to
draw only suspend current. The host may or may not be powered down.
3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE[1:0] to
10b and transmits a K for at least 20 ms. The peripheral link sees the resume K on
LINESTATE, and asserts STP to wake up the PHY.
4. EOP: When STP is asserted, the ISP1507 on the host side automatically appends an
EOP of two bits of SE0 at low-speed bit rate, followed by one bit of J. The ISP1507 on
the host side knows to add the EOP because DP_PULLDOWN and DM_PULLDOWN
are set to 1b for a host. After the EOP is completed, the host link sets OPMODE[1:0]
to 00b for normal operation. The peripheral link sees the EOP and also resumes
normal operation.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
37 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
suspend
idle
FS or LS host (XCVRSELECT = 01b (FS)
or 10b (LS), DP_PULLDOWN = 1b,
DM_PULLDOWN = 1b, TERMSELECT = 1b)
TXCMD
(REGW)
EOP
resume K
TXCMD
NOPID
K
K
...
idle
TXCMD
K
DATA
[7:0]
DIR
STP
NXT
OPMODE
10b
00b
LINE
STATE
K
J
00b
J
SE0
FS or LS peripheral (XCVRSELECT = 01b (FS)
or 10b (LS), DP_PULLDOWN = 0b, TERMSELECT = 1b)
CLOCK
TXCMD
(REGW)
LINESTATE J
LINESTATE K
SE0
J
DATA
[7:0]
DIR
STP
NXT
OPMODE
00b
10b
00b
SUSPENDM
USB signals
(only FS is shown)
LINE
STATE
K
J
SE0
J
DP
DM
004aab123
Timing is not to scale.
Fig 18. Full-speed suspend and resume
9.10.2 High-speed suspend and resume
Figure 19 illustrates how a host or a hub places a high-speed enabled peripheral into
suspend and then initiates resume signaling. The high-speed peripheral will wake up and
return to high-speed operations. Note that Figure 19 timing is not to scale, and does not
show all RXCMD LINESTATE updates.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
38 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
The sequence of events related to a host and a peripheral, both with ISP1507, is as
follows:
1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ
pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b)
and 45 Ω terminations enabled (TERMSELECT is set to 0b). The peripheral has its
45 Ω terminations enabled (TERMSELECT is set to 0b).
2. Full-speed suspend: When the peripheral sees no bus activity for 3 ms, it enters the
suspend state. The peripheral link places the ISP1507 into full-speed mode
(XCVRSELECT is set to 01b), removes 45 Ω terminations, and enables the 1.5 kΩ
pull-up resistor on DP (TERMSELECT is set to 1b). The peripheral link then places
the ISP1507 into low-power mode by clearing SUSPENDM, causing the ISP1507 to
draw only suspend current. The host also changes the ISP1507 to full-speed
(XCVRSELECT is set to 01b), removes 45 Ω terminations (TERMSELECT is set to
1b), and then may or may not be powered down.
3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE to 10b
and transmits a full-speed K for at least 20 ms. The peripheral link sees the resume K
(10b) on LINESTATE, and asserts STP to wake up the ISP1507.
4. High-speed traffic: The host link sets high-speed (XCVRSELECT is set to 00b) and
enables its 45 Ω terminations (TERMSELECT is set to 0b). The peripheral link sees
SE0 on LINESTATE and also sets high-speed (XCVRSELECT is set to 00b), and
enables its 45 Ω terminations (TERMSELECT is set to 0b). The host link sets
OPMODE to 00b for normal high-speed operation.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
39 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
FS suspend
HS idle
resume K
TXCMD TXCMD
(REGW) NOPID K K
TXCMD
(REGW)
HS idle
TXCMD
... K (REGW)
ULPI HS host (DP_PULLDOWN = 1b,
DM_PULLDOWN = 1b)
DATA
[7:0]
DIR
STP
NXT
XCVR
SELECT
01b
00b
00b
TERM
SELECT
OP
MODE
!SQUELCH SQUELCH
(00b)
(01b)
LINE
STATE
10b
00b
00b
FS K (10b)
FS J (01b)
SQUELCH (00b)
!SQUELCH
(01b)
CLOCK
TXCMD
(REGW)
TXCMD
SE0 (REGW)
LINESTATE K
LINESTATE J
ULPI HS peripheral (DP_PULLDOWN = 0b)
DATA
[7:0]
DIR
STP
NXT
XCVR
SELECT
01b
00b
00b
TERM
SELECT
OP
MODE
00b
10b
00b
SUSPENDM
USB signals
LINE
STATE
!SQUELCH SQUELCH
(01b)
(00b)
FS J (01b)
FS K (10b)
SQUELCH (00b)
!SQUELCH
(01b)
DP
DM
004aab124
Timing is not to scale.
Fig 19. High-speed suspend and resume
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
40 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
9.10.3 Remote wake-up
The ISP1507 supports peripherals that initiate remote wake-up resume. When placed into
USB suspend, the peripheral link remembers at what speed it was originally operating.
Depending on the original speed, the link follows one of the protocols detailed here. In
Figure 20, timing is not to scale, and not all RXCMD LINESTATE updates are shown.
The sequence of events related to a host and a peripheral, both with ISP1507, is as
follows:
1. Both the host and the peripheral are assumed to be in low-power mode.
2. The peripheral begins remote wake-up by re-enabling its clock and setting its
SUSPENDM bit to 1b.
3. The peripheral begins driving K on the bus to signal resume. Note that the peripheral
link must assume that LINESTATE is K (01b) while transmitting because it will not
receive any RXCMDs.
4. The host recognizes the resume, re-enables its clock and sets its SUSPENDM bit.
5. The host takes over resume driving within 1 ms of detecting the remote wake-up.
6. The peripheral stops driving resume.
7. The peripheral sees the host continuing to drive resume.
8. The host stops driving resume and the ISP1507 automatically adds the EOP to the
end of resume. The peripheral recognizes the EOP as the end of resume.
9. Both the host and the peripheral revert to normal operation by writing 00b to
OPMODE. If the host or the peripheral was previously in high-speed mode, it must
revert to high-speed before the SE0 of the EOP is completed. This can be achieved
by writing XCVRSELECT[1:0] = 00b and TERMSELECT = 0b after LINESTATE
indicates SE0.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
41 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
TXCMD
REGW
LINESTATE
TXCMD
NOPID
TXCMD
REGW
00h
DATA
[ 7:0]
ULPI host
DIR
STP
NXT
XCVR
SELECT
00b (HS only)
01b (FS), 10b (LS)
TERM
SELECT
0b (HS only)
OP
MODE
00b
10b
LINESTATE
TXCMD
REGW
TXCMD
NOPID
RXCMD
00h
RXCMD
TXCMD
RXCMD REGW
DATA
[ 7:0]
ULPI peripheral
DIR
STP
NXT
00b (HS only)
XCVR
SELECT
00b (HS), 01b (FS), 10b (LS)
TERM
SELECT
0b (HS only)
OP
MODE
10b
00b
004aaa718
Timing is not to scale.
Fig 20. Remote wake-up from low-power mode
9.11 No automatic SYNC and EOP generation (optional)
This setting allows the link to turn off the automatic SYNC and EOP generation, and must
be used for high-speed packets only. It is provided for backward compatibility with legacy
controllers that include SYNC and EOP bytes in the data payload when transmitting
packets. The ISP1507 will not automatically generate the SYNC and EOP patterns when
OPMODE[1:0] is set to 11b. The ISP1507 will still NRZI encode data and perform bit
stuffing. An example of a sequence is shown in Figure 21. The link must always send
packets using the TXCMD (NOPID) type. The ISP1507 does not provide a mechanism to
control bit stuffing in individual bytes, but will automatically turn off bit stuffing for EOP
when STP is asserted with data set to FEh. If data is set to 00h when STP is asserted, the
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
42 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
PHY will not transmit any EOP. The ISP1507 will also detect if the PID byte is A5h,
indicating an SOF packet, and automatically send a long EOP when STP is asserted. To
transmit chirp and resume signaling, the link must set OPMODE to 10b.
CLOCK
ULPI signals
TXCMD
00h
00h 00h 80h PID
D1
D2
D3
...
... D
N − 1 DN
FEh
DATA
[7:0]
DIR
STP
USB bus
UTMI+ equivalent
signals
NXT
TXVALID
TXREADY
TXBIT
STUFF
ENABLE
IDLE
SYNC
PID
DATA PAYLOAD
EOP
IDLE
DP, DM
004aab125
Fig 21. Transmitting USB packets without automatic SYNC and EOP generation
9.12 On-The-Go operations
On-The-Go (OTG) is a supplement to Universal Serial Bus Specification Rev. 2.0 that
allows a portable USB device to assume the role of a limited USB host by defining
improvements, such as a small connector and low power. Non-portable devices, such as
standard hosts and embedded hosts, can also benefit from OTG features.
The ISP1507 OTG PHY is designed to support all the tasks specified in the OTG
supplement. The ISP1507 provides the front-end analog support for Host Negotiation
Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices. The
supporting components include:
• Built-in 5 V charge pump
• Voltage comparators
– A_VBUS_VLD
– SESS_VLD (session valid, can be used for both A-session and B-session valid)
– SESS_END (session end)
• Pull-up and pull-down resistors on DP and DM
• ID detector indicates if micro-A or micro-B plug is inserted
• Charge and discharge resistors on VBUS
The following subsections describe how to use the ISP1507 OTG components.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
43 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
9.12.1 OTG charge pump
A description of the charge pump is given in Section 7.6.4. When the controller is
configured as an A-device, it can provide the VBUS power by turning on the charge pump.
Control of the charge pump is described in Section 9.4.1 and Section 10.1.4.
9.12.2 OTG comparators
The ISP1507 provides comparators that conform to On-The-Go Supplement to the
USB 2.0 Specification Rev. 1.3 requirements of VA_VBUS_VLD, VA_SESS_VLD, VB_SESS_VLD
and VB_SESS_END. In this data sheet, VA_SESS_VLD and VB_SESS_VLD are combined into
VB_SESS_VLD. Comparators are described in Section 7.6.2. Changes in comparator values
are communicated to the link by RXCMDs as described in Section 9.5.2.2. Control over
comparators is described in Section 10.1.5 to Section 10.1.8.
9.12.3 Pull-up and pull-down resistors
The USB resistors on DP and DM can be used to initiate data-line pulsing SRP. The link
must set the required bus state using mode settings in Table 8.
9.12.4 ID detection
The ISP1507 provides an internal pull-up resistor to sense the value of the ID pin. The
pull-up resistor must first be enabled by setting the ID_PULLUP register bit to logic 1. If
the value on ID has changed, the ISP1507 will send an RXCMD or interrupt to the link by
time tID. If the link does not receive any RXCMD or interrupt by tID, then the ID value has
not changed.
9.12.5 VBUS charge and discharge resistors
A pull-up resistor, RUP(VBUS), is provided to perform VBUS pulsing SRP. A B-device is
allowed to charge VBUS above the session valid threshold to request the host to turn on
the VBUS power.
A pull-down resistor, RDN(VBUS), is provided for a B-device to discharge VBUS. This is done
whenever the A-device turns off the VBUS power. The B-device can use the pull-down
resistor to ensure VBUS is below VB_SESS_END before starting a session.
For details, refer to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3.
9.13 Serial modes
The ISP1507 supports both 6-pin serial mode and 3-pin serial mode, controlled by
bits 6PIN_FSLS_SERIAL and 3PIN_FSLS_SERIAL of the INTF_CTRL register (see
Section 10.1.3). For details, refer to UTMI+ Low Pin Interface (ULPI) Specification
Rev. 1.1, Section 3.10.
Figure 22 and Figure 23 provide examples of 6-pin serial mode and 3-pin serial mode,
respectively.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
44 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
TRANSMIT
SYNC
DATA
RECEIVE
EOP
SYNC
DATA
EOP
DATA0
(TX_ENABLE)
DATA1
(TX_DAT)
DATA2
(TX_SE0)
DATA4
(RX_DP)
DATA5
(RX_DM)
DATA6
(RX_RCV)
DP
DM
004aaa692
Fig 22. Example of transmit followed by receive in 6-pin serial mode
TRANSMIT
SYNC
DATA
RECEIVE
EOP
SYNC
DATA
EOP
DATA0
(TX_ENABLE)
DATA1
(TX_DAT/
RX_RCV)
DATA2
(TX_SE0/
RX_SE0)
DP
DM
004aaa693
Fig 23. Example of transmit followed by receive in 3-pin serial mode
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
45 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
9.14 Aborting transfers
The ISP1507 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4.
9.15 Avoiding contention on the ULPI data bus
Because the ULPI data bus is bidirectional, avoid situations in which both the link and the
PHY simultaneously drive the data bus.
The following points must be considered while implementing the data bus drive control on
the link.
After power-up and clock stabilization, default states are as follows:
• The ISP1507 drives DIR to LOW.
• The data bus is input to the ISP1507.
• The ULPI link data bus is output, with all data bus lines driven to LOW.
When the ISP1507 wants to take control of the data bus to initiate a data transfer, it
changes the DIR value from LOW to HIGH.
At this point, the link must disable its output buffers. This must be as fast as possible so
the link must use a combinational path from DIR.
The ISP1507 will not immediately enable its output buffers, but will delay the enabling of
its buffers until the next clock edge, avoiding bus contention.
When the data transfer is no longer required by the ISP1507, it changes DIR from HIGH to
LOW and starts to immediately turn off its output drivers. The link senses the change of
DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle,
avoiding data bus contention.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
46 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
10. Register map
Table 19.
Immediate register set overview
Field name
VENDOR_ID_LOW
Size (bit)
8
Address (6 bit)
References
R[1]
W[2]
S[3]
C[4]
00h
-
-
-
Section 10.1.1 on page 48
VENDOR_ID_HIGH
8
01h
-
-
-
PRODUCT_ID_LOW
8
02h
-
-
-
PRODUCT_ID_HIGH
8
03h
-
-
-
FUNC_CTRL
8
04h to 06h
04h
05h
06h
Section 10.1.2 on page 48
INTF_CTRL
8
07h to 09h
07h
08h
09h
Section 10.1.3 on page 49
OTG_CTRL
8
0Ah to 0Ch
0Ah
0Bh
0Ch
Section 10.1.4 on page 51
USB_INTR_EN_R_E
8
0Dh to 0Fh
0Dh
0Eh
0Fh
Section 10.1.5 on page 52
USB_INTR_EN_F_E
8
10h to 12h
10h
11h
12h
Section 10.1.6 on page 52
USB_INTR_STAT
8
13h
-
-
-
Section 10.1.7 on page 53
USB_INTR_L
8
14h
-
-
-
Section 10.1.8 on page 53
DEBUG
8
15h
-
-
-
Section 10.1.9 on page 54
SCRATCH
8
16h to 18h
16h
17h
18h
Section 10.1.10 on page 54
Reserved (do not use)
-
Access extended register set
8
-
2Fh
Vendor-specific registers
8
30h to 3Ch
Section 10.1.13 on page 55
PWR_CTRL
8
3Dh to 3Fh
Section 10.1.14 on page 55
Section 10.1.11 on page 55
19h to 2Eh
-
Section 10.1.12 on page 55
-
[1]
Read (R): A register can be read. Read-only if this is the only mode given.
[2]
Write (W): The pattern on the data bus will be written over all bits of a register.
[3]
Set (S): The pattern on the data bus is OR-ed with and written to a register.
[4]
Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero
(cleared).
Table 20.
Extended register set overview
Field name
Size
(bit)
Address (6 bit)
R[1]
W[2]
References
S[3]
Maps to immediate register set above
8
00h to 3Fh
Reserved (do not use)
8
40h to FFh
C[4]
Section 10.2 on page 55
[1]
Read (R): A register can be read. Read-only if this is the only mode given.
[2]
Write (W): The pattern on the data bus will be written over all bits of a register.
[3]
Set (S): The pattern on the data bus is OR-ed with and written to a register.
[4]
Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero
(cleared).
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
47 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
10.1 Immediate register set
10.1.1 Vendor ID and Product ID registers
10.1.1.1
VENDOR_ID_LOW register
Table 21 shows the bit description of the register.
Table 21.
VENDOR_ID_LOW - Vendor ID Low register (address R = 00h) bit description
Bit
Symbol
Access
Value
Description
7 to 0
VENDOR_ID_
LOW[7:0]
R
CCh
Vendor ID Low: Lower byte of the NXP vendor ID supplied by USB-IF;
has a fixed value of CCh
10.1.1.2
VENDOR_ID_HIGH register
The bit description of the register is given in Table 22.
Table 22.
VENDOR_ID_HIGH - Vendor ID High register (address R = 01h) bit description
Bit
Symbol
Access Value
Description
7 to 0
VENDOR_ID_
HIGH[7:0]
R
Vendor ID High: Upper byte of the NXP vendor ID supplied by USB-IF;
has a fixed value of 04h
10.1.1.3
04h
PRODUCT_ID_LOW register
The bit description of the PRODUCT_ID_LOW register is given in Table 23.
Table 23.
PRODUCT_ID_LOW - Product ID Low register (address R = 02h) bit description
Bit
Symbol
7 to 0
PRODUCT_ID_ R
LOW[7:0]
Access
10.1.1.4
Value
Description
04h
Product ID Low: Lower byte of the NXP product ID number; has a fixed
value of 04h
PRODUCT_ID_HIGH register
The bit description of the register is given in Table 24.
Table 24.
PRODUCT_ID_HIGH - Product ID High register (address R = 03h) bit description
Bit
Symbol
7 to 0
PRODUCT_ID_ R
HIGH[7:0]
Access
Value
Description
15h
Product ID High: Upper byte of the NXP product ID number; has a fixed
value of 15h
10.1.2 FUNC_CTRL register
This register controls UTMI function settings of the PHY. The bit allocation of the register
is given in Table 25.
Table 25.
FUNC_CTRL - Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit allocation
Bit
Symbol
7
6
5
reserved
SUSPENDM
RESET
Reset
Access
4
3
OPMODE[1:0]
2
TERM
SELECT
1
0
XCVRSELECT[1:0]
0
1
0
0
0
0
0
1
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
48 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 26.
FUNC_CTRL - Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit
description
Bit
Symbol
Description
7
-
reserved
6
SUSPENDM
Suspend LOW: Active LOW PHY suspend.
Places the PHY into low-power mode. The PHY will power down all blocks, except the
full-speed receiver, OTG comparators and ULPI interface pins.
To come out of low-power mode, the link must assert STP. The PHY will automatically clear
this bit when it exits low-power mode.
0b — Low-power mode
1b — Powered (default)
5
RESET
Reset: Active HIGH transceiver reset.
After the link sets this bit, the PHY will assert DIR and reset the digital core. This does not
reset the ULPI interface or the ULPI register set.
When reset is completed, the PHY will deassert DIR and automatically clear this bit, followed
by an RXCMD update to the link.
0b — Do not reset (default)
1b — Reset
The link must wait for DIR to deassert before using the ULPI bus. Does not reset the ULPI
interface or the ULPI register set.
4 to 3
OPMODE[1:0]
Operation Mode: Selects the required bit-encoding style during transmit.
00b — Normal operation (default)
01b — Non-driving
10b — Disable bit-stuffing and NRZI encoding
11b — Do not automatically add SYNC and EOP when transmitting; must be used only for
high-speed packets
2
TERMSELECT Termination Select: Controls the internal 1.5 kΩ full-speed pull-up resistor and 45 Ω
high-speed terminations. Control over bus resistors changes, depending on
XCVRSELECT[1:0], OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in
Table 8.
1 to 0
XCVRSELECT Transceiver Select: Selects the required transceiver speed.
[1:0]
00b — Enable the high-speed transceiver
01b — Enable the full-speed transceiver (default)
10b — Enable the low-speed transceiver
11b — Enable the full-speed transceiver for low-speed packets (full-speed preamble is
automatically prefixed)
10.1.3 INTF_CTRL register
The INTF_CTRL register enables alternative interfaces. All of these modes are optional
features provided for legacy link cores. Setting more than one of these fields results in
undefined behavior. Table 27 provides the bit allocation of the register.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
49 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 27.
INTF_CTRL - Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation
Bit
Symbol
7
6
5
4
3
2
INTF_
PROT_DIS
IND_PASS
THRU
IND_
COMPL
reserved
CLOCK_
SUSPENDM
reserved
0
0
0
0
0
0
0
0
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
Reset
Access
Table 28.
1
0
3PIN_FSLS 6PIN_FSLS
_SERIAL
_SERIAL
INTF_CTRL - Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit
description
Bit
Symbol
Description
7
INTF_PROT_DIS
Interface Protect Disable: Controls circuitry built into the ISP1507 to protect the ULPI
interface when the link 3-states STP and DATA[7:0]. When this bit is enabled, the ISP1507
will automatically detect when the link stops driving STP.
0b — Enables the interface protect circuit (default). The ISP1507 attaches a weak pull-up
resistor on STP. If STP is unexpectedly HIGH, the ISP1507 attaches weak pull-down
resistors on DATA[7:0], protecting data inputs.
1b — Disables the interface protect circuit, detaches weak pull-down resistors on
DATA[7:0], and a weak pull-up resistor on STP.
6
IND_PASSTHRU
Indicator Pass-through: Controls whether the complement output is qualified with the
internal A_VBUS_VLD comparator before being used in the VBUS state in RXCMD. For
details, see Section 9.5.2.2.
0b — The complement output signal is qualified with the internal A_VBUS_VLD comparator
(default).
1b — The complement output signal is not qualified with the internal A_VBUS_VLD
comparator.
5
IND_COMPL
Indicator Complement: Informs the PHY to invert the FAULT input signal, generating the
complement output. For details, see Section 9.5.2.2.
0b — The ISP1507 will not invert the FAULT signal (default).
1b — The ISP1507 will invert the FAULT signal.
4
-
reserved
3
CLOCK_SUSPENDM Clock Suspend LOW: Active LOW clock suspend.
Powers down the internal clock circuitry only. By default, the clock will not be powered in
6-pin serial mode or 3-pin serial mode.
Valid only in 6-pin serial mode and 3-pin serial mode. Valid only when SUSPENDM is set to
logic 1, otherwise this bit is ignored.
0b — Clock will not be powered in 3-pin or 6-pin serial mode (default).
1b — Clock will be powered in 3-pin and 6-pin serial mode.
2
-
reserved
1
3PIN_FSLS_SERIAL
3-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 3-bit serial
interface. The PHY will automatically clear this bit when 3-pin serial mode is exited.
0b — Full-speed or low-speed packets are sent using the parallel interface (default).
1b — Full-speed or low-speed packets are sent using the 3-pin serial interface.
0
6PIN_FSLS_SERIAL
6-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 6-bit serial
interface. The PHY will automatically clear this bit when 6-pin serial mode is exited.
0b — Full-speed or low-speed packets are sent using the parallel interface (default).
1b — Full-speed or low-speed packets are sent using the 6-pin serial interface.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
50 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
10.1.4 OTG_CTRL register
This register controls various OTG functions of the ISP1507. The bit allocation of the
OTG_CTRL register is given in Table 29.
Table 29.
OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation
Bit
7
Symbol
Reset
Access
Table 30.
6
USE_EXT_
DRV_
VBUS_IND VBUS_EXT
5
4
3
2
1
0
DRV_
VBUS
CHRG_
VBUS
DISCHRG_
VBUS
DM_PULL
DOWN
DP_PULL
DOWN
ID_PULL
UP
0
0
0
0
0
1
1
0
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit
description
Bit
Symbol
Description
7
USE_EXT_VBUS_ Use External VBUS Indicator: Informs the PHY to use an external VBUS overcurrent indicator.
IND
0b — Use the internal OTG comparator (default).
1b — Use the external VBUS valid indicator signal input from the FAULT pin.
6
DRV_VBUS_EXT
Drive VBUS External: Selects between the internal and external 5 V VBUS supply. Using an
external charge pump or a 5 V supply is optional.
0b — Drive VBUS using the internal charge pump. Also ensures PSW_N is not driven to LOW
(default).
1b — Drive VBUS using the external charge pump or the 5 V supply. Drives PSW_N to LOW.
5
DRV_VBUS
Drive VBUS: Signals the ISP1507 to drive 5 V on VBUS. If DRV_VBUS_EXT is set to logic 1,
then setting DRV_VBUS is optional.
0b — Do not drive VBUS (default).
1b — Drive 5 V on VBUS.
4
CHRG_VBUS
Charge VBUS: Charges VBUS through a resistor. Used for the VBUS pulsing SRP. The link must
first check that VBUS is discharged (see bit DISCHRG_VBUS), and that both the DP and DM
data lines have been LOW (SE0) for 2 ms.
0b — Do not charge VBUS (default).
1b — Charge VBUS.
3
DISCHRG_VBUS
Discharge VBUS: Discharges VBUS through a resistor. If the link sets this bit to logic 1, it waits
for an RXCMD indicating that SESS_END has changed from 0 to 1, and then resets this bit to
0 to stop the discharge.
0b — Do not discharge VBUS (default).
1b — Discharge VBUS.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
51 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 30.
OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit
description …continued
Bit
Symbol
Description
2
DM_PULLDOWN
DM Pull Down: Enables the 15 kΩ pull-down resistor on DM.
0b — Pull-down resistor is not connected to DM.
1b — Pull-down resistor is connected to DM (default).
1
DP_PULLDOWN
DP Pull Down: Enables the 15 kΩ pull-down resistor on DP.
0b — Pull-down resistor is not connected to DP.
1b — Pull-down resistor is connected to DP (default).
0
ID_PULLUP
ID Pull Up: Connects a pull-up to the ID line and enables sampling of the ID level. Disabling
the ID line sampler will reduce PHY power consumption.
0b — Disables sampling of the ID line (default).
1b — Enables sampling of the ID line.
10.1.5 USB_INTR_EN_R_E register
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding
bits in the USB_INTR_STAT register change from logic 0 to logic 1. By default, all
transitions are enabled. Table 31 shows the bit allocation of the register.
Table 31.
USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh,
S = 0Eh, C = 0Fh) bit allocation
Bit
7
6
Symbol
5
reserved
Reset
Access
Table 32.
4
3
2
1
0
ID_GND_R
SESS_
END_R
SESS_
VALID_R
VBUS_
VALID_R
HOST_
DISCON_R
0
0
0
1
1
1
1
1
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh,
S = 0Eh, C = 0Fh) bit description
Bit
Symbol
Description
7 to 5
-
reserved
4
ID_GND_R
ID Ground Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on ID_GND.
3
SESS_END_R
Session End Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
SESS_END.
2
SESS_VALID_R
Session Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
SESS_VLD.
1
VBUS_VALID_R
VBUS Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
A_VBUS_VLD.
0
HOST_DISCON_
R
Host Disconnect Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
HOST_DISCON.
10.1.6 USB_INTR_EN_F_E register
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding
bits in the USB_INTR_STAT register change from logic 1 to logic 0. By default, all
transitions are enabled. See Table 33.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
52 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 33.
USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h,
S = 11h, C = 12h) bit allocation
Bit
7
6
Symbol
5
reserved
Reset
Access
Table 34.
4
3
2
1
0
ID_GND_F
SESS_
END_F
SESS_
VALID_F
VBUS_
VALID_F
HOST_
DISCON_F
0
0
0
1
1
1
1
1
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h,
S = 11h, C = 12h) bit description
Bit
Symbol
Description
7 to 5
-
reserved
4
ID_GND_F
ID Ground Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on ID_GND.
3
SESS_END_F
Session End Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
SESS_END.
2
SESS_VALID_F
Session Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
SESS_VLD.
1
VBUS_VALID_F
VBUS Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
A_VBUS_VLD.
0
HOST_DISCON
_F
Host Disconnect Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
HOST_DISCON.
10.1.7 USB_INTR_STAT register
This register (see Table 35) indicates the current value of the interrupt source signal.
Table 35.
USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit allocation
Bit
7
6
Symbol
5
reserved
4
3
2
1
0
ID_GND
SESS_END
SESS_
VALID
VBUS_
VALID
HOST_
DISCON
Reset
X
X
X
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Table 36.
USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit description
Bit
Symbol
Description
7 to 5
-
reserved
4
ID_GND
ID Ground: Reflects the current value of the ID detector circuit.
3
SESS_END
Session End: Reflects the current value of the session end voltage comparator.
2
SESS_VALID
Session Valid: Reflects the current value of the session valid voltage comparator.
1
VBUS_VALID
VBUS Valid: Reflects the current value of the VBUS valid voltage comparator.
0
HOST_DISCON
Host Disconnect: Reflects the current value of the host disconnect detector.
10.1.8 USB_INTR_L register
The bits of the USB_INTR_L register are automatically set by the ISP1507 when an
unmasked change occurs on the corresponding interrupt source signal. The ISP1507 will
automatically clear all bits when the link reads this register, or when the PHY enters
low-power mode.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
53 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Remark: It is optional for the link to read this register when the clock is running because
all signal information will automatically be sent to the link through the RXCMD byte.
The bit allocation of this register is given in Table 37.
Table 37.
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit allocation
Bit
7
6
Symbol
5
reserved
4
3
2
1
0
ID_GND_L
SESS_
END_L
SESS_
VALID_L
VBUS_
VALID_L
HOST_
DISCON_L
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Table 38.
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit description
Bit
Symbol
Description
7 to 5
-
reserved
4
ID_GND_L
ID Ground Latch: Automatically set when an unmasked event occurs on ID_GND. Cleared
when this register is read.
3
SESS_END_L
Session End Latch: Automatically set when an unmasked event occurs on SESS_END.
Cleared when this register is read.
2
SESS_VALID_L
Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD.
Cleared when this register is read.
1
VBUS_VALID_L
VBUS Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD.
Cleared when this register is read.
0
HOST_DISCON_L
Host Disconnect Latch: Automatically set when an unmasked event occurs on
HOST_DISCON. Cleared when this register is read.
10.1.9 DEBUG register
The bit allocation of the DEBUG register is given in Table 39. This register indicates the
current value of signals useful for debugging.
Table 39.
DEBUG - Debug register (address R = 15h) bit allocation
Bit
7
6
5
Symbol
4
3
2
reserved
1
0
LINE
STATE1
LINE
STATE0
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Table 40.
DEBUG - Debug register (address R = 15h) bit description
Bit
Symbol
Description
7 to 2
-
reserved
1
LINESTATE1
Line State 1: Contains the current value of LINESTATE 1.
0
LINESTATE0
Line State 0: Contains the current value of LINESTATE 0.
10.1.10 SCRATCH register
This is an empty register for testing purposes; see Table 41.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
54 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 41.
SCRATCH - Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description
Bit
Symbol
Access
Value Description
7 to 0
SCRATCH R/W/S/C 00h
[7:0]
Scratch: This is an empty register byte for testing purposes. Software can read,
write, set and clear this register. The functionality of the PHY will not be affected.
10.1.11 Reserved
Registers 19h to 2Eh are not implemented. Operating on these addresses will have no
effect on the PHY.
10.1.12 Access extended register set
Address 2Fh does not contain register data. Instead it links to the extended register set.
The immediate register set maps to the lower end of the extended register set.
10.1.13 Vendor-specific registers
Addresses 30h to 3Fh contain vendor-specific registers.
10.1.14 PWR_CTRL register
This register controls various aspects of the ISP1507. See Table 42.
Table 42.
PWR_CTRL - Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation
Bit
7
6
Symbol
4
reserved
Reset
Access
Table 43.
5
3
2
BVALID_
FALL
BVALID_
RISE
1
0
reserved
0
0
0
0
0
0
0
0
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
R/W/S/C
PWR_CTRL - Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description
Bit
Symbol
Description
7 to 4
-
reserved; the link must never write logic 1 to these bits.
3
BVALID_FALL
BVALID Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID
changes from HIGH to LOW, the ISP1507 will send an RXCMD to the link with the ALT_INT bit
set to logic 1.
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging
purposes. The session valid comparator should be used instead.
2
BVALID_RISE
BVALID Rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID
changes from LOW to HIGH, the ISP1507 will send an RXCMD to the link with the ALT_INT bit
set to logic 1.
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging
purposes. The session valid comparator should be used instead.
1 to 0
-
reserved; the link must never write logic 1 to these bits.
10.2 Extended register set
Addresses 00h to 3Fh of the extended register set directly map to the immediate set. This
means a read, write, set or clear operation to these extended addresses will operate on
the immediate register set.
Addresses 40h to FFh are not implemented. Operating on these addresses may result in
undefined behavior of the PHY.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
55 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
11. ElectroStatic Discharge (ESD)
11.1 ESD protection
The pins that are connected to the USB connector (DP, DM, ID, VBUS and GND) have a
minimum of ±4 kV ESD protection. Capacitors 0.1 µF and 1 µF must be connected in
parallel from VBUS to GND to achieve this ±4 kV ESD protection (see Figure 24).
Remark: Capacitors 0.1 µF and 1 µF are also required by Universal Serial Bus
Specification Rev. 2.0. For details on the requirements for CVBUS, see Section 16.
RC
1 MΩ
RD
1500 Ω
charge current
limit resistor
discharge
resistance
DEVICE UNDER
TEST
VBUS
A
HIGH VOLTAGE
DC SOURCE
CS
100 pF
storage
capacitor
B
0.1 µF
1 µF
GND
004aaa881
Fig 24. Human body ESD test model
11.2 ESD test conditions
A detailed report on test setup and results is available on request.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
56 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
12. Limiting values
Table 44. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCC
supply voltage
VCC(I/O)
input/output supply voltage
VI
input voltage
VESD
Conditions
electrostatic discharge
voltage
Ilu
latch-up current
Tstg
storage temperature
Min
Max
Unit
−0.5
+4.6
V
−0.5
+4.6
V
on pins STP, DATA[7:0], RESET_N
and CHIP_SELECT_N
−0.5
VCC(I/O) + 0.5
V
on pins VBUS, FAULT and PSW_N
−0.5
+6.0
V
on pin XTAL1
−0.5
+2.5
V
on pin ID
−0.5
+4.6
V
on pins DP and DM
[1]
−0.5
+4.6
V
pins DP, DM, ID, VBUS and GND;
ILI < 1 µA
[2]
−4
+4
kV
all other pins; ILI < 1 µA
[2]
−1.5
+1.5
kV
-
100
mA
−40
+125
°C
−0.5 × VCC < V < +1.5 × VCC
[1]
The ISP1507 has been tested according to the additional requirements listed in Universal Serial Bus Specification Rev. 2.0,
Section 7.1.1. The short circuit withstand test and the AC stress test were performed for 24 hours, and the ISP1507 was found to be fully
operational after the test completed.
[2]
Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor (Human Body Model JESD22-A114D).
13. Recommended operating conditions
Table 45.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
VCC(I/O)
input/output supply voltage
VI
input voltage
Conditions
Min
Typ
Max
Unit
3.0
3.3
3.6
V
1.65
-
3.6
V
on pins STP, DATA[7:0], RESET_N
and CHIP_SELECT_N
0
-
VCC(I/O)
V
on pins VBUS, FAULT and PSW_N
0
-
5.5
V
on pins DP, DM and ID
0
-
3.6
V
on pin XTAL1
[1]
0
-
1.95
V
Tamb
ambient temperature
−40
+25
+85
°C
Tj
junction temperature
−40
-
+125
°C
[1]
VCC(I/O) must be less than or equal to VCC.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
57 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
14. Static characteristics
Table 46. Static characteristics: supply pins
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
V(REG3V3) voltage on pin REG3V3
3.0
3.3
3.6
V
V(REG1V8) voltage on pin REG1V8
1.65
1.8
1.95
V
1.0
-
1.5
V
low-power mode; VBUS valid detector
disabled; 1.5 kΩ pull-up resistor on
pin DP disconnected
-
35
85
µA
low-power mode; VBUS valid detector
disabled; 1.5 kΩ pull-up resistor on
pin DP connected
-
215
280
µA
full-speed idle; no USB activity
-
10
-
mA
VPOR(trip)
power-on reset trip voltage
ICC
supply current
Conditions
charge pump disabled
high-speed idle; no USB activity
-
19
-
mA
full-speed continuous data transmit;
50 pF load on pins DP and DM
[1]
-
15
-
mA
full-speed continuous data receive
[1]
-
11
-
mA
high-speed continuous data transmit;
45 Ω load on pins DP and DM to ground
[1]
-
48
-
mA
high-speed continuous data receive
[1]
-
28
-
mA
IO(VBUS) = 8 mA; charge pump supply
current only
-
20
23
mA
IO(VBUS) = 0 mA; charge pump supply
current only
-
300
-
µA
-
-
1
µA
charge pump enabled
ICC(I/O)
[1]
supply current on
pin VCC(I/O)
ULPI interface pins are static
A continuous stream of 1 kB packets with minimum inter-packet gap and all data bits set to logic 0 for continuous toggling.
Table 47. Static characteristics: digital pins
Digital pins: CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N and CHIP_SELECT_N; unless otherwise specified.
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
0.3 × VCC(I/O) V
Input levels
VIL
LOW-level input voltage
-
VIH
HIGH-level input voltage
0.7 × VCC(I/O) -
-
V
IIL
LOW-level input current
VI = 0 V
-
-
1
µA
IIH
HIGH-level input current
VI = VCC(I/O)
-
-
1
µA
ILI
input leakage current
−1
+0.1
+1
µA
-
-
0.4
V
Output levels
VOL
LOW-level output voltage
IOL = +2 mA
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
58 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 47. Static characteristics: digital pins …continued
Digital pins: CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N and CHIP_SELECT_N; unless otherwise specified.
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage IOH = −2 mA
VCC(I/O) − 0.4 -
-
V
IOH
HIGH-level output current VO = VCC(I/O) − 0.4 V
−4.8
-
-
mA
IOL
LOW-level output current
VO = 0.4 V
4.2
-
-
mA
IOZ
off-state output current
0 V < VO < VCC(I/O)
-
-
1
µA
45
-
65
Ω
Impedance
ZL
load impedance
Pull-up and pull-down
Ipd
pull-down current
interface protect enabled;
DATA[7:0] pins only;
VI = VCC(I/O)
25
50
90
µA
Ipu
pull-up current
interface protect enabled;
STP pin only; VI = 0 V
−30
−50
−80
µA
pins STP, RESET_N,
DATA[7:0],
CHIP_SELECT_N
-
-
3.5
pF
Capacitance
Cin
input capacitance
Table 48. Static characteristics: digital pin FAULT
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input levels
VIL
LOW-level input voltage
-
-
0.8
V
VIH
HIGH-level input voltage
2.0
-
-
V
IIL
LOW-level input current
VI = 0 V
-
-
1
µA
IIH
HIGH-level input current
VI = VCC(I/O)
-
-
1
µA
Table 49. Static characteristics: digital pin PSW_N
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Output levels
VOH
HIGH-level output voltage
external pull-up resistor connected
-
-
5.5
V
VOL
LOW-level output voltage
IOL = −4 mA
-
-
0.4
V
IOH
HIGH-level output current
external pull-up resistor connected
-
-
1
µA
IOL
LOW-level output current
VO = 0.4 V
4.0
-
-
mA
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
59 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 50. Static characteristics: analog I/O pins (DP, DM)
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Original USB transceiver (low-speed and full-speed)
Input levels (differential receiver)
VDI
differential input sensitivity voltage
|VDP − VDM|
0.2
-
-
V
VCM
differential common mode voltage
range
includes VDI range
0.8
-
2.5
V
Input levels (single-ended receivers)
VIL
LOW-level input voltage
-
-
0.8
V
VIH
HIGH-level input voltage
2.0
-
-
V
Output levels
VOL
LOW-level output voltage
pull-up on pin DP;
RL = 1.5 kΩ to 3.6 V
0.0
0.18
0.3
V
VOH
HIGH-level output voltage
pull-down on
pins DP and DM;
RL = 15 kΩ to GND
2.8
3.2
3.6
V
termination voltage for upstream
facing port pull-up
for 1.5 kΩ pull-up
resistor
3.0
-
3.6
V
1425
1500
1575
Ω
Termination
VTERM
Resistance
RUP(DP)
pull-up resistance on pin DP
High-speed USB transceiver
Input levels (differential receiver)
VHSSQ
high-speed squelch detection
threshold voltage (differential signal
amplitude)
100
-
150
mV
VHSDSC
high-speed disconnect detection
threshold voltage (differential signal
amplitude)
525
-
625
mV
VHSDI
high-speed differential input sensitivity |VDP − VDM|
300
-
-
mV
VHSCM
high-speed data signaling common
mode voltage range (guideline for
receiver)
−50
-
+500
mV
VHSOI
high-speed idle level voltage
−10
-
+10
mV
VHSOL
high-speed data signaling LOW-level
voltage
−10
-
+10
mV
includes VDI range
Output levels
VHSOH
high-speed data signaling HIGH-level
voltage
360
-
440
mV
VCHIRPJ
Chirp J level (differential voltage)
700
-
1100
mV
VCHIRPK
Chirp K level (differential voltage)
−900
-
−500
mV
−1
-
+1
µA
-
-
5
pF
Leakage current
ILZ
off-state leakage current
Capacitance
Cin
input capacitance
pin to GND
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
60 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 50. Static characteristics: analog I/O pins (DP, DM) …continued
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Resistance
RDN(DP)
pull-down resistance on pin DP
14.25
15
15.75
kΩ
RDN(DM)
pull-down resistance on pin DM
14.25
15
15.75
kΩ
40.5
45
49.5
Ω
Termination
ZO(drv)(DP)
driver output impedance on pin DP
ZO(drv)(DM)
driver output impedance on pin DM
ZINP
input impedance exclusive of
pull-up/pull-down (for low-/full-speed)
[1]
steady-state drive
[1]
steady-state drive
[1]
40.5
45
49.5
Ω
10
-
-
MΩ
For high-speed USB and full-speed USB.
Table 51. Static characteristics: charge pump
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VO(VBUS)
output voltage on pin VBUS
IO(VBUS) = 50 mA;
Ccp(C_A)-(C_B) = 270 nF
4.65
5.0
5.25
V
VL(VBUS)
leakage voltage on pin VBUS
charge pump disabled
-
-
0.2
V
output current on pin VBUS
Ccp(C_A)-(C_B) = 270 nF
45
75
-
mA
charge pump efficiency
IO(VBUS) = 50 mA
60
72
78
%
Voltage
Current
IO(VBUS)
Efficiency
ηcp
Table 52. Static characteristics: VBUS comparators
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
VA_VBUS_VLD
A-device VBUS valid voltage
VB_SESS_VLD
B-device session valid voltage
Vhys(B_SESS_VLD)
VB_SESS_END
Conditions
Min
Typ
Max
Unit
4.4
4.5
4.65
V
0.8
1.6
2.0
V
B-device session valid hysteresis voltage
70
90
110
mV
B-device session end voltage
0.2
0.5
0.8
V
for A-device and
B-device
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
61 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 53. Static characteristics: VBUS resistors
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RUP(VBUS)
pull-up resistance on pin VBUS
connect to pin REG3V3
when CHRG_VBUS is
logic 1
281
680
-
Ω
RDN(VBUS)
pull-down resistance on pin VBUS connect to GND when
DISCHRG_VBUS is
logic 1
656
1100
-
Ω
RI(idle)(VBUS)(A)
idle input resistance on pin VBUS
(A-device)
ID pin LOW and charge
pump disabled
40
57
80
kΩ
RI(idle)(VBUS)(B)
idle input resistance on pin VBUS
(B-device)
ID pin HIGH or charge
pump enabled
170
240
310
kΩ
Table 54. Static characteristics: ID detection circuit
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
tID
ID detection time
Vth(ID)
ID detector threshold voltage
RUP(ID)
ID pull-up resistance
Conditions
ID_PULLUP is logic 1
Min
Typ
Max
Unit
50
-
-
ms
0.8
1.2
2.0
V
40
50
60
kΩ
Table 55. Static characteristics: resistor reference
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
VO(RREF)
output voltage on pin RREF SUSPENDM is logic 1
ISP1507A_ISP1507B_1
Product data sheet
Min
Typ
Max
Unit
-
1.22
-
V
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
62 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
004aaa876
120
ICC(cp)
(mA)
100
004aaa877
5.50
VCC = 3.6 V
VCC = 3.6 V
3.3 V
3.0 V
80
3.3 V
3.0 V
VO(VBUS)
(V)
5.00
60
4.50
40
20
4.00
0
0
10
20
30
0
40
50
IO(VBUS) (mA)
10
20
30
40
50
IO(VBUS) (mA)
ICC(cp) denotes charge pump supply current.
Fig 25. Charge pump supply current as a function of
VBUS output current
5.50
004aaa878
004aaa879
108
IO(VBUS) = 0 mA
ICC(cp)
(mA)
8 mA
50 mA
VO(VBUS)
(V)
Fig 26. VBUS output voltage as a function of VBUS
output current
106
5.00
IO(VBUS) = 50 mA
104
4.50
102
4.00
3
3.1
3.2
3.3
3.4
3.5
3.6
VCC(cp) (V)
VCC(cp) denotes charge pump supply voltage.
100
−40
0
+20
+40
+60
+80 +100
Tamb (°C)
ICC(cp) denotes charge pump supply current.
Fig 27. VBUS output voltage as a function of charge
pump supply voltage
Fig 28. Charge pump supply current as a function of
temperature
ISP1507A_ISP1507B_1
Product data sheet
−20
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
63 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
15. Dynamic characteristics
Table 56. Dynamic characteristics: reset and clock
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset
tW(POR)
internal power-on reset pulse
width
0.2
-
-
µs
tw(REG1V8_H)
REG1V8 HIGH pulse width
2
-
-
µs
tw(REG1V8_L)
REG1V8 LOW pulse width
11
-
-
µs
tW(RESET_N)
external RESET_N pulse width
200
-
-
ns
tPWRUP
regulator start-up time
4.7 µF ± 20 % capacitor each on
pins REG1V8 and REG3V3
-
-
1
ms
ISP1507ABS
-
19.2
-
MHz
ISP1507BBS
-
26
-
MHz
ISP1507ABS
-
-
200
ps
Crystal or clock applied to XTAL1
fi(XTAL1)
input frequency on pin XTAL1
tjit(i)(XTAL1)RMS
RMS input jitter on pin XTAL1
δi(XTAL1)
input duty cycle on pin XTAL1
∆fi(XTAL1)
input frequency tolerance on
pin XTAL1
tr(XTAL1)
rise time on pin XTAL1
tf(XTAL1)
V(XTAL1)(p-p)
ISP1507BBS
-
-
300
ps
-
50
-
%
-
50
200
ppm
only for square wave input
-
-
5
ns
fall time on pin XTAL1
only for square wave input
-
-
5
ns
peak-to-peak voltage on
pin XTAL1
only for square wave input
0.566
-
1.95
V
-
60
-
MHz
tjit(o)(CLOCK)RMS RMS output jitter on pin
CLOCK
-
-
500
ps
δo(CLOCK)
output clock duty cycle on
pin CLOCK
45
50
55
%
tstartup(PLL)
PLL startup time
applicable only when clock is
applied on pin XTAL1
[1]
Output CLOCK characteristics
fo(CLOCK)
output frequency on
pin CLOCK
tstartup(o)(CLOCK) output CLOCK start-up time
[1]
measured from power good or
assertion of pin STP
-
650
-
µs
450
650
900
µs
The internal PLL is triggered only on the positive edge from the crystal oscillator. Therefore, the duty cycle is not critical.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
64 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 57. Dynamic characteristics: digital I/O pins
VCC = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC(I/O) = 1.65 V to 1.95 V
tsu(DATA)
DATA set-up time with respect to 20 pF total external load
the rising edge of pin CLOCK
per pin
5.7
-
-
ns
th(DATA)
DATA hold time with respect to
the rising edge of pin CLOCK
20 pF total external load
per pin
0
-
-
ns
td(DATA)
DATA output delay with respect 20 pF total external load
to the rising edge of pin CLOCK per pin
-
-
7.8
ns
tsu(STP)
STP set-up time with respect to
the rising edge of pin CLOCK
20 pF total external load
per pin
4.5
-
-
ns
th(STP)
STP hold time with respect to
the rising edge of pin CLOCK
20 pF total external load
per pin
0
-
-
ns
td(DIR)
DIR output delay with respect to 20 pF total external load
the rising edge of pin CLOCK
per pin
-
-
8.9
ns
td(NXT)
NXT output delay with respect to 20 pF total external load
the rising edge of pin CLOCK
per pin
-
-
8.9
ns
VCC(I/O) = 3.0 V to 3.6 V
tsu(DATA)
DATA set-up time with respect to 30 pF total external load
the rising edge of pin CLOCK
per pin
3.3
-
-
ns
th(DATA)
DATA hold time with respect to
the rising edge of pin CLOCK
0.8
-
-
ns
td(DATA)
DATA output delay with respect 30 pF total external load
to the rising edge of pin CLOCK per pin
-
-
5.5
ns
tsu(STP)
STP set-up time with respect to
the rising edge of pin CLOCK
30 pF total external load
per pin
3.4
-
-
ns
th(STP)
STP hold time with respect to
the rising edge of pin CLOCK
30 pF total external load
per pin
0.8
-
-
ns
td(DIR)
DIR output delay with respect to 30 pF total external load
the rising edge of pin CLOCK
per pin
-
-
6.6
ns
td(NXT)
NXT output delay with respect to 30 pF total external load
the rising edge of pin CLOCK
per pin
-
-
6.6
ns
30 pF total external load
per pin
Table 58. Dynamic characteristics: analog I/O pins (DP and DM)
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
High-speed driver
tHSR
rise time (10 % to 90 %)
500
-
-
ps
tHSF
fall time (10 % to 90 %)
500
-
-
ps
Full-speed driver
tFR
rise time
CL = 50 pF; 10 % to 90 % of
|VOH − VOL|
4
-
20
ns
tFF
fall time
CL = 50 pF; 10 % to 90 % of
|VOH − VOL|
4
-
20
ns
tFRFM
differential rise and fall
time matching
excluding the first transition
from the idle state
90
-
111.1
%
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
65 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 58. Dynamic characteristics: analog I/O pins (DP and DM) …continued
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCRS
output signal crossover
voltage
excluding the first transition
from the idle state
1.3
-
2.0
V
Low-speed driver
tLR
transition time: rise time
CL = 200 pF to 600 pF;
1.5 kΩ pull-up on pin DM
enabled; 10 % to 90 % of
|VOH − VOL|
75
-
300
ns
tLF
transition time: fall time
CL = 200 pF to 600 pF;
1.5 kΩ pull-up on pin DM
enabled; 10 % to 90 % of
|VOH − VOL|
75
-
300
ns
tLRFM
rise and fall time matching tLR/tLF; excluding the first
transition from the idle state
80
-
125
%
Driver timing
tPLH(drv)
driver propagation delay
(LOW to HIGH)
TX_DAT, TX_SE0 to DP, DM;
see Figure 30
-
-
11
ns
tPHL(drv)
driver propagation delay
(HIGH to LOW)
TX_DAT, TX_SE0 to DP, DM;
see Figure 30
-
-
11
ns
tPHZ
driver disable delay from
HIGH level
TX_ENABLE to DP, DM;
see Figure 31
-
-
12
ns
tPLZ
driver disable delay from
LOW level
TX_ENABLE to DP, DM;
see Figure 31
-
-
12
ns
tPZH
driver enable delay to
HIGH level
TX_ENABLE to DP, DM;
see Figure 31
-
-
20
ns
tPZL
driver enable delay to
LOW level
TX_ENABLE to DP, DM;
see Figure 31
-
-
20
ns
Receiver timing
Differential receiver
tPLH(rcv)
receiver propagation
delay (LOW to HIGH)
DP, DM to RX_RCV, RX_DP
and RX_DM; see Figure 32
-
-
17
ns
tPHL(rcv)
receiver propagation
delay (HIGH to LOW)
DP, DM to RX_RCV, RX_DP
and RX_DM; see Figure 32
-
-
17
ns
Single-ended receiver
tPLH(se)
single-ended propagation
delay (LOW to HIGH)
DP, DM to RX_RCV, RX_DP
and RX_DM; see Figure 32
-
-
17
ns
tPHL(se)
single-ended propagation
delay (HIGH to LOW)
DP, DM to RX_RCV, RX_DP
and RX_DM; see Figure 32
-
-
17
ns
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
66 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
1.8 V
0.9 V
logic input 0.9 V
tHSF, tFF, tLF
tHSR, tFR, tLR
0V
VOH
VOL
90 %
tPLH(drv)
90 %
tPHL(drv)
VOH
10 %
differential
data lines
10 %
VCRS
VOL
004aaa861
Fig 29. Rise time and fall time
VCRS
004aaa573
Fig 30. Timing of TX_DAT and TX_SE0 to DP and DM
2.0 V
1.8 V
logic 0.9 V
input
differential
data lines
0.9 V
VCRS
VCRS
0.8 V
0V
VOH
tPLH(rcv)
tPLH(se)
tPHZ
tPLZ
tPZH
tPZL
VOH
VOH − 0.3 V
differential
data lines
VOL + 0.3 V
VOL
004aaa574
Fig 31. Timing of TX_ENABLE to DP and DM
0.9 V
0.9 V
logic output
VCRS
VOL
tPHL(rcv)
tPHL(se)
004aaa575
Fig 32. Timing of DP and DM to RX_RCV, RX_DP and
RX_DM
15.1 ULPI timing
ULPI interface timing requirements are given in Figure 33. This timing applies to
synchronous mode only. All timing is measured with respect to the ISP1507 CLOCK pin.
All signals are clocked on the rising edge of CLOCK.
CLOCK
tsu(STP) th(STP)
CONTROL IN
(STP)
tsu(DATA) th(DATA)
DATA IN
(8-BIT)
td(DIR),
td(NXT)
CONTROL OUT
(DIR, NXT)
td(DATA)
td(DIR),
td(NXT)
DATA OUT
(8-BIT)
004aaa722
Fig 33. ULPI interface timing
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
67 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
16. Application information
Table 59.
Recommended bill of materials
Designator[1] Application
Value
Comment
-
Cbypass
highly recommended for all
applications
0.1 µF
Ccp(C_A)-(C_B)
charge pump is used
22 nF (8 mA), 270 nF (50 mA); up to 470 nF (50 mA)
Cfilter
highly recommended for all
applications
4.7 µF ± 20 %; use a LOW
ESR capacitor (0.2 Ω to 2 Ω)
for best performance
-
CVBUS
mandatory for peripherals
0.1 µF and 1 µF to 10 µF in
parallel
-
mandatory for host
0.1 µF and 120 µF ± 20 %
(min) in parallel
-
mandatory for OTG
0.1 µF and 1 µF to 6.5 µF in
parallel
-
DESD
recommended for all
ESD-sensitive applications
IP4359CX4/LF
Wafer-Level Chip-Scale Package (WLCSP);
ESD IEC 61000-4-2 level 4; ±15 kV contact;
±15 kV air discharge compliant protection
Rpullup
recommended; for
applications with an
external VBUS supply
controlled by PSW_N
4.7 kΩ (recommended)
maximum value is determined by the voltage
drop on PSW_N caused by leakage into
PSW_N and the external supply control pin
RRREF
mandatory in all
applications
12 kΩ ± 1 %
-
RVBUS
strongly recommended for
peripheral or external 5 V
applications only
1 kΩ ± 5 %
-
RXTAL
47 kΩ ± 5 %
required only for
applications driving a
square wave into the XTAL1
pin
used to avoid floating input on the XTAL1 pin
XTAL
crystal is used
CL = 10 pF; RS < 220 Ω; CXTAL = 18 pF
C(XTAL)SQ
19.2 MHz
26 MHz
CL = 10 pF; RS < 130 Ω; CXTAL = 18 pF
CSTCE26M0XK2***-R0[2]
CXTAL is not required
100 pF
required only for
applications driving a
square wave into the XTAL1
pin that has a DC offset
used to AC couple the input square wave to
the XTAL1 pin
[1]
For detailed information and alternative interface options, refer to the Interfacing to the ISP1507 (AN10080) application note.
[2]
For more information, contact Murata.
Remark: In the following application diagrams, because the ULPI bus is not shared, the
CHIP_SELECT_N pin is connected to ground. In other applications, CHIP_SELECT_N
can be controlled by a link to 3-state the ULPI bus so that those pins can be used for other
purposes.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
68 of 81
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
ISP1507A_ISP1507B_1
Product data sheet
VCC(I/O)
Cbypass
DATA0
VCC
VCC(I/O)
1
2
3
4
Cbypass
VBUS
RRREF
RREF
D−
DM
DP
D+
FAULT
ID
Rev. 01 — 19 May 2008
ID
USB
5 GND
MICRO-AB
RECEPTACLE
6 SHIELD
A1
CPGND
B1
B2
C_B
DESD
7 SHIELD
Ccp(C_A)-(C_B)
C_A
Cbypass
DATA1
1
32
2
31
3
30
DATA2
4
29
VCC(I/O)
DATA0
CHIP_
SELECT_N
DATA1
DATA3
5
28
DATA2
CLOCK
6
27
DATA3
DATA4
7
26
8
25
DATA4
A2
IP4359CX4/LF
Cbypass
DATA5
ISP1507
9
DATA5
DATA6
24
DATA6
OTG
CONTROLLER
DATA7
10
23
11
22
12
21
13
20
14
19
15
18
DATA7
8 SHIELD
VCC(I/O)
CLOCK
9 SHIELD
PSW_N
CVBUS
REG3V3
Cbypass
XTAL1
Cfilter
69 of 81
© NXP B.V. 2008. All rights reserved.
XTAL(1)
CXTAL
XTAL2
CXTAL
16
NXT
STP
STP
DIR
DIR
REG1V8
RESET_N
17
GND (die pad)
Cbypass
Cfilter
004aab040
(1) Frequency is version dependent: ISP1507ABS: 19.2 MHz; ISP1507BBS: 26 MHz.
Fig 34. Using the ISP1507 with an OTG controller; internal charge pump is utilized and crystal is attached
ULPI HS USB OTG transceiver
VBUS
NXT
ISP1507A; ISP1507B
VCC
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
+5 V
IN
Cbypass
FAULT
Rpullup
VBUS
SWITCH
ON
Cbypass
DATA0
OUT
VCC(I/O)
1
2
USB
STANDARD-A
RECEPTACLE
3
4
NXP Semiconductors
ISP1507A_ISP1507B_1
Product data sheet
VCC(I/O)
VCC
RRREF
VBUS
RREF
D−
DM
D+
DP
FAULT
GND
1
32
2
31
3
30
4
29
5
28
6
27
7
26
Cbypass
Cbypass
DATA1
DATA2
VCC(I/O)
DATA0
CHIP_SELECT_N
DATA1
DATA3
DATA2
CLOCK
DATA3
CVBUS
Rev. 01 — 19 May 2008
5
6
SHIELD
SHIELD
ID
A1
CPGND
A2
C_B
B2
DESD
C_A
DATA5
HOST
DATA5 CONTROLLER
PSW_N
VBUS
Cbypass
Cfilter
XTAL1
70 of 81
© NXP B.V. 2008. All rights reserved.
XTAL2
(1)
24
10
23
11
22
12
21
13
20
14
19
18
15
16
GND (die pad)
C(XTAL)SQ
17
DATA6
DATA6
DATA7
DATA7
VCC(I/O)
CLOCK
NXT
NXT
STP
STP
DIR
DIR
REG1V8
RESET_N
Cbypass
RXTAL
Cfilter
004aab041
(1) Frequency is version dependent: ISP1507ABS: 19.2 MHz; ISP1507BBS: 26 MHz.
Fig 35. Using the ISP1507 with a standard USB host controller; external 5 V source with built-in FAULT and external square wave input on XTAL1
ULPI HS USB OTG transceiver
REG3V3
9
ISP1507A; ISP1507B
VCC
fi(XTAL1)
DATA4
ISP1507
IP4359CX4/LF
B1
25
8
DATA4
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
VCC(I/O)
Cbypass
Cbypass
1
2
3
USB
STANDARD-B
RECEPTACLE 4
Rev. 01 — 19 May 2008
5
6
VBUS
RVBUS
RRREF
D−
D+
GND
SHIELD
SHIELD
1
32
VCC(I/O)
2
31
RREF
3
30
DP
FAULT
A2
ID
IP4359CX4/LF
B1
B2
CPGND
DESD
C_B
C_A
VCC
VBUS
DATA2
VCC(I/O)
29
4
Cbypass
71 of 81
© NXP B.V. 2008. All rights reserved.
CXTAL
DATA2
28
5
CLOCK
DATA3
27
6
DATA4
DATA4
26
7
DATA5
DATA5
25
8
ISP1507
DATA6
9
24
10
23
11
22
12
21
13
20
14
19
15
18
PERIPHERAL
CONTROLLER
DATA6
DATA7
DATA7
VCC(I/O)
CLOCK
NXT
NXT
STP
STP
DIR
DIR
REG1V8
Cfilter
XTAL(1) XTAL2
DATA1
DATA3
RESET_N
16
GND (die pad)
CXTAL
(1) Frequency is version dependent: ISP1507ABS: 19.2 MHz; ISP1507BBS: 26 MHz.
Fig 36. Using the ISP1507 with a standard USB peripheral controller; external crystal
17
Cbypass
Cfilter
004aab042
ULPI HS USB OTG transceiver
XTAL1
DATA0
CHIP_SELECT_N
CVBUS
REG3V3
Cbypass
ISP1507A; ISP1507B
PSW_N
Cbypass
DATA1
DATA0
DM
A1
NXP Semiconductors
ISP1507A_ISP1507B_1
Product data sheet
VCC
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
17. Package outline
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
A
B
D
SOT617-1
terminal 1
index area
A
A1
E
c
detail X
C
e1
e
1/2 e
16
y
y1 C
v M C A B
w M C
b
9
L
17
8
e
e2
Eh
1/2 e
1
terminal 1
index area
24
32
25
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
5.1
4.9
3.25
2.95
5.1
4.9
3.25
2.95
0.5
3.5
3.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT617-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-18
Fig 37. Package outline SOT617-1 (HVQFN32)
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
72 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
73 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 38) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 60 and 61
Table 60.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 61.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 38.
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
74 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 38. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
19. Abbreviations
Table 62.
Abbreviations
Acronym
Description
ASIC
Application-Specific Integrated Circuit
ATX
Analog USB Transceiver
CD-RW
Compact Disc-ReWritable
EOP
End-Of-Packet
ESD
ElectroStatic Discharge
ESR
Effective Series Resistance
FS
Full-Speed
HBM
Human Body Model
HNP
Host Negotiation Protocol
HS
High-Speed
ID
Identification
IEC
International Electrotechnical Commission
LS
Low-Speed
NRZI
Non-Return-to-Zero Inverted
OTG
On-The-Go
PCB
Printed-Circuit Board
PHY
Physical Layer[1]
PID
Packet Identifier
PLD
Programmable Logic Device
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
75 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
Table 62.
Abbreviations …continued
Acronym
Description
PLL
Phase-Locked Loop
POR
Power-On Reset
RXCMD
Receive Command
SE0
Single-Ended Zero
SOF
Start-Of-Frame
SRP
Session Request Protocol
SYNC
Synchronous
TTL
Transistor-Transistor Logic
TXCMD
Transmit Command
USB
Universal Serial Bus
USB-IF
USB Implementers Forum
ULPI
UTMI+ Low Pin Interface
UTMI
USB 2.0 Transceiver Macrocell Interface
UTMI+
USB 2.0 Transceiver Macrocell Interface Plus
[1]
Physical layer containing the USB transceiver. The ISP1507 is a PHY.
20. References
[1]
Universal Serial Bus Specification Rev. 2.0
[2]
On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3
[3]
UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
[4]
UTMI+ Specification Rev. 1.0
[5]
USB 2.0 Transceiver Macrocell Interface (UTMI) Specification Ver. 1.05
[6]
Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)
(JESD22-A114D)
[7]
Interfacing to the ISP1507 (AN10080)
21. Revision history
Table 63.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
ISP1507A_ISP1507B_1
20080519
Product data sheet
-
-
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
76 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
22. Legal information
22.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
22.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
23. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
77 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended charge pump capacitor value .12
ULPI signal description . . . . . . . . . . . . . . . . . .15
Signal mapping during low-power mode . . . . .16
Signal mapping for 6-pin serial mode . . . . . . .17
Signal mapping for 3-pin serial mode . . . . . . .18
Operating states and their corresponding
resistor settings . . . . . . . . . . . . . . . . . . . . . . . .18
OTG_CTRL register power control bits . . . . . .25
TXCMD byte format . . . . . . . . . . . . . . . . . . . . .26
RXCMD byte format . . . . . . . . . . . . . . . . . . . . .26
LINESTATE[1:0] encoding for upstream
facing ports: peripheral . . . . . . . . . . . . . . . . . .27
LINESTATE[1:0] encoding for downstream
facing ports: host . . . . . . . . . . . . . . . . . . . . . . .28
Encoded VBUS voltage state . . . . . . . . . . . . . .28
VBUS indicators in RXCMD required for
typical applications . . . . . . . . . . . . . . . . . . . . . .29
Encoded USB event signals . . . . . . . . . . . . . .30
PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .34
Link decision times . . . . . . . . . . . . . . . . . . . . .35
Immediate register set overview . . . . . . . . . . .47
Extended register set overview . . . . . . . . . . . .47
VENDOR_ID_LOW - Vendor ID Low
register (address R = 00h) bit description . . . .48
VENDOR_ID_HIGH - Vendor ID High
register (address R = 01h) bit description . . . .48
PRODUCT_ID_LOW - Product ID Low
register (address R = 02h) bit description . . . .48
PRODUCT_ID_HIGH - Product ID High
register (address R = 03h) bit description . . . .48
FUNC_CTRL - Function Control register
(address R = 04h to 06h, W = 04h, S = 05h,
C = 06h) bit allocation . . . . . . . . . . . . . . . . . . .48
FUNC_CTRL - Function Control register
(address R = 04h to 06h, W = 04h, S = 05h,
C = 06h) bit description . . . . . . . . . . . . . . . . . .49
INTF_CTRL - Interface Control register
(address R = 07h to 09h, W = 07h, S = 08h,
C = 09h) bit allocation . . . . . . . . . . . . . . . . . . .50
INTF_CTRL - Interface Control register
(address R = 07h to 09h, W = 07h, S = 08h,
C = 09h) bit description . . . . . . . . . . . . . . . . . .50
OTG_CTRL - OTG Control register (address
R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .51
OTG_CTRL - OTG Control register (address
R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .51
USB_INTR_EN_R_E - USB Interrupt Enable
Rising Edge register (address R = 0Dh to 0Fh,
W = 0Dh, S = 0Eh, C = 0Fh) bit allocation . . . .52
USB_INTR_EN_R_E - USB Interrupt Enable
Rising Edge register (address R = 0Dh to 0Fh,
W = 0Dh, S = 0Eh, C = 0Fh) bit description . .52
Table 33. USB_INTR_EN_F_E - USB Interrupt
Enable Falling Edge register (address
R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 34. USB_INTR_EN_F_E - USB Interrupt Enable
Falling Edge register (address R = 10h to 12h,
W = 10h, S = 11h, C = 12h) bit description . . . 53
Table 35. USB_INTR_STAT - USB Interrupt Status
register (address R = 13h) bit allocation . . . . . 53
Table 36. USB_INTR_STAT - USB Interrupt Status
register (address R = 13h) bit description . . . . 53
Table 37. USB_INTR_L - USB Interrupt Latch register
(address R = 14h) bit allocation . . . . . . . . . . . 54
Table 38. USB_INTR_L - USB Interrupt Latch register
(address R = 14h) bit description . . . . . . . . . . 54
Table 39. DEBUG - Debug register (address R = 15h)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 40. DEBUG - Debug register (address R = 15h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 41. SCRATCH - Scratch register (address R =
16h to 18h, W = 16h, S = 17h, C = 18h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 42. PWR_CTRL - Power Control register
(address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,
C = 3Fh) bit allocation . . . . . . . . . . . . . . . . . . . 55
Table 43. PWR_CTRL - Power Control register
(address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,
C = 3Fh) bit description . . . . . . . . . . . . . . . . . . 55
Table 44. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 45. Recommended operating conditions . . . . . . . . 57
Table 46. Static characteristics: supply pins . . . . . . . . . . 58
Table 47. Static characteristics: digital pins . . . . . . . . . . 58
Table 48. Static characteristics: digital pin FAULT . . . . . 59
Table 49. Static characteristics: digital pin PSW_N . . . . 59
Table 50. Static characteristics: analog I/O pins
(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 51. Static characteristics: charge pump . . . . . . . . 61
Table 52. Static characteristics: VBUS comparators . . . . 61
Table 53. Static characteristics: VBUS resistors . . . . . . . . 62
Table 54. Static characteristics: ID detection circuit . . . . 62
Table 55. Static characteristics: resistor reference . . . . . 62
Table 56. Dynamic characteristics: reset and clock . . . . 64
Table 57. Dynamic characteristics: digital I/O pins . . . . . 65
Table 58. Dynamic characteristics: analog I/O pins
(DP and DM) . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 59. Recommended bill of materials . . . . . . . . . . . . 68
Table 60. SnPb eutectic process (from J-STD-020C) . . . 74
Table 61. Lead-free process (from J-STD-020C) . . . . . . 74
Table 62. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 63. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 76
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
78 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
25. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Fig 29.
Fig 30.
Fig 31.
Fig 32.
Fig 33.
Fig 34.
Fig 35.
Fig 36.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin configuration HVQFN32; top view . . . . . . . . . .5
External capacitors connection . . . . . . . . . . . . . .10
Charge pump capacitor . . . . . . . . . . . . . . . . . . . .12
Internal power-on reset timing . . . . . . . . . . . . . . .20
Power-up and reset sequence required before
the ULPI bus is ready for use. . . . . . . . . . . . . . . .22
Interface behavior with respect to RESET_N. . . .23
Entering and exiting 3-state in normal mode . . . .24
Entering and exiting 3-state in suspend mode. . .24
Single and back-to-back RXCMDs from the
ISP1507 to the link. . . . . . . . . . . . . . . . . . . . . . . .27
RXCMD A_VBUS_VLD indicator source . . . . . . .29
Example of register write, register read,
extended register write and extended
register read. . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
USB reset and high-speed detection
handshake (chirp) sequence . . . . . . . . . . . . . . . .33
Example of using the ISP1507 to transmit and
receive USB data . . . . . . . . . . . . . . . . . . . . . . . . .34
High-speed transmit-to-transmit packet timing. . .35
High-speed receive-to-transmit packet timing . . .36
Preamble sequence . . . . . . . . . . . . . . . . . . . . . . .37
Full-speed suspend and resume . . . . . . . . . . . . .38
High-speed suspend and resume . . . . . . . . . . . .40
Remote wake-up from low-power mode . . . . . . .42
Transmitting USB packets without automatic
SYNC and EOP generation . . . . . . . . . . . . . . . . .43
Example of transmit followed by receive in
6-pin serial mode . . . . . . . . . . . . . . . . . . . . . . . . .45
Example of transmit followed by receive in
3-pin serial mode . . . . . . . . . . . . . . . . . . . . . . . . .45
Human body ESD test model. . . . . . . . . . . . . . . .56
Charge pump supply current as a function of
VBUS output current . . . . . . . . . . . . . . . . . . . . . . .63
VBUS output voltage as a function of
VBUS output current . . . . . . . . . . . . . . . . . . . . . . .63
VBUS output voltage as a function of charge
pump supply voltage . . . . . . . . . . . . . . . . . . . . . .63
Charge pump supply current as a function of
temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Rise time and fall time . . . . . . . . . . . . . . . . . . . . .67
Timing of TX_DAT and TX_SE0 to DP and DM . .67
Timing of TX_ENABLE to DP and DM. . . . . . . . .67
Timing of DP and DM to RX_RCV, RX_DP and
RX_DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
ULPI interface timing . . . . . . . . . . . . . . . . . . . . . .67
Using the ISP1507 with an OTG controller;
internal charge pump is utilized and crystal is
attached . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Using the ISP1507 with a standard USB host
controller; external 5 V source with built-in
FAULT and external square wave input on
XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Using the ISP1507 with a standard USB
peripheral controller; external crystal. . . . . . . . . .71
Fig 37. Package outline SOT617-1 (HVQFN32) . . . . . . . 72
Fig 38. Temperature profiles for large and small
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
79 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
26. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.6.1
7.6.2
7.6.2.1
7.6.2.2
7.6.2.3
7.6.3
7.6.4
7.7
7.8
7.9
7.9.1
7.9.2
7.9.3
7.9.4
7.9.5
7.9.6
7.9.7
7.9.8
7.9.9
7.9.10
7.9.11
7.9.12
7.9.13
7.9.14
7.9.15
7.9.16
7.9.17
7.9.18
7.9.19
7.9.20
8
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 7
ULPI interface controller . . . . . . . . . . . . . . . . . . 7
USB data serializer and deserializer. . . . . . . . . 7
Hi-Speed USB (USB 2.0) ATX . . . . . . . . . . . . . 7
Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . 8
Crystal oscillator and PLL. . . . . . . . . . . . . . . . . 8
OTG module . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VBUS comparators. . . . . . . . . . . . . . . . . . . . . . . 9
VBUS valid comparator . . . . . . . . . . . . . . . . . . . 9
Session valid comparator . . . . . . . . . . . . . . . . . 9
Session end comparator. . . . . . . . . . . . . . . . . . 9
SRP charge and discharge resistors . . . . . . . . 9
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . 10
Band gap reference voltage . . . . . . . . . . . . . . 10
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 10
Detailed description of pins . . . . . . . . . . . . . . 10
DATA[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VCC(I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CPGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
C_A and C_B . . . . . . . . . . . . . . . . . . . . . . . . . 12
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PSW_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
REG3V3 and REG1V8 . . . . . . . . . . . . . . . . . . 13
XTAL1 and XTAL2. . . . . . . . . . . . . . . . . . . . . . 13
RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
NXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CHIP_SELECT_N. . . . . . . . . . . . . . . . . . . . . . 14
GND (die pad). . . . . . . . . . . . . . . . . . . . . . . . . 14
Modes of operation . . . . . . . . . . . . . . . . . . . . . 15
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.2
9
9.1
9.2
9.3
9.3.1
9.3.2
9.3.3
9.4
9.4.1
9.4.2
9.5
9.5.1
9.5.2
9.5.2.1
9.5.2.2
9.5.2.3
9.5.2.4
9.6
9.7
9.8
9.8.1
9.8.1.1
9.8.1.2
9.9
9.10
9.10.1
9.10.2
9.10.3
9.11
9.12
9.12.1
9.12.2
9.12.3
9.12.4
9.12.5
9.13
9.14
9.15
ULPI modes . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous mode . . . . . . . . . . . . . . . . . . . .
Low-power mode . . . . . . . . . . . . . . . . . . . . . .
6-pin full-speed or low-speed serial mode . . .
3-pin full-speed or low-speed serial mode . . .
USB and OTG state transitions . . . . . . . . . . .
Protocol description . . . . . . . . . . . . . . . . . . . .
ULPI references . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset (POR) . . . . . . . . . . . . . . . . .
Power-up, reset and bus idle sequence . . . . .
Interface protection. . . . . . . . . . . . . . . . . . . . .
Interface behavior with respect to RESET_N.
Interface behavior with respect to
CHIP_SELECT_N . . . . . . . . . . . . . . . . . . . . .
VBUS power and fault detection . . . . . . . . . . .
Driving 5 V on VBUS . . . . . . . . . . . . . . . . . . . .
Fault detection . . . . . . . . . . . . . . . . . . . . . . . .
TXCMD and RXCMD . . . . . . . . . . . . . . . . . . .
TXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linestate encoding . . . . . . . . . . . . . . . . . . . . .
VBUS state encoding . . . . . . . . . . . . . . . . . . . .
Using and selecting the VBUS state encoding.
RxEvent encoding . . . . . . . . . . . . . . . . . . . . .
Register read and write operations . . . . . . . .
USB reset and high-speed detection
handshake (chirp) . . . . . . . . . . . . . . . . . . . . .
USB packet transmit and receive . . . . . . . . . .
USB packet timing . . . . . . . . . . . . . . . . . . . . .
ISP1507 pipeline delays. . . . . . . . . . . . . . . . .
Allowed link decision time . . . . . . . . . . . . . . .
Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB suspend and resume . . . . . . . . . . . . . . .
Full-speed or low-speed host-initiated
suspend and resume . . . . . . . . . . . . . . . . . . .
High-speed suspend and resume . . . . . . . . .
Remote wake-up . . . . . . . . . . . . . . . . . . . . . .
No automatic SYNC and EOP generation
(optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-The-Go operations . . . . . . . . . . . . . . . . . .
OTG charge pump . . . . . . . . . . . . . . . . . . . . .
OTG comparators. . . . . . . . . . . . . . . . . . . . . .
Pull-up and pull-down resistors . . . . . . . . . . .
ID detection . . . . . . . . . . . . . . . . . . . . . . . . . .
VBUS charge and discharge resistors . . . . . . .
Serial modes . . . . . . . . . . . . . . . . . . . . . . . . .
Aborting transfers. . . . . . . . . . . . . . . . . . . . . .
Avoiding contention on the ULPI data bus . . .
15
15
16
17
17
18
20
20
20
20
22
23
23
25
25
25
25
25
26
27
28
29
30
31
31
34
34
34
34
36
37
37
38
41
42
43
44
44
44
44
44
44
46
46
continued >>
ISP1507A_ISP1507B_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 19 May 2008
80 of 81
ISP1507A; ISP1507B
NXP Semiconductors
ULPI HS USB OTG transceiver
10
Register map . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1
Immediate register set . . . . . . . . . . . . . . . . . .
10.1.1
Vendor ID and Product ID registers . . . . . . . .
10.1.1.1 VENDOR_ID_LOW register . . . . . . . . . . . . . .
10.1.1.2 VENDOR_ID_HIGH register. . . . . . . . . . . . . .
10.1.1.3 PRODUCT_ID_LOW register . . . . . . . . . . . . .
10.1.1.4 PRODUCT_ID_HIGH register . . . . . . . . . . . .
10.1.2
FUNC_CTRL register . . . . . . . . . . . . . . . . . . .
10.1.3
INTF_CTRL register . . . . . . . . . . . . . . . . . . . .
10.1.4
OTG_CTRL register . . . . . . . . . . . . . . . . . . . .
10.1.5
USB_INTR_EN_R_E register . . . . . . . . . . . . .
10.1.6
USB_INTR_EN_F_E register . . . . . . . . . . . . .
10.1.7
USB_INTR_STAT register. . . . . . . . . . . . . . . .
10.1.8
USB_INTR_L register . . . . . . . . . . . . . . . . . . .
10.1.9
DEBUG register . . . . . . . . . . . . . . . . . . . . . . .
10.1.10 SCRATCH register . . . . . . . . . . . . . . . . . . . . .
10.1.11 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.12 Access extended register set . . . . . . . . . . . . .
10.1.13 Vendor-specific registers . . . . . . . . . . . . . . . .
10.1.14 PWR_CTRL register . . . . . . . . . . . . . . . . . . . .
10.2
Extended register set . . . . . . . . . . . . . . . . . . .
11
ElectroStatic Discharge (ESD) . . . . . . . . . . . .
11.1
ESD protection . . . . . . . . . . . . . . . . . . . . . . . .
11.2
ESD test conditions . . . . . . . . . . . . . . . . . . . .
12
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .
13
Recommended operating conditions. . . . . . .
14
Static characteristics. . . . . . . . . . . . . . . . . . . .
15
Dynamic characteristics . . . . . . . . . . . . . . . . .
15.1
ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
Application information. . . . . . . . . . . . . . . . . .
17
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
18
Soldering of SMD packages . . . . . . . . . . . . . .
18.1
Introduction to soldering . . . . . . . . . . . . . . . . .
18.2
Wave and reflow soldering . . . . . . . . . . . . . . .
18.3
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . .
18.4
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . .
19
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .
20
References . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
Revision history . . . . . . . . . . . . . . . . . . . . . . . .
22
Legal information. . . . . . . . . . . . . . . . . . . . . . .
22.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
22.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
Contact information. . . . . . . . . . . . . . . . . . . . .
24
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
48
48
48
48
48
48
48
49
51
52
52
53
53
54
54
55
55
55
55
55
56
56
56
57
57
58
64
67
68
72
73
73
73
73
74
75
76
76
77
77
77
77
77
77
78
79
26
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 19 May 2008
Document identifier: ISP1507A_ISP1507B_1