WEDC EDI9LC644V1312BC 128kx32 ssram/1mx32 sdram Datasheet

EDI9LC644V
128Kx32 SSRAM/1Mx32 SDRAM
EXTERNAL MEMORY SOLUTION FOR TEXAS INSTRUMENTS TMS320C6000 DSP
FEATURES
DESCRIPTION
n Clock speeds:
The EDI9LC644VxxBC is a 3.3V, 128K x 32 Synchronous
Pipeline SRAM and a 1Mx32 Synchronous DRAM array constructed with one 128K x 32 SBSRAM and two 1Mx16
SDRAM die mounted on a multilayer laminate substrate. The
device is packaged in a 153 lead, 14mm by 22mm, BGA.
• SSRAM: 200, 166,150, and 133 MHz
• SDRAMs: 125 and 100 MHz
n
DSP Memory Solution
• Texas Instruments TMS320C6201
The EDI9LC644VxxBC provides a total memory solution for
the Texas Instr uments TMS320C6201 and the
TMS320C6701 DSPs
• Texas Instruments TMS320C6701
n
Packaging:
The Synchronous Pipeline SRAM is available with clock
speeds of 200, 166,150, and 133 MHz, allowing the user
to develop a fast external memory for the SSRAM interface port .
• 153 pin BGA, JEDEC MO-163
n
n
n
n
n
3.3V Operating supply voltage
Direct control interface to both the SSRAM and SDRAM
ports on the “C6x”
The SDRAM is available in clock speeds of 125 and 100
MHz, allowing the user to develop a fast external memory
for the SDRAM interface port .
Common address and databus
65% space savings vs. monolithic solution
Reduced system inductance and capacitance
FIG. 1
PIN CONFIGURATION
BOTTOM VIEW
P IN D ESCRIPTION
1
2
3
4
5
6
7
8
9
A
DQ19
DQ23
VCC
VSS
VSS
VSS
VCC
DQ24
DQ28
A
B
DQ18
DQ22
VCC
VSS
SDCE
VSS
VCC
DQ25
DQ29
Address Bus
Data Bus
B
SSCLK
SSRAM Clock
SSRAM Address Status Control
C
VCCQ
VCCQ
VCC
NC
VCC
VCCQ
VCCQ
C
SSADC
D
DQ17
DQ21
VCC
VSS
VSS
VSS
VCC
DQ26
DQ30
D
SSWE
SSRAM Write Enable
E
DQ16
DQ20
VCC
VSS
SDCLK
VSS
VCC
DQ27
DQ31
E
SSOE
SSRAM Output Enable
F
VCCQ
VCCQ
VCC
VSS
VSS
VSS
VCC
VCCQ
VCCQ
F
SDCLK
SDRAM Clock
G
NC
NC
NC
SDRAS SDCAS VSS
A2
A4
A5
G
SDRAS
SDRAM Row Address Strobe
H
NC
NC
A8
A1
A3
A10
H
SDCAS
SDRAM Column Address Strobe
J
K
L
A6
A7
A9
NC/A17 NC/A18 NC/A19
NC
SDWE SDA10
A0-16
DQ0-31
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
BWE2 BWE3
BWE0 BWE1
NC
NC
A0
A11
A12
J
NC
NC
A13
A14
K
NC
NC
A15
A16
L
M
VCCQ
VCCQ
VCC
NC
VCC
VCCQ
VCCQ
M
N
DQ12
DQ11
VCC
VSS
VSS
VSS
VCC
DQ4
DQ0
N
P
DQ13
DQ10
VCC
VSS
SSCLK
VSS
VCC
DQ5
DQ1
P
R
VCCQ
VCCQ
VCC
VSS
VSS
VSS
VCC
VCCQ
VCCQ
R
T
DQ14
DQ9
VCC SSADC SSWE
NC
VCC
DQ6
DQ2
T
U
DQ15
DQ8
VCC
NC
VCC
DQ7
DQ3
U
1
2
3
6
7
8
9
January 2002 Rev. 4
ECO# 14667
SSOE SSCE
4
5
1
SDWE
SDRAM Write Enable
SDA10
SDRAM Address 10/auto precharge
BWE0-3
SSRAM Byte Write Enables
SDRAM SDQM 0 - 3
SSCE
Chip Enable SSRAM Device
SDCE
Chip Enable SDRAM Device
VCC
Power Supply pins, 3.3V
VCCQ
Data Bus Power Supply pins,
3.3V (2.5V future)
VSS
Ground
NC
No Connect
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EDI9LC644V
FIG. 2
BLOCK DIAGRAM
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
2
EDI9LC644V
OUTPUT FUNCTIONAL DESCRIPTIONS
Symbol
Type
Signal
SSCLK
Input
Pulse
SSADS
SSOE
SSWE
Input
Pulse
Polarity
Function
Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
Active Low
When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define the operation
to be executed by the SSRAM.
Active Low
SSCE disable or enable SSRAM device operation.
SSCE
Input
Pulse
SDCLK
Input
Pulse
SDCE
Input
Pulse
Active Low
SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3.
SDRAS
SDCAS
SDWE
Input
Pulse
Active Low
When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define the
operation to be executed by the SDRAM.
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Address bus for SSRAM and SDRAM
A0 and A1 are the burst address inputs for the SSRAM
During a Bank Active command cycle, A0-9, SDA10 defines the row address (RA0-10) when sampled
at the rising clock edge.
A0-16,
SDA10
Input
Level
—
During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at
the rising clock edge. In addition to the row address, SDA10 is used to invoke Autoprecharge
operation at the end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and
A11 defines the bank to be precharged (low = bank A, high = bank B). If SDA10 is low,
autoprecharge is disabled.
During a Precharge command cycle, SDA 10 is used in conjunction with A11 to control which bank(s)
to precharge. If SDA10 is high, both bank A and Bank B will be precharged regardless of the state of
A11. If SDA10 is low, then A11 is used to define which bank to precharge.
DQ0-31
Input
Output
Level
—
Data Input/Output are multiplexed on the same pins.
BWE0-3
Input
Pulse
VCC, VSS
Supply
Power and ground for the input buffers and the core logic.
VCCQ
Supply
Data base power supply pins, 3.3V (2.5V future).
BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM.
BWE0 is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31.
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI9LC644V
RECOMMENDED DC OPERATING
ABSOLUTE MAXIMUM RATINGS
Voltage on Vcc Relative to Vss
CONDITIONS
-0.5V to +4.6V
Vin (DQx)
-0.5V to Vcc +0.5V
Storage Temperature (BGA)
(0°C ­ T A ­ 70°C;
-55°C to +125°C
Junction Temperature
+175°C
Short Circuit Output Current
100 mA
V CC = 3.3V -5% / +10%
Parameter
Min
Max
Units
VCC
VIH
VIL
ILI
3.135
2.0
-0.3
-10
3.6
VCC +0.3
0.8
10
V
V
V
µA
ILO
-10
10
µA
VOH
VOL
2.4
—
—
0.4
V
V
Supply Voltage1
Input High Voltage1,2
Input Low Voltage1,2
Input Leakage Current
0 - VIN - V c c
Output Leakage (Output Disabled)
0 - VIN - V c c
Output High (IOH = -4mA)1
Output Low (IOL = 8mA)1
*Stress greater than those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions greater
than those indicated in operational sections of this specifications is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
UNLESS OTHERWISE NOTED )
Symbol
NOTES:
1. All voltages referenced to Vss (GND).
2. Overshoot: VIH +6.0V for t - tKC/2
Underershoot: VIL -2.0V for t - tKC/2
£
³
DC ELECTRIC AL CHARACTERISTICS
Description
Conditions
Symbol
Power Supply Current:
Operating (1,2,3)
SSRAM Active / DRAM Auto Refresh
ICC1
Power Supply Current
Operating1,2,3
SSRAM Active / DRAM Idle
ICC2
Power Supply Current
Operating1,2,3
SDRAM Active / SSRAM Idle
ICC3
CMOS Standby
TTL Standby
£
SSCE and SDCE VCC -0.2V,
All other inputs at VSS +0.2 VIN or
VIN VCC -0.2V, Clk frequency = 0
SSCE and SDCE VIH min
All other inputs at VIL max VIN or
VIN VCC -0.2V, Clk frequency = 0
£
Max
400
450
500
TBD
300
350
400
TBD
220
235
255
20.0
550
580
625
TBD
450
480
525
TBD
240
250
280
40.0
Units
mA
mA
mA
mA
ISB2
£
£
Typ
133MHz
150MHz
166MHz
200MHz
133MHz
150MHz
166MHz
200MHz
83MHz
100MHz
125MHz
ISB1
£
£
Frequency
30.0
55.0
mA
Auto Refresh
ICC5
190
250
mA
NOTES:
1. ICC (operating) is specified with no output current. ICC (operating) increases with faster cycle times and greater output loading.
2. “Device idle” means device is deselected (CE VIH) Clock is running at max frequency and Addresses are switching each cycle.
3. Typical values are measured at 3.3V, 25°C. ICC (operating) is specified at specified frequency.
³
BGA C APACITANCE
Description
Conditions
Symbol
Typ
Max
Units
Address Input Capacitance 1
TA = 25°C; f = 1MHz
CI
5
8
pF
Input/Output Capacitance (DQ)1
TA = 25°C; f = 1MHz
CO
8
10
pF
Control Input Capacitance1
TA = 25°C; f = 1MHz
CA
5
8
pF
Clock Input Capacitance 1
TA = 25°C; f = 1MHz
C CK
4
6
pF
NOTE:
1. This parameter is sampled.
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4
EDI9LC644V
SSRAM AC CHARACTERISTICS (EDI9LC644V)
Symbol
Parameter
200MHz
Min
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Clock to output valid
Clock to output invalid
Clock to output on Low-Z
Clock to output in High-Z
Output Enable to output valid
Output Enable to output in Low-Z
Output Enable to output in High-Z
Address, Control, Data-in Setup Time to Clock
Address, Control, Data-in Hold Time to Clock
t KHKH
tKLKH
tKHKL
tKHQV
tKHQX
t KQLZ
tKQHZ
tOELQV
tOELZ
t OEHZ
tS
tH
Max
5
1.6
1.6
166MHz
Min
Max
150MHz
Min
6
2.4
2.4
7
2.6
2.6
2.5
1.5
0
1.5
3
2.5
0
3.5
1.5
0
1.5
133MHz
Min
0
3.8
3.8
0
3.5
1.5
0.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.0
1.5
0
1.5
4.0
4.0
0
3.5
1.5
0.5
Max
8
2.8
2.8
3.8
1.5
0
1.5
3.5
3.5
3.0
1.5
0.5
Max
3.8
1.5
0.5
SSRAM OPERATION TRUTH TABLE
Operation
Address Used
SSCE
SSADS
SSWE
SSOE
DQ
None
External
External
External
Current
Current
Current
Current
Current
Current
H
L
L
L
X
X
H
H
X
H
L
L
L
L
H
H
H
H
H
H
X
L
H
H
H
H
H
H
L
L
X
X
L
H
L
H
L
H
X
X
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Deselected Cycle, Power Down
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Note:
1. X means “don’t care”, H means logic HIGH. L means logic LOW.
2. All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK.
3. Suspending burst generates wait cycle
4. For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and staying
HIGH though out the input data hold time.
5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
SSRAM PARTIAL TRUTH TABLE
Function
SSWE
BWE0
BWE1
BWE2
READ
H
X
X
X
BWE3
X
WRITE one Byte (DQ0-7)
L
L
H
H
H
WRITE all Bytes
L
L
L
L
L
5
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EDI9LC644V
FIG. 3
SSRAM READ TIMING
FIG. 4
SSRAM WRITE TIMING
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
6
EDI9LC644V
SDRAM AC CHARACTERISTICS
Symbol
Parameter
Clock Cycle Time1
CL = 3
CL = 2
Clock to valid Output delay 1,2
Output Data Hold Time2
Clock HIGH Pulse Width 3
Clock LOW Pulse Width 3
Input Setup Time 3
Input Hold Time 3
CLK to Output Low-Z 2
CLK to Output High-Z
Row Active to Row Active Delay 4
RAS to CAS Delay 4
Row Precharge Time 4
Row Active Time 4
Row Cycle Time - Operation 4
Row Cycle Time - Auto Refresh 4,8
Last Data in to New Column Address Delay 5
Last Data in to Row Precharge 5
Last Data in to Burst Stop5
Column Address to Column Address Delay 6
Number of Valid Output Data7
t CC
t CC
t SAC
tOH
tCH
t CL
tSS
t SH
t SLZ
tSHZ
tRRD
tRCD
t RP
t RAS
tRC
t RFC
t CDL
t RDL
t BDL
tCCD
125MHz
100MHz
83MHz
Min
Max
Min
Max
Min
Max
Units
8
10
1000
1000
6
10
12
1000
1000
7
12
15
1000
1000
8
ns
3
3
3
2
1
2
3
3
3
2
1
2
7
20
20
20
50
70
70
1
1
1
1.5
2
1
10,000
3
3
3
2
1
2
7
20
20
20
50
80
80
1
1
1
1.5
2
2
10,000
8
24
24
24
60
90
90
1
1
1
1.5
2
1
10,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
CLK
CLK
ea
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If tRISE of tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter.
4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the
next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
8. A new command may be given tRFC after self-refresh exit.
7
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EDI9LC644V
CLOCK FREQUENCY AND LATENCY PARAMETERS - 125MHZ SDRAM
(U NIT =
Frequency
CAS
t
RC
t
NUMBER OF CLOCK )
RAS
t
RP
t
RRD
t
RCD
t
CCD
t
CDL
t
RDL
Latency
70ns
50ns
20ns
20ns
20ns
10ns
10ns
10ns
125MHz (8.0ns)
3
9
6
3
2
3
1
1
1
100MHz (10.0ns)
3
7
5
2
2
2
1
1
1
83MHz (12.0ns)
2
6
4
2
2
2
1
1
1
CLOCK FREQUENCY AND LATENCY PARAMETERS - 100MHZ SDRAM
(U NIT =
Frequency
CAS
Latency
t
RC
t
70ns
NUMBER OF CLOCK )
RAS
t
50ns
RP
t
20ns
RRD
t
20ns
RCD
t
20ns
CCD
t
10ns
CDL
t
10ns
RDL
10ns
100MHz (12.0ns)
3
7
5
2
2
2
1
1
1
83MHz (12.0ns)
2
6
5
2
2
2
1
1
1
REFRESH CYCLE PARAMETERS
-10
Parameter
Refresh Period 1,2
-12
Symbol
Min
Max
Min
Max
Units
tREF
—
64
—
64
ms
NOTES:
1. 4096 cycles
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device.
SDRAM COMMAND TRUTH TABLE
Function
SDCE
SDRAS
SDCAS
SDWE
BWE
SDA10
A 11
Notes
A 9-0
Mode Register Set
L
L
L
L
X
Auto Refresh (CBR)
L
L
L
H
X
X
OP CODE
Precharge
Single Bank
L
L
H
L
X
BA
L
Precharge all Banks
L
L
H
L
X
X
H
X
2
Bank Activate
L
L
H
H
X
BA
Row Address
2
Write
L
H
L
L
X
BA
L
2
Write with Auto Precharge
L
H
L
L
X
BA
H
2
Read
L
H
L
L
X
BA
L
2
Read with Auto Precharge
L
H
L
H
X
BA
H
2
Burst Termination
L
H
H
L
X
X
X
3
No Operation
L
H
H
H
X
X
X
Device Deselect
H
X
X
X
X
X
X
Data Write/Output Disable
X
X
X
X
L
X
X
4
Data Mask/Output Disable
X
X
X
X
H
X
X
4
NOTES:
1. All of the SDRAM operations are defined by states of SDCE, SDWE, SDRAS, SDCAS, and BWE0-3 at the positive rising edge of the clock.
2. Bank Select (BA), if A11 = 0 then bank A is selected, if BA = 1 then bank B is selected.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. The BWE has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE goes high at a clock timing the data outputs are
disabled and become high impedance after a two clock delay. BWE also provides a data mask function for Write cycles. When it activates, the Write
operation at the clock is prohibited (zero clock latency).
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
8
EDI9LC644V
SDRAM CURRENT STATE TRUTH TABLE
Command
Current State
SDCE
SDRAS
SDCAS
SDWE
Action
A 11
SDA 10-A 0
Notes
Description
(BA)
Idle
Row Active
Read
Write
L
L
L
L
Mode Register Set
Set the Mode Register
1
L
L
L
H
X
OP Code
X
Auto or Self Refresh
Start Auto
1
L
L
H
L
X
X
Precharge
No Operation
L
L
H
H
BA
Row Address
Bank Activate
Activate the specified bank and row
L
H
L
L
BA
Column
Write w/o Precharge
ILLEGAL
2
L
H
L
H
BA
Column
Read w/o Precharge
ILLEGAL
1
L
H
H
L
X
X
Burst Termination
No Operation
1
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
Device Deselect
No Operation
L
L
L
L
L
L
L
H
L
L
H
L
X
L
L
H
H
BA
L
H
L
L
BA
L
H
L
H
BA
L
H
H
L
X
X
X
OP Code
Mode Register Set
ILLEGAL
Auto or Self Refresh
ILLEGAL
X
Precharge
Precharge
3
Row Address
Bank Activate
ILLEGAL
1
Column
Write
Start Write; Determine if Auto Precharge
4,5
Column
Read
Start Read; Determine if Auto Precharge
4,5
Burst Termination
No Operation
X
X
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
Terminate Burst; Start the Precharge
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
L
H
L
L
BA
Column
Write
Terminate Burst; Start the Write cycle
5,6
L
H
L
H
BA
Column
Read
Terminate Burst; Start a new Read cycle
5,6
L
H
H
L
X
X
Burst Termination
Terminate the Burst
OP Code
X
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
Terminate Burst; Start the Precharge
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
L
H
L
L
BA
Column
Write
Terminate Burst; Start a new Write cycle
5,6
L
H
L
H
BA
Column
Read
Terminate Burst; Start the Read cycle
5,6
L
H
H
L
X
X
Burst Termination
Terminate the Burst
OP Code
X
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
Auto or Self Refresh
ILLEGAL
OP Code
X
L
L
H
L
X
X
Precharge
ILLEGAL
2
Read with
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
Auto Precharge
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
ILLEGAL
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
9
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EDI9LC644V
SDRAM CURRENT STATE TRUTH TABLE (CONT.)
Command
Current State
SDCE
SDRAS
SDCAS
SDWE
Action
A 11
SDA 10-A 0
Notes
Description
(BA)
L
L
L
L
L
L
L
H
OP Code
X
X
Mode Register Set
ILLEGAL
Auto or Self Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
2
Write with
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
Auto Precharge
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
ILLEGAL
Precharging
Row Activating
Write Recovering
Write Recovering
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
No Operation; Bank(s) idle after tRP
OP Code
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
L
H
L
L
BA
Column
Write w/o Precharge
ILLEGAL
2
L
H
L
H
BA
Column
Read w/o Precharge
ILLEGAL
2
L
H
H
L
X
X
Burst Termination
No Operation; Bank(s) idle after tRP
L
H
H
H
X
X
No Operation
No Operation; Bank(s) idle after tRP
H
X
X
X
X
X
Device Deselect
No Operation; Bank(s) idle after tRP
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
2
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
L
H
L
L
BA
Column
Write
ILLEGAL
2
L
H
L
H
BA
Column
Read
ILLEGAL
2
L
H
H
L
X
X
Burst Termination
No Operation; Row active after tRCD
OP Code
X
L
H
H
H
X
X
No Operation
No Operation; Row active after tRCD
H
X
X
X
X
X
Device Deselect
No Operation; Row active after tRCD
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
2
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
OP Code
L
H
L
L
BA
Column
Write
Start Write; Determine if Auto Precharge
6
L
H
L
H
BA
Column
Read
Start Read; Determine if Auto Precharge
6
L
H
H
L
X
X
Burst Termination
No Operation; Row active after tDPL
L
H
H
H
X
X
No Operation
No Operation; Row active after tDPL
H
X
X
X
X
X
Device Deselect
No Operation; Row active after tDPL
Mode Register Set
ILLEGAL
X
Auto orSelf Refresh
ILLEGAL
L
L
L
L
L
L
L
H
OP Code
L
L
H
L
X
X
Precharge
ILLEGAL
2
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
X
with Auto
L
H
L
L
BA
Column
Write
ILLEGAL
2,6
Precharge
L
H
L
H
BA
Column
Read
ILLEGAL
2,6
L
H
H
L
X
X
Burst Termination
No Operation; Precharge after tDPL
L
H
H
H
X
X
No Operation
No Operation; Precharge after tDPL
H
X
X
X
X
X
Device Deselect
No Operation; Precharge after tDPL
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
10
EDI9LC644V
SDRAM CURRENT STATE TRUTH TABLE (CONT.)
Command
Current State
SDWE
Action
SDCE
SDRAS
SDCAS
A 11
L
L
L
L
L
L
L
H
L
L
H
L
X
L
L
H
H
BA
L
H
L
L
BA
Column
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
No Operation; Idle after tRC
SDA 10-A 0
Notes
Description
(BA)
Refreshing
OP Code
Mode Register Set
ILLEGAL
Auto or Self Refresh
ILLEGAL
X
Precharge
ILLEGAL
Row Address
Bank Activate
ILLEGAL
Write
ILLEGAL
X
X
L
H
H
H
X
X
No Operation
No Operation; Idle after tRC
H
X
X
X
X
X
Device Deselect
No Operation; Idle after tRC
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
Auto or Self Refresh
ILLEGAL
ILLEGAL
OP Code
X
L
L
H
L
X
X
Precharge
Mode Register
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
Accessing
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
ILLEGAL
L
H
H
H
X
X
No Operation
No Operation; Idle after two clock cycles
H
X
X
X
X
X
Device Deselect
No Operation; Idle after two clock cycles
NOTES:
1. Both Banks must be idle otherwise it is an illegal action.
2. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the
Current State then the action may be legal depending on the state of that bank.
3. The minimum and maximum Active time (tRAS) must be satisfied.
4. The RAS to CAS Delay (tRCD) must occur before the command is given.
5. Address SDA10 is used to determine if the Auto Precharge function is activated.
6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank
delay time (tRRD) is not satisfied.
11
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EDI9LC644V
SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE)
@ CAS LATENCY = 3, BURST LENGTH = 1
FIG. 5
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12
EDI9LC644V
FIG. 6
SDRAM POWER UP SEQUENCE
13
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EDI9LC644V
FIG. 7
SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
NOTES:
1. Minimum row cycle times are required to complete internal DRAM operation.
2 Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will
be Hi-Z (tSHZ) after the clock.
3. Access time from Row active command. tCC *(tRCD + CAS Latency - 1) + tSAC .
4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
14
EDI9LC644V
FIG. 8
SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
NOTES:
1. To write data before burst read ends. BWE should be asserted three cycle prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written.
3. BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge
cycle will be masked internally.
15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI9LC644V
FIG. 9
SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
NOTES:
1. SDCE can be “don’t care” when SDRAS, SDCAS and SDWE are high at the clock going high edge.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
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16
EDI9LC644V
FIG. 10
SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
Notes:
1. To interrupt burst write by Row precharge, BWE should be asserted to mask invalid input data.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
17
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI9LC644V
FIG. 11
SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
NOTES:
1. tCDL should be met to complete write.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
18
EDI9LC644V
FIG. 12
SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH
=4
NOTES:
1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2 and BRSW mode)
19
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI9LC644V
SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST
STOP @ BURST LENGTH = FULL PAGE
FIG. 13
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. About the valid DQs after burst stop, it is the same as the case of SDRAS interrupt. Both cases are illustrated in the above timing diagram. See the label
1, 2 on each of them. But at burst write, burst stop and SDRAS interrupt should be compared carefully. Refer to the timing diagram of “Full page write
burst stop cycle”.
3. Burst stop is valid at every burst length.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
20
EDI9LC644V
SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST
STOP @ BURST LENGTH = FULL PAGE
FIG. 14
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL.
BWE at write interrupt by precharge command is needed to prevent invalid write.
BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge
cycle will be masked internally.
3. Burst stop is valid at every burst length.
21
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EDI9LC644V
FIG. 15
SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2
NOTES:
1. BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at Write is fixed to “1” regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the
burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
22
EDI9LC644V
FIG. 16
SDRAM AUTO REFRESH CYCLE
SDRAM MODE REGISTER SET CYCLE
HIGH
*Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycle.
NOTES:
MODE REGISTER SET CYCLE
1. SDCE, SDRAS, SDCAS & SDWE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new SDRAS activation.
7. Please refer to Mode Register Set table.
23
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI9LC644V
153 LEAD BGA (17 X 9 BALL ARRAY)
PACKAGE DESCRIPTION:
JEDEC MO-163
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
Note:
Ball attach pad for above BGA is 480 microns, in diameter. Pad is solder mask defined.
ORDERING INFORMATION
Part Number
SSRAM Access
SDRAM Access
EDI9LC644V2012BC
200MHz
125MHz
EDI9LC644V2010BC
200MHz
100MHz
EDI9LC644V1612BC
166MHz
125MHz
EDI9LC644V1610BC
166MHz
100MHz
EDI9LC644V1512BC
150MHz
125MHz
EDI9LC644V1510BC
150MHz
100MHz
EDI9LC644V1312BC
133MHz
125MHz
EDI9LC644V1310BC
133MHz
100MHz
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
24
EDI9LC644V
FIG. 17
INTERFACING THE TEXAS INSTRUMENTS TMS320C6 X WITH
THE ED9LC644V (128K X 32 SSRAM/1M X 32 SDRAM)
Address Bus
EA2-21
EA2 A0
EA3 A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
Texas Instruments
TMS320C6x
DSP
SSWE\
CE2\
SSOE\
SSADS\
SSCLK
BE0\
BE1\
BE2\
BE3\
Data Bus
ED0-31
SDA10
CE0\
SDRAS\
SDCAS\
SDWE\
SDCLK
25
EDI9LC644V
128K x 32 SSRAM
1M x 32 SDRAM
DQ0-7
DQ8-15
DQ16-23
DQ24-31
SSWE\
SSCE\
SSOE\
SSADC\
SSCLK
SSRAM
Control
BWE0\
BWE1\
BWE2\
BWE3\
Shared
Controls
SDA10
SDCE\
SDRAS\
SDCAS\
SDWE\
SDCLK
SDRAM
Control
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com