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Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. HD74LV245A Octal Bus Transceivers with 3-state Outputs REJ03D0329–0300Z (Previous ADE-205-247A (Z)) Rev.3.00 Jun. 24, 2004 Description The HD74LV245A has eight buffers with three-state outputs in a 20-pin package. When DIR is high, data is transferred from the A inputs to the B outputs, and when DIR is low, data is transferred from the B inputs to the A outputs. The A and B buses are separated by making the enable input (OE) high level. Low-voltage operation is suitable for battery-powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • VCC = 2.0 V to 5.5 V operation • All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) • All outputs VO (Max.) = 5.5 V (@VCC = 0 V) • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) • Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V) Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV245AFPEL HD74LV245ARPEL HD74LV245ATELL SOP–20 pin (JEITA) SOP–20 pin (JEDEC) TSSOP–20 pin FP–20DAV FP–20DBV TTP–20DAV FP RP T EL (2,000 pcs/reel) EL (1,000 pcs/reel) ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs OE DIR Operation L L H L H X B data to A bus A data to B bus Isolation Note: H: High level L: Low level X: Immaterial Rev.3.00 Jun. 24, 2004 page 1 of 9 HD74LV245A Pin Arrangement DIR 1 20 VCC A1 2 19 OE A2 3 18 B1 A3 4 17 B2 A4 5 16 B3 A5 6 15 B4 A6 7 14 B5 A7 8 13 B6 A8 9 12 B7 GND 10 11 B8 (Top view) Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range Input voltage range*1 Output voltage range*1, *2 VCC VI VO V V V Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25°C (in still air)*3 IIK IOK IO –0.5 to 7.0 –0.5 to 7.0 –0.5 to VCC + 0.5 –0.5 to 7.0 –20 ±50 ±35 ±70 Storage temperature Tstg ICC or IGND PT 835 757 –65 to 150 mA mA mA mA mW Conditions Output: H or L VCC: OFF or Output: Z VI < 0 VO < 0 or VO > VCC VO = 0 to VCC SOP TSSOP °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded even if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The data above are measured by ∆VBE method mounting on glass epoxy board (40 × 40 × 1.6 mm) with 10% of wiring density. Rev.3.00 Jun. 24, 2004 page 2 of 9 HD74LV245A Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage range VCC Input voltage range Output voltage range VI VO IOH 5.5 5.5 VCC 5.5 –50 –2 –8 –16 50 2 8 16 200 100 20 V V V Output current 2.0 0 0 0 — — — — — — — — 0 0 0 –40 85 °C IOL Input transition rise or fall rate ∆t /∆v Operating free-air temperature Ta Conditions Output: H or L High impedance state VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V µA mA µA mA ns/V Note: Unused or floating inputs must be held high or low. Logic Diagram DIR 1 19 A1 2 18 Other seven channels Rev.3.00 Jun. 24, 2004 page 3 of 9 OE B1 HD74LV245A DC Electrical Characteristics Ta = –40 to 85°C 1 Item Symbol VCC (V)* Min Typ Max Unit Input voltage VIH 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 — — — — VCC –0.1 2.0 2.48 3.8 — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 — — — — 0.1 0.4 0.44 0.55 ±1 ±5 V Input current Off-state output current IIN IOZ*2 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 5.5 Quiescent supply current ICC 5.5 — — Output leakage current IOFF 0 — Input capacitance Output capacitance CIN CO 3.3 3.3 — — VIL Output voltage VOH VOL Test Conditions µA µA IOH = –50 µA IOH = –2 mA IOH = –8 mA IOH = –16 mA IOL = 50 µA IOL = 2 mA IOL = 8 mA IOL = 16 mA VIN = 5.5 V or GND VO = VCC or GND 20 µA VIN = VCC or GND, IO = 0 — 5 µA VI or VO = 0 V to 5.5 V 3.0 5.5 — — pF pF VI = VCC or GND VO = VCC or GND V Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. 2. For I/O ports, the parameter IOZ includes the input leakage current. Rev.3.00 Jun. 24, 2004 page 4 of 9 HD74LV245A Switching Characteristics VCC = 2.5 ± 0.2 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Propagation delay time tPLH tPHL tZH tZL Disable time tHZ tLZ 8.3 11.2 11.8 14.1 11.8 17.6 13.0 15.9 19.9 22.7 18.1 23.1 1.0 1.0 1.0 1.0 1.0 1.0 15.0 18.0 22.0 26.0 20.0 25.0 ns Enable time — — — — — — ns ns Test Conditions FROM (Input) TO (Output) CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF A or B B or A OE A or B OE A or B VCC = 3.3 ± 0.3 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Propagation delay time tPLH tPHL tZH tZL Disable time tHZ tLZ 5.9 7.9 8.2 9.9 9.6 13.9 8.4 11.9 13.2 16.7 16.5 19.8 1.0 1.0 1.0 1.0 1.0 1.0 10.0 13.5 15.5 19.0 19.5 22.0 ns Enable time — — — — — — ns ns Test Conditions FROM (Input) TO (Output) CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF A or B B or A OE A or B OE A or B VCC = 5.0 ± 0.5 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Propagation delay time tPLH tPHL tZH tZL Disable time tHZ tLZ 4.3 5.6 5.7 7.0 7.8 10.9 5.5 7.5 8.5 10.6 12.8 14.7 1.0 1.0 1.0 1.0 1.0 1.0 6.5 8.5 10.0 12.0 14.2 16.0 ns Enable time — — — — — — ns ns Test Conditions FROM (Input) TO (Output) CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF A or B B or A OE A or B OE A or B Output-skew Characteristics CL = 50 pF Ta = 25°C Ta = –40 to 85°C Item Symbol VCC (V) Min Max Min Max Unit Output skew tsk (O) 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 — — — 2.0 1.5 1.0 — — — 2.0 1.5 1.0 ns Note: Skew between any outputs of the same package switching in the same direction. This parameter is warranted but not production tested. Rev.3.00 Jun. 24, 2004 page 5 of 9 HD74LV245A Operating Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Test Conditions Power dissipation capacitance CPD 3.3 5.0 — — 20.0 25.0 — — pF f = 10 MHz Noise Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Quiet output, maximum dynamic VOL VOL (P) 3.3 — 0.5 0.8 V Quiet output, minimum dynamic VOL VOL (V) 3.3 — –0.4 –0.8 V Quiet output, minimum dynamic VOH VOH (V) 3.3 — 2.9 — V High-level dynamic input voltage VIH (D) 3.3 2.31 — — V Low level dynamic input voltage VIL (D) 3.3 — — 0.99 V Test Conditions Test Circuit VCC VCC Input Pulse generator Zout = 50 Ω See Function Table OE Output A1 S1 1 kΩ S2 B1 OPEN GND CL = 15 or 50 pF VCC DIR Notes : 1. C L includes the probe and jig capacitance. 2. A2−B2 to A8−B8 are identical to above load circuit. 3. S1 : Input−Output change switch. Rev.3.00 Jun. 24, 2004 page 6 of 9 TEST t PLH /tPHL S2 OPEN t ZH/tHZ t ZL /tLZ GND VCC HD74LV245A • Waveform − 1 tr tf 90% 50% VCC Input 10% VCC 90% 50% VCC 10% t PHL t PLH 0V VOH In phase output 50% VCC 50% VCC VOL • Wareform − 2 OE tf tr 90% 50% VCC 10% t ZL 10% 0V t LZ VCC Waveform − A 50% VCC t ZH Waveform − B VCC 90% 50% VCC VOL + 0.3 V t HZ 50% VCC VOH − 0.3 V VOL VOH 0V Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns 2. Waveform−A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform−B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.3.00 Jun. 24, 2004 page 7 of 9 HD74LV245A Package Dimensions As of January, 2002 Unit: mm 12.6 13 Max 11 1 10 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0˚ – 8˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 20 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Pd plating FP–20DAV — Conforms 0.31 g As of January, 2003 Unit: mm 12.8 13.2 Max 11 1 10 1.27 *0.40 ± 0.06 0.20 ± 0.10 0.935 Max *0.25 ± 0.05 2.65 Max 7.50 20 0.25 10.40 +– 0.40 1.45 0˚ – 8˚ 0.57 0.70 +– 0.30 0.15 0.12 M *Ni/Pd/Au plating Rev.3.00 Jun. 24, 2004 page 8 of 9 Package Code JEDEC JEITA Mass (reference value) FP-20DBV Conforms — 0.52 g HD74LV245A As of January, 2002 Unit: mm 6.50 6.80 Max 11 1 10 4.40 20 0.65 *0.20 ± 0.05 1.0 0.13 M 6.40 ± 0.20 *Pd plating Rev.3.00 Jun. 24, 2004 page 9 of 9 0.07 +0.03 –0.04 0.10 *0.15 ± 0.05 1.10 Max 0.65 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP–20DAV — — 0.07 g Sales Strategic Planning Div. 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