ICST ICS840021AGILFT Femtoclocksâ ¢ crystal-to lvcmos/lvttl frequency synthesizer Datasheet

ICS840021I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS840021I is a Gigabit Ethernet Clock
Generator and a member of the HiPerClocksTM
HiPerClockS™ family of high performance devices from ICS. The
ICS840021I uses a 25MHz crystal to synthesize
125MHz. The ICS840021I has excellent phase
jitter performance, over the 1.875MHz – 20MHz integration
range. The ICS840021I is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
• 1 LVCMOS/LVTTL output, 15Ω output impedence
ICS
• Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
• Output frequency: 125MHz
• VCO range: 560MHz to 680MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.48ps (typical) (3.3V)
Offset
Noise Power
100Hz ............... -97.8 dBc/Hz
1kHz .............. -124.6 dBc/Hz
10kHz .............. -132.5 dBc/Hz
100kHz .............. -131.1 dBc/Hz
• Voltage supply modes:
VDD/VDDA = 3.3V
VDD/VDDA = 2.5V
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
OE
25MHz
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
Q0
÷5
VDDA
OE
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
VDD
Q0
GND
nc
ICS840021I
÷25
(fixed)
840021AGI
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
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1
REV. A MAY 19, 2005
ICS840021I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
VDDA
Power
Type
2
OE
Input
5
XTAL_OUT,
XTAL_IN
nc
Unused
6
GND
Power
7
Q0
Output
8
VDD
Power
3, 4
Input
Description
Pullup
Analog supply pin.
Output enable pin. When HIGH, Q0 output is enabled.
When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
No connect.
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
15Ω output impedence.
Core supply pin.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
VDD, VDDA = 3.465V
Minimum
Typical
Maximum
Units
4
pF
7
pF
CPD
Power Dissipation Capacitance
7
pF
RPULLUP
Input Pullup Resistor
51
kΩ
ROUT
Output Impedance
15
Ω
VDD, VDDA = 2.625V
TABLE 3. CONTROL FUNCTION TABLE
Control Inputs
Output
OE
Q0
0
Hi-Z
1
Active
840021AGI
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REV. A MAY 19, 2005
ICS840021I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
101.7°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
3.135
3.3
VDDA
Analog Supply Voltage
3.465
V
IDD
Power Supply Current
65
mA
IDDA
Analog Supply Current
10
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
Test Conditions
2.375
2.5
2.625
V
2.375
2.5
VDDA
Analog Supply Voltage
2.625
V
IDD
Power Supply Current
60
mA
IDDA
Analog Supply Current
10
mA
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
VIH
VIL
Parameter
Input High Voltage
Input Low Voltage
Test Conditions
Minimum
Maximum
Units
VDD = 3.3V
2
Typical
VDD + 0.3
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
5
µA
IIH
Input High Current
OE
VDD = VIN = 3.465V or 2.625V
IIL
Input Low Current
OE
VDD = 3.465V or 2.625V, VIN = 0V
-150
µA
VOH
Output High Voltage; NOTE 1
VDD = 3.465V
2.6
V
VDD = 2.625V
1. 8
VOL
Output Low Voltage; NOTE 1
VDD = 3.465V or 2.625V
V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section,
"Output Load Test Circuit" diagrams.
840021AGI
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REV. A MAY 19, 2005
ICS840021I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Ω
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
Drive Level
1
mW
Maximum
Units
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
RMS Phase Jitter
(Random); NOTE 1
Output Rise/Fall Time
tjit(Ø)
tR / tF
Test Conditions
Minimum
Integration Range: 1.875MHz to 20MHz
20% to 80%
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plot.
Typical
125
MHz
0.48
ps
200
500
ps
48
52
%
Maximum
Units
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
RMS Phase Jitter
(Random); NOTE 1
Output Rise/Fall Time
tjit(Ø)
tR / tF
Test Conditions
Integration Range: 1.875MHz to 20MHz
20% to 80%
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plot.
840021AGI
Minimum
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4
Typical
125
MHz
0.50
ps
250
550
ps
48
52
%
REV. A MAY 19, 2005
ICS840021I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 125MHZ (3.3V OR 2.5V)
➤
0
-10
-20
Gigabit Ethernet Filter
-30
125MHz
-50
-60
RMS Phase Jitter (Random)
1.875MHz to 20MHz (3.3V) = 0.48ps (typical)
1.875MHz to 20MHz (2.5V) = 0.50ps (typical)
-70
-80
-90
Raw Phase Noise Data
-100
-110
➤
NOISE POWER dBc
Hz
-40
-120
-130
-140
-150
-160
➤
-170
-180
-190
100
1k
10k
Phase Noise Result by adding
Gigabit Ethernet Filter to raw data
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
840021AGI
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REV. A MAY 19, 2005
ICS840021I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.25V ± 5%
1.65V ± 5%
SCOPE
VDD,
VDDA
Qx
LVCMOS
SCOPE
VDD,
VDDA
Qx
LVCMOS
GND
GND
-1.25V ± 5%
-1.65V ± 5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
Noise Power
Phase Noise Plot
80%
80%
Phase Noise Mask
Clock
Outputs
f1
Offset Frequency
20%
20%
tR
tF
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
V
DD
2
Q0
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
840021AGI
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REV. A MAY 19, 2005
ICS840021I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS840021I provides separate
power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10μF and a .01μF
bypass capacitor should be connected to each VDDA pin.
3.3V or 2.5V
VDD
.01μF
10 Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840021I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
840021AGI
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REV. A MAY 19, 2005
ICS840021I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
APPLICATION SCHEMATIC
Figure 3A shows a schematic example of the ICS840021I. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18pF
parallel resonant 25MHz crystal is used for generating 125MHz
VDD
output frequency. The C1 = 22pF and C2 = 33pF are recommended for frequency accuracy. For different board layout, the
C1 and C2 values may be slightly adjusted for optimizing frequency accuracy.
VDDA
R2
10
C3
C4
10uF
0.1u
U1
OE
C2
33pF
1
2
3
4
VDDA
OE
XTAL_OUT
XTAL_IN
VDD
Q0
GND
NC
8
7
6
5
R3
33
VDD
Q
Zo = 50 Ohm
X1
C5
0.1u
ICS840021i
C1
22pF
LVCMOS
VDD=3.3V
FIGURE 3A. ICS840021I SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of ICS840021I P.C. board layout.
The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed
in the Table 7. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 7. FOOTPRINT TABLE
Reference
Size
C1, C2
0402
C3
0805
C4, C5
0603
R2, R3
0603
NOTE: Table 7, lists component
sizes shown in this layout example.
FIGURE 3B. ICS840021I PC BOARD LAYOUT EXAMPLE
840021AGI
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REV. A MAY 19, 2005
ICS840021I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
101.7°C/W
90.5°C/W
89.8°C/W
TRANSISTOR COUNT
The transistor count for ICS840021I is: 1961
840021AGI
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REV. A MAY 19, 2005
ICS840021I
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
FOR
FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
8 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
A
Maximum
8
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
2.90
3.10
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
840021AGI
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REV. A MAY 19, 2005
ICS840021I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS840021AGI
021AI
8 lead TSSOP
tube
-40°C to 85°C
ICS840021AGIT
021AI
8 lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS840021AGILF
TBD
8 lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS840021AGILFT
TBD
8 lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
840021AGI
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REV. A MAY 19, 2005
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