TI DAC101C081 Dac101c081/dac101c081q/dac101c085 10-bit micro power digital-to-analog converter with an i2câ ¢-compatible interface Datasheet

DAC101C081, DAC101C081Q, DAC101C085
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SNVS801A – APRIL 2012 – REVISED MARCH 2013
DAC101C081/DAC101C081Q/DAC101C085 10-Bit Micro Power Digital-to-Analog Converter
with an I2C™-Compatible Interface
Check for Samples: DAC101C081, DAC101C081Q, DAC101C085
FEATURES
DESCRIPTION
•
•
•
The DAC101C081 is a 10-bit, single channel, voltageoutput digital-to-analog converter (DAC) that operates
from a +2.7V to 5.5V supply. The output amplifier
allows rail-to-rail output swing and has an 6µsec
settling time. The DAC101C081 uses the supply
voltage as the reference to provide the widest
dynamic output range and typically consumes 132µA
while operating at 5.0V. It is available in 6-lead SOT
and WSON packages and provides three address
options (pin selectable).
1
23
•
•
•
•
Ensured Monotonicity to 10-bits
Low Power Operation: 156 µA max @ 3.3V
Extended Power Supply Range (+2.7V to
+5.5V)
I2C-Compatible 2-Wire Interface which
Supports Standard (100kHz), Fast (400kHz),
and High Speed (3.4MHz) Modes
Rail-to-Rail Voltage Output
Very Small Package
DAC101C081Q is AEC Q100 Grade 1 Qualified
and Manufactured on Automotive Grade Flow
KEY SPECIFICATIONS
•
•
•
•
•
•
•
•
Resolution: 10 bits
INL: ±2 LSB (max)
DNL: +0.3/-0.2 LSB (max)
Setting Time: 6 µs (max)
Zero Code Error: +10 mV (max)
Full-Scale Error: −0.7 %FS (max)
Supply Power (Normal): 380 µW (3V) / 730 µW
(5V) typ
Supply Power (Power Down): 0.5 µW (3V) / 0.9
µW (5V) typ
APPLICATIONS
•
•
•
•
•
•
Industrial Process Control
Portable Instruments
Digital Gain and Offset Adjustment
Programmable Voltage & Current Sources
Test Equipment
Automotive
As an alternative, the DAC101C085 provides nine
I2C™ addressing options and uses an external
reference. It has the same performance and settling
time as the DAC101C081. It is available in an 8-lead
VSSOP.
The DAC101C081 and DAC101C085 use a 2-wire,
I2C™-compatible serial interface that operates in all
three speed modes, including high speed mode
(3.4MHz). An external address selection pin allows up
to three DAC101C081 or nine DAC101C085 devices
per 2-wire bus. Pin compatible alternatives to the
DAC101C081 are available that provide additional
address options.
The DAC101C081 and DAC101C085 each have a
16-bit register that controls the mode of operation, the
power-down condition, and the output voltage. A
power-on reset circuit ensures that the DAC output
powers up to zero volts. A power-down feature
reduces power consumption to less than a microWatt.
Their low power consumption and small packages
make these DACs an excellent choice for use in
battery operated equipment. Each DAC operates over
the extended industrial temperature range of −40°C
to +125°C.
The DAC101C081 and DAC101C085 are each part of
a family of pin compatible DACs that also provide 12
and 8 bit resolution. For 12-bit DACs see the
DAC121C081 and DAC121C085. For 8-bit DACs see
the DAC081C081 and DAC081C085.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
2
2
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
DAC101C081, DAC101C081Q, DAC101C085
SNVS801A – APRIL 2012 – REVISED MARCH 2013
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Table 1. Pin-Compatible Alternatives (1)
(1)
Resolution
SOT-6 and WSON-6 Packages
VSSOP-8 Package w/ External Reference
12-bit
DAC121C081
DAC121C085
10-bit
DAC101C081
DAC101C085
8-bit
DAC081C081
DAC081C085
All devices are fully pin and function compatible.
Connection Diagrams
ADR0 1
SCL
SDA
6
2 WSON 5
3
4
VOUT
VA
VOUT
1
VA
2
GND
GND
SOT
3
6
ADR0
5
SCL
4
ADR0
1
ADR1
2
8
VOUT
7
VREF
VSSOP
SDA
SCL
3
6
VA
SDA
4
5
GND
DAC101C081
DAC101C081
DAC101C085
Figure 1. 6-Lead WSON Package
See Package Number NGF0006A
Figure 2. 6-Lead SOT Package
See Package Number DDC0006A
Figure 3. 8-Lead VSSOP Package
See Package Number DGK0008A
Block Diagram
VA*
VREF*
GND
DAC101C081 / DAC101C085
POWER-ON
RESET
REF
DAC
REGISTER
10 BIT DAC
VOUT
BUFFER
10
10
2.5k
100k
POWER-DOWN
CONTROL
LOGIC
2
I C
INTERFACE
* NOTE: ADR1 and VREF are for the DAC101C085 only. The DAC101C085 uses an external
reference (VREF), whereas, the DAC101C081 uses the supply (VA) as the reference.
ADR1* ADR0
2
SCL
SDA
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PIN DESCRIPTIONS
Symbol
Type
Equivalent Circuit
VOUT
Analog Output
VA
Supply
Power supply input. For the SOT and WSON versions, this
supply is used as the reference. Must be decoupled to GND.
GND
Ground
Ground for all on-chip circuitry.
SDA
Digital
Input/Output
SCL
Digital Input
ADR0
Digital Input,
three levels
Analog Output Voltage.
Serial Data bi-directional connection. Data is clocked into or
out of the internal 16-bit register relative to the clock edges
of SCL. This is an open drain data line that must be pulled
to the supply (VA) by an external pull-up resistor.
PIN
D1
Snap
Back
Serial Clock Input. SCL is used together with SDA to control
the transfer of data in and out of the device.
GND
Tri-state Address Selection Input. Sets the two Least
Significant Bits (A1 & A0) of the 7-bit slave address. (see
Table 2)
V+
PIN
ADR1
Description
Snap
Back
Digital Input,
three levels
2.1k
D1
41.5k
41.5k
Tri-State Address Selection Input. Sets Bits A6 & A3 of the
7-bit slave address. (see Table 2)
GND
VREF
Supply
Unbufferred reference voltage. For the VSSOP-8, this
supply is used as the reference. VREF must be free of noise
and decoupled to GND.
PAD
(WSON only)
Ground
Exposed die attach pad can be connected to ground or left
floating. Soldering the pad to the PCB offers optimal thermal
performance and enhances package self-alignment during
reflow.
Package Pinouts
PACKAGE
VOUT
VA
GND
SDA
SCL
ADR0
ADR1
VREF
PAD (WSON only)
N/A
SOT
1
2
3
4
5
6
N/A
N/A
WSON
6
5
4
3
2
1
N/A
N/A
7
VSSOP-8
8
6
5
4
3
1
2
7
N/A
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3)
Supply Voltage, VA
−0.3V to +6.5V
Voltage on any Input Pin
−0.3V to +6.5V
Input Current at Any Pin (4)
Package Input Current
±10 mA
(4)
±20 mA
Power Consumption at TA = 25°C
See
Human Body Model
ADR0, ADR1 pins:
ESD Susceptibility (6)
VA, GND, VREF, VOUT,
SDA, SCL pins:
Machine Model
(5)
2500V
250V
Charged Device Model (CDM)
1000V
Human Body Model
5000V
Machine Model
Charged Device Model (CDM)
350V
1000V
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
(1)
(2)
(3)
(4)
(5)
(6)
4
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10
mA to two.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe
fault condition (e.g., when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).
Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged
through 0 Ω. Charge device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an
automated assembler) then rapidly being discharged.
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Operating Ratings (1) (2)
−40°C ≤ TA ≤ +125°C
Operating Temperature Range
Supply Voltage, VA
+2.7V to 5.5V
Reference Voltage, VREFIN
+1.0V to VA
Digital Input Voltage (3) (4)
0.0V to 5.5V
Output Load
0 to 1500 pF
(1)
(2)
(3)
(4)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion
result. For example, if VA is 3V, the digital input pins can be driven with a 5V logic device.
To ensure accuracy, it is required that VA and VREF be well bypassed.
Package Thermal Resistances (1)
(1)
Package
θJA
6-Lead SOT
250°C/W
6-Lead WSON
190°C/W
8-Lead VSSOP
240°C/W
Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.()
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Electrical Characteristics
The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, CL = 200 pF to GND, input code range 12 to 1011.
Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
Limits (1)
Units
(Limits)
Resolution
10
Bits (min)
Monotonicity
10
Bits (min)
+2
LSB (max)
Symbol
Parameter
Typ (1)
Test Conditions
STATIC PERFORMANCE
INL
+0.6
Integral Non-Linearity
DNL
Differential Non-Linearity
−0.4
−2
LSB (min)
+0.12
+0.3
LSB (max)
−0.04
−0.2
LSB (min)
ZE
Zero Code Error
IOUT = 0
+1.1
+10
mV (max)
FSE
Full-Scale Error
IOUT = 0
−0.1
−0.7
%FSR (max)
GE
Gain Error
All ones Loaded to DAC register
−0.2
−0.7
%FSR (max)
−20
µV/°C
VA = 3V
−0.7
ppm FSR/°C
VA = 5V
−1.0
ppm FSR/°C
ZCED
TC GE
Zero Code Error Drift
Gain Error Tempco
ANALOG OUTPUT CHARACTERISTICS (VOUT)
Output Voltage Range
ZCO
FSO
DAC101C085
0
VREF
V (min)
V (max)
DAC101C081
0
VA
V (min)
V (max)
(2)
Zero Code Output
Full Scale Output
VA = 3V, IOUT = 200 µA
1.3
mV
VA = 5V, IOUT = 200 µA
7.0
mV
VA = 3V, IOUT = 200 µA
2.984
V
VA = 5V, IOUT = 200 µA
4.989
V
56
mA
IOS
Output Short Circuit Current
(ISOURCE)
VA = 3V, VOUT = 0V, Input Code = FFFh.
VA = 5V, VOUT = 0V, Input Code = FFFh.
69
mA
IOS
Output Short Circuit Current
(ISINK)
VA = 3V, VOUT = 3V, Input Code = 000h.
−52
mA
VA = 5V, VOUT = 5V, Input Code = 000h.
−75
mA
IO
Continuous Output
Current (2)
CL
Maximum Load Capacitance
ZOUT
Available on the DAC output
11
mA (max)
RL = ∞
1500
pF
RL = 2kΩ
1500
pF
7.5
Ω
DC Output Impedance
REFERENCE INPUT CHARACTERISTICS- (DAC101C085 only)
Input Range Minimum
VREF
0.2
Input Range Maximum
Input Impedance
1.0
V (min)
VA
V (max)
120
kΩ
LOGIC INPUT CHARACTERISTICS (SCL, SDA)
VIH
Input High Voltage
0.7 x VA
V (min)
VIL
Input Low Voltage
0.3 x VA
V (max)
IIN
Input Current
±1
µA (max)
CIN
Input Pin Capacitance (2)
3
pF (max)
0.1 x VA
V (min)
VHYST
(1)
(2)
6
Input Hysteresis
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing
Quality Level).
This parameter is ensured by design and/or characterization and is not tested in production.
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Electrical Characteristics (continued)
The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, CL = 200 pF to GND, input code range 12 to 1011.
Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
Symbol
Parameter
Test Conditions
Typ (1)
Limits (1)
Units
(Limits)
LOGIC INPUT CHARACTERISTICS (ADR0, ADR1)
VIH
Input High Voltage
VA- 0.5V
V (min)
VIL
Input Low Voltage
0.5
V (max)
IIN
Input Current
±1
µA (max)
ISINK = 3 mA
0.4
V (max)
ISINK = 6 mA
0.6
V (max)
±1
µA (max)
Supply Voltage Minimum
2.7
V (min)
Supply Voltage Maximum
5.5
V (max)
LOGIC OUTPUT CHARACTERISTICS (SDA)
VOL
Output Low Voltage
IOZ
High-Impedence Output
Leakage Current
POWER REQUIREMENTS
VA
Normal -- VOUT set to midscale. 2-wire interface quiet (SCL = SDA = VA). (output unloaded)
IST_VA-1
VADAC101C081 Supply Current
VA = 2.7V to 3.6V
105
156
µA (max)
VA = 4.5V to 5.5V
132
214
µA (max)
VA = 2.7V to 3.6V
86
118
µA (max)
VA = 4.5V to 5.5V
98
152
µA (max)
IST_VA-5
VADAC101C085 Supply Current
IST_VREF
VREF Supply Current
(DAC101C085 only)
VA = 2.7V to 3.6V
37
43
µA (max)
VA = 4.5V to 5.5V
53
61
µA (max)
Power Consumption
(VA & VREF for DAC101C085)
VA = 3.0V
380
µW
VA = 5.0V
730
µW
PST
Continuous Operation -- 2-wire interface actively addressing the DAC and writing to the DAC register. (output unloaded)
fSCL=400kHz
ICO_VA-1
VADAC101C081 Supply Current
fSCL=3.4MHz
fSCL=400kHz
ICO_VA-5
VADAC101C085 Supply Current
fSCL=3.4MHz
ICO_VREF
VREF Supply Current
(DAC101C085 only)
fSCL=400kHz
PCO
Power Consumption
(VA & VREF for DAC101C085)
fSCL=3.4MHz
VA = 2.7V to 3.6V
134
220
µA (max)
VA = 4.5V to 5.5V
192
300
µA (max)
VA = 2.7V to 3.6V
225
320
µA (max)
VA = 4.5V to 5.5V
374
500
µA (max)
VA = 2.7V to 3.6V
101
155
µA (max)
VA = 4.5V to 5.5V
142
220
µA (max)
VA = 2.7V to 3.6V
193
235
µA (max)
VA = 4.5V to 5.5V
325
410
µA (max)
VA = 2.7V to 3.6V
33.5
55
µA (max)
VA = 4.5V to 5.5V
49.5
71.4
µA (max)
VA = 3.0V
480
µW
VA = 5.0V
1.06
mW
VA = 3.0V
810
µW
VA = 5.0V
2.06
mW
Power Down -- 2-wire interface quiet (SCL = SDA = VA) after PD mode written to DAC register. (output unloaded)
IPD
PPD
Supply Current
(VA & VREF for DAC101C085)
Power Consumption
(VA & VREF for DAC101C085)
Copyright © 2012–2013, Texas Instruments Incorporated
All Power Down Modes
All Power Down Modes
VA = 2.7V to 3.6V
0.13
1.52
µA (max)
VA = 4.5V to 5.5V
0.15
3.25
µA (max)
VA = 3.0V
0.5
µW
VA = 5.0V
0.9
µW
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AC and Timing Characteristics
The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, RL = Infinity, CL = 200 pF to GND. Boldface limits
apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
Typ (2)
Limits (1) (2)
Units
(Limits)
100h to 300h code change
RL = 2kΩ, CL = 200 pF
4.5
6
µs (max)
1
V/µs
Code change from 200h to 1FFh
12
nV-sec
0.5
nV-sec
Multiplying Bandwidth (4)
VREF = 2.5V ± 0.1Vpp
160
kHz
Total Harmonic Distortion (4)
VREF = 2.5V ± 0.1Vpp
input frequency = 10kHz
70
dB
VA = 3V
0.8
µsec
VA = 5V
0.5
µsec
Symbol
Test Conditions (1)
Parameter
ts
Output Voltage Settling Time (3)
SR
Output Slew Rate
Glitch Impulse
Digital Feedthrough
tWU
Wake-Up Time
DIGITAL TIMING SPECS (SCL, SDA)
fSCL
Serial Clock Frequency
Standard Mode
Fast Mode
High Speed Mode, Cb = 100pF
High Speed Mode, Cb = 400pF
100
400
3.4
1.7
kHz (max)
kHz (max)
MHz (max)
MHz (max)
tLOW
SCL Low Time
Standard Mode
Fast Mode
High Speed Mode, Cb = 100pF
High Speed Mode, Cb = 400pF
4.7
1.3
160
320
µs (min)
µs (min)
ns (min)
ns (min)
tHIGH
SCL High Time
Standard Mode
Fast Mode
High Speed Mode, Cb = 100pF
High Speed Mode, Cb = 400pF
4.0
0.6
60
120
µs (min)
µs (min)
ns (min)
ns (min)
tSU;DAT
Data Setup Time
Standard Mode
Fast Mode
High Speed Mode
250
100
10
ns (min)
ns (min)
ns (min)
Standard Mode
0
3.45
µs (min)
µs (max)
Fast Mode
0
0.9
µs (min)
µs (max)
High Speed Mode, Cb = 100pF
0
70
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
0
150
ns (min)
ns (max)
tHD;DAT
Data Hold Time
tSU;STA
Setup time for a start or a repeated
start condition
Standard Mode
Fast Mode
High Speed Mode
4.7
0.6
160
µs (min)
µs (min)
ns (min)
tHD;STA
Hold time for a start or a repeated start
condition
Standard Mode
Fast Mode
High Speed Mode
4.0
0.6
160
µs (min)
µs (min)
ns (min)
tBUF
Bus free time between a stop and start
condition
Standard Mode
Fast Mode
4.7
1.3
µs (min)
µs (min)
tSU;STO
Setup time for a stop condition
Standard Mode
Fast Mode
High Speed Mode
4.0
0.6
160
µs (min)
µs (min)
ns (min)
(1)
(2)
(3)
(4)
8
Cb refers to the capacitance of one bus line. Cb is expressed in pF units.
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing
Quality Level).
This parameter is ensured by design and/or characterization and is not tested in production.
Applies to the Multiplying DAC configuration. In this configuration, the reference is used as the analog input. The value loaded in the
DAC Register will digitally attenuate the signal at Vout.
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AC and Timing Characteristics (continued)
The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, RL = Infinity, CL = 200 pF to GND. Boldface limits
apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
Symbol
Test Conditions (1)
Parameter
Typ (2)
Standard Mode
Rise time of SDA signal
1000
ns (max)
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
10
80
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
20
160
ns (min)
ns (max)
Standard Mode
250
ns (max)
20+0.1Cb
250
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
10
80
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
20
160
ns (min)
ns (max)
Standard Mode
1000
ns (max)
20+0.1Cb
300
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
10
40
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
20
80
ns (min)
ns (max)
1000
ns (max)
20+0.1Cb
300
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
10
80
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
20
160
ns (min)
ns (max)
Standard Mode
300
ns (max)
20+0.1Cb
300
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
10
40
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
20
80
ns (min)
ns (max)
400
pF (max)
50
10
ns (max)
ns (max)
270
60
ns (max)
ns (max)
Fast Mode
tfDA
Fall time of SDA signal
Fast Mode
trCL
Rise time of SCL signal
Standard Mode
trCL1
Rise time of SCL signal after a
repeated start condition and after an
acknowledge bit.
Fast Mode
Fast Mode
tfCL
Fall time of a SCL signal
Cb
Capacitive load for each bus line (SCL
and SDA)
tSP
Pulse Width of spike suppressed (5) (6)
Fast Mode
High Speed Mode
toutz
SDA output delay (see Section 1.9)
Fast Mode
High Speed Mode
(5)
(6)
Units
(Limits)
20+0.1Cb
300
Fast Mode
trDA
Limits (1) (2)
87
38
Spike suppression filtering on SCL and SDA will supress spikes that are less than 50ns for standard-fast mode and less than 10ns for
hs-mode.
This parameter is ensured by design and/or characterization and is not tested in production.
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Specification Definitions
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB, which is VREF / 1024 = VA / 1024.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital
inputs when the DAC output is not updated. It is measured with a full-scale code change on the data bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded
into the DAC and the value of VA x 1023 / 1024.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and
Full-Scale Errors as:
GE = FSE - ZE
where
•
•
•
GE is Gain error
FSE is Full-Scale Error
and ZE is Zero Error.
(1)
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register
changes. It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line
through the input to output transfer function. The deviation of any given code from this straight line is measured
from the center of that code value. The end point method is used. INL for this product is specified over a limited
range, per the Electrical Characteristics Table.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is
LSB = VREF / 2n
where
•
VREF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 10 for the
DAC101C081.
(2)
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output
stability maintained.
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when
the input code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is
1/2 of VA.
MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3dB below the input sine wave
on VREFIN with a full-scale code loaded into the DAC.
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from
the power supply. The difference between the supply and output currents is the power consumed by the device
without a load.
SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is
updated.
TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs
with an ideal sine wave applied to VREFIN. THD is measured in dB.
WAKE-UP TIME is the time for the output to exit power-down mode. This time is measured from the rising edge
of SCL during the ACK bit of the lower data byte to the time the output voltage deviates from the power-down
voltage of 0V.
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been
entered.
10
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FSE
1023 x VREF
1024
GE = FSE - ZE
FSE = GE + ZE
OUTPUT
VOLTAGE
ZE
0
0
1023
DIGITAL INPUT CODE
Figure 4. Input / Output Transfer Characteristic
SDA
tLOW
tf
tr
tHD;STA
tr
tf
tBUF
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
tSU;STO
tSU;DAT
STOP
REPEATED
START
START
START
Figure 5. Serial Timing Diagram
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Typical Performance Characteristics
VREF = VA, fSCL = 3.4MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated.
12
INL
DNL
Figure 6.
Figure 7.
INL/DNL vs Temperature at VA = 3.0V
INL/DNL vs Temperature at VA = 5.0V
Figure 8.
Figure 9.
INL/DNL vs VREFIN at VA = 3.0V
INL/DNL vs VREFIN at VA = 5.0V
Figure 10.
Figure 11.
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Typical Performance Characteristics (continued)
VREF = VA, fSCL = 3.4MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated.
INL/DNL vs VA
Zero Code Error vs. VA
Figure 12.
Figure 13.
Zero Code Error vs. Temperature
Full Scale Error vs. VA
Figure 14.
Figure 15.
Full Scale Error vs. Temperature
Total Supply Current vs. VA
Figure 16.
Figure 17.
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Typical Performance Characteristics (continued)
VREF = VA, fSCL = 3.4MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated.
VREF Supply Current vs. VA
Total Supply Current vs. Temperature @ VA = 3V
Figure 18.
Figure 19.
Total Supply Current vs. Temperature @ VA = 5V
5V Glitch Response
Figure 20.
Figure 21.
Power-On Reset
Figure 22.
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FUNCTIONAL DESCRIPTION
DAC SECTION
The DAC101C081 is fabricated on a CMOS process with an architecture that consists of switches and resistor
strings that are followed by an output buffer.
For simplicity, a single resistor string is shown in Figure 23. This string consists of 1024 equal valued resistors
with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register
determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight
binary with an ideal output voltage of:
VOUT = VREF x (D / 1024)
where
•
D is the decimal equivalent of the binary code that is loaded into the DAC register. D can take on any integer
value between 0 and1023. This configuration ensures that the DAC is monotonic.
(3)
VREF
R
R
R
To Output Amplifier
R
R
Figure 23. DAC Resistor String
OUTPUT AMPLIFIER
The output amplifier is rail-to-rail, providing an output voltage range of 0V to VA when the reference is VA. All
amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA,
in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the
reference is less than VA, there is only a loss in linearity in the lowest codes. The output capabilities of the
amplifier are described in the Electrical Characteristics Table.
The output amplifiers are capable of driving a load of 2 kΩ in parallel with 1500 pF to ground or to VA. The zerocode and full-scale outputs for given load currents are available in the Electrical Characteristics Table.
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REFERENCE VOLTAGE
The DAC101C081 uses the supply (VA) as the reference. With that said, VA must be treated as a reference. The
Analog output will only be as clean as the reference (VA). It is recommended that the reference be driven by a
voltage source with low output impedance.
The DAC101C085 comes with an external reference supply pin (VREF). For the DAC101C085, it is important that
VREF be kept as clean as possible.
The Applications Information section describes a handful of ways to drive the reference appropriately. Refer to
Using References as Power Supplies for details.
SERIAL INTERFACE
The I2C™-compatible interface operates in all three speed modes. Standard mode (100kHz) and Fast mode
(400kHz) are functionally the same and will be referred to as Standard-Fast mode in this document. High-Speed
mode (3.4MHz) is an extension of Standard-Fast mode and will be referred to as Hs-mode in this document. The
following diagrams describe the timing relationships of the clock (SCL) and data (SDA) signals. Pull-up resistors
or current sources are required on the SCL and SDA busses to pull them high when they are not being driven
low. A logic zero is transmitted by driving the output low. A logic high is transmitted by releasing the output and
allowing it to be pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus
capacitance and operating speed.
Basic I2C ™ Protocol
The I2C™ interface is bi-directional and allows multiple devices to operate on the same bus. To facilitate this bus
configuration, each device has a unique hardware address which is referred to as the "slave address." To
communicate with a particular device on the bus, the controller (master) sends the slave address and listens for
a response from the slave. This response is referred to as an acknowledge bit. If a slave on the bus is addressed
correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match a
device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled high. ACKs also occur
on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte
is successfully received. When the master is reading data, the master ACKs after every data byte is received to
let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after
the last data byte and creates a Stop condition on the bus.
All communication on the bus begins with either a Start condition or a Repeated Start condition. The protocol for
starting the bus varies between Standard-Fast mode and Hs-mode. In Standard-Fast mode, the master
generates a Start condition by driving SDA from high to low while SCL is high. In Hs-mode, starting the bus is
more complicated. Please refer to High-Speed (Hs) Mode for the full details of a Hs-mode Start condition. A
Repeated Start is generated to either address a different device, or switch between read and write modes. The
master generates a Repeated Start condition by driving SDA low while SCL is high. Following the Repeated
Start, the master sends out the slave address and a read/write bit as shown in Figure 24. The bus continues to
operate in the same speed mode as before the Repeated Start condition.
All communication on the bus ends with a Stop condition. In either Standard-Fast mode or Hs-Mode, a Stop
condition occurs when SDA is pulled from low to high while SCL is high. After a Stop condition, the bus remains
idle until a master generates a Start condition.
Please refer to the Philips I2C™ Specification (Version 2.1 Jan, 2000) for a detailed description of the serial
interface.
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SDA
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1
2
6
MSB
R/W
Direction
Bit
Acknowledge
from the Device
7-bit Slave Address
SCL
ACK
LSB
MSB
7
8
9
LSB
N/ACK
Data Byte
*Acknowledge
or Not-ACK
1
8
2
9
Repeated for the Lower Data Byte
and Additional Data Transfers
START or
REPEATED
START
STOP
*Note: In continuous mode, this bit must be an ACK from
the data receiver. Immediately preceding a STOP
condition, this bit must be a NACK from the master.
Figure 24. Basic Operation.
Standard-Fast Mode
In Standard-Fast mode, the master generates a start condition by driving SDA from high to low while SCL is
high. The Start condition is always followed by a 7-bit slave address and a Read/Write bit. After these eight bits
have been transmitted by the master, SDA is released by the master and the DAC101C081 either ACKs or
NACKs the address. If the slave address matches, the DAC101C081 ACKs the master. If the address doesn't
match, the DAC101C081 NACKs the master.
For a write operation, the master follows the ACK by sending the upper eight data bits to the DAC101C081.
Then the DAC101C081 ACKs the transfer by driving SDA low. Next, the lower eight data bits are sent by the
master. The DAC101C081 then ACKs the transfer. At this point, the DAC output updates to reflect the contents
of the 16-bit DAC register. Next, the master either sends another pair of data bytes, generates a Stop condition
to end communication, or generates a Repeated Start condition to communicate with another device on the bus.
For a read operation, the DAC101C081 sends out the upper eight data bits of the DAC register. This is followed
by an ACK by the master. Next, the lower eight data bits of the DAC register are sent to the master. The master
then produces a NACK by letting SDA be pulled high. The NACK is followed by a master-generated Stop
condition to end communication on the bus, or a Repeated Start to communicate with another device on the bus.
High-Speed (Hs) Mode
For Hs-mode, the sequence of events to begin communication differ slightly from Standard-Fast mode. Figure 25
describes this in further detail. Initially, the bus begins running in Standard-Fast mode. The master generates a
Start condition and sends the 8-bit Hs master code (00001XXX) to the DAC101C081. Next, the DAC101C081
responds with a NACK. Once the SCL line has been pulled to a high level, the master switches to Hs-mode by
increasing the bus speed and generating a Repeated Start condition (driving SDA low while SCL is pulled high).
At this point, the master sends the slave address to the DAC101C081, and communication continues as shown
above in the "Basic Operation" Diagram (see Figure 24).
When the master generates a Repeated Start condition while in Hs-mode, the bus stays in Hs-mode awaiting the
slave address from the master. The bus continues to run in Hs-mode until a Stop condition is generated by the
master. When the master generates a Stop condition on the bus, the bus must be started in Standard-Fast mode
again before increasing the bus speed and switching to Hs-mode.
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SDA
NACK
MSB
8-ELW 0DVWHU FRGH ³00001[[[´
7-bit Slave
Address
Not-Acknowledge
from the Device
1
SCL
2
6
5
8
7
9
1
2
Repeated
START
START
Standard-Fast Mode
Hs-Mode
Figure 25. Beginning Hs-Mode Communication
I2C™ Slave (Hardware) Address
The DAC has a seven-bit I2C™ slave address. For the VSSOP-8 version of the DAC, this address is configured
by the ADR0 and ADR1 address selection inputs. For the DAC101C081, the address is configured by the ADR0
address selection input. ADR0 and ADR1 can be grounded, left floating, or tied to VA. If desired, the address
selection inputs can be set to VA/2 rather than left floating. The state of these inputs sets the address the DAC
responds to on the I2C™ bus (see Table 2). In addition to the selectable slave address, there is also a broadcast
address (1001000) for all DAC101C081's and DAC101C085's on the 2-wire bus. When the bus is addressed by
the broadcast address, all the DAC101C081's and DAC101C085's will respond and update synchronously.
Figure 26 and Figure 27 describe how the master device should address the DAC via the I2C™-Compatible
interface.
Keep in mind that the address selection inputs (ADR0 and ADR1) are only sampled until the DAC is correctly
addressed with a non-broadcast address. At this point, the ADR0 and ADR1 inputs Tri-State and the slave
address is "locked". Changes to ADR0 and ADR1 will not update the selected slave address until the device is
power-cycled.
Table 2. Slave Addresses
ADR1
ADR0
ADR0
0001100
Floating
Floating
Floating
0001101
Floating
GND
GND
0001110
Floating
VA
VA
0001000
GND
Floating
---------------
0001001
GND
GND
---------------
0001010
GND
VA
---------------
1001100
VA
Floating
---------------
1001101
VA
GND
---------------
1001110
VA
VA
---------------
1001000
(1)
18
DAC101C081 (SOT &
WSON) (1)
DAC101C085 (VSSOP-8)
Slave Address
[A6 - A0]
--------------- Broadcast Address ---------------
Pin-compatible alternatives to the DAC101C081 options are available with additional address options.
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Writing to the DAC Register
To write to the DAC, the master addresses the part with the correct slave address (A6-A0) and writes a "zero" to
the read/write bit. If addressed correctly, the DAC returns an ACK to the master. The master then sends out the
upper data byte. The DAC responds by sending an ACK to the master. Next, the master sends the lower data
byte to the DAC. The DAC responds by sending an ACK again. At this point, the master either sends the upper
byte of the next data word to be converted by the DAC, generates a Stop condition to end communication, or
generates a Repeated Start condition to begin communication with another device on the bus. Until generating a
Stop condition, the master can continuously write the upper and lower data bytes to the DAC register. This
allows for a maximum DAC conversion rate of 188.9 kilo-conversions per second in Hs-mode.
1
9
1
9
1
9
SCL
SDA
A6
Start by
Master
A5
A4
A3
A2
A1
A0 R/W
0
ACK
by
DAC101C081
Frame 1
Address Byte
from Master
0
PD1 PD0 D11 D10 D9
Frame 2
Data Byte from
Master
D7
ACK
by
DAC101C081
D8
D6
D5
D4
D3
D2
D1
D0
ACK Stop by
by
Master
DAC101C081
Frame 3
Data Byte from
Master
Repeat Frames
2 and 3 for
Continuous Mode
Figure 26. Typical Write to the DAC Register
Reading from the DAC Register
To read from the DAC register, the master addresses the part with the correct slave address (A6-A0) and writes
a "one" to the read/write bit. If addressed correctly, the DAC returns an ACK to the master. Next, the DAC sends
out the upper data byte. The master responds by sending an ACK to the DAC to indicate that it wants to receive
another data byte. Then the DAC sends the lower data byte to the master. Assuming only one 16-bit data word is
read, the master sends a NACK after receiving the lower data byte. At this point, the master either generates a
Stop condition to end communication, or a Repeated Start condition to begin communication with another device
on the bus.
1
9
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
Start by
Master
Frame 1
Address Byte
from Master
A0 R/W
0
ACK
by
DAC101C081
0
PD1 PD0 D11 D10 D9
Frame 2
Data Byte from
DAC101C081
D8
D7
D6
D5
ACK
by
Master
D4
D3
D2
Frame 3
Data Byte from
DAC101C081
D1
D0
NACK
by
Master
Stop by
Master
Figure 27. Typical Read from the DAC Register
DAC REGISTER
The DAC register, Figure 28, has sixteen bits. The first two bits are always zero. The next two bits determine the
mode of operation (normal mode or one of three power-down modes). The final twelve bits of the shift register
are the data bits. The data format is straight binary (MSB first, LSB last), with twelve 0's corresponding to an
output of 0V and twelve 1's corresponding to a full-scale output of VA - 1 LSB. When writing to the DAC Register,
VOUT will update on the rising edge of the ACK following the lower data byte.
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LSB
MSB
X
X PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
DATA BITS
0
0
1
1
0
1
0
1
Normal Operation.
2.5 kÖ to GND.
100 kÖ to GND.
High Impedance.
Power-Down Modes
Figure 28. DAC Register Contents
POWER-ON RESET
The power-on reset circuit controls the output voltage of the DAC during power-up. Upon application of power,
the DAC register is filled with zeros and the output voltage is 0 Volts. The output remains at 0V until a valid write
sequence is made to the DAC.
When resetting the device, it is crutial that the VA supply be lowered to a maximum of 200mV before the supply
is raised again to power-up the device. Dropping the supply to within 200mV of GND during a reset will ensure
the ADC performs as specified.
SIMULTANEOUS RESET
The broadcast address allows the I2C™ master to write a single word to multiple DACs simultaneously. Provided
that all of the DACs exist on a single I2C™ bus, every DAC will update when the broadcast address is used to
address the bus. This feature allows the master to reset all of the DACs on a shared I2C™ bus to a specific
digital code. For instance, if the master writes a power-down code to the bus with the broadcast address, all of
the DACs will power-down simultaneously.
POWER-DOWN MODES
The DAC101C081 has three power-down modes. In power-down mode, the supply current drops to 0.13µA at 3V
and 0.15µA at 5V (typ). The DAC101C081 is put into power-down mode by writing a one to PD1 and/or PD0.
The outputs can be set to high impedance, terminated by 2.5 kΩ to GND, or terminated by 100 kΩ to GND (see
Figure 28).
The bias generator, output amplifier, resistor string, and other linear circuitry are all shut down in any of the
power-down modes. When the DAC101C081 is powered down, the value written to the DAC register, including
the power-down bits, is saved. While the DAC is in power-down, the saved DAC register contents can be read
back. When the DAC is brought out of power-down mode, the DAC register contents will be overwritten and VOUT
will be updated with the new 10-bit data value.
The time to exit power-down (Wake-Up Time) is typically 0.8µsec at 3V and 0.5µsec at 5V.
ADDITIONAL TIMING INFORMATION: toutz
The toutz specification is provided to aid the design of the I2C bus. After the SCL bus is driven low by the I2C™
master, the SDA bus will be held for a short time by the DAC101C081. This time is referred to as toutz. The
following figure illustrates the relationship between the fall of SCL, at the 30% threshold, to the time when the
DAC begins to transition the SDA bus. The toutz specification only applies when the DAC is in control of the SDA
bus. The DAC is only in control of the bus during an ACK by the DAC101C081 or a data byte read from the DAC
(see Figure 27).
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SCL
SDA
toutz
Figure 29. Data Output Timing
The toutz specification is typically 87nsec in Standard-Fast Mode and 38nsec in Hs-Mode.
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APPLICATIONS INFORMATION
USING REFERENCES AS POWER SUPPLIES
While the simplicity of the DAC101C081 implies ease of use, it is important to recognize that the path from the
reference input (VA for the DAC101C081 & VREF for the DAC101C085) to VOUT will have essentially zero Power
Supply Rejection Ratio (PSRR). Therefore, it is necessary to provide a noise-free supply voltage to the
reference. In order to use the full dynamic range of the DAC101C085, the supply pin (VA) and VREF can be
connected together and share the same supply voltage. Since the DAC101C081 consumes very little power, a
reference source may be used as the supply voltage. (2) The advantages of using a reference source over a
voltage regulator are accuracy and stability. Some low noise regulators can also be used. Listed below are a few
reference and power supply options for the DAC101C081. When using the DAC101C081, it is important to treat
the analog supply (VA) as the reference.
LM4132
The LM4132, with its 0.05% accuracy over temperature, is a good choice as a reference source for the
DAC101C081. The 4.096V version is useful if a 0 to 4.095V output range is desirable or acceptable. Bypassing
the LM4132 VIN pin with a 0.1µF capacitor and the VOUT pin with a 2.2µF capacitor will improve stability and
reduce output noise. The LM4132 comes in a space-saving 5-pin SOT-23.
Input
Voltage
LM4132-4.1
C1
0.1 PF
C2
2.2 PF
C3
0.1 PF
VA VREF
DAC101C081/5
VOUT = 0V to 4.092V
SDA
SCL
Figure 30. The LM4132 as a Power Supply
(2)
22
To ensure accuracy, it is required that VA and VREF be well bypassed.
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LM4050
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a reference for the
DAC101C081. It is available in 4.096V and 5V versions and comes in a space-saving 3-pin SOT-23.
Input
Voltage
R
IDAC
VZ
IZ
0.1 PF
0.47 PF
LM4050-4.1
or
LM4050-5.0
VA VREF
DAC101C081/5
VOUT = 0V to 5V
SDA
SCL
Figure 31. The LM4050 as a Power Supply
The minimum resistor value in the circuit of Figure 31 must be chosen such that the maximum current through
the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at
its maximum, the LM4050 voltage at its minimum, and the DAC101C081 drawing zero current. The maximum
resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum
DAC101C081 current in full operation. The conditions for minimum current include the input voltage at its
minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the
DAC101C081 draws its maximum current. These conditions can be summarized as:
R(min) = ( VIN(max) − VZ(min) ) /IZ(max)
(4)
and
R(max) = ( VIN(min) − VZ(max) ) / ( (IDAC(max) + IZ(min) )
where
•
•
•
•
VZ(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over
temperature
IZ(max) is the maximum allowable current through the LM4050
IZ(min) is the minimum current required by the LM4050 for proper regulation and
IDAC(max) is the maximum DAC101C081 supply current.
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23
DAC101C081, DAC101C081Q, DAC101C085
SNVS801A – APRIL 2012 – REVISED MARCH 2013
www.ti.com
LP3985
The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good
choice for applications that do not require a precision reference for the DAC101C081. It comes in 3.0V, 3.3V and
5V versions, among others, and sports a low 30 µV noise specification at low frequencies. Since low frequency
noise is relatively difficult to filter, this specification could be important for some applications. The LP3985 comes
in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages.
Input
Voltage
LP3985
0.1 PF
1 PF
0.01 PF
0.1 PF
VA
VREF
DAC101C081/5
VOUT = 0V to 5V
SDA
SCL
Figure 32. Using the LP3985 Regulator
An input capacitance of 1.0µF without any ESR requirement is required at the LP3985 input, while a 1.0µF
ceramic capacitor with an ESR requirement of 5mΩ to 500mΩ is required at the output. Careful interpretation
and understanding of the capacitor specification is required to ensure correct device operation.
LP2980
The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon
grade. It is available in 3.0V, 3.3V and 5V versions, among others.
VIN
Input
Voltage
VOUT
LP2980
ON /OFF
1 PF
0.1 PF
VA VREF
DAC101C081/5
VOUT = 0V to 5V
SDA
SCL
Figure 33. Using the LP2980 Regulator
Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor
must be at least 1.0µF over temperature, but values of 2.2µF or more will provide even better performance. The
ESR of this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid
tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to
their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic
capacitors are typically not a good choice due to their large size and have ESR values that may be too high at
low temperatures.
24
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Product Folder Links: DAC101C081 DAC101C081Q DAC101C085
DAC101C081, DAC101C081Q, DAC101C085
www.ti.com
SNVS801A – APRIL 2012 – REVISED MARCH 2013
BIPOLAR OPERATION
The DAC101C081 is designed for single supply operation and thus has a unipolar output. However, a bipolar
output may be obtained with the circuit in Figure 34. This circuit will provide an output voltage range of ±5 Volts.
A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5V.
10 pF
R2
+5V
R1
+5V
10 PF
+
-
0.1 PF
±5V
+
DAC101C081
SDA
-5V
VOUT
SCL
Figure 34. Bipolar Operation
The output voltage of this circuit for any code is found to be:
VO = (VA x (D / 1024) x ((R1 + R2) / R1) - VA x R2 / R1)
where
•
D is the input code in decimal form.
(6)
With VA = 5V and R1 = R2,
VO = (10 x D / 1024) - 5V
(7)
A list of rail-to-rail amplifiers suitable for this application are indicated in Table 3.
Table 3. Some Rail-to-Rail Amplifiers
AMP
PKGS
LMP7701
SOT-23-5
Typ VOS
37 uV
Typ ISUPPLY
0.79 mA
LMV841
SC70-5
50 uV
1 mA
LMC7111
SOT-23-5
0.9 mV
25 µA
LM7301
SO-8
SOT-23-5
0.03 mV
620 µA
LM8261
SOT-23-5
0.7 mV
1 mA
DSP/MICROPROCESSOR INTERFACING
Interfacing the DAC101C081 to microprocessors and DSPs is quite simple. The following guidelines are offered
to simplify the design process.
Interfacing to the 2-wire Bus
Figure 35 shows a microcontroller interfacing to the DAC101C081 via the 2-wire bus. Pull-up resistors (Rp)
should be chosen to create an appropriate bus rise time and to limit the current that will be sunk by the opendrain outputs of the devices on the bus. Please refer to the I2C™ Specification for further details. Typical pull-up
values to use in Standard-Fast mode bus applications are 2kΩ to 10kΩ. SCL and SDA series resisters (RS) near
the DAC101C081 are optional. If high-voltage spikes are expected on the 2-wire bus, series resistors should be
used to filter the voltage on SDA and SCL. The value of the series resistance must be picked to ensure the VIL
threshold can be achieved. If used, RS is typically 51Ω.
Copyright © 2012–2013, Texas Instruments Incorporated
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25
DAC101C081, DAC101C081Q, DAC101C085
SNVS801A – APRIL 2012 – REVISED MARCH 2013
www.ti.com
DAC101C081/5
10 PF
VREF
4.7 PF
VA
0.1 PF
Regulated Supply
RP RP
VDD
PController
R S*
SDA
SDA
SCL
SCL
R S*
ADC101C021
SDA
SCL
I2C Device
SDA
SCL
*NOTE: RS is optional.
Figure 35. Serial Interface Connection Diagram
Interfacing to a Hs-mode Bus
Interfacing to a Hs-mode bus is very similar to interfacing to a Standard-Fast mode bus. In Hs-mode, the
specified rise time of SCL is shortened. To create a faster rise time, the master device (microcontroller) can drive
the SCL bus high and low. In other words, the microcontroller can drive the line high rather than leaving it to the
pull-up resistor. It is also possible to decrease the value of the pull-up resistors or increase the pull-up current to
meet the tighter timing specs. Please refer to the I2C™ Specification for further details.
LAYOUT, GROUNDING, AND BYPASSING
For best accuracy and minimum noise, the printed circuit board containing the DAC101C081 should have
separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.
Both of these planes should be located on the same board layer. There should be a single ground plane. A
single ground plane is preferred if digital return current does not flow through the analog ground area. Frequently
a single ground plane design will utilize a "fencing" technique to prevent the mixing of analog and digital ground
current. Separate ground planes should only be utilized when the fencing technique is inadequate. The separate
ground planes must be connected in one place, preferably near the DAC101C081. Special care is required to
ensure that digital signals with fast edge rates do not pass over split ground planes. They must always have a
continuous return path below their traces.
The DAC101C081 power supply should be bypassed with a 4.7µF and a 0.1µF capacitor as close as possible to
the device with the 0.1µF right at the device supply pin. The 4.7µF capacitor should be a tantalum type and the
0.1µF capacitor should be a low ESL, low ESR type. The power supply for the DAC101C081 should only be
used for analog circuits.
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the
board. These clock and data lines should have controlled impedances.
26
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Product Folder Links: DAC101C081 DAC101C081Q DAC101C085
DAC101C081, DAC101C081Q, DAC101C085
www.ti.com
SNVS801A – APRIL 2012 – REVISED MARCH 2013
REVISION HISTORY
Changes from Original (March 2013) to Revision A
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 26
Copyright © 2012–2013, Texas Instruments Incorporated
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27
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
DAC101C081CIMK/NOPB
ACTIVE
SOT
DDC
6
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
X85C
DAC101C081CIMKX/NOPB
ACTIVE
SOT
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
X85C
DAC101C081CISD
ACTIVE
WSON
NGF
6
1000
TBD
Call TI
Call TI
X88
DAC101C081CISD/NOPB
ACTIVE
WSON
NGF
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
X88
DAC101C081CISDX
ACTIVE
WSON
NGF
6
4500
TBD
Call TI
Call TI
X88
DAC101C081CISDX/NOPB
ACTIVE
WSON
NGF
6
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
X88
DAC101C081QISD/NOPB
ACTIVE
WSON
NGF
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
Q88
DAC101C081QISDX/NOPB
ACTIVE
WSON
NGF
6
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
Q88
DAC101C085CIMM
ACTIVE
VSSOP
DGK
8
1000
TBD
Call TI
Call TI
X91C
DAC101C085CIMM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
X91C
DAC101C085CIMMX
ACTIVE
VSSOP
DGK
8
3500
TBD
Call TI
Call TI
-40 to 125
X91C
DAC101C085CIMMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
X91C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DAC101C081CIMK/NOPB
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SOT
DDC
6
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT
DDC
6
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
WSON
NGF
6
1000
178.0
12.4
2.8
2.5
1.0
8.0
12.0
Q1
DAC101C081CISD/NOPB WSON
NGF
6
1000
178.0
12.4
2.8
2.5
1.0
8.0
12.0
Q1
WSON
NGF
6
4500
330.0
12.4
2.8
2.5
1.0
8.0
12.0
Q1
WSON
NGF
6
4500
330.0
12.4
2.8
2.5
1.0
8.0
12.0
Q1
DAC101C081QISD/NOPB WSON
DAC101C081CIMKX/NOP
B
DAC101C081CISD
DAC101C081CISDX
DAC101C081CISDX/NOP
B
DAC101C081QISDX/NOP
B
DAC101C085CIMM
DAC101C085CIMM/NOP
B
DAC101C085CIMMX
DAC101C085CIMMX/NO
PB
NGF
6
1000
178.0
12.4
2.8
2.5
1.0
8.0
12.0
Q1
WSON
NGF
6
4500
330.0
12.4
2.8
2.5
1.0
8.0
12.0
Q1
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC101C081CIMK/NOPB
SOT
DDC
6
1000
210.0
185.0
35.0
SOT
DDC
6
3000
210.0
185.0
35.0
DAC101C081CIMKX/NOP
B
DAC101C081CISD
WSON
NGF
6
1000
210.0
185.0
35.0
DAC101C081CISD/NOPB
WSON
NGF
6
1000
210.0
185.0
35.0
DAC101C081CISDX
WSON
NGF
6
4500
367.0
367.0
35.0
WSON
NGF
6
4500
367.0
367.0
35.0
WSON
NGF
6
1000
210.0
185.0
35.0
WSON
NGF
6
4500
367.0
367.0
35.0
DAC101C085CIMM
VSSOP
DGK
8
1000
210.0
185.0
35.0
DAC101C085CIMM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
DAC101C085CIMMX
VSSOP
DGK
8
3500
367.0
367.0
35.0
VSSOP
DGK
8
3500
367.0
367.0
35.0
DAC101C081CISDX/NOP
B
DAC101C081QISD/NOPB
DAC101C081QISDX/NOP
B
DAC101C085CIMMX/NOP
B
Pack Materials-Page 2
MECHANICAL DATA
NGF0006A
www.ti.com
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