LM10000 www.ti.com SNVS643C – JUNE 2010 – REVISED APRIL 2013 AVS System Controller Check for Samples: LM10000 FEATURES KEY SPECIFICATIONS • • • • 1 23 • • • • Flexible Enable Inputs to Allow Independent Enable Control of External Controller and LM10000 Fault Input Restores Output Voltage Setting to Default Value CNTL_EN Output That Enables/Disables External Controller 7-Bit Current DAC That Can Directly Connect to the Feedback Node of an External Controller and Provide Smooth Voltage Control Programmable Slew Rate Control DESCRIPTION The LM10000 is used to enable Adaptive Voltage Scaling (AVS) to non-AVS regulators. It includes a complete Slave Power Controller (SPC 2.0) to communicate to the PowerWise™ Interface (PWI 2.0), and a programmable current output DAC that allows voltage control to any regulator utilizing a feedback node/resistors to set the output voltage. In addition to enabling AVS the LM10000 allows the system to control power states such as sleep and shutdown, and to configure the voltage step slew rate from the PWI. APPLICATIONS • PWI 2.0 Interface AVS Control for One Output Precision Enable AVS-Enabled ASICs and FPGAs TYPICAL APPLICATION CIRCUIT Slave Regulator Single or Multi-Phase Controller or Switcher ASIC/FPGA VIN External Controller VIN VOUT 0.6V - 1.2V, 20A HG VOUT LG CORE RTN PGN D HPM PWRGD Enable FB LM10000 V I/O 3V ± 5.5V CNTL_EN IAVS FLT_N SPWI EN_BIAS SCLK AVS 0 PA ± 60 PA, 7 bit 2 APC 2 CONTROL VPWI RESET_N VDD AGND AGND ADDR 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerWise is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2013, Texas Instruments Incorporated LM10000 SNVS643C – JUNE 2010 – REVISED APRIL 2013 www.ti.com CONNECTION DIAGRAM Figure 1. 14-Lead Plastic WSON PIN DESCRIPTIONS Pin No. 2 Pad Name Type Pad Description 1 FLT_N Input External fault input. Usually connected to PWGD output of integrated regulator. 2 AGND GND 3 VDD Power 4 AGND GND 5 ADDR Input PWI address selection 6 EN_BIAS Input Enable input. 7 CONTROL Input VOUT control input from system. Logic level. 8 IAVS Output Current DAC output that connects to feedback node of integrated regulator 9 IAVS_MIRROR Output Current DAC output that mirrors IAVS output current 10 RESET_N Input Reset, active low. 11 CNTL_EN Output Enable signal that connects to integrated regulator 12 VPWI Power PWI IO bias power 13 SPWI I/O PWI Data 14 SCLK Input PWI Clock Analog Bias power input. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 LM10000 www.ti.com SNVS643C – JUNE 2010 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) (3) −0.2V to VDD VPWI to GND FLT_N, VDD, ADR, EN_BIAS, CONTROL, IAVS, IAVS_MIRROR, RESET_N, CNTL_EN, VPWI, SPWI, SCLK to GND −0.2V to 6V Junction Temperature −45°C to +125°C Storage Temperature −45°C to +150°C Soldering Information: See http://www.ti.com/lit/SNOA549 ESD Ratings (4) Human Body Model 2kV Machine Model (1) 200V Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device operates correctly. Operating Ratings do not imply ensured performance limits. The power MOSFETs can run on a separate 1V to 14V rail (Input voltage, VIN). Practical lower limit of VIN depends on selection of the external MOSFET. See the MOSFET GATE DRIVERS section under Application Information for further details. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. ESD using the human body model which is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (2) (3) (4) OPERATING RATINGS (1) (2) VDD 3.0V to 5.5V VPWI (3) 1.6V to 3.6V (1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device operates correctly. Operating Ratings do not imply ensured performance limits. The power MOSFETs can run on a separate 1V to 14V rail (Input voltage, VIN). Practical lower limit of VIN depends on selection of the external MOSFET. See the MOSFET GATE DRIVERS section under Application Information for further details. VPWI cannot be higher than VDD. (2) (3) THERMAL PROPERTIES Junction-to-Ambient thermal resistance 54.7°C ELECTRICAL CHARACTERISTICS Limits appearing in standard type apply for TJ = 25°C. Limits appearing in boldface type apply over full operating junction temperature range (−40°C ≤ TJ ≤ +125°C. Unless otherwise noted, specifications apply to the LM10000 Typical Application Circuit (pg. 2) with: VDD = 5.0V, CIN = 1µF. Symbol Iq Parameter Quiescent Current Typ Max EN_BIAS = 0V, CONTROL = 0V Conditions Min 1.5 10 EN_BIAS = VDD, CONTROL = VDD R0 = 0x7F 315 410 EN_BIAS = VDD, PWI Sleep Command 196 300 EN_BIAS = VDD, PWI Shutdown Command Rising Threshold UVLO IADDR Falling Threshold 2.27 23 75 2.65 2.75 Units µA V 2.40 Hysteresis 257 mV Address pin source current 7.5 µA IDAC ACC LSB Accuracy DAC Step Size Measured at full scale IDAC-MAX / 2 (1≤ n ≤ 7) Resolution FS Full Scale INL Integral Non-Linearity DNL −3 n 3 % 470 nA 7 Bits 59.69 Differential Non-Linearity µA −2 2 LSB −0.5 0.5 LSB Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 3 LM10000 SNVS643C – JUNE 2010 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Limits appearing in standard type apply for TJ = 25°C. Limits appearing in boldface type apply over full operating junction temperature range (−40°C ≤ TJ ≤ +125°C. Unless otherwise noted, specifications apply to the LM10000 Typical Application Circuit (pg. 2) with: VDD = 5.0V, CIN = 1µF. Symbol ZE Parameter Conditions Min Zero Code Error/Offset Error Typ Max 57 Units nA LOGIC AND CONTROL INPUTS EN_BIASTH IIL Precision enable threshold Input Current Low Rising 1.32 Falling 1.09 FLT_N, RESET_N −10 ENBIAS, CONTROL −1 SPWI, SCLK −1 1.4 1.19 µA FLT_N, RESET_N 1 ENBIAS, CONTROL 10 IIH Input Current High VIL Input Low Voltage CONTROL, FLT_N, RESET_N VIH Input High Voltage CONTROL, FLT_N, RESET_N VIL_PWI Input Low Voltage, PWI SPWI, SCLK, 1.6 < VPWI < 3.6 VIH_PWI Input High Voltage, PWI SPWI, SCLK, 1.6 < VPWI < 3.6 70 fSCLK PWI2 SCLK **DC useful for testing/debug 0 SPWI, SCLK V µA 5 0.5 1.1 V V 30 15M % of VPWI Hz LOGIC AND CONTROL OUTPUTS VOL Output Low Level CNTL_EN, ISINK ≤ 100 µA 0.4 VOH Output High Level CNTL_EN, ISOURCE ≤ 100 µA VDD 0.4 VOH_PWI Output High Level, PWI SPWI, ISOURCE ≤ 1mA VPWI 0.4 4 Submit Documentation Feedback V Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 LM10000 www.ti.com SNVS643C – JUNE 2010 – REVISED APRIL 2013 BLOCK DIAGRAM UVLO VDD Slew Rate Control CNTL_EN Ready CONTROL IDAC IAVS IDAC IAVS_MIRROR VPWI FLT_N ADDR Slave Power Controller (SPC 2) SPWI SCLK RESET_N + - 1.3V EN_BIAS Precision Enable Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 5 LM10000 SNVS643C – JUNE 2010 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS EN_BIAS to CNTL_EN Delay (CONTROL held HIGH) CONTROL to CNTL_EN Delay (EN_BIAS held HIGH) CONTROL EN_BIAS 2V/DIV 2V/DIV CNTL_EN CNTL_EN 200 ns/DIV 50 Ps/DIV 6 Figure 2. Figure 3. VOUT Reset by FLT_N Trigger IAVS Slew Rate Programmability Figure 4. Figure 5. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 LM10000 www.ti.com SNVS643C – JUNE 2010 – REVISED APRIL 2013 LM10000 PWI REGISTER MAP The PWI 2.0 standard defines 32 8-bit base registers, and up to 256 8-bit extended registers, on each PWI slave. The table below summarizes these registers and shows default register bit values after reset, as programmed by the factory. The following sub-sections provide additional details on the use of each individual register. Table 1. SUMMARY (1) Base Registers Register Address Register Name Register Usage Typ e 0x00 R0 IAVS R/W 0* 0x03 R3 R/O 0 0 0 0 0x04 R4 R/O 0 0 0 0 (1) Device Capability Reset Default Value 7 6 5 4 3 2 1 0 1 1 1 FLT_N 0 0 1 0 Configured by R9 0x09 R9 IAVS Default R/W 0x0A R10 Ramp Control R/W IAVS Default Code 1 0 0 1 1 1 0 0 0x0F R15 Revision ID N/A 0 0 0 0 0 0 0 0 0x1F R31 Reserved Do not write to R/W - - - - - - - - A bit with an asterisk (*) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. A bit with a hyphen (-) denotes a bit in an unimplemented register location. A write into unimplemented register(s) will be ignored. A read of an unimplemented register(s) will produce a “No response frame”. Please refer to PWI specification version 2.0 for further information. R0 - IAVS AVS FEEDBACK CURRENT INJECTION Address 0x00 Type R/W Reset Default 8h'7F Bit Field Name 7 Description or Comment Sign This bit is fixed to '0'. Reading this bit will result in a '0'. Any data written into this bit position using the Register Write command is ignored. Programmed voltage value. Default value is in bold. Current Data Code [6:0] 6:0 IAVS Sourcing Current Current (µA) 7h'00 60 7h'xx Linear Scaling 7h'7F 0 (default) R3 - STATUS LM10520 ADDRESS Address 0x03 Type R/O Reset Default – Bit Field Name Description or Comment 7:4 Not Used Always read back 0 3:1 Not Used Always read back 1 FLT_N 1: FLT_N is high (no fault) 0: FLT_N is low (fault) 0 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 7 LM10000 SNVS643C – JUNE 2010 – REVISED APRIL 2013 www.ti.com R4 - DEVICE CAPABILITY REGISTER Address 0x04 Type R/O Reset Default 8h'02 Bit Field Name Description or Comment 7:3 Always read back 0 2:0 Always read back 010, specifying PWI 2.0 R9 - IAVS DEFAULT REGISTER Address 0x09 Type R/W Reset Default 8h'7F Bit Field Name 7 Sign Description or Comment Always read back 0. Current Data Code [6:0] 6:0 Current (µA) 7h'00 60 7h'xx Linear Scaling 7h'7F 0 (Default) IAVS Default R10 - RAMP CONTROL Address 0x0A Type R/W Reset Default 8h'9C Bit Field Name Description or Comment 7 Ramp Control Enable 1: Enabled 0: Disabled 6 Not Used Always read 0 Ramp Time Step Control Ramp Time Step Control 5:3 0 0 0 0 1 1 1 1 2:0 Ramp Code Step Control 0 1 0 1 0 1 0 1 Ramp Code Step 0 0 0 0 1 1 1 1 8 Ramp Time Step (µs) 0 0 1 1 0 0 1 1 1 2 3 4 6 8 12 16 Rising Step (LSB) 0 0 1 1 0 0 1 1 Submit Documentation Feedback 0 1 0 1 0 1 0 1 1 2 3 4 6 8 12 16 Falling Step (LSB) 1 1 2 3 4 5 6 8 Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 LM10000 www.ti.com SNVS643C – JUNE 2010 – REVISED APRIL 2013 R15 - REVISION ID REGISTER Address 0x0F Type R/O Reset Default 8h'00 Bit Field Name 7:0 Description or Comment Always read back 0 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 9 LM10000 SNVS643C – JUNE 2010 – REVISED APRIL 2013 www.ti.com OPERATION DESCRIPTION GENERAL DESCRIPTION The LM10000 provides all the circuitry needed to enable most DC/DC regulators to work in a PowerWise® Adaptive Voltage Scaling (AVS) system. It communicates via the PowerWise Interface (PWI), and has analog outputs to control the output voltage of a slave power regulator. The slave power regulator can be any device that sets its output voltage with a feedback resistor divider. THEORY OF OPERATION The LM10000 can be thought of as a D/A converter, converting PWI communication to analog outputs. One of the outputs is a current DAC (IAVS), which is connected to the feedback node of a slave regulator. Therefore, all PWI Change Voltage Commands (CVC) are decoded into a 7-bit current DAC output. The impedance of the feedback node at DC appears as the top feedback resistor. This is because the control loop of the slave regulator effectively maintains a constant current/voltage across the bottom feedback resistor, and creates low impedance at the VOUT node. Therefore, as more current is sourced into the feedback node, the more the output voltage is reduced. See Figure 6. Slave Regulator VOUT + + FB IRFB1 RFB1 LM10000 IAVS VRFB1 - + - VOUT IAVS LM10000 + RFB2 PWI IAVS IRFB2 VFB - - Figure 6. Output Voltage Is Controlled Via current Injection Into Feedback Node DIGITAL POWER MANAGEMENT In addition to adaptive voltage scaling, the PWI and LM10000 enhance the slave regulator with basic digital power management control. This includes control of power states such as SHUTDOWN, SLEEP, and ACTIVE, ON/OFF sequencing, and voltage scaling slew rate. Figure 7 shows the LM10000 with available system connectivity options. The LM10000 has a flexible set of logic enable pins to allow the system easy interface to power states and sequencing. A logic CNTL_EN output is provided to drive the slave regulator enable according the power state of the LM10000. For example, if a PWI SHUTDOWN command is issued to LM10000, the CNTL_EN output is immediately driven to 0V, which if connected to the slave regulator enable input, will turn off the output voltage and enter a low Iq state. A summary of the logic inputs and outputs is given is LOGIC INPUTS AND OUTPUTS table. 10 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 LM10000 www.ti.com SNVS643C – JUNE 2010 – REVISED APRIL 2013 LM10000 Logic output for enabling slave regulator Slave Regulator CNTL_EN (Non AVS) IAVS VDD FB ASIC RTN AVS APC2 SCLK PWI 2.0 SPWI System uC EN_BIAS RESETN Logic inputs for Vout sequencing control CONTROL FLTN Figure 7. LM10000 provides flexible digital power management via multi-master PWI 2.0, and flexible VOUT sequencing control IAVS OUTPUT CURRENT: CONTROLLING THE OUTPUT VOLTAGE The LM10000 uses a 7-bit current DAC to control the output voltage of a slave power regulator. Since it is a current output, IAVS can be connected directly to the feedback node of the slave power regulator. IAVS has a range of 0 – 60 µA with 7 bits of resolution, or a 0.469 µA LSB. A typical connection of the IAVS injection current into a slave regulator is shown in Figure 8. The output voltage VOUT is expressed as: VOUT = VFB x §1 + © RFB1 · - IAVS x RFB1 RFB2 ¹ (1) Where VFB = the regulated feedback voltage of the slave regulator. This equation is valid for VOUT > VFB. Slave DC/DC VOUT FB RFB1 LM10000 RFB2 IAVS Figure 8. IAVS Injection Current Into A Slave Regulator Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 11 LM10000 SNVS643C – JUNE 2010 – REVISED APRIL 2013 www.ti.com USING REGISTER R9 TO CHANGE THE DEFAULT OUTPUT VOLTAGE The LM10000 default IAVS current is set by R9. R9 is trimmed to 0x7F, so that IAVS = 0µA when power is applied to LM10000. Between power cycling, R9 can be changed so that IAVS defaults to values between 0 - 60 µA. This can be useful for software trim of the default output voltage of the LM10000 controlled regulator. In order to do this, the system must take care to write to R9 before enabling the output (the output can be enabled/disabled while keeping the LM10000 logic on via the CONTROL input). Therefore, R9 must be written to by some system controller that is on a different power domain than that provided by LM10000. In addition, the “INITIAL_VDD” register in the Advanced Power Controller (APC) must have the same value as R9 so that the APC and LM10000 default to the same voltage code. IAVS MIRROR OUTPUT CURRENT IAVS Mirror sources a current equal to IAVS. DIGITAL SLEW RATE CONTROL The IAVS and IAVS Mirror outputs have an adjustable, digital slew rate control. The slew rate control is programmed in register R10. The slew rate of the output voltage will effect both the output and input inrush current needed to scale the output voltage up or down. The amount of output current source or sink needed to scale the output voltage is governed by the equation describing current in a capacitor: iC = C x dV/dt (2) Therefore, more current is needed for larger voltage steps (dV) and for smaller settling times (dt). This current is in addition to the load current that the slave regulator is providing. It is recommended that the total current (load current + voltage slew current) not exceed the slave regulator current limit. Single PWI Core Voltage Adjust Command (value) Code Step Time Step Figure 9. Digital Slew Rate Control PWI ADDRESS A resistor from the ADDR pin to ground sets the device's PWI address. The device senses the resistance as it is initializing from the shutdown state. The device will not update the address until it cycles through shutdown again. Use the table below to choose the appropriate resistor to place form ADDR pin to ground. 12 PWI Address Resistance (± 1% tolerance) 0 ≤ 40.2 kΩ 1 60.4 kΩ 2 80.6 kΩ 3 100 kΩ 4 120 kΩ 5 140 kΩ 6 160 kΩ 7 180 kΩ Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 LM10000 www.ti.com SNVS643C – JUNE 2010 – REVISED APRIL 2013 INPUTS: ENBIAS, CONTROL, FLT_N, RESET_N, SCLK, SPWI ENBIAS The ENBIAS logic input enables the internal circuitry of the LM10000. The LM10000 goes through an initialization procedure upon the rising edge of ENBIAS. Initialization is complete within 100 µsec, after which the device is ready to be used. If at any point ENBIAS goes low, the device enters a low Iq shutdown state. CONTROL The CONTROL logic input allows control of the CNTL_EN output without incurring delays associated with initialization. This signal is effectively ANDed with the internal ‘ready’ signal, which is high once initialization is complete. The CONTROL pin level toggles the device between Active and Sleep states, and will reset the R0 register FLT_N The FLT_N logic input resets and holds the R0 register when its input signal is low. It has no effect on CNTL_EN. This provides a convenient way to support automatic fault recovery modes in the slave power regulator. When connected to a standard PWGD pin of a DC/DC regulator, FLT_N will reset and hold R0 as long as PWGD is low, allowing the slave regulator to recover from the fault by returning to the default voltage. Once FLT_N returns high, R0 can be written to. RESET_N The RESET_N provides a separate, level controlled logic reset. SCLK and SPWI SCLK and SPWI provide serial PWI communication OUTPUTS: CNTL_EN, IAVS CNTL_EN The CNTL_EN output connects to the slave regulator enable pin. CNTL_EN allows power state control via the PWI interface or ENBIAS/CONTROL logic inputs. For a direct connection from CNTL_EN to the enable pin of the slave regulator, the enable pin on the slave regulator needs to be level based and active high (a logic high voltage enables the slave regulator). LM10000 will drive CNTL_EN to the VDD voltage to enable the slave regulator, and to 0V to disable the slave regulator. In the case that the enable/disable on the slave regulator is a different function (impedance based or active low), extra circuitry is required. UVLO The LM10000 includes a UVLO circuit with hysteresis that triggers off of VDD. The system designer should be aware of the different UVLO thresholds of LM10000 and the slave regulator it is controlling. Since LM10000 is controlling the output of the slave regulator, the UVLO circuits in both the LM10000, and the slave regulator can react to severe input voltage transients. This is normally not a problem unless the application is operating very close to the UVLO thresholds of the two devices. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 13 LM10000 SNVS643C – JUNE 2010 – REVISED APRIL 2013 www.ti.com STATES STARTUP During the startup state, the LM10000 initializes all its registers and enables its bandgap. This process typically takes 100 µsec. CNTL_EN is low during startup. ACTIVE During the active state, CNTL_EN is high, the IAVS DACs are enabled, and PWI registers can be accessed. SLEEP During the sleep state, CNTL_EN is low, the IAVS DACs are disabled, and PWI registers can be accessed. FAULT During the fault state, the IAVS current register (R0) is reset, after which the LM10000 automatically returns to its previous state. SHUTDOWN During the shutdown state, CNTL_EN is low, the IAVS DACs are disabled, and most internal circuitry is disabled. Only the PWI state machine is biased to allow register access. Pin State ENBIAS Falling Edge ENBIAS Rising Edge Shutdown CNTL_EN = 0 Low iq state RESET Cmd Startup CNTL_EN = 0 Shutdown Cmd Shutdown Cmd CONTROL = 0 CONTROL = 0 Wakeup Cmd (Reset R0) CONTROL = 1 (Reset R0) SLEEP CNTL_EN = 0 CONTROL = 1 Active CNTL_EN = 1 CONTROL = 0 Sleep Cmd FLTN = 1 FLTN = 0 FLTN = 0 FLTN = 1 Fault Reset and hold R0 Figure 10. LM10000 State Diagram 14 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 LM10000 www.ti.com SNVS643C – JUNE 2010 – REVISED APRIL 2013 APPLICATION CIRCUITS VIN CVIN VIN VIN RVIN 5V RFBT VDD NBASE RFBB RFF CFF VCC CIN VIN CVCC DBOOT1 SNSP SNSM SNSM VDIF FB SW1 COMP CS1 LG1 CHF CBOOT1 PGOOD RFRQ1 CSM FAULT QB1 FREQ VIN HG2 QT2 L2 ASIC/FPGA RDCR2 CDCR2 SW2 SYNC SYNCOUT CBOOT2 CS2 EN PGND PH LM3754 SGND LG2 TRACK/SS IAVE LM3753 CSS DBOOT2 BOOT2 CFRQ1 TRACK L1 RDCR1 CDCR1 LM3753/54 RPGD PGOOD QT1 HG1 RCOMP CCOMP VEXT CVDD1 VIN BOOT1 SNSP QB2 VOUT RILIM1 0.6 ± 1.2 V 40 ± 60 A ILIM VDD SNSP COUT CAV1 RAV1 SNSM RTN 5V AVS LM10000 VPWI VDD CNTLEN SPWI FLTN SCLK IAVS RESET! ADDR GND CONTROL ENBIAS V I/O APC 2 System Enable Control Figure 11. 60A AVS solution using LM10000 paired with LM3573/4 2-Phase Controller Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 15 LM10000 SNVS643C – JUNE 2010 – REVISED APRIL 2013 13.2k www.ti.com 6.6k LMZ10505 0.8V - 1.2V 5A FB EN ASIC/FPGA VIN VDD VOUT + CIN 47 PF COUT 47 PF GND 5V RTN AVS LM10000 VDD VPWI FLTN SPWI CNTLEN IAVS ADDR GND V I/O SCLK APC 2 RESET! CONTROL ENBIAS System Enable Control Figure 12. 5A AVS solution LM10000 paired with LMZ10505 Simple Switcher Module 16 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 LM10000 www.ti.com SNVS643C – JUNE 2010 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision B (April 2013) to Revision C • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 16 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM10000 17 PACKAGE OPTION ADDENDUM www.ti.com 22-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM10000SD/NOPB ACTIVE WSON NHK 14 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 10000SD LM10000SDE/NOPB ACTIVE WSON NHK 14 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 10000SD LM10000SDX/NOPB ACTIVE WSON NHK 14 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 10000SD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LM10000SD/NOPB WSON NHK 14 LM10000SDE/NOPB WSON NHK LM10000SDX/NOPB WSON NHK SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 3.3 4.3 1.0 8.0 12.0 Q1 14 250 178.0 12.4 3.3 4.3 1.0 8.0 12.0 Q1 14 4500 330.0 12.4 3.3 4.3 1.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM10000SD/NOPB WSON NHK 14 1000 210.0 185.0 35.0 LM10000SDE/NOPB WSON NHK 14 250 210.0 185.0 35.0 LM10000SDX/NOPB WSON NHK 14 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NHK0014A SDA14A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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