Microsemi A1240A-PLG176M Act 2 family fpgas Datasheet

Revision 8
ACT 2 Family FPGAs
Features
• Up to 8,000 Gate Array Gates
(20,000 PLD equivalent gates)
• Replaces up to 200 TTL Packages
• Replaces up to eighty 20-Pin PAL® Packages
• Design Library with over 500 Macro Functions
• Single-Module Sequence Functions
• Wide-Input Combinatorial Functions
• Up to 1,232 Programmable Logic Modules
• Up to 998 Flip-Flops
• Datapath Performance at 105 MHz
• 16-Bit Accumulator Performance to 39 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 50 MHz
• Two High-Speed, Low-Skew Clock Networks
• I/O Drive to 10 mA
• Nonvolatile, User Programmable
• Logic Fully Tested Prior to Shipment
• 1.0 micron CMOS Technology
Table 1 • ACT 2 Product Family Profile
Device
A1225A
A1240A
A1280A
Gate Array Equivalent Gates
2,500
4,000
8,000
PLD Equivalent Gates
6,250
10,000
20,000
63
100
200
Capacity
TTL Equivalent Package
20-Pin PAL Equivalent Packages
Logic Modules
25
40
80
451
684
1,232
S-Module
231
348
624
C-Module
220
336
608
382
568
998
Horizontal Tracks/Channel
36
36
36
Vertical Tracks/Channel
15
15
15
250,000
400,000
750,000
83
104
140
16-Bit Prescaled Counters
105 MHz
100 MHz
85 MHz
16-Bit Loadable Counters
70 MHz
69 MHz
67 MHz
16-Bit Accumulators
39 MHz
38 MHz
36 MHz
PG100
PL84
PQ100
VQ100
PG132
PL84
PQ144
–
TQ176
–
PG176
PL84
PQ160
–
TQ176
CQ172
Flip-Flops (maximum)
Routing Resources
PLICE Antifuse Elements
User I/Os (maximum)
1
Performance
Packages2
CPGA
PLCC
PQFP
VQFP
TQFP
CQFP
–
–
Notes:
1. Performance is based on –2 speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1,
Version 1.2, dated 3-28-93. Any analysis is not endorsed by PREP.
2. See the "Product Plan" on page III for package availability.
January 2012
© 2012 Microsemi Corporation
I
ACT 2 Family FPGAs
Ordering Information
A1280
A
_
PG
1
G
176
C
Application (T emperature Range)
C = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
PL = Plastic J-Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
CQ = Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% faster than Standard
–2 = Approximately 25% faster than Standard
Die Revision
A = 1.0 μm CMOS Process
Part Number
A1225 = 2,500 Gates
A1240 = 4,000 Gates
A1280 = 8,000 Gates
II
R ev i si o n 8
ACT 2 Family FPGAs
Product Plan
Speed Grade1
Device/Package
Application1
Std.
–1
–2
C
I
M
B
84-Pin Plastic Leaded Chip Carrier (PL)
✓
✓
✓
✓
✓
–
–
100-Pin Plastic Quad Flatpack (PQ)
✓
✓
✓
✓
✓
–
–
100-Pin Very Thin Quad Flatpack (VQ)
✓
✓
✓
✓
–
–
–
100-Pin Ceramic Pin Grid Array (PG)
✓
✓
✓
✓
–
–
–
84-Pin Plastic Leaded Chip Carrier (PL)
✓
✓
✓
✓
✓
–
–
132-Pin Ceramic Pin Grid Array (PG)
✓
✓
✓
✓
–
✓
✓
144-Pin Plastic Quad Flat Pack (PQ)
✓
✓
✓
✓
✓
–
–
176-Pin Thin (1.4 mm) Quad Flat Pack (TQ)
✓
✓
✓
✓
–
–
–
160-Pin Plastic Quad Flatpack (PQ)
✓
✓
✓
✓
✓
–
–
172-Pin Ceramic Quad Flatpack (CQ)
✓
✓
✓
✓
–
✓
✓
176-Pin Ceramic Pin Grid Array (PG)
✓
✓
✓
✓
–
✓
✓
176-Pin Thin (1.4 mm) Quad Flat Pack (TQ)
✓
✓
✓
✓
–
–
–
A1225A Device
A1240A Device
A1280A Device
Notes:
1. Applications:
C = Commercial
I = Industrial
M = Military
B = MIL-STD-883
Speed Grade:
–1 = Approx. 15% faster than Std.
–2 = Approx. 25% faster than Std.
Availability:
✓ = Available
P = Planned
– = Not planned
2. Contact your Microsemi SoC Products Group sales representative for product availability.
Device Resources
User I/Os
Device
Series
Logic
Modules
Gates
PG176
PG132
PG100
PQ160
PQ144
PQ100
PL84
CQ172
TQ176
VQ100
A1225A
451
2,500
–
–
83
–
–
83
72
–
–
83
A1240A
684
4,000
–
104
–
–
104
–
72
–
104
–
A1280A
1,232
8,000
140
–
–
125
–
–
72
140
140
–
Contact your local Microsemi SoC Products Group representative for device availability:
http://www.microsemi.com/soc/contact/default.aspx.
R e visi on 8
III
ACT 2 Family FPGAs
Table of Contents
ACT 2 Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Detailed Specifications
Operating Conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
ACT 2 Timing Model1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Package Pin Assignments
PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
PQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
CQ172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
PG100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
PG132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
PG176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Revision 8
IV
1 – ACT 2 Family Overview
General Description
The ACT 2 family represents Actel’s second generation of field programmable gate arrays
(FPGAs). The ACT 2 family presents a two-module architecture, consisting of C-modules and Smodules. These modules are optimized for both combinatorial and sequential designs. Based on Actel’s
patented channeled array architecture, the ACT 2 family provides significant enhancements to gate
density and performance while maintaining downward compatibility with the ACT 1 design environment
and upward compatibility with the ACT 3 design environment. The devices are implemented in silicon
gate, 1.0-μm, two-level metal CMOS, and employ Actel’s PLICE® antifuse technology. This revolutionary
architecture offers gate array design flexibility, high performance, and fast time-to-production with user
programming. The ACT 2 family is supported by the Designer and Designer Advantage Systems, which
offers automatic pin assignment, validation of electrical and design rules, automatic placement and
routing, timing analysis, user programming, and diagnostic probe capabilities. The systems are
supported on the following platforms: 386/486™ PC, Sun™, and HP™ workstations. The systems
provide CAE interfaces to the following design environments: Cadence, Viewlogic®, Mentor Graphics®,
and OrCAD™.
Revision 8
1 -1
2 – Detailed Specifications
Operating Conditions
Table 2-1 • Absolute Maximum Ratings1
Symbol
Parameter
VCC
DC supply voltage
VI
Input voltage
VO
Output voltage
IIO
I/O source sink current
TSTG
Storage temperature
Limits
Units
–0.5 to +7.0
V
–0.5 to VCC + 0.5
V
–0.5 to VCC + 0.5
V
±20
mA
–65 to +150
°C
2
Notes:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be
operated outside the recommended operating conditions.
2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater
than VCC + 0.5 V for less than GND –0.5 V, the internal protection diodes will be forward biased and can draw
excessive current.
Table 2-2 • Recommended Operating Conditions
Parameter
Temperature range*
Power supply tolerance
Commercial
Industrial
Military
Units
0 to +70
–40 to +85
–55 to +125
°C
±5
±10
±10
%VCC
Note: *Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military.
Revision 8
2 -1
Detailed Specifications
Table 2-3 • Electrical Specifications
Commercial
Symbol
Military
Min.
Max.
Min.
Max.
Min.
Max.
Units
2.4
–
–
–
–
–
V
(IOH = –6 mA)
3.84
–
–
–
–
–
V
(IOH = –4 mA)
–
–
3.7
–
3.7
–
V
(IOL = 10 mA)2
–
0.5
–
–
–
–
V
(IOL = 6 mA)
–
0.33
–
0.40
–
0.40
V
VIL
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
VIH
2.0
VCC + 0.3
2.0
VCC + 0.3
2.0
VCC + 0.3
V
–
500
–
500
–
500
ns
CIO I/O capacitance
–
10
–
10
–
10
pF
Standby Current, ICC4 (typical = 1 mA)
–
2
–
10
–
20
mA
–10
+10
–10
+10
–10
+10
µA
1
VOH
VOL1
Parameter
Industrial
(IOH = –10 mA)
2
Input Transition Time tR, tF2
2,3
Leakage
ICC(D)
Current5
Dynamic VCC supply current. See the Power Dissipation section.
Notes:
1.
2.
3.
4.
Only one output tested at a time. VCC = minimum.
Not tested, for information only.
Includes worst-case PG176 package capacitance. VOUT = 0 V, f = 1 MHz
All outputs unloaded. All inputs = VCC or GND, typical ICC = 1 mA. ICC limit includes IPP and ISV during normal
operations.
5. VOUT, VIN = VCC or GND.
2-2
R e vi s i o n 8
ACT 2 Family FPGAs
Package Thermal Characteristics
The device junction to case thermal characteristic is θjc, and the junction to ambient air characteristic is
θja. The thermal characteristics for θja are shown with two different air flow rates.
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power dissipation allowed for a PQ160 package at
commercial temperature and still air is as follows:
150°C – 70°C
Max.
junction temp. (°C) – Max. ambient temp. (°C)-------------------------------------------------------------------------------------------------------------------------------------= ------------------------------------ = 2.4 W
33°C/W
θ ja °C/W
EQ 1
Table 2-4 • Package Thermal Characteristics
Pin Count
θjc
θja
Still Air
θja
300 ft./min.
Units
100
5
35
17
°C/W
132
5
30
15
°C/W
176
8
23
12
°C/W
Ceramic Quad Flatpack
172
8
25
15
°C/W
Plastic Quad Flatpack1
100
13
48
40
°C/W
144
15
40
32
°C/W
160
15
38
30
°C/W
Plastic Leaded Chip Carrier
84
12
37
28
°C/W
Very Thin Quad Flatpack
100
12
43
35
°C/W
Thin Quad Flatpack
176
15
32
25
°C/W
Package Type*
Ceramic Pin Grid Array
Notes: (Maximum Power in Still Air)
1. Maximum power dissipation values for PQFP packages are 1.9 W (PQ100), 2.3 W (PQ144), and 2.4 W
(PQ160).
2. Maximum power dissipation for PLCC packages is 2.7 W.
3. Maximum power dissipation for VQFP packages is 2.3 W.
4. Maximum power dissipation for TQFP packages is 3.1 W.
Power Dissipation
P = [ICC standby + ICCactive] * VCC + IOL * VOL * N + IOH* (VCC – VOH) * M
EQ 2
where:
ICC standby is the current flowing when no inputs or outputs are changing
ICCactive is the current flowing due to CMOS switching.
IOL and IOH are TTL sink/source currents.
VOL and VOH are TTL level output voltages.
N is the number of outputs driving TTL loads to VOL.
M is the number of outputs driving TTL loads to VOH.
An accurate determination of N and M is problematical because their values depend on the family type,
design details, and on the system I/O. The power can be divided into two components: static and active.
Revision 8
2 -3
Detailed Specifications
Static Power Component
Microsemi FPGAs have small static power components that result in lower power dissipation than PALs
or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level
power dissipation can be achieved.
The power due to standby current is typically a small component of the overall power. Standby power is
calculated in Table 2-5 for commercial, worst case conditions.
Table 2-5 • Standby Power Calculation
ICC
2 mA
VCC
Power
5.25 V
10.5 mW
The static power dissipated by TTL loads depends on the number of outputs driving high or low and the
DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33 V will
generate 42 mW with all outputs driving low, and 140 mW with all outputs driving high. The actual
dissipation will average somewhere between as I/Os switch states with time.
Active Power Component
Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This
component is frequency dependent, a function of the logic and the external I/O. Active power dissipation
results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module
inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs.
An additional component of the active power dissipation is the totem-pole current in CMOS transistor
pairs. The net effect can be associated with an equivalent capacitance that can be combined with
frequency and voltage to represent active power dissipation.
Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by EQ 3.
Power (µW) = CEQ * VCC2 * F
EQ 3
Where:
CEQ is the equivalent capacitance expressed in pF.
VCC is the power supply in volts.
F is the switching frequency in MHz.
Equivalent capacitance is calculated by measuring ICC active at a specified frequency and voltage for
each circuit component of interest. Measurements have been made over a range of frequencies at a
fixed value of VCC. Equivalent capacitance is frequency independent so that the results may be used
over a wide range of operating conditions. Equivalent capacitance values are shown in Table 2-6.
Table 2-6 • CEQ Values for Microsemi FPGAs
Item
2-4
CEQ Value
Modules (CEQM)
5.8
Input Buffers (CEQI)
12.9
Output Buffers (CEQO)
23.8
Routed Array Clock Buffer Loads (CEQCR)
3.9
R e vi s i o n 8
ACT 2 Family FPGAs
To calculate the active power dissipated from the complete design, the switching frequency of each part
of the logic must be known. EQ 4 shows a piece-wise linear summation over all components.
Power =VCC2 * [(m * CEQM * fm)modules + (n * CEQI * fn) inputs
+ (p * (CEQO+ CL) * fp)outputs
+ 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1
+ 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2
EQ 4
Where:
m = Number of logic modules switching at fm
n = Number of input buffers switching at fn
p = Number of output buffers switching at fp
q1 = Number of clock loads on the first routed array clock
q2 = Number of clock loads on the second routed array clock
r1 = Fixed capacitance due to first routed array clock
r2 = Fixed capacitance due to second routed array clock
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in pF
CL = Output lead capacitance in pF
fm = Average logic module switching rate in MHz
fn = Average input buffer switching rate in MHz
fp = Average output buffer switching rate in MHz
fq1 = Average first routed array clock rate in MHz
fq2 = Average second routed array clock rate in MHz
Table 2-7 • Fixed Capacitance Values for Microsemi FPGAs
Device Type
r1, routed_Clk1
r2, routed_Clk2
A1225A
106
106.0
A1240A
134
134.2
A1280A
168
167.8
Revision 8
2 -5
Detailed Specifications
Determining Average Switching Frequency
To determine the switching frequency for a design, you must have a detailed understanding of the data
input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that
they can be generally used to predict the upper limits of power dissipation. These guidelines are given in
Table 2-8.
Table 2-8 • Guidelines for Predicting Power Dissipation
Data
2-6
Value
Logic Modules (m)
80% of modules
Inputs switching (n)
# inputs/4
Outputs switching (p)
# output/4
First routed array clock loads (q1)
40% of sequential modules
Second routed array clock loads (q2)
40% of sequential modules
Load capacitance (CL)
35 pF
Average logic module switching rate (fm)
F/10
Average input switching rate (fn)
F/5
Average output switching rate (fp)
F/10
Average first routed array clock rate (fq1)
F
Average second routed array clock rate (fq2)
F/2
R e vi s i o n 8
ACT 2 Family FPGAs
ACT 2 Timing Model1
Input Delays
I/O Module
Predicted
Routing
Delays
Internal Delays
t INYL= 2.6 ns
t IRD2= 4.8 ns(2)
Combinatorial
Logic Module
Output Delays
I/O Module
t DLH = 8.0 ns
D
Q
t RD1 = 1.4 ns
t RD2 = 1.7 ns
t RD4 = 3.1 ns
t RD8 = 4.7 ns
t PD = 3.8 ns
G
Combinatorial
Logic
Included
in tSUD
t CKH = 11.8 ns
tDLH = 8.0 ns
Sequential
Logic Module
t INH = 2.0 ns
t INSU = 4.0 ns
t INGL = 4.7 ns
ARRAY
CLOCKS
I/O Module
FO = 256
tSUD = 0.4 ns
t HD = 0.0 ns
D
D
Q
Q
t RD1 = 1.4 ns
tENHZ = 7.1 ns
G
t CO = 3.8 ns
t OUTH = 0.0 ns
tOUTSU = 0.4 ns
t GLH = 9.0 ns
F MAX = 100 MHz
Notes:
1. Values shown for A1240A-2 at worst-case commercial conditions.
2. Input module predicted routing delay
Figure 2-1 •
Timing Model
Revision 8
2 -7
Detailed Specifications
Parameter Measurement
E
D
VCC
In
50%
PAD
VOL
50%
VOH
PAD To AC test loads (shown below)
TRIBUFF
VCC
GND
E
1.5 V
1.5 V
50%
VCC
VCC
GND
50%
1.5 V
PAD
10%
VOL
tDHS,
Figure 2-2 •
tENZL
tDHS
E
50%
PAD
GND
50%
VOH
90%
1.5 V
tENZH
tENLZ
GND
tENHZ
Output Buffer Delays
Load 2
(Used to measure rising/falling edges)
Load 1
(Used to measure propagation delay)
VCC
GND
To the output under test
50 pF
To the output under test
R to VCC for tPLZ / tPZL
R to GND for tPHZ / tPZH
R = 1 kΩ
50 pF
Figure 2-3 •
AC Test Loads
PAD
Y
INBUF
3V
PAD
1.5 V 1.5 V
VCC
Y
GND
2-8
50%
50%
tINYH
Figure 2-4 •
0V
tINYL
Input Buffer Delays
R e vi s i o n 8
ACT 2 Family FPGAs
S
A
B
Y
VCC
S, A or B
50% 50%
VCC
Y
GND
50%
GND
50%
tPLH
tPHL
VCC
Y
GND
50%
tPHL
Figure 2-5 •
50%
tPLH
Module Delays
Sequential Module Timing Characteristics
D
E
CLK
Y
CLR
(Positive edge triggered)
tHD
D*
tSUD
tA
tWCLKA
G, CLK
tSUENA
tWCLKI
tHENA
E
tCO
Q
tRS
PRE, CLR
tWASYN
Note: D represents all data functions involving A, B, and S for multiplexed flip-flops.
Figure 2-6 • Flip-Flops and Latches
Revision 8
2 -9
Detailed Specifications
PAD
DATA
IBDL
G
PAD
CLK
CLKBUF
DATA
t INH
G
t INSU
t HEXT
CLK
t SUEXT
Figure 2-7 •
Input Buffer Latches
D
PAD
OBDLHS
G
D
tOUTSU
G
tOUTH
Figure 2-8 •
2- 10
Output Buffer Latches
R e visio n 8
ACT 2 Family FPGAs
Timing Derating Factor (Temperature and Voltage)
Table 2-9 • Timing Derating Factor (Temperature and Voltage)
(Commercial Minimum/Maximum Specification) x
Industrial
Military
Min.
Max.
Min.
0.69
1.11
0.67
Max.
1.23
Table 2-10 • Timing Derating Factor for Designs at Typical Temperature (TJ = 25°C)
and Voltage (5.0 V)
(Commercial Maximum Specification) x
0.85
Table 2-11 • Temperature and Voltage Derating Factors
(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)
–55
–40
0
25
70
85
125
4.50
0.75
0.79
0.86
0.92
1.06
1.11
1.23
4.75
0.71
0.75
0.82
0.87
1.00
1.05
1.13
5.00
0.69
0.72
0.80
0.85
0.97
1.02
1.13
5.25
0.68
0.69
0.77
0.82
0.95
0.98
1.09
5.50
0.67
0.69
0.76
0.81
0.93
0.97
1.08
1.3
D er at i n g Fac t o r
1.2
1.1
125˚C
1.0
85˚C
70˚C
0.9
25˚C
0.8
0˚C
–40˚C
–55˚C
0.7
0.6
4.504.755.005.255.50
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
Figure 2-9 • Junction Temperature and Voltage Derating Curves
(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)
Revision 8
2- 11
Detailed Specifications
A1225A Timing Characteristics
Table 2-12 • A1225A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
Logic Module Propagation Delays1
–2 Speed3
Parameter/Description
Min.
Max.
–1 Speed
Min.
Max.
Std. Speed
Min.
Units
Max.
tPD1
Single Module
3.8
4.3
5.0
ns
tCO
Sequential Clock to Q
3.8
4.3
5.0
ns
tGO
Latch G to Q
3.8
4.3
5.0
ns
tRS
Flip-Flop (Latch) Reset to Q
3.8
4.3
5.0
ns
Predicted Routing Delays2
tRD1
FO = 1 Routing Delay
1.1
1.2
1.4
ns
tRD2
FO = 2 Routing Delay
1.7
1.9
2.2
ns
tRD3
FO = 3 Routing Delay
2.3
2.6
3.0
ns
tRD4
FO = 4 Routing Delay
2.8
3.1
3.7
ns
tRD8
FO = 8 Routing Delay
4.4
4.9
5.8
ns
Sequential Timing Characteristics
3,4
tSUD
Flip-Flop (Latch) Data Input Setup
0.4
0.4
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
0.8
0.9
1.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
4.5
5.0
6.0
ns
tWASYN
Flip-Flop (Latch) Clock Asynchronous Pulse Width
4.5
5.0
6.0
ns
tA
Flip-Flop Clock Input Period
9.4
11.0
13.0
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Setup
0.4
0.4
0.5
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Setup
0.4
0.4
0.5
ns
fMAX
Flip-Flop (Latch) Clock Frequency
105.0
90.0
75.0
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD —whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to
shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
2- 12
R e visio n 8
ACT 2 Family FPGAs
A1225A Timing Characteristics (continued)
Table 2-13 • A1225A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
I/O Module Input Propagation Delays
–2 Speed
Parameter/Description
Min.
Max.
–1 Speed
Min.
Max.
Std. Speed
Min.
Units
Max.
tINYH
Pad to Y High
2.9
3.3
3.8
ns
tINYL
Pad to Y Low
2.6
3.0
3.5
ns
tINGH
G to Y High
5.0
5.7
6.6
ns
tINGL
G to Y Low
4.7
5.4
6.3
ns
*
Input Module Predicted Input Routing Delays
tIRD1
FO = 1 Routing Delay
4.1
4.6
5.4
ns
tIRD2
FO = 2 Routing Delay
4.6
5.2
6.1
ns
tIRD3
FO = 3 Routing Delay
5.3
6.0
7.1
ns
tIRD4
FO = 4 Routing Delay
5.7
6.4
7.6
ns
tIRD8
FO = 8 Routing Delay
7.4
8.3
9.8
ns
FO = 32
10.2
11.0
12.8
ns
FO = 256
11.8
13.0
15.7
FO = 32
10.2
11.0
12.8
FO = 256
12.0
13.2
15.9
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
fMAX
Input Low to High
Input High to Low
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
Input Latch External Setup
Input Latch External Hold
Minimum Period
Maximum Frequency
FO = 32
3.4
4.1
4.5
FO = 256
3.8
4.5
5.0
FO = 32
3.4
4.1
4.5
FO = 256
3.8
4.5
5.0
ns
ns
FO = 32
0.7
0.7
0.7
FO = 256
3.5
3.5
3.5
FO = 32
0.0
0.0
0.0
FO = 256
0.0
0.0
0.0
FO = 32
7.0
7.0
7.0
FO = 256
11.2
11.2
11.2
FO = 32
7.7
8.3
9.1
FO = 256
8.1
8.8
10.0
ns
ns
ns
ns
ns
FO = 32
130.0
120.0
110.0
FO = 256
125.0
115.0
100.0
ns
Note: *These parameters should be used for estimating device performance. Optimization techniques may further
reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Postroute timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
Revision 8
2- 13
Detailed Specifications
A1225A Timing Characteristics (continued)
Table 2-14 • A1225A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
TTL Output Module Timing1
Parameter/Description
–2 Speed
Min.
Max.
–1 Speed
Min.
Max.
Std. Speed
Min.
Units
Max.
tDLH
Data to Pad High
8.0
9.0
10.6
ns
tDHL
Data to Pad Low
10.1
11.4
13.4
ns
tENZH
Enable Pad Z to High
8.9
10.0
11.8
ns
tENZL
Enable Pad Z to Low
11.6
13.2
15.5
ns
tENHZ
Enable Pad High to Z
7.1
8.0
9.4
ns
tENLZ
Enable Pad Low to Z
8.3
9.5
11.1
ns
tGLH
G to Pad High
8.9
10.2
11.9
ns
tGHL
G to Pad Low
11.2
12.7
14.9
ns
dTLH
Delta Low to High
0.07
0.08
0.09
ns/pF
dTHL
Delta High to Low
0.12
0.13
0.16
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
10.1
11.5
13.5
ns
tDHL
Data to Pad Low
8.4
9.6
11.2
ns
tENZH
Enable Pad Z to High
8.9
10.0
11.8
ns
tENZL
Enable Pad Z to Low
11.6
13.2
15.5
ns
tENHZ
Enable Pad High to Z
7.1
8.0
9.4
ns
tENLZ
Enable Pad Low to Z
8.3
9.5
11.1
ns
tGLH
G to Pad High
8.9
10.2
11.9
ns
tGHL
G to Pad Low
11.2
12.7
14.9
ns
dTLH
Delta Low to High
0.12
0.13
0.16
ns/pF
dTHL
Delta High to Low
0.09
0.10
0.12
ns/pF
Notes:
1. Delays based on 50 pF loading.
2. SSO information can be found at www.microsemi.com/soc/techdocs/appnotes/board_consideration.aspx.
2- 14
R e visio n 8
ACT 2 Family FPGAs
A1240A Timing Characteristics
Table 2-15 • A1240A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
Logic Module Propagation Delays1
–2 Speed3
Parameter/Description
Min.
Max.
–1 Speed
Min.
Max.
Std. Speed
Min.
Units
Max.
tPD1
Single Module
3.8
4.3
5.0
ns
tCO
Sequential Clock to Q
3.8
4.3
5.0
ns
tGO
Latch G to Q
3.8
4.3
5.0
ns
tRS
Flip-Flop (Latch) Reset to Q
3.8
4.3
5.0
ns
Predicted Routing Delays2
tRD1
FO = 1 Routing Delay
1.4
1.5
1.8
ns
tRD2
FO = 2 Routing Delay
1.7
2.0
2.3
ns
tRD3
FO = 3 Routing Delay
2.3
2.6
3.0
ns
tRD4
FO = 4 Routing Delay
3.1
3.5
4.1
ns
tRD8
FO = 8 Routing Delay
4.7
5.4
6.3
ns
Sequential Timing Characteristics
3,4
tSUD
Flip-Flop (Latch) Data Input Setup
0.4
0.4
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
0.8
0.9
1.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
4.5
6.0
6.5
ns
tWASYN
Flip-Flop (Latch) Clock Asynchronous Pulse Width
4.5
6.0
6.5
ns
tA
Flip-Flop Clock Input Period
9.8
12.0
15.0
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Setup
0.4
0.4
0.5
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Setup
0.4
0.4
0.5
ns
fMAX
Flip-Flop (Latch) Clock Frequency
100.0
80.0
66.0
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD —whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to
shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
Revision 8
2- 15
Detailed Specifications
A1240A Timing Characteristics (continued)
Table 2-16 • A1240A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
I/O Module Input Propagation Delays
–2 Speed
Parameter/Description
Min.
Max.
–1 Speed
Min.
Max.
Std. Speed
Min.
Units
Max.
tINYH
Pad to Y High
2.9
3.3
3.8
ns
tINYL
Pad to Y Low
2.6
3.0
3.5
ns
tINGH
G to Y High
5.0
5.7
6.6
ns
tINGL
G to Y Low
4.7
5.4
6.3
ns
*
Input Module Predicted Input Routing Delays
tIRD1
FO = 1 Routing Delay
4.2
4.8
5.6
ns
tIRD2
FO = 2 Routing Delay
4.8
5.4
6.4
ns
tIRD3
FO = 3 Routing Delay
5.4
6.1
7.2
ns
tIRD4
FO = 4 Routing Delay
5.9
6.7
7.9
ns
tIRD8
FO = 8 Routing Delay
7.9
8.9
10.5
ns
FO = 32
10.2
11.0
12.8
ns
FO = 256
11.8
13.0
15.7
FO = 32
10.2
11.0
12.8
FO = 256
12.0
13.2
15.9
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
fMAX
Input Low to High
Input High to Low
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
Input Latch External Setup
Input Latch External Hold
Minimum Period
Maximum Frequency
FO = 32
3.8
4.5
5.5
FO = 256
4.1
5.0
5.8
FO = 32
3.8
4.5
5.5
FO = 256
4.1
5.0
5.8
ns
ns
FO = 32
0.5
0.5
0.5
FO = 256
2.5
2.5
2.5
FO = 32
0.0
0.0
0.0
FO = 256
0.0
0.0
0.0
FO = 32
7.0
7.0
7.0
FO = 256
11.2
11.2
11.2
FO = 32
8.1
9.1
11.1
FO = 256
8.8
10.0
11.7
ns
ns
ns
ns
ns
FO = 32
125.0
110.0
90.0
FO = 256
115.0
100.0
85.0
ns
Note: *These parameters should be used for estimating device performance. Optimization techniques may further
reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Postroute timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
2- 16
R e visio n 8
ACT 2 Family FPGAs
A1240A Timing Characteristics (continued)
Table 2-17 • A1240A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
TTL Output Module Timing1
Parameter/Description
–2 Speed
Min.
Max.
–1 Speed
Min.
Max.
Std. Speed
Min.
Units
Max.
tDLH
Data to Pad High
8.0
9.0
10.6
ns
tDHL
Data to Pad Low
10.1
11.4
13.4
ns
tENZH
Enable Pad Z to High
8.9
10.0
11.8
ns
tENZL
Enable Pad Z to Low
11.7
13.2
15.5
ns
tENHZ
Enable Pad High to Z
7.1
8.0
9.4
ns
tENLZ
Enable Pad Low to Z
8.4
9.5
11.1
ns
tGLH
G to Pad High
9.0
10.2
11.9
ns
tGHL
G to Pad Low
11.2
12.7
14.9
ns
dTLH
Delta Low to High
0.07
0.08
0.09
ns/pF
dTHL
Delta High to Low
0.12
0.13
0.16
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
10.2
11.5
13.5
ns
tDHL
Data to Pad Low
8.4
9.6
11.2
ns
tENZH
Enable Pad Z to High
8.9
10.0
11.8
ns
tENZL
Enable Pad Z to Low
11.7
13.2
15.5
ns
tENHZ
Enable Pad High to Z
7.1
8.0
9.4
ns
tENLZ
Enable Pad Low to Z
8.4
9.5
11.1
ns
tGLH
G to Pad High
9.0
10.2
11.9
ns
tGHL
G to Pad Low
11.2
12.7
14.9
ns
dTLH
Delta Low to High
0.12
0.13
0.16
ns/pF
dTHL
Delta High to Low
0.09
0.10
0.12
ns/pF
Notes:
1. Delays based on 50 pF loading.
2. SSO information can be found at www.microsemi.com/soc/techdocs/appnotes/board_consideration.aspx.
Revision 8
2- 17
Detailed Specifications
A1280A Timing Characteristics
Table 2-18 • A1280A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
Logic Module Propagation Delays1
–2 Speed3
Parameter/Description
Min.
Max.
–1 Speed
Min.
Max.
Std. Speed
Min.
Units
Max.
tPD1
Single Module
3.8
4.3
5.0
ns
tCO
Sequential Clock to Q
3.8
4.3
5.0
ns
tGO
Latch G to Q
3.8
4.3
5.0
ns
tRS
Flip-Flop (Latch) Reset to Q
3.8
4.3
5.0
ns
Predicted Routing Delays2
tRD1
FO = 1 Routing Delay
1.7
2.0
2.3
ns
tRD2
FO = 2 Routing Delay
2.5
2.8
3.3
ns
tRD3
FO = 3 Routing Delay
3.0
3.4
4.0
ns
tRD4
FO = 4 Routing Delay
3.7
4.2
4.9
ns
tRD8
FO = 8 Routing Delay
6.7
7.5
8.8
ns
Sequential Timing Characteristics
3,4
tSUD
Flip-Flop (Latch) Data Input Setup
0.4
0.4
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
0.8
0.9
1.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
5.5
6.0
7.0
ns
tWASYN
Flip-Flop (Latch) Clock Asynchronous Pulse Width
5.5
6.0
7.0
ns
tA
Flip-Flop Clock Input Period
11.7
13.3
18.0
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Setup
0.4
0.4
0.5
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Setup
0.4
0.4
0.5
ns
fMAX
Flip-Flop (Latch) Clock Frequency
85.0
75.0
50.0
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD —whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to
shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
2- 18
R e visio n 8
ACT 2 Family FPGAs
A1280A Timing Characteristics (continued)
Table 2-19 • A1280A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
I/O Module Input Propagation Delays
–2 Speed
Parameter/Description
Min.
Max.
–1 Speed
Min.
Max.
Std. Speed
Min.
Units
Max.
tINYH
Pad to Y High
2.9
3.3
3.8
ns
tINYL
Pad to Y Low
2.7
3.0
3.5
ns
tINGH
G to Y High
5.0
5.7
6.6
ns
tINGL
G to Y Low
4.8
5.4
6.3
ns
*
Input Module Predicted Input Routing Delays
tIRD1
FO = 1 Routing Delay
4.6
5.1
6.0
ns
tIRD2
FO = 2 Routing Delay
5.2
5.9
6.9
ns
tIRD3
FO = 3 Routing Delay
5.6
6.3
7.4
ns
tIRD4
FO = 4 Routing Delay
6.5
7.3
8.6
ns
tIRD8
FO = 8 Routing Delay
9.4
10.5
12.4
ns
FO = 32
10.2
11.0
12.8
ns
FO = 256
13.1
14.6
17.2
FO = 32
10.2
11.0
12.8
FO = 256
13.3
14.9
17.5
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
fMAX
Input Low to High
Input High to Low
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
Input Latch External Setup
Input Latch External Hold
Minimum Period
Maximum Frequency
FO = 32
5.0
5.5
6.6
FO = 256
5.8
6.4
7.6
FO = 32
5.0
5.5
6.6
FO = 256
5.8
6.4
7.6
ns
ns
FO = 32
0.5
0.5
0.5
FO = 256
2.5
2.5
2.5
FO = 32
0.0
0.0
0.0
FO = 256
0.0
0.0
0.0
FO = 32
7.0
7.0
7.0
FO = 256
11.2
11.2
11.2
FO = 32
9.6
11.2
13.3
FO = 256
10.6
12.6
15.3
ns
ns
ns
ns
ns
FO = 32
105.0
90.0
75.0
FO = 256
95.0
80.0
65.0
ns
Note: *These parameters should be used for estimating device performance. Optimization techniques may further
reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Postroute timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
A1280A Timing Characteristics (continued)
Revision 8
2- 19
Detailed Specifications
Table 2-20 • A1280A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
TTL Output Module Timing1
Parameter/Description
–2 Speed
Min.
Max.
–1 Speed
Min.
Max.
Std. Speed
Min.
Units
Max.
tDLH
Data to Pad High
8.1
9.0
10.6
ns
tDHL
Data to Pad Low
10.2
11.4
13.4
ns
tENZH
Enable Pad Z to High
9.0
10.0
11.8
ns
tENZL
Enable Pad Z to Low
11.8
13.2
15.5
ns
tENHZ
Enable Pad High to Z
7.1
8.0
9.4
ns
tENLZ
Enable Pad Low to Z
8.4
9.5
11.1
ns
tGLH
G to Pad High
9.0
10.2
11.9
ns
tGHL
G to Pad Low
11.3
12.7
14.9
ns
dTLH
Delta Low to High
0.07
0.08
0.09
ns/pF
dTHL
Delta High to Low
0.12
0.13
0.16
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
10.3
11.5
13.5
ns
tDHL
Data to Pad Low
8.5
9.6
11.2
ns
tENZH
Enable Pad Z to High
9.0
10.0
11.8
ns
tENZL
Enable Pad Z to Low
11.8
13.2
15.5
ns
tENHZ
Enable Pad High to Z
7.1
8.0
9.4
ns
tENLZ
Enable Pad Low to Z
8.4
9.5
11.1
ns
tGLH
G to Pad High
9.0
10.2
11.9
ns
tGHL
G to Pad Low
11.3
12.7
14.9
ns
dTLH
Delta Low to High
0.12
0.13
0.16
ns/pF
dTHL
Delta High to Low
0.09
0.10
0.12
ns/pF
Notes:
1. Delays based on 50 pF loading.
2. SSO information can be found at www.microsemi.com/soc/techdocs/appnotes/board_consideration.aspx.
2- 20
R e visio n 8
ACT 2 Family FPGAs
Pin Descriptions
CLKA
Clock A (Input)
TTL Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic
modules. This pin can also be used as an I/O.
CLKB
Clock B (Input)
TTL Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic
modules. This pin can also be used as an I/O.
DCLK
Diagnostic Clock (Input)
TTL Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is
High. This pin functions as an I/O when the MODE pin is Low.
GND
Ground
Low supply voltage.
I/O
Input/Output (Input, Output)
The I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output levels are
compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically driven Low
by the ALS software.
MODE
Mode (Input)
The MODE pin controls the use of multifunction pins (DCLK, PRA, PRB, SDI). When the MODE pin is
High, the special functions are active. When the MODE pin is Low, the pins function as I/Os. To provide
Actionprobe capability, the MODE pin should be terminated to GND through a 10K resistor so that the
MODE pin can be pulled High when required.
NC
No Connection
This pin is not connected to circuitry within the device.
PRA
Probe A (Output)
The Probe A pin is used to output data from any user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic
output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when
debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is active when the MODE pin is High. This pin functions as an
I/O when the MODE pin is Low.
PRB
Probe B (Output)
The Probe B pin is used to output data from any user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic
output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when
debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is active when the MODE pin is High. This pin functions as an
I/O when the MODE pin is Low.
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is High.
This pin functions as an I/O when the MODE pin is Low.
SDO
Serial Data Output (Output)
Serial data output for diagnostic probe. SDO is active when the MODE pin is High. This pin functions as
an I/O when the MODE pin is Low.
VCC
5.0 V Supply Voltage
High supply voltage.
Revision 8
2- 21
3 – Package Pin Assignments
PL84
11
10
9
8
7
6
5
4
3
2
1
84 83
82
81
80
79 78
77 76
75
12
74
13
73
14
72
15
71
16
70
17
69
18
68
19
67
20
66
21
65
84-Pin
PLCC
22
64
23
63
24
62
25
61
26
60
27
59
28
58
29
57
30
56
31
55
32
54
33
34 35
36
37
38 39
40
41 42
43 44 45
46
47
48
49 50
51 52
53
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.
Revision 8
3 -1
Package Pin Assignments
PL84
Pin Number
A1225A Function
A1240A Function
A1280A Function
2
CLKB, I/O
CLKB, I/O
CLKB, I/O
4
PRB, I/O
PRB, I/O
PRB, I/O
6
GND
GND
GND
10
DCLK, I/O
DCLK, I/O
DCLK, I/O
12
MODE
MODE
MODE
22
VCC
VCC
VCC
23
VCC
VCC
VCC
28
GND
GND
GND
43
VCC
VCC
VCC
49
GND
GND
GND
52
SDO
SDO
SDO
63
GND
GND
GND
64
VCC
VCC
VCC
65
VCC
VCC
VCC
70
GND
GND
GND
76
SDI, I/O
SDI, I/O
SDI, I/O
81
PRA, I/O
PRA, I/O
PRA, I/O
83
CLKA, I/O
CLKA, I/O
CLKA, I/O
84
VCC
VCC
VCC
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
3-2
R e vi s i o n 8
ACT 2 Family FPGAs
PQ100
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
50
82
49
83
48
84
47
85
46
86
45
87
44
88
43
89
42
100-Pin
90
41
PQFP
91
40
92
39
93
38
94
37
95
36
96
35
97
34
98
33
99
32
100
31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
Revision 8
3 -3
Package Pin Assignments
PQ100
PQ100
Pin Number
A1225A Function
Pin Number
A1225A Function
2
DCLK, I/O
65
VCC
4
MODE
66
VCC
9
GND
67
VCC
16
VCC
72
GND
17
VCC
79
SDI, I/O
22
GND
84
GND
34
GND
87
PRA, I/O
40
VCC
89
CLKA, I/O
46
GND
90
VCC
52
SDO
92
CLKB, I/O
57
GND
94
PRB, I/O
64
GND
96
GND
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
3-4
R e vi s i o n 8
ACT 2 Family FPGAs
PQ144
1
144
144-Pin
PQFP
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
Revision 8
3 -5
Package Pin Assignments
PQ144
PQ144
Pin Number
A1240A Function
Pin Number
A1240A Function
2
MODE
89
VCC
9
GND
90
VCC
10
GND
91
VCC
11
GND
92
VCC
18
VCC
93
VCC
19
VCC
100
GND
20
VCC
101
GND
21
VCC
102
GND
28
GND
110
SDI, I/O
29
GND
116
GND
30
GND
117
GND
44
GND
118
GND
45
GND
123
PRA, I/O
46
GND
125
CLKA, I/O
54
VCC
126
VCC
55
VCC
127
VCC
56
VCC
128
VCC
64
GND
130
CLKB, I/O
65
GND
132
PRB, I/O
71
SDO
136
GND
79
GND
137
GND
80
GND
138
GND
81
GND
144
DCLK, I/O
88
GND
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
3-6
R e vi s i o n 8
ACT 2 Family FPGAs
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
PQ160
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
160-Pin
PQFP
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Note: This is the top view of the package
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
Revision 8
3 -7
Package Pin Assignments
PQ160
PQ160
Pin Number
A1280A Function
Pin Number
A1280A Function
2
DCLK, I/O
69
GND
6
VCC
80
GND
11
GND
82
SDO
16
PRB, I/O
86
VCC
18
CLKB, I/O
89
GN
20
VCC
98
GND
21
CLKA, I/O
99
GND
23
PRA, I/O
109
GND
30
GND
114
VCC
35
VCC
120
GND
38
SDI, I/O
125
GND
40
GND
130
GND
44
GND
135
VCC
49
GND
138
VCC
54
VCC
139
VCC
57
VCC
140
GND
58
VCC
145
GND
59
GND
150
VCC
60
VCC
155
GND
61
GND
159
MODE
64
GND
160
GND
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
3-8
R e vi s i o n 8
ACT 2 Family FPGAs
76
77
78
80
79
81
82
84
83
86
85
87
88
89
91
90
93
92
94
95
96
97
98
99
100
VQ100
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
66
11
65
100-Pin
VQFP
12
13
64
63
50
49
48
47
46
45
44
43
42
41
40
39
38
51
37
52
25
36
53
24
35
54
23
34
55
22
33
56
21
32
57
20
31
58
19
30
59
18
29
60
17
28
61
16
27
62
15
26
14
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
Revision 8
3 -9
Package Pin Assignments
VQ100
VQ100
Pin Number
A1225A Function
Pin Number
A1225A Function
2
MODE
64
VCC
7
GND
65
VCC
14
VCC
70
GND
15
VCC
77
SDI, I/O
20
GND
82
GND
32
GND
85
PRA, I/O
38
VCC
87
CLKA, I/O
44
GND
88
VCC
50
SDO
90
CLKB, I/O
55
GND
92
PRB, I/O
62
GND
94
GND
63
VCC
100
DCLK, I/O
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
3- 10
R e visio n 8
ACT 2 Family FPGAs
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
TQ176
176-Pin
TQFP
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
Revision 8
3- 11
Package Pin Assignments
TQ176
TQ176
Pin Number
A1240A Function
A1280A Function
Pin Number
A1240A Function
A1280A Function
1
GND
GND
82
NC
VCC
2
MODE
MODE
86
NC
I/O
8
NC
NC
87
SDO
SDO
10
NC
I/O
89
GND
GND
11
NC
I/O
96
NC
I/O
13
NC
VCC
97
NC
I/O
18
GND
GND
101
NC
NC
19
NC
I/O
103
NC
I/O
20
NC
I/O
106
GND
GND
22
NC
I/O
107
NC
I/O
23
GND
GND
108
NC
I/O
24
NC
VCC
109
GND
GND
25
VCC
VCC
110
VCC
VCC
26
NC
I/O
111
GND
GND
27
NC
I/O
112
VCC
VCC
28
VCC
VCC
113
VCC
VCC
29
NC
I/O
114
NC
I/O
33
NC
NC
115
NC
I/O
37
NC
I/O
116
NC
VCC
38
NC
NC
121
NC
NC
45
GND
GND
124
NC
I/O
52
NC
VCC
125
NC
I/O
54
NC
I/O
126
NC
NC
55
NC
I/O
133
GND
GND
57
NC
NC
135
SDI, I/O
SDI, I/O
61
NC
I/O
136
NC
I/O
64
NC
I/O
140
NC
VCC
66
NC
I/O
143
NC
I/O
67
GND
GND
144
NC
I/O
68
VCC
VCC
145
NC
NC
74
NC
I/O
147
NC
I/O
77
NC
NC
151
NC
I/O
78
NC
I/O
152
PRA, I/O
PRA, I/O
80
NC
I/O
154
CLKA, I/O
CLKA, I/O
3- 12
R e visio n 8
ACT 2 Family FPGAs
TQ176
Pin Number
A1240A Function
A1280A Function
155
VCC
VCC
156
GND
GND
158
CLKB, I/O
CLKB, I/O
160
PRB, I/O
PRB, I/O
161
NC
I/O
165
NC
NC
166
NC
I/O
168
NC
I/O
170
NC
VCC
173
NC
I/O
175
DCLK, I/O
DCLK, I/O
Notes:
1. NC denotes no connection.
2. All unlisted pin numbers are user I/Os.
3. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
Revision 8
3- 13
Package Pin Assignments
CQ172
172
Pin #1
Index
1
172-Pin
CQFP
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
3- 14
R e visio n 8
ACT 2 Family FPGAs
CQ172
CQ172
Pin Number
A1280A Function
Pin Number
A1280A Function
1
MODE
107
VCC
7
GND
108
GND
12
VCC
109
VCC
17
GND
110
VCC
22
GND
113
VCC
23
VCC
118
GND
24
VCC
123
GND
27
VCC
131
SDI, I/O
32
GND
136
VCC
37
GND
141
GND
50
VCC
148
PRA, I/O
55
GND
150
CLKA, I/O
65
GND
151
VCC
66
VCC
152
GND
75
GND
154
CLKB, I/O
80
VCC
156
PRB, I/O
85
SDO
161
GND
98
GND
166
VCC
103
GND
171
DCLK, I/O
106
GND
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
Revision 8
3- 15
Package Pin Assignments
PG100
1
2
3
4
5
6
7
8
9
10 11
A
A
B
B
C
C
D
D
E
E
100-Pin
CPGA
F
F
G
G
H
H
J
J
K
K
L
L
1
2
3
4
5
6
7
8
9
10 11
Orientation Pin
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
3- 16
R e visio n 8
ACT 2 Family FPGAs
PG100
PG100
Pin Number
A1225A Function
Pin Number
A1225A Function
A4
PRB, I/O
E11
VCC
A7
PRA, I/O
F3
VCC
B6
VCC
F9
VCC
C2
MODE
F10
VCC
C3
DCLK, I/O
F11
GND
C5
GND
G1
VCC
C6
CLKA, I/O
G3
GND
C7
GND
G9
GND
C8
SDI, I/O
J5
GND
D6
CLKB, I/O
J7
GND
D10
GND
J9
SDO
E3
GND
K6
VCC
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
Revision 8
3- 17
Package Pin Assignments
PG132
1
2
3
4
5
6
7
8
9
10 11 12 13
A
A
B
B
C
C
D
D
E
E
F
F
132-Pin
CPGA
G
G
H
H
J
J
K
K
L
L
M
M
N
N
1
2
3
4
5
6
7
8
9
10 11 12 13
Orientation Pin
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
3- 18
R e visio n 8
ACT 2 Family FPGAs
PG132
PG132
Pin Number
A1240A Function
Pin Number
A1240A Function
A1
MODE
G3
VCC
B5
GND
G4
VCC
B6
CLKB, I/O
G10
VCC
B7
CLKA, I/O
G11
VCC
B8
PRA, I/O
G12
VCC
B9
GND
G13
VCC
B12
SDI, I/O
H13
GND
C3
DCLK, I/O
J2
GND
C5
GND
J3
GND
C6
PRB, I/O
J11
GND
C7
VCC
K7
VCC
C9
GND
K12
GND
D7
VCC
L5
GND
E3
GND
L7
VCC
E11
GND
L9
GND
E12
GND
M9
GND
F4
GND
N12
SDO
G2
VCC
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
Revision 8
3- 19
Package Pin Assignments
PG176
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A
A
B
B
C
C
D
D
E
E
F
F
G
G
176-Pin
CPGA
H
H
J
J
K
K
L
L
M
M
N
N
P
P
R
R
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/docs.aspx
3- 20
R e visio n 8
ACT 2 Family FPGAs
PG176
PG176
Pin Number
A1280A Function
Pin Number
A1280A Function
A9
CLKA, I/O
H3
VCC
B3
DCLK, I/O
H4
GND
B8
CLKB, I/O
H12
GND
B14
SDI, I/O
H13
VCC
C3
MODE
H14
VCC
C8
GND
J4
VCC
C9
PRA, I/O
J12
GND
D4
GND
J13
GND
D5
VCC
J14
VCC
D6
GND
K4
GND
D7
PRB, I/O
K12
GND
D8
VCC
L4
GND
D10
GND
M4
GND
D11
VCC
M5
VCC
D12
GND
M6
GND
E4
GND
M8
GND
E12
GND
M10
GND
F4
VCC
M11
VCC
F12
GND
M12
GND
G4
GND
N8
VCC
G12
VCC
P13
SDO
H2
VCC
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can
be terminated directly to GND.
Revision 8
3- 21
4 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each version of the datasheet.
Revision
Revision 8
(January 2012)
Changes
Page
The ACT 2 datasheet was formatted newly in the style used for current datasheets.
The same information is present (other than noted in the list of changes for this
revision) but divided into chapters.
N/A
Package names used in Table 1 • ACT 2 Product Family Profile and throughout the
document were revised to match standards given in Package Mechanical Drawings
(SAR 27395).
I
The description for SDO pins had earlier been removed from the datasheet and has
now been included again, in the "Pin Descriptions" section (SAR 35819).
2-21
SDO pin numbers had earlier been removed from package pin assignment tables in
the datasheet, and have now been restored to the pin tables (SAR 35819).
3-2
Revision 7
(June 2006)
The "Ordering Information" section was revised to include RoHS information.
Revision 6
(December 2000)
In the "PG176" package, pin A3 was incorrectly assigned as CLKA, I/O. A3 is a user
I/O. Pin A9 is CLKA, I/O.
Revision 8
II
3-21
4 -1
Datasheet Information
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided for a given device is
designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these
categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general
product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production. This label only applies to the
DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not
been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Production
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Safety Critical, Life Support, and High-Reliability Applications
Policy
The products described in this advance status document may not have completed the Microsemi
qualification process. Products may be amended or enhanced during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the responsibility of
each customer to ensure the fitness of any product (but especially a new product) for a particular
purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications.
Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating
to life-support applications. A reliability report covering all of the SoC Products Group’s products is
available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety
of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for
additional reliability information.
4-2
R e vi s i o n 8
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