AD AD5452W 12-bit high bandwidth multiplying dac with serial interface Datasheet

FEATURES
12 MHz multiplying bandwidth
8-lead MSOP package
2.5 V to 5.5 V supply operation
Pin-compatible 12-bit current output DAC
±10 V reference input
50 MHz serial interface
2.7 MSPS update rate
Extended temperature range: –40°C to +125°C
4-quadrant multiplication
Power-on reset with brownout detect
<0.4 µA typical current consumption
Guaranteed monotonic
Qualified for automotive applications
FUNCTIONAL BLOCK DIAGRAM
VDD
VREF
AD5452W
R
12-BIT REF
R-2R DAC
IOUT1
DAC REGISTER
POWER-ON
RESET
INPUT LATCH
SYNC
SCLK
SDIN
CONTROL LOGIC
AND INPUT SHIFT
REGISTER
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
RFB
GND
10657-001
Data Sheet
12-Bit High Bandwidth
Multiplying DAC with Serial Interface
AD5452W
Figure 1.
GENERAL DESCRIPTION
The AD5452W is a CMOS 12-bit current output digital-to-analog
converter. This device operates from a 2.5 V to 5.5 V power supply,
making it suited to several applications, including batterypowered applications.
As a result of manufacture on a CMOS submicron process, this
DAC offers excellent four-quadrant multiplication characteristics of up to 12 MHz.
This DAC utilizes a double-buffered, 3-wire serial interface that
is compatible with SPI, QSPI™, MICROWIRE™, and most DSP
interface standards. Upon power-up, the internal shift register
and latches are filled with 0s, and the DAC output is at zero scale.
The applied external reference input voltage (VREF) determines
the full-scale output current. This part can handle ±10 V inputs
on the reference, despite operating from a single-supply power
supply of 2.5 V to 5.5 V. An integrated feedback resistor (RFB)
provides temperature tracking and full-scale voltage output
when combined with an external current-to-voltage precision
amplifier.
The AD5452W DAC is available in an 8-lead MSOP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
AD5452W
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
DAC Section................................................................................ 14
Applications ....................................................................................... 1
Circuit Operation ....................................................................... 14
Functional Block Diagram .............................................................. 1
Single-Supply Applications ....................................................... 16
General Description ......................................................................... 1
Adding Gain ................................................................................ 16
Revision History ............................................................................... 2
Divider or Programmable Gain Element ................................ 16
Specifications..................................................................................... 3
Reference Selection .................................................................... 17
Timing Characteristics ................................................................ 5
Amplifier Selection .................................................................... 17
Absolute Maximum Ratings ............................................................ 6
Serial Interface ............................................................................ 19
ESD Caution .................................................................................. 6
Microprocessor Interfacing ....................................................... 19
Pin Configuration and Function Descriptions ............................. 7
PCB Layout and Power Supply Decoupling ........................... 21
Typical Performance Characteristics ............................................. 8
Outline Dimensions ....................................................................... 23
Terminology .................................................................................... 13
Ordering Guide .......................................................................... 23
Theory of Operation ...................................................................... 14
Automotive Products ................................................................. 23
REVISION HISTORY
4/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
Data Sheet
AD5452W
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V. TA = full operating temperature range. All specifications TMIN to TMAX, unless otherwise noted. DC
performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error
Gain Error
Gain Error Temperature Coefficient 1
Output Leakage Current
REFERENCE INPUT1
Reference Input Range
VREF Input Resistance
RFB Feedback Resistance
Input Capacitance
Zero-Scale Code
Full-Scale Code
DIGITAL INPUTS/OUTPUTS1
Input High Voltage, VIH
Min
Typ
Max
Unit
12
±0.5
±1
±1
±0.5
±1
±10
Bits
LSB
LSB
LSB
LSB
ppm FSR/°C
nA
nA
Data = 0x0000, TA = 25°C, IOUT1
Data = 0x0000, TA = −40°C to +125°C, IOUT1
±10
9
9
11
11
V
kΩ
kΩ
Input resistance, TC = −50 ppm/°C
Input resistance, TC = −50 ppm/°C
18
18
22
22
pF
pF
±2
7
7
2.0
1.7
VDD = 3.6 V to 5 V
VDD = 2.5 V to 3.6 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
VDD = 4.5 V to 5 V, ISOURCE = 200 µA
VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA
VDD = 4.5 V to 5 V, ISINK = 200 µA
VDD = 2.5 V to 3.6 V, ISINK = 200 µA
TA = 25°C
TA = −40°C to +125°C
12
MHz
72
64
44
dB
dB
dB
VREF = ±3.5 V, DAC loaded with all 1s
VREF = ±3.5 V, DAC loaded with all 0s
100 kHz
1 MHz
10 MHz
VREF = 10 V, RLOAD = 100 Ω; DAC latch alternately
loaded with 0s and 1s
0.8
0.7
VDD − 1
VDD − 0.5
Output Low Voltage, VOL
0.4
0.4
±1
±10
10
Input Leakage Current, IIL
Input Capacitance
DYNAMIC PERFORMANCE1
Reference Multiplying BW
Multiplying Feedthrough Error
Output Voltage Settling Time
Measured to ±1 mV of FS
Measured to ±4 mV of FS
Measured to ±16 mV of FS
Digital Delay
10% to 90% Settling Time
Digital-to-Analog Glitch Impulse
Output Capacitance
IOUT1
Guaranteed monotonic
V
V
V
V
V
V
V
V
nA
nA
pF
Input Low Voltage, VIL
Output High Voltage, VOH
Test Conditions/Comments
100
24
16
20
10
2
13
28
110
40
33
40
30
ns
ns
ns
ns
ns
nV-sec
Interface delay time
Rise and fall times, VREF = 10 V, RLOAD = 100 Ω
1 LSB change around major carry, VREF = 0 V
pF
pF
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Rev. 0 | Page 3 of 24
AD5452W
Parameter
Digital Feedthrough
Analog THD
Digital THD
50 kHz fOUT
20 kHz fOUT
Output Noise Spectral Density
SFDR Performance (Wideband)
50 kHz fOUT
20 kHz fOUT
SFDR Performance (Narrow-Band)
50 kHz fOUT
20 kHz fOUT
Intermodulation Distortion
POWER REQUIREMENTS
Power Supply Range
IDD
Data Sheet
Min
Typ
0.5
Max
Test Conditions/Comments
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz
Clock = 1 MHz, VREF = 3.5 V
83
dB
71
77
25
dB
dB
nV/√Hz
78
74
dB
dB
87
85
79
dB
dB
dB
f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, VREF = 3.5 V
V
µA
µA
%/%
TA = −40°C to +125°C, logic inputs = 0 V or VDD
TA = 25°C, logic inputs = 0 V or VDD
∆VDD = ±5%
@ 1 kHz
Clock = 1 MHz, VREF = 3.5 V
Clock = 1 MHz, VREF = 3.5 V
2.5
5.5
10
0.6
0.001
0.4
Power Supply Sensitivity1
1
Unit
nV-sec
Guaranteed by design and characterization; not subject to production test.
Rev. 0 | Page 4 of 24
Data Sheet
AD5452W
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, TA = full operating temperature range. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter 1
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
Update Rate
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
Conditions/Comments
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK active edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK active edge
Minimum SYNC high time
Consists of cycle time, SYNC high time, data setup, and
output voltage settling time
Guaranteed by design and characterization, not subject to production test.
t1
SCLK
t2
t8
t3
t7
t4
SYNC
t6
t5
SDIN
DB15
DB0
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 24
10657-002
1
VDD = 2.5 V to 5.5 V
50
20
8
8
8
5
4.5
5
30
2.7
AD5452W
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VREF, RFB to GND
IOUT1 to GND
Input Current to Any Pin Except Supplies
Logic Inputs and Output 1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
8-Lead MSOP
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
1
Rating
−0.3 V to +7 V
−12 V to +12 V
−0.3 V to +7 V
±10 mA
−0.3 V to VDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
206°C/W
300°C
235°C
Overvoltages at SCLK, SYNC, and SDIN are clamped by internal diodes.
Rev. 0 | Page 6 of 24
Data Sheet
AD5452W
IOUT1
1
8
RFB
GND
2
AD5452W
7
VREF
SCLK
3
TOP VIEW
(Not to Scale)
6
VDD
SDIN
4
5
SYNC
10657-004
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No
1
2
3
Mnemonic
IOUT1
GND
SCLK
4
SDIN
5
SYNC
6
7
8
VDD
VREF
RFB
Description
DAC Current Output.
Ground Pin.
Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge
of the serial clock input. Alternatively, by means of the serial control bits, the device can be
configured such that data is clocked into the shift register upon the rising edge of SCLK.
Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial
clock input. By default, in power-up mode data is clocked into the shift register upon the falling
edge of SCLK. The control bits allow the user to change the active edge to a rising edge.
Active Low Control Input. This is the frame synchronization signal for the input data. Data is
loaded to the shift register upon the active edge of the following clocks.
Positive Power Supply Input. These parts can operate from a supply of 2.5 V to 5.5 V.
DAC Reference Voltage Input.
DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external
amplifier output.
Rev. 0 | Page 7 of 24
AD5452W
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
0.5
TA = 25°C
VREF = 10V
VDD = 5V
0.4
TA = 25°C
VDD = 5V
AD5452
1.5
0.3
1.0
MAX DNL
0.5
0.1
DNL (LSB)
INL (LSB)
0.2
0
–0.1
0
MIN DNL
–0.5
–0.2
–1.0
–0.3
0
512
1024
1536
2048
2560
3072
2584
4096
CODE
–2.0
10657-022
–0.5
2
3
Figure 4. INL vs. Code
5
6
7
8
REFERENCE VOLTAGE (V)
9
10
2584
4096
9
10
Figure 7. DNL vs. Reference Voltage
1.0
1.0
TA = 25°C
VREF = 10V
VDD = 5V
0.6
0.4
0.4
0.2
0.2
TUE (LSB)
0.6
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
512
1024
1536
2048
2560
3072
2584
4096
CODE
–1.0
10657-026
–1.0
0
TA = 25°C
VREF = 10V
VDD = 5V
0.8
0
512
1024
1536
2048
2560
3072
10657-032
0.8
DNL (LSB)
4
10657-071
–1.5
–0.4
CODE
Figure 8. TUE vs. Code
Figure 5. DNL vs. Code
1.00
2.0
TA = 25°C
VDD = 5V
AD5452
0.75
TA = 25°C
VDD = 5V
AD5452
1.5
0.50
MAX INL
1.0
MAX TUE
TUE (LSB)
0.5
0
MIN INL
0
MIN TUE
–0.5
–0.50
–1.0
–0.75
–1.5
–1.00
2
3
4
5
6
7
8
REFERENCE VOLTAGE (V)
9
10
Figure 6. INL vs. Reference Voltage
–2.0
2
3
4
5
8
6
7
REFERENCE VOLTAGE (V)
Figure 9. TUE vs. Reference Voltage
Rev. 0 | Page 8 of 24
10657-072
–0.25
10657-070
INL (LSB)
0.25
Data Sheet
AD5452W
2.5
0.3
TA = 25°C
2.0
0.1
VDD = 3V
CURRENT (mA)
GAIN ERROR (LSB)
0.2
VDD = 5V
0
–0.1
1.5
1.0
VDD = 5V
0.5
–0.2
VDD = 3V
20
40
0
60
TEMPERATURE (°C)
–20
80
100
120
140
0
0
Figure 10. Gain Error (LSB) vs. Temperature
2
3
INPUT VOLTAGE (V)
4
0.7
TA = 25°C
VDD = 5V
AD5452
1.5
5
Figure 13. Supply Current vs. Logic Input Voltage
2.0
ALL 1s
ALL 0s
0.6
1.0
0.5
VDD = 5V
CURRENT (µA)
0.5
0
–0.5
0.4
0.3
0.2
–1.0
VDD = 3V
0.1
–1.5
2
3
4
6
7
5
8
REFERENCE VOLTAGE (V)
9
10
0
–40
10657-074
–2.0
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 11. Gain Error (LSB) vs. Reference Voltage
10657-037
GAIN ERROR (LSB)
1
10657-038
–40
10657-073
–0.3
–60
Figure 14. Supply Current vs. Temperature
2.0
6
TA = 25°C
AD5452
LOADING 010101010101
VDD = 5V
5
1.6
CURRENT (mA)
1.2
0.8
4
3
VDD = 5V
2
0.4
1
–20
0
20
40
60
80
100
TEMPERATURE (°C)
120
Figure 12. IOUT1 Leakage Current vs. Temperature
0
VDD = 3V
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 15. Supply Current vs. Update Rate
Rev. 0 | Page 9 of 24
10M
10657-075
0
–40
10657-039
LEAKAGE (nA)
VDD = 3V
AD5452W
Data Sheet
3
1.8
TA = 25°C
TA = 25°C
VDD = 5V
1.6
VIL
0
1.2
GAIN (dB)
1.0
0.8
–3
0.6
0.2
3.5
4.0
VOLTAGE (V)
4.5
5.0
5.5
–9
10k
0
DB11
DB10
–30
DB9
DB8
–40
DB7
DB6
–50
DB5
DB4
DB3
–70
DB2
–80
10k
VDD = 5V
VREF = ±3.5V
CCOMP = 1.8pF
AD8038 AMPLIFIER
100k
1M
10M
100M
FREQUENCY (Hz)
0
VDD = 5V
0x800 TO 0x7FF
NRG = 0.694nV-sec
–0.02
VDD = 5V
0x800 TO 0x7FF
NRG = 0.694nV-sec
–0.06
50
75
100
125
150
175
225
250
TIME (ns)
–1.66
VDD = 5V
0x7FF TO 0x800
NRG = 2.154nV-sec
0.4
–1.68
OUTPUT VOLTAGE (V)
0.2
0
–0.2
–0.4
–0.6
TA = 25°C
VDD = 5V
VREF = ±3.5V
CCOMP = 1.8pF
AD8038 AMPLIFIER
–1.2
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 18. Reference Multiplying Bandwidth—All 1s Loaded
TA = 25°C
VDD = 3.5V
AD8038 AMPLIFIER
CCOMP = 1.8pF
VDD = 3V
0x7FF TO 0x800
NRG = 1.794nV-sec
–1.70
–1.72
–1.74
–1.76
VDD = 5V
0x800 TO 0x7FF
NRG = 0.694nV-sec
VDD = 5V
0x800 TO 0x7FF
NRG = 0.694nV-sec
–1.78
10657-109
GAIN (dB)
200
Figure 20. Midscale Transition, VREF = 0 V
0.6
–1.0
TA = 25°C
VDD = 0V
AD8038 AMPLIFIER
CCOMP = 1.8pF
0.02
Figure 17. Reference Multiplying Bandwidth vs. Frequency and Code
–0.8
100M
VDD = 3V
0x7FF TO 0x800
NRG = 1.794nV-sec
0.04
–0.04
10657-108
–60
VDD = 5V
0x7FF TO 0x800
NRG = 2.154nV-sec
0.06
DB12
–20
10M
0.08
OUTPUT VOLTAGE (V)
GAIN (dB)
–10
1M
Figure 19. Reference Multiplying Bandwidth vs. Frequency and
Compensation Capacitor
TA = 25°C
LOADING
ZS TO FS
ALL ON
DB13
100k
FREQUENCY (Hz)
Figure 16. Threshold Voltage vs. Supply Voltage
10
= ±2V, AD8038 C COMP = 1pF
= ±2V, AD8038 C COMP = 1.5pF
= ±15V, AD8038 C COMP = 1pF
= ±15V, AD8038 C COMP = 1.5pF
= ±15V, AD8038 C COMP = 1.8pF
10657-080
3.0
10657-076
0
2.5
VREF
VREF
VREF
VREF
VREF
10657-079
–6
0.4
–1.80
50
75
100
125
150
175
200
TIME (ns)
Figure 21. Midscale Transition, VREF = 3.5 V
Rev. 0 | Page 10 of 24
225
250
10657-081
THRESHOLD VOLTAGE (V)
VIH
1.4
Data Sheet
AD5452W
0
10
TA = 25°C
VDD = 3V
AD8038 AMPLIFIER
0
TA = 25°C
VDD = 5V
VREF = 3.5V
AD8038 AMPLIFIER
–20
–10
–20
–40
SFDR (dB)
PSRR (dB)
–30
–40
FULL SCALE
–50
–60
–60
–80
ZERO SCALE
–70
–80
–100
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–120
10657-082
–100
0
200k
300k
500k
Figure 25. Wideband SFDR, fOUT = 20 kHz, Clock = 1 MHz
0
–60
TA = 25°C
VDD = 5V
VREF = ±3.5V
–65
TA = 25°C
VDD = 5V
VREF = 3.5V
AD8038 AMPLIFIER
–20
–40
SFDR (dB)
–70
–60
–80
–80
–85
–100
10k
100k
FREQUENCY (Hz)
10657-083
–120
1k
0
100k
200k
300k
400k
500k
FREQUENCY (Hz)
10657-086
–75
–90
100
Figure 26. Wideband SFDR, fOUT = 50 kHz, Clock = 1 MHz
Figure 23. THD + Noise vs. Frequency
0
100
TA = 25°C
VDD = 5V
VREF = 3.5V
AD8038 AMPLIFIER
MCLK = 200kHz
MCLK = 500kHz
–20
80
MCLK = 1MHz
SFDR (dB)
–40
60
40
–60
–80
20
0
0
10
20
30
40
fOUT (kHz)
50
–120
10k
15k
20k
25k
30k
FREQUENCY (Hz)
Figure 27. Narrow-Band SFDR, fOUT = 20 kHz, Clock = 1 MHz
Figure 24. Wideband SFDR vs. fOUT Frequency
Rev. 0 | Page 11 of 24
10657-087
–100
TA = 25°C
VREF = ±3.5V
AD8038 AMPLIFIER
10657-084
SFDR (dB)
400k
FREQUENCY (Hz)
Figure 22. Power Supply Rejection Ratio vs. Frequency
THD + N (dB)
100k
10657-085
–90
AD5452W
Data Sheet
0
0
TA = 25°C
VDD = 5V
VREF = 3.5V
AD8038 AMPLIFIER
–20
–20
–30
IMD (dB)
–40
SFDR (dB)
TA = 25°C
VREF = 3.5V
AD8038 AMPLIFIER
–10
–60
–80
–40
–50
–60
–70
–80
–100
50k
60k
70k
FREQUENCY (Hz)
10657-088
40k
–100
0
100k
200k
300k
400k
500k
FREQUENCY (Hz)
Figure 28. Narrow-Band SFDR , fOUT = 50 kHz, Clock = 1 MHz
Figure 30. Wideband IMD, fOUT = 20 kHz, 25 kHz, Clock = 1 MHz
0
80
TA = 25°C
VREF = 3.5V
AD8038 AMPLIFIER
–10
10657-090
–90
–120
30k
TA = 25°C
AD8038 AMPLIFIER
70
–40
–50
–60
–70
60
FULL SCALE
LOADED TO DAC
50
40
MIDSCALE
LOADED TO DAC
30
20
–80
–100
10k
ZERO SCALE
LOADED TO DAC
10
–90
15k
20k
25k
30k
35k
FREQUENCY (Hz)
10657-089
IMD (dB)
–30
0
100
1k
10k
100k
FREQUENCY (Hz)
Figure 31. Output Noise Spectral Density
Figure 29. Narrow-Band IMD, fOUT = 20 kHz, 25 kHz, Clock = 1 MHz
Rev. 0 | Page 12 of 24
1M
10657-091
OUTPUT NOISE (nV/ Hz)
–20
Data Sheet
AD5452W
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
A measure of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally
expressed in LSBs or as a percentage of the full-scale reading.
Differential Nonlinearity
The difference between the measured change and the ideal 1
LSB change between any two adjacent codes. A specified
differential nonlinearity of −1 LSB maximum over the operating
temperature range ensures monotonicity.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For these DACs, ideal maximum output is
VREF − 1 LSB. Gain error of the DACs is adjustable to zero with
external resistance.
Output Leakage Current
The current that flows into the DAC ladder switches when it is
turned off. For the IOUT1 terminal, it can be measured by loading
all 0s to the DAC and measuring the IOUT1 current.
Output Capacitance
Capacitance from IOUT1 to AGND.
Output Current Settling Time
The amount of time it takes for the output to settle to a
specified level for a full-scale input change. For these devices, it
is specified with a 100 Ω resistor to ground. The settling time
specification includes the digital delay from the SYNC rising
edge to the full-scale output change.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-sec or nV-sec,
depending on whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs may be capacitively coupled
through the device and produce noise on the IOUT pins. This
noise is coupled from the outputs of the device onto follow-on
circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics, such as
second to fifth, are included.
THD = 20 log
V 2 2 + V3 2 + V 4 2 + V5 2
V1
Digital Intermodulation Distortion (IMD)
Second-order intermodulation measurements are the relative
magnitudes of the fa and fb tones generated digitally by the
DAC and the second-order products at 2fa − fb and 2fb − fa.
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Spurious-Free Dynamic Range (SFDR)
The usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonically or nonharmonically related spur
from dc to full Nyquist bandwidth (half the DAC sampling rate
or fS/2). Narrow-band SFDR is a measure of SFDR over an
arbitrary window size, in this case 50% of the fundamental.
Digital SFDR is a measure of the usable dynamic range of the
DAC when the signal is a digitally generated sine wave.
Rev. 0 | Page 13 of 24
AD5452W
Data Sheet
THEORY OF OPERATION
DAC SECTION
The AD5452W is 12-bit current output DAC, consisting of a
segmented (4-bit) inverting R-2R ladder configuration. A
simplified diagram for the DAC is shown in Figure 32.
R
VDD
R2
VDD
R
2R
2R
S2
S1
2R
S3
2R
S12
VREF
VREF
2R
AD5452W
R1
RFB
A1
GND
VOUT = 0 TO –VREF
SYNC SCLK SDIN
AGND
10657-060
AGND
µCONTROLLER
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 32. AD5452W Simplified Ladder
The feedback resistor, RFB, has a value of R. The value of R is
typically 9 kΩ (with a minimum value of 7 kΩ and a maximum
value of 11 kΩ). If IOUT1 is kept at the same potential as GND, a
constant current flows in each ladder leg, regardless of digital
input code. Therefore, the input resistance presented at VREF is
always constant and nominally of value R. The DAC output
(IOUT1) is code-dependent, producing various resistances and
capacitances. When choosing the external amplifier, take into
account the variation in impedance generated by the DAC on
the amplifier’s inverting input node.
Access is provided to the VREF, RFB, and IOUT1 terminals of the
DAC, making the device extremely versatile and allowing it to be
configured in several operating modes; for example, it can provide
a unipolar output or can provide 4-quadrant multiplication in
bipolar mode. Note that a matching switch is used in series with
the internal RFB feedback resistor. If users attempt to measure
RFB, power must be applied to VDD to achieve continuity.
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, this device can easily be configured to
provide a two-quadrant multiplying operation or a unipolar
output voltage swing, as shown in Figure 33. When an output
amplifier is connected in unipolar mode, the output voltage is
given by
VOUT = −
IOUT1
R
IOUT1
DAC DATA LATCHES
AND DRIVERS
C1
RFB
VREF
10657-009
R
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages.
Figure 33. Unipolar Mode Operation
This DAC is designed to operate with either negative or positive
reference voltages. The VDD power pin is only used by the
internal digital logic to drive the on and off states of the DAC
switches.
This DAC is designed to accommodate ac reference input
signals in the range of −10 V to +10 V.
With a fixed 10 V reference, the circuit shown in Figure 33 gives
a unipolar 0 V to −10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
Table 5 shows the relationship between the digital code and
the expected output voltage for a unipolar operation using the
12-bit AD5452W.
Table 5. Unipolar Code Table for the AD5452W
Digital Input
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
D
× V REF
2n
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 4095 (12-bit AD5452W).
n is the number of bits.
Rev. 0 | Page 14 of 24
Analog Output (V)
−VREF (4095/4096)
−VREF (2048/4096) = −VREF/2
−VREF (1/4096)
−VREF (0/4096) = 0
Data Sheet
AD5452W
Bipolar Mode
Table 6. Bipolar Code Table for the AD5452W
In some applications, it may be necessary to generate a full fourquadrant multiplying operation or a bipolar output swing. This
can be easily accomplished by using another external amplifier
and some external resistors, as shown in Figure 34. In this
circuit, the second amplifier, A2, provides a gain of 2. Biasing
the external amplifier with an offset from the reference voltage
results in full 4-quadrant multiplying operation. The transfer
function of this circuit shows that both negative and positive
output voltages are created as the input data (D) is incremented
from Code 0 (VOUT = − VREF) to midscale (VOUT = 0 V ) to full
scale (VOUT = +VREF).
Digital Input
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
Analog Output (V)
+VREF (2047/2048)
0
−VREF (2047/2048)
−VREF (2048/2048)
Stability
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited gain bandwidth
product (GBP) and there is excessive parasitic capacitance at the
inverting node. This parasitic capacitance introduces a pole into
the open-loop response, which can cause ringing or instability
in the closed-loop applications circuit.
D
VOUT =  VREF × n −1  − VREF
2 

where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 4095 (12-bit AD5452W).
n is the resolution of the DAC.
An optional compensation capacitor, C1, can be added in parallel
with RFB for stability, as shown in Figure 33 and Figure 34. Too
small a value of C1 can produce ringing at the output, and too
large a value can adversely affect the settling time. C1 should be
found empirically, but 1 pF to 2 pF is generally adequate for the
compensation.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication. Table 6 shows the relationship between the
digital code and the expected output voltage for a bipolar
operation using the 12-bit AD5452W.
R3
20kΩ
VDD
VDD
VREF
±10V
VREF
R5
20kΩ
R2
C1
RFB
AD5452W
R1
IOUT1
A1
R4
10kΩ
A2
GND
VOUT = –VREF TO +VREF
SYNC SCLK SDIN
AGND
Figure 34. Bipolar Mode Operation (4-Quadrant Multiplication)
Rev. 0 | Page 15 of 24
10657-010
µCONTROLLER
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
AD5452W
Data Sheet
SINGLE-SUPPLY APPLICATIONS
ADDING GAIN
Voltage-Switching Mode
In applications in which the output voltage is required to be
greater than VIN, gain can be added with an additional external
amplifier, or it can be achieved in a single stage. It is important
to consider the effect of the temperature coefficients of the
DAC’s thin film resistors. Simply placing a resistor in series
with the RFB resistor causes mismatches in the temperature
coefficients and results in larger gain temperature coefficient
errors. Instead, increase the gain of the circuit by using the
recommended configuration shown in Figure 37. R1, R2, and
R3 should have similar temperature coefficients, but they need
not match the temperature coefficients of the DAC. This
approach is recommended in circuits where gains greater than 1
are required.
Figure 35 shows these DACs operating in the voltage-switching
mode. The reference voltage, VIN, is applied to the IOUT1 pin, and
the output voltage is available at the VREF terminal. In this
configuration, a positive reference voltage results in a positive
output voltage, making single-supply operation possible. The
output from the DAC is voltage at a constant impedance (the
DAC ladder resistance); therefore, an op amp is necessary to
buffer the output voltage. The reference input no longer sees
constant input impedance, but one that varies with code;
therefore, the voltage input should be driven from a low
impedance source.
VDD
RFB
R2
VDD
VDD
IOUT1
VIN
R1
VOUT
GND
VIN
R1
C1
RFB
VDD
VREF
IOUT1
VREF
VOUT
R3
R2
GAIN =
R2R3
R1 =
NOTES
R2 + R3
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 35. Single-Supply Voltage-Switching Mode
It is important to note that, with this configuration, VIN is
limited to low voltages because the switches in the DAC ladder
do not have the same source-drain drive voltage. As a result,
their on resistance differs, which degrades the integral linearity
of the DAC. Also, VIN must not go negative by more than 0.3V,
or an internal diode turns on, causing the device to exceed the
maximum ratings. In this type of application, the full range of
multiplying capability of the DAC is lost.
Figure 37. Increasing Gain of Current-Output DAC
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Current-steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp and RFB is used as the input
resistor as shown in Figure 38, the output voltage is inversely
proportional to the digital input fraction, D.
Positive Output Voltage
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistors’ tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the VOUT and GND pins of the reference become the virtual
ground and −2.5 V, respectively, as shown in Figure 36.
For D = 1 − 2−n, the output voltage is
VOUT =
−V IN
−V IN
=
(1 − 2 −n )
D
As D is reduced, the output voltage increases. For small values
of the digital fraction, D, it is important to ensure that the amplifier
does not saturate and that the required accuracy is met.
VDD
VIN
VDD = +5V
ADR03
RFB
VIN
VOUT
VDD
–2.5V
VDD
IOUT1
GND
+5V
IOUT1
VREF
VREF
GND
C1
RFB
VOUT = 0V TO +2.5V
VOUT
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 36. Positive Output Voltage with Minimum Components
Rev. 0 | Page 16 of 24
NOTE
ADDITIONAL PINS OMITTED FOR CLARITY
10657-014
GND
10657-012
–5V
R2 + R3
R2
10657-013
GND
10657-011
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 38. Current-Steering DAC Used as a Divider or
Programmable Gain Element
Data Sheet
AD5452W
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction, D, of the current in the VREF terminal is
routed to the IOUT1 terminal, the output voltage changes as follows:
Output Error Voltage Due to Leakage = (Leakage × R)/D
where R is the DAC resistance at the VREF terminal.
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain
(that is, 1/D) of 16, the error voltage is 1.6 mV.
REFERENCE SELECTION
When selecting a reference for use with this current-output
DAC, pay attention to the reference’s output voltage temperature coefficient specification. This parameter not only affects
the full-scale error, but also may affect the linearity (INL and
DNL) performance. The reference temperature coefficient
should be consistent with the system accuracy specifications.
A 12-bit system within 2 LSB accuracy requires a maximum
drift of 10 ppm/°C. Choosing a precision reference with a low
output temperature coefficient minimizes this error source.
Table 7 lists some dc references available from Analog Devices,
Inc., that are suitable for use with this current-output DAC.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
The input offset voltage of an op amp is multiplied by the variable
gain of the circuit due to the code-dependent output resistance of
the DAC. A change in this noise gain between two adjacent digital
fractions produces a step change in the output voltage due to the
offset voltage of the amplifier’s input. This output voltage change
is superimposed on the desired change in output between the two
codes and gives rise to a differential linearity error, which, if
large enough, may cause the DAC to be nonmonotonic.
The input bias current of an op amp generates an offset at the
voltage output as a result of the bias current flowing in the
feedback resistor, RFB. Most op amps have input bias currents
low enough to prevent significant errors in 12-bit applications.
Common-mode rejection of the op amp is important in voltageswitching circuits because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 12-bit resolutions.
Provided that the DAC switches are driven from true wideband
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltageswitching DAC circuit is determined largely by the output op
amp. To obtain minimum settling time in this configuration, it
is important to minimize capacitance at the VREF node (the voltage
output node in this application) of the DAC. This is done by using
low input-capacitance buffer amplifiers and careful board design.
Most single-supply circuits include ground as part of the analog
signal range, which in turn requires an amplifier that can handle
rail-to-rail signals. There is a large range of single-supply amplifiers
available from Analog Devices.
Rev. 0 | Page 17 of 24
AD5452W
Data Sheet
Table 7. Suitable Analog Devices Precision References
Part No.
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR431
ADR435
ADR391
ADR395
Output Voltage (V)
10
10
5
5
2.5
2.5
3
3
2.5
5
2.5
5
Initial Tolerance (%)
0.05
0.05
0.06
0.06
0.10
0.10
0.10
0.10
0.04
0.04
0.16
0.10
Temp Drift (ppm/°C)
3
9
3
9
3
9
3
9
3
3
9
9
ISS (mA)
1
1
1
1
1
1
1
1
0.8
0.8
0.12
0.12
Output Noise (µV p-p)
20
20
10
10
6
6
10
10
3.5
8
5
8
Package
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
SOIC-8
TSOT-23
TSOT-23
Table 8. Suitable Analog Devices Precision Op Amps
Part No.
OP97
OP1177
AD8551
AD8603
AD8628
Supply Voltage (V)
±2 to ±20
±2.5 to ±15
2.7 to 5
1.8 to 6
2.7 to 6
VOS (Max) (µV)
25
60
5
50
5
IB (Max) (nA)
0.1
2
0.05
0.001
0.1
0.1 Hz to 10 Hz
Noise (µV p-p)
0.5
0.4
1
2.3
0.5
Supply Current (µA)
600
500
975
50
850
Package
SOIC-8
MSOP, SOIC-8
MSOP, SOIC-8
TSOT
TSOT, SOIC-8
Table 9. Suitable Analog Devices High Speed Op Amps
Part No.
AD8065
AD8021
AD8038
AD9631
Supply Voltage (V)
5 to 24
±2.5 to ±12
3 to 12
±3 to ±6
BW @ ACL (MHz)
145
490
350
320
Slew Rate (V/µs)
180
120
425
1300
Rev. 0 | Page 18 of 24
VOS (Max) (µV)
1500
1000
3000
10000
IB (Max) (nA)
0.006
10500
750
7000
Package
SOIC-8, SOT-23, MSOP
SOIC-8, MSOP
SOIC-8, SC70-5
SOIC-8
Data Sheet
AD5452W
SERIAL INTERFACE
ADSP-21xx-to-AD5452W Interface
The AD5452W has an easy-to-use 3-wire interface that is
compatible with SPI, QSPI, MICROWIRE, and most DSP
interface standards. Data is written to the device in 16-bit words.
This 16-bit word consists of two control bits and 12 data bits, as
shown in Figure 39. The AD5452W uses 12 bits and ignores the
two LSBs.
The ADSP-21xx family of DSPs is easily interfaced to an
AD5452W DAC without the need for extra glue logic.
Figure 40 is an example of an SPI interface between the DAC
and the ADSP-2191M. SCK of the DSP drives the serial data line,
SDIN. SYNC is driven from one of the port lines, in this
case SPIxSEL.
Table 10. DAC Control Bits
C1
0
0
1
1
C0
0
1
0
1
Function Implemented
Load and update (power-on default)
Reserved
Reserved
Clock data to shift register upon rising edge
SYNC Function
SYNC is an edge-triggered input that acts as a framesynchronization signal and chip enable. Data can only be
transferred to the device while SYNC is low. To start the serial
data transfer, SYNC should be taken low, observing the
minimum SYNC falling to SCLK falling edge setup time, t4. To
minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
upon the falling edge of SYNC. The SCLK and SDIN input
buffers are powered down upon the rising edge of SYNC.
After the falling edge of the 16th SCLK pulse, bring SYNC high
to transfer data from the input shift register to the DAC register.
DB15 (MSB)
C0
DB0 (LSB)
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
X
10657-007
C1
DATA BITS
CONTROL BITS
Figure 39. AD5452W 12-Bit Input Shift Register Contents
AD5452W*
ADSP-2191*
SYNC
SPIxSEL
MOSI
SDIN
SCK
SCLK
10657-100
Control Bits C1 and C0 allow the user to load and update the
new DAC code and to change the active clock edge. By default,
the shift register clocks data upon the falling edge; this can be
changed via the control bits. If changed, the DAC core is
inoperative until the next data frame, and a power recycle is
required to return it to active on the falling edge. A power cycle
resets the core to default condition. On-chip power-on reset
circuitry ensures that the device powers on with zero scale
loaded to the DAC register and IOUT1 line.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 40. ADSP-2191 SPI-to-AD5452W Interface
A serial interface between the DAC and DSP SPORT is shown
in Figure 41. In this example, SPORT0 is used to transfer data to
the DAC shift register. Transmission is initiated by writing a
word to the Tx register after the SPORT has been enabled. In a
write sequence, data is clocked out upon each rising edge of the
DSP’s serial clock and clocked into the DAC input shift register
upon the falling edge of its SCLK. The update of the DAC
output takes place upon the rising edge of the SYNC signal.
AD5452W*
ADSP-2101/
ADSP-2191*
TFS
SYNC
DT
SDIN
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 41. ADSP-2101/ADSP-2191 PORT-to-AD5452W Interface
Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
frame SYNC delay and frame SYNC setup-and-hold, data delay
and data setup-and-hold, and SCLK width. The DAC interface
expects a t4 (SYNC falling edge to SCLK falling edge setup time)
of 8 ns minimum. See the ADSP-21xx User Manual for information on clock and frame SYNC frequencies for the SPORT
register. Table 11 shows the setup for the SPORT control register.
Table 11. SPORT Control Register Setup
MICROPROCESSOR INTERFACING
Microprocessor interfacing to an AD5452W DAC is through a
serial bus that uses standard protocol and is compatible with
microcontrollers and DSP processors. The communication
channel is a 3-wire interface consisting of a clock signal, a data
signal, and a synchronization signal. The AD5452W requires a
16-bit word, with the default being data valid upon the falling
edge of SCLK, but this is changeable using the control bits in
the data-word.
10657-051
DAC Control Bits C1, C0
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
Rev. 0 | Page 19 of 24
Setting
1
1
00
1
1
1
1111
Description
Alternate framing
Active low frame signal
Right justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
AD5452W
Data Sheet
ADSP-BF5xx-to-AD5452W Interface
input register acquires its data with the MSB as the first bit received.
The transmit routine should take this into account.
SCK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 42. ADSP-BF5xx-to-AD5452W Interface
The ADSP-BF5xx processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and
the DSP SPORT is shown in Figure 43. When the SPORT is
enabled, initiate transmission by writing a word to the Tx
register. The data is clocked out upon each rising edge of the
DSP’s serial clock and clocked into the DAC’s input shift
register upon the falling edge of SCLK. The DAC output is
updated by using the transmit frame synchronization (TFS) line
to provide a SYNC signal.
AD5452W*
TFS
SYNC
DT
SDIN
SCLK
Figure 45 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR); see the 68HC11 User Manual. SCK
of the 68HC11 drives the SCLK of the DAC interface; the MOSI
output drives the serial data line (SDIN) of the DAC.
The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5452W, the SYNC line is taken
low (PC7). Data appearing on the MOSI output is valid upon the
falling edge of SCK. Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. To load data to the
DAC, PC7 is left low after the first eight bits are transferred, and a
second serial write operation is performed to the DAC. PC7 is
taken high at the end of this procedure.
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5452W*
MC68HC11*
PC7
10657-103
ADSP-BF5xx*
SYNC
MC68HC11-to-AD5452W Interface
10657-102
SDIN
SDIN
P1.1
Figure 44. 80C51/80L51-to-AD5452W Interface
SYNC
MOSI
SCLK
Figure 43. ADSP-BF5xx SPORT-to-AD5452W Interface
SYNC
SCK
SCLK
MOSI
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
80C51/80L51-to-AD5452W Interface
Figure 45. MC68HC11-to-AD5452W Interface
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 44. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, and RxD drives the serial data line,
SDIN. P1.1 is a bit-programmable pin on the serial port and is used
to drive SYNC. As data is transmitted to the switch, P1.1 is taken
low. The 80C51/80L51 transmit data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle.
If the user wants to verify the data previously written to the
input shift register, the SDO line can be connected to MISO of
the MC68HC11. In this configuration with SYNC low, the shift
register clocks data out upon the rising edges of SCLK.
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and a second write cycle is initiated to
transmit the second byte of data. Data on RxD is clocked out of
the microcontroller upon the rising edge of TxD and is valid upon
the falling edge. As a result, no glue logic is required between the
DAC and microcontroller interface. P1.1 is taken high following
the completion of this cycle. The 80C51/80L51 provide the LSB
of its SBUF register as the first bit in the data stream. The DAC
Rev. 0 | Page 20 of 24
10657-105
SPIxSEL
TxD
RxD
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5452W*
ADSP-BF5xx*
AD5452W*
8051*
10657-104
The ADSP-BF5xx family of processors has an SPI-compatible
port that enables the processor to communicate with SPIcompatible devices. A serial interface between the Blackfin®
processor and the AD5452W DAC is shown in Figure 42.
In this configuration, data is transferred through the MOSI
(master output, slave input) pin. SYNC is driven by the SPIxSEL
pin, which is a reconfigured programmable flag pin.
Data Sheet
AD5452W
MICROWIRE-to-AD5452W Interface
PCB LAYOUT AND POWER SUPPLY DECOUPLING
Figure 46 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
upon the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register upon the rising edge of SK, which
corresponds to the falling edge of the DAC’s SCLK.
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which an
AD5452W DAC is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the DAC is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
AD5452W*
MICROWIRE*
SCLK
SDIN
CS
SYNC
10657-106
SK
SO
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 46. MICROWIRE-to-AD5452W Interface
PIC16C6x/PIC16C7x-to-AD5452W Interface
The PIC16C6x/PIC16C7x synchronous serial port (SSP) is
configured as an SPI master with the clock polarity bit (CKP) = 0.
This is done by writing to the synchronous serial port control
register (SSPCON); see the PIC16/PIC17 Microcontroller
User Manual.
In this example, I/O Port RA1 is used to provide a SYNC signal
and enable the serial port of the DAC. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, two consecutive write operations are
required. Figure 47 shows the connection diagram.
AD5452W*
SCK/RC3
SCLK
SDI/RC4
SDIN
RA1
Components, such as clocks, that produce fast switching signals
should be shielded with a digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 47. PIC16C6x/7x-to-AD5452W Interface
10657-107
PIC16C6x/PIC16C7x*
These DACs should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply located as close to the package
as possible, ideally right up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), like the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is the best solution, but its use is not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane and signal
traces are placed on the solder side.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To optimize high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
Rev. 0 | Page 21 of 24
AD5452W
Data Sheet
Table 12. Overview of AD54xx and AD55xx Current Output Devices
Part No.
AD5424
AD5426
AD5428
AD5429
AD5450
AD5432
AD5433
AD5439
AD5440
AD5451
AD5443
AD5444
AD5415
AD5405
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
1
Resolution
8
8
8
8
8
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
No. DACs
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
INL (LSB)
±0.25
±0.25
±0.25
±0.25
±0.25
±0.5
±0.5
±0.5
±0.5
±0.25
±1
±0.5
±1
±1
±1
±1
±1
±0.5
±1
±2
±1
±1
±1
±1
±2
±2
±2
±2
Interface
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
Serial
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
Serial
Parallel
Package 1
RU-16, CP-20
RM-10
RU-20
RU-10
UJ-8
RM-10
RU-20, CP-20
RU-16
RU-24
UJ-8
RM-10
RM-10
RU-24
CP-40
RU-20, CP-20
RU-24
RU-16
UJ-8, RM-8
RM-10
UJ-8, RM-8
RM-8
RU-28
RM-8
RU-38
RM-8
RU-28
RU-16
RU-38
RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
Rev. 0 | Page 22 of 24
Features
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
12 MHZ BW, 50 MHz serial interface
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
12 MHz BW, 50 MHz serial interface
10 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial interface
12 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 n WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
Data Sheet
AD5452W
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.09
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.55
0.40
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
Figure 48. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADW50007Z-0REEL7
1
2
Resolution
12
INL
±0.5
Temperature Range
−40°C to +125°C
Package Description
8-Lead MSOP
Package Option
RM-8
Branding
D70
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADW50007Z model is available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for this model.
Rev. 0 | Page 23 of 24
AD5452W
Data Sheet
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10657-0-4/12(0)
Rev. 0 | Page 24 of 24