Intersil ISL75051SRHEVAL1Z 3a, rad hard, positive, ultra low dropout regulator Datasheet

3A, Rad Hard, Positive, Ultra Low Dropout Regulator
ISL75051SRH
Features
The ISL75051SRH is a radiation hardened low-voltage,
high-current, single-output LDO specified for up to 3.0A of
continuous output current. These devices operate over an input
voltage range of 2.2V to 6.0V and are capable of providing
output voltages of 0.8V to 5.0V adjustable based on resistor
divider setting. Dropout voltages as low as 65mV can be
realized using the device.
• DLA SMD#5962-11212
The OCP pin allows the short circuit output current limit
threshold to be programmed by means of a resistor from the
OCP pin to GND. The OCP setting range is from 0.5A minimum
to 8.5A maximum. The resistor sets the constant current
threshold for the output under fault conditions. The thermal
shutdown disables the output if the device temperature
exceeds the specified value. It subsequently enters an ON/OFF
cycle until the fault is removed. The ENABLE feature allows the
part to be placed into a low current shutdown mode that
typically draws about 1µA. When enabled, the device operates
with a typical low ground current of 11mA, which provides for
operation with low quiescent power consumption.
The device is optimized for fast transient response and single
event effects. This reduces the magnitude of SET seen on the
output. Additional protection diodes and filters are not needed.
The device is stable with tantalum capacitors as low as 47µF
and provides excellent regulation all the way from no load to
full load. Programmable soft-start allows the user to program
the inrush current by means of the decoupling capacitor value
used on the BYP pin.
Applications
• Output Current Up to 3.0A at TJ = 150°C
• Output Accuracy ±1.5% over MIL Temp Range
• Ultra Low Dropout:
- 65mV Typ Dropout at 1.0A
- 225mV Typ Dropout at 3.0A
• Noise of 100µVRMS from 300Hz to 300kHz
• SET Mitigation with No Added Filtering/Diodes
• Input Supply Range: 2.2V to 6.0V
• Fast Load Transient Response
• Shutdown Current of 1µA Typ
• Output Adjustable Using External Resistors
• PSRR 66dB Typ @ 1kHz
• Enable and PGood Feature
• Programmable Soft-start/Inrush Current Limiting
• Adjustable Overcurrent Limit from 0.5A to 8.5A
• Over-temperature Shutdown
• Stable with 47µF Min Tantalum Capacitor
• 18 Ld Ceramic Flatpack Package
• Radiation Environment
- High Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 krad(Si)
- SET/SEL/SEB . . . . . . . . . . . . . . . . . . . . . . . .86 MeV•cm2/mg
• LDO Regulator for Space Application
• DSP, FPGA and µP Core Power Supplies
• Post-regulation of Switched Mode Power Supplies
• Down-hole Drilling
0.30
EN
EN
BYP
OCP
0.1uF
ADJ
ISL75051SRH
VIN
220uF
VOUT
VIN
VOUT
PG
GND
R1
0.1uF
0.1uF
2.67k
VIN
4.7n
PG
R2
100pF
220uF
DROPOUT VOLTAGE (V)
ROCP
+150°C
0.25
+125°C
0.20
0.15
+25°C
0.10
0.05
0.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
IOUT (A)
FIGURE 1. TYPICAL APPLICATION
November 4, 2011
FN7610.1
1
FIGURE 2. DROPOUT vs IOUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL75051SRH
Block Diagram
VIN
CURRENT
LIMIT ADJ
OCP
520MV
POWER
PMOS
REFERENCE
BIAS
BYPASS
VOUT
CURRENT
LIMIT
THERMAL
SHUTDOWN
LEVEL
SHIFT
ENABLE
ADJ
VADJ
PGOOD
DELAY
450mV
GND
Typical Applications
EN
EN
10
9
BYP
OCP
11
8
ADJ
VIN
12
7
VOUT
VIN
13
6
VOUT
VIN
14
5
ISL75051SRH
VOUT
VIN
15
4
VOUT
VIN
16
3
VOUT
VIN
17
2
VOUT
PG
18
1
GND
511
0.2uF
VIN
VOUT
220uF
0.1uF
0.1uF
4.32k
220uF
2.67k
4.7n
VIN
2.26k
5.49k
100pF
PG
2
FN7610.1
November 4, 2011
ISL75051SRH
Pin Configuration
ISL75051SRH
(18LD CDFP)
TOP VIEW
GND
1
18
PG
VOUT
2
17
VIN
VOUT
3
16
VIN
VOUT
4
15
VIN
VOUT
5
14
VIN
VOUT
6
13
VIN
VOUT
7
12
VIN
VADJ
8
11
OCP
BYP
9
10
EN
GND
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
12, 13, 14
15, 16, 17
VIN
Input supply pins
18
PG
VOUT in regulation signal. Logic low defines when VOUT is not in regulation. Must be grounded if not used.
1
GND
GND pin
2, 3, 4
5, 6, 7
VOUT
Output voltage pins
8
VADJ
VADJ pin allows VOUT to be programmed with an external resistor divider.
9
BYP
To filter the internal reference, connect a 0.1µF capacitor from BYP pin to GND.
10
EN
VIN independent chip enable. TTL and CMOS compatible.
11
OCP
Allows current limit to be programmed with an external resistor.
Top Lid
GND
The top lid is connected to GND pin of the package.
3
FN7610.1
November 4, 2011
ISL75051SRH
Ordering Information
ORDERING
NUMBER
PART NUMBER
(NOTES 1, 2)
TEMP
RANGE (°C)
PACKAGE
PKG DWG. #
5962R1121201VXC
ISL75051SRHVF
-55 to +125
18 Ld CDFP
K18.D
5962R1121201QXC
ISL75051SRHQF
-55 to +125
18 Ld CDFP
K18.D
5962R1121201V9A
ISL75051SRHVX
-55 to +125
Die
ISL75051SRHX/SAMPLE
ISL75051SRHX/SAMPLE
-55 to +125
Die Sample
ISL75051SRHF/PROTO
ISL75051SRHF/PROTO
-55 to +125
18 Ld CDFP
ISL75051SRHEVAL1Z
Evaluation Board
K18.D
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL75051SRH. For more information on MSL please see
Tech Brief TB363.
4
FN7610.1
November 4, 2011
ISL75051SRH
Absolute Maximum Ratings
Thermal Information
VIN Relative to GND (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.7V
VOUT Relative to GND (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.7V
PG, EN, OCP/ADJ Relative to GND (Note 3). . . . . . . . . . . . . -0.3 to +6.7VDC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
18 Ld CDFP Package (Notes 5, 6) . . . . . . .
28
4
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Recommended Operating Conditions (Note 4)
Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Junction Temperature (TJ) (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2V to 6.0V
VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8V to 5.0V
PG, EN, OCP/ADJ relative to GND . . . . . . . . . . . . . . . . . . . . . . . 0V to +6.0V
Radiation Information
Max Total Dose
(Dose Rate = 50 - 300radSi/s . . . . . . . . . . . . . . . . . . . . . . . 100 krad (Si)
SET (VOUT < ±5% During Events (Note 7). . . . . . . . . . . . . . 86MeV•cm2/mg
SEL/B (No Latchup/Burnout . . . . . . . . . . . . . . . . . . . . . . . . 86MeV•cm2/mg
The output capacitance used for SEE testing is 220µF for CIN and COUT,
200nF for BYPASS
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions
define limits where specifications are guaranteed.
4. Refer to “Thermal Guidelines” on page 12.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379
6. For θJC, the “case temp” location is the center of the package underside.
7. The device can work down to VOUT = 0.8V; however, the SET performance of < ±5% at LET = 86MeV.cm2/mg is guaranteed at VOUT = >1.5V only. SET
tests performed with 220µF 10V 25mΩ and 0.1µF CDR04 capacitor on the input and output.
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the following specified conditions:
VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 220µF 25mΩ and 0.1µF X7R, TJ = +25°C, IL = 0A. Applications must follow thermal guidelines of
the package to determine worst-case junction temperature. Please refer to “Applications Information” on page 11 of the datasheet and
Tech Brief TB379. Boldface limits apply over the operating temperature range, -55°C to +125°C. Pulse load techniques used by ATE to ensure
TJ = TA defines guaranteed limits.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
-1.5
0.2
1.5
%
-1.5
0.2
1.5
%
514.8
520
525.2
mV
DC CHARACTERISTICS
DC Output Voltage Accuracy
VOUT
VOUT Resistor adjust to 0.52V, 1.5V and 1.8V
2.2V < VIN < 3.6V; 0A < ILOAD < 3.0A
VOUT Resistor adjust to 5.0V
VOUT + 0.4V < VIN < 6.0V; 0A < ILOAD < 3.0A
Feedback Pin
VADJ
2.2V < VIN < 6.0V; ILOAD = 0A
BYP Pin
VBYP
2.2V < VIN < 6.0V; ILOAD = 0A
520
DC Input Line Regulation
2.2V < VIN < 3.6V, VOUT = 1.5V, +25°C & -55°C
(Note 9)
1.13
3.5
mV
DC Input Line Regulation
2.2V < VIN < 3.6V, VOUT = 1.5V, +125°C (Note 9)
1.13
8.0
mV
DC Input Line Regulation
2.2V < VIN < 3.6V, VOUT = 1.8V, +25°C & -55°C
(Note 9)
1.62
3.5
mV
DC Input Line Regulation
2.2V < VIN < 3.6V, VOUT = 1.8V, +125°C (Note 9)
1.62
10.5
mV
DC Input Line Regulation
VOUT + 0.4V < VIN < 6.0V, VOUT = 5.0V (Note 9)
12.50
20.0
mV
DC Output Load Regulation
VOUT = 1.5V; 0A < ILOAD < 3.0A, VIN = VOUT + 0.4V
(Note 9)
-4.0
-0.8
-0.1
mV
DC Output Load Regulation
VOUT = 1.8V; 0A < ILOAD < 3.0A, VIN = VOUT + 0.4V
(Note 9)
-4.0
-1.2
-0.05
mV
DC Output Load Regulation
VOUT = 5.0V; 0A < ILOAD < 3.0A, VIN = VOUT + 0.4V
(Note 9)
-15.0
-6.0
-0.05
mV
5
mV
FN7610.1
November 4, 2011
ISL75051SRH
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the following specified conditions:
VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 220µF 25mΩ and 0.1µF X7R, TJ = +25°C, IL = 0A. Applications must follow thermal guidelines of
the package to determine worst-case junction temperature. Please refer to “Applications Information” on page 11 of the datasheet and
Tech Brief TB379. Boldface limits apply over the operating temperature range, -55°C to +125°C. Pulse load techniques used by ATE to ensure
TJ = TA defines guaranteed limits. (Continued)
PARAMETER
SYMBOL
Feedback Input Current
TEST CONDITIONS
MIN
(Note 8)
TYP
VADJ = 0.5V
MAX
(Note 8)
UNITS
1
µA
Ground Pin Current
IQ
VOUT = 1.5V; ILOAD = 0A, VIN = 2.2V
11
12
mA
Ground Pin Current
IQ
VOUT = 5.0V; ILOAD = 0A, VIN = 6.0V
16
18
mA
Ground Pin Current
IQ
VOUT = 1.5V; ILOAD = 3.0A, VIN = 2.2V
11
13
mA
Ground Pin Current
IQ
VOUT = 5.0V; ILOAD = 3.0A, VIN = 6.0V
16
18
mA
ENABLE Pin = 0V, VIN = 6.0V
1
10
µA
Ground Pin Current in Shutdown
ISHDN
Dropout Voltage
VDO
ILOAD = 1.0A, VOUT = 2.5V (Note 10)
65
100
mV
Dropout Voltage
VDO
ILOAD = 2.0A, VOUT = 2.5V (Note 10)
140
200
mV
Dropout Voltage
VDO
ILOAD = 3.0A, VOUT = 2.5V (Note 10)
225
300
mV
Output Short Circuit Current
ISCL
VOUT = 0V, VIN = 2.2V, RSET = 5.11k
1.1
A
Output Short Circuit Current
ISCL
VOUT = 0V, VIN = 6.0V, RSET = 5.11k
1.2
A
Output Short Circuit Current
ISCH
VOUT = 0V, VIN = 2.2V, RSET = 511Ω
5.7
A
Output Short Circuit Current
ISCH
VOUT = 0V, VIN = 6.0V, RSET = 511Ω
6.2
A
Thermal Shutdown Temperature
TSD
VOUT + 0.4V < VIN < 6.0V
175
°C
Thermal Shutdown Hysteresis
(Rising Threshold)
TSDn
VOUT + 0.4V < VIN < 6.0V
25
°C
Input Supply Ripple Rejection
PSRR
VP-P = 300mV, f = 1kHz, ILOAD = 3A; VIN = 2.5V,
VOUT = 1.8V
66
dB
Input Supply Ripple Rejection
PSRR
VP-P = 300mV, f = 100kHz, ILOAD = 3A; VIN = 2.5V,
VOUT = 1.8V
30
dB
AC CHARACTERISTICS
42
Phase Margin
PM
VOUT = 1.8V, CL = 220µF Tantalum
70
dB
Gain Margin
GM
VOUT = 1.8V, CL = 220µF Tantalum
16
dB
ILOAD = 10mA, BW = 300Hz < f < 300kHz, BYPASS
to GND capacitor = 0.2µF
100
µVRMS
Output Noise Voltage
DEVICE START-UP CHARACTERISTICS: ENABLE PIN
Rising Threshold
2.2V < VIN < 6.0V
0.6
0.9
1.2
V
Falling Threshold
2.2V < VIN < 6.0V
0.47
0.7
0.9
V
Enable Pin Leakage Current
VIN = 6.0V, EN = 6.0V
1
µA
Enable Pin Propagation Delay
VIN = 2.2V, EN rise to IOUT rise
450
µs
Enable Pin Turn-on Delay
VIN = 2.2V, VOUT = 1.8V, ILOAD = 1A, COUT = 220µF,
CBYP = 0.2µF
6
ms
Enable Pin Turn-on Delay
VIN = 2.2V, VOUT=1.8V, ILOAD = 1A, COUT = 47µF,
CBYP = 0.2µF
50
µs
Hysteresis
Must be independent of VIN; 2.2V < VIN < 6.0V
90
200
318
mV
VOUT Error Flag Rising Threshold
2.2V < VIN < 6.0V
85
90
96
%
VOUT Error Flag Falling Threshold
2.2V < VIN < 6.0V
82
88
93
%
VOUT Error Flag Hysteresis
2.2V < VIN < 6.0V
2.5
3.2
4.0
%VOUT
225
300
DEVICE START-UP CHARACTERISTICS: PG PIN
6
FN7610.1
November 4, 2011
ISL75051SRH
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the following specified conditions:
VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 220µF 25mΩ and 0.1µF X7R, TJ = +25°C, IL = 0A. Applications must follow thermal guidelines of
the package to determine worst-case junction temperature. Please refer to “Applications Information” on page 11 of the datasheet and
Tech Brief TB379. Boldface limits apply over the operating temperature range, -55°C to +125°C. Pulse load techniques used by ATE to ensure
TJ = TA defines guaranteed limits. (Continued)
PARAMETER
SYMBOL
MIN
(Note 8)
TEST CONDITIONS
TYP
MAX
(Note 8)
UNITS
Error Flag Low Voltage
ISINK = 1mA
35
100
mV
Error Flag Low Voltage
ISINK = 6mA
185
400
mV
Error Flag Leakage Current
VIN = 6.0V, PG = 6.0V
0.01
1
µA
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at -55°C, +25°C and +125°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
9. Line and Load Regulation done under pulsed condition for T<10ms.
10. Dropout is defined as the difference between the supply VIN and VOUT, when the supply produces a 2% drop in VOUT from its nominal value. Data
measured within a 3ms period.
Typical Operating Performance
0.522
1.528
1.524
VOUT (V)
1.522
+25°C, VOUT (mV)
-58°C, VOUT (mV)
0.520
1.520
1.518
+128°C, VOUT (mV)
1.516
-58°C, VADJ (mV)
0.519
0.518
+128°C, VADJ (mV)
0.517
1.514
1.512 VIN = 2.5V
V
= 1.5V
1.510 OUT
0.0
0.5
1.0
+25°C, VADJ (mV)
0.521
VADJ (V)
1.526
1.5
2.0
2.5
3.0
0.516 V = 2.5V
IN
V
= 1.5V
0.515 OUT
0.0
0.5
1.0
3.5
FIGURE 3. LOAD REGULATION, VOUT vs IOUT
2.510
0.5210
3.5
+25°C, VADJ (mV)
-58°C, VADJ (mV)
0.5200
+25°C, VOUT (mV)
+128°C, VOUT (mV)
0.5195
0.5190
0.5185
0.5180
0.5170
0.5165
1.5
2.0
2.5
3.0
IOUT (A)
FIGURE 5. LOAD REGULATION, VOUT vs IOUT
7
+128°C, VADJ (mV)
0.5175
2.495
2.490 VIN = 3.3V
V
= 2.5V
2.485 OUT
0.0
0.5
1.0
3.0
0.5205
-58°C, VOUT (mV)
2.505
2.500
2.5
0.5215
VADJ (V)
VOUT (V)
2.515
2.0
FIGURE 4. LOAD REGULATION, VADJ vs IOUT
2.525
2.520
1.5
IOUT (A)
IOUT (A)
3.5
VIN = 3.3V
VOUT = 2.5V
0.5160
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IOUT (A)
FIGURE 6. LOAD REGULATION, VADJ vs IOUT
FN7610.1
November 4, 2011
ISL75051SRH
Typical Operating Performance
(Continued)
0.5215
4.090
+25°C, VADJ (mV)
0.5210
4.085
0.5205
+128°C, VOUT (mV)
4.070
1.0
1.5
2.0
0.5190
+128°C, VADJ (mV)
0.5185
0.5180
0.5170
VIN = 5V
VOUT = 4V
0.5
0.5195
0.5175
-58°C, VOUT (mV)
4.060
0.0
VADJ (V)
VOUT (V)
+25°C, VOUT (mV)
4.075
4.065
-58°C, VADJ (mV)
0.5200
4.080
2.5
3.0
3.5
0.5165 VIN = 5V
V
= 4V
0.5160 OUT
0.0
0.5
1.0
1.5
IOUT (A)
FIGURE 7. LOAD REGULATION, VOUT vs IOUT
2.5
3.0
3.5
FIGURE 8. LOAD REGULATION, VADJ vs IOUT
8
0.525
ROCP = 0.511k
7
0.523
6
+25°C, VADJ (mV)
0.521
0.519
-58°C, VADJ (mV)
+128°C, VADJ (mV)
ROCP = 0.681k
5
OCP (A)
VADJ (V)
2.0
IOUT (A)
ROCP = 0.75k
ROCP = 1.00k
4
3
ROCP = 1.47k
ROCP = 2.00k
ROCP = 2.61k
ROCP = 3.83
2
0.517
1
0.515
2.0
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
2.0
2.5
3.0
3.5
4.0
VIN (V)
5.5
6.0
6.5
7.0
FIGURE 10. ROCP vs OCP AT +25°C, VOUT = 1.5V
8
8
ROCP = 0.511k
7
6
7
6
ROCP = 0.681k
5
4
3
ROCP = 0.75k
ROCP = 1.00k
ROCP = 1.47k
ROCP = 2.00k
OCP (A)
OCP (A)
5.0
VIN (V)
FIGURE 9. VIN vs VADJ OVER TEMPERATURE
2
ROCP = 0.511k
ROCP = 0.681k
5
4
3
ROCP = 0.75k
ROCP = 1.00k
ROCP = 1.47k
ROCP = 2.00k
2
1
0
2.0
4.5
ROCP = 5.11k
1
ROCP = 2.61k
2.5
3.0
3.5
ROCP = 3.83
4.0
4.5 5.0
VIN (V)
5.5
ROCP = 5.11k
6.0
6.5
FIGURE 11. ROCP vs OCP AT +128°C, VOUT = 1.5V
8
7.0
0
2.0
ROCP = 3.83
ROCP = 2.61k
2.5
3.0
3.5
4.0
4.5 5.0
VIN (V)
ROCP = 5.11k
5.5
6.0
6.5
7.0
FIGURE 12. ROCP vs OCP AT -58°C, VOUT = 1.5V
FN7610.1
November 4, 2011
ISL75051SRH
Typical Operating Performance
FIGURE 13. TRANSIENT LOAD RESPONSE, VIN = 3.3V,
VOUT = 2.5V, COUT = 47µF, 35mΩ
(Continued)
FIGURE 14. TRANSIENT LOAD RESPONSE, VIN = 3.3V,
VOUT = 2.5V, COUT = 220µF, 25mΩ
FIGURE 15. POWER-ON AND POWER-OFF, EN = 0 TO 1,
+25°C, VIN = 6V, VOUT = 0.8V, IOUT = 0.5A, PGOOD
TURN-ON
FIGURE 16. POWER-ON AND POWER-OFF, EN = 0 TO 1,
+25°C, VIN = 2.2V, VOUT = 0.8V, IOUT = 0.5A,
PGOOD TURN-ON
FIGURE 17. POWER-ON AND POWER-OFF, EN = 1 TO 0,
+25°C, VIN = 6V, VOUT = 0.8V, IOUT = 0.5A, PGOOD
TURN-OFF
FIGURE 18. POWER-ON AND POWER-OFF, EN = 1 TO 0,
+25°C, VIN = 2.2V, VOUT = 0.8V, IOUT = 0.5A,
PGOOD TURN-OFF
9
FN7610.1
November 4, 2011
ISL75051SRH
Typical Operating Performance
(Continued)
140
NOISE (µV/√Hz 0.5)
120
100
80
60
40
>
20
0
0
50k
100k
150k
200k
250k
300k
FREQUENCY (Hz)
>
FIGURE 19. NOISE (µV/√Hz O.5)
>
FIGURE 20. PSRR
10
FN7610.1
November 4, 2011
ISL75051SRH
Applications Information
Input Voltage Requirements
This RH LDO will work from a VIN in the range of 2.2V to 6.0V. The
input supply can have a tolerance of as much as ±10% for
conditions noted in the “Electrical Specifications” table starting
on page 5. Minimum guaranteed input voltage is 2.2V. However,
due to the nature of an LDO, VIN must be some margin higher
than the output voltage, plus dropout at the maximum rated
current of the application, if active filtering (PSRR) is expected
from VIN to VOUT. The dropout spec of this family of LDOs has
been generously specified to allow applications to design for
efficient operation.
TABLE 2. TYPICAL GM/PM WITH VARIOUS CAPACITORS
CAPACITANCE
(µF)
ESR
(mΩ)
GAIN MARGIN
(dB)
PHASE MARGIN
(°)
47
35
14
55
100
25
16
57
220
6
19
51
220
25
16
69
100
100
10
62
Type numbers of KEMET capacitors used in the device are shown
in Table 3.
Adjustable Output Voltage
TABLE 3. KEMET CAPACITORS USED IN DEVICE
The output voltage of the RH LDO can be set to any user
programmable level between 0.8V to 5.0V. This is achieved with
a resistor divider connected between the OUT, ADJ and GND pins.
With the internal reference at 0.52V, the divider ratio should be
fixed such that when the desired VOUT level is reached, the
voltage presented to the ADJ pin is 0.52V. Resistor values for
typical voltages are shown in Table 1.
TABLE 1. RESISTOR VALUES FOR TYPICAL VOLTAGES
RBOTTOM
0.8V
7.87k
4.32k
1.5V
2.26k
4.32k
1.8V
1.74k
4.32k
2.5V
1.13k
4.32k
4.0V
634
4.32k
5.0V
499
4.32k
Input and Output Capacitor Selection
RH operation requires the use of a combination of tantalum and
ceramic capacitors to achieve a good volume-to-capacitance
ratio. The recommended combination is a 220µF, 25mΩ 10V
DSSC 04051-032 rated tantalum capacitor in parallel with a
0.1µF MIL-PRF-49470 CDR04 ceramic capacitor, to be
connected between VIN to GND pins and VOUT to GND pins of the
LDO, with PCB traces no longer than 0.5cm.
The stability of the device depends on the capacitance and ESR
of the output capacitor. The usable ESR range for the device is
6mΩ to 100mΩ. At the lower limit of ESR = 6mΩ, the phase
margin is about 51°C. On the high side, an ESR of 100mΩ is
found to limit the gain margin at around 10dB. The typical
GM/PM seen with capacitors are shown in Table 2.
T525D476M016ATE035
47µF, 10V, 35mΩ
T525D107M010ATE025
100µF, 10V, 25mΩ
T530D227M010ATE006
220µF, 10V, 6mΩ
T525D227M010ATE025
220µF, 10V, 25mΩ
T495X107K016ATE100
100µF, 16V, 100mΩ
A typical gain phase plot measured on the ISL75051SRHEVAL1Z
evaluation board for VIN = 3.3V, VOUT = 1.8V and IOUT = 3A with a
220µF, 10V, 25mΩ capacitor is shown in Figure 21 and is
measured at GM = 16.3dB and PM = 69.16°.
GAIN (dB)
RTOP
CAPACITOR DETAILS
60
50
40
30
20
10
0
-10 3.3V
-20 1.8V
-30 3.0A
-40 1x220µF
-50
T525D
-60
500
180
150
120
90
60
30
0
-30
-60
-90
-120
-150
-180
PHASE
GAIN
5k
50k
500k
PHASE (°)
VOUT
KEMET TYPE NUMBER
5M
FREQUENCY (Hz)
FIGURE 21. TYPICAL GAIN PHASE PLOT
Enable
The device can be enabled by applying a logic high on the EN pin.
The enable threshold is typically 0.9V. A soft-start cycle is
initiated when the device is enabled using this pin. Taking this pin
to logic low disables the device.
EN can be driven from either an open drain or a totem pole logic
drive between EN pin and GND. Assuming an open drain
configuration, M1 will actively pull down the EN line, as shown in
Figure 22, and thereby discharge the input capacitance, shutting
off the device immediately.
11
FN7610.1
November 4, 2011
ISL75051SRH
Current Limit Protection
VIN
R1
10k
INT EN GATE
EN PIN
INT EN BUS
M1
EN
The RH LDO incorporates protection against overcurrent due to
any short or overload condition applied to the output pin. The
current limit circuit becomes a constant current source when the
output current exceeds the current limit threshold, which can be
adjusted by means of a resistor connected between the OCP pin
and GND. If the short or overload condition is removed from VOUT,
then the output returns to normal voltage mode regulation. OCP
can be calculated with Equation 2:
(EQ. 2)
OCP = 9.5 • EXP ( – 0.6 • ( ROCP ⁄ ( 1 + 0.1ROCP ) ) )
0
where OCP = Overcurrent Threshold in amps, and ROCP = OCP
resistor in kΩ.
FIGURE 22. ENABLE
Power Good
The Power-Good pin is asserted high when the voltage on the ADJ
pin crosses the rising threshold of 0.9 x VADJ typ. On the falling
threshold, Power-Good is asserted low when the voltage on the
ADJ pin crosses the falling threshold of 0.88 x VADJ. The
power-good output is an open-drain output rated for a continuous
sink current of 1mA.
In the event of an overload condition based on the set OCP limit,
the die temperature may exceed the internal over-temperature
limit, and the LDO begins to cycle on and off due to the fault
condition (Figure 24). However, thermal cycling may never occur
if the heatsink used for the package can keep the die
temperature below the limits specified for thermal shutdown.
8
7
Soft-start is achieved by means of the charging time constant of
the BYP pin. The capacitor value on the pin determines the time
constant and can be calculated using Equation 1:
6
T S = 0.00577xC S
(EQ. 1)
OCP (A)
Soft-start
5
4
OCP = +25°C
3
2
where TS = soft-start time in ms, and CS = BYPASS capacitor in
nF.
The BYPASS capacitor, C1, charges with a 90µA source current
and provides an EA reference, -IN, with an SS ramp. VOUT, in turn,
follows this ramp. The ramp rate can be calculated based on the
C1 value. For conditions in which C1 is opened, or for small
values of C1, the ramp is provided by C2 = 50pF, with a source of
0.5µA. Connecting C1 min = 0.1µF to the BYPASS pin is
recommended for normal operation.
ADJ PIN
VIN
VIN
I1
I2
90µAdc
BYPASS
EXT PIN
C1
0.1µF
0
0.5µAdc
U1
+IN
INT SS NODE -IN OUT
-IN
ISL75051SRH EA
C2
50pF
0
FIGURE 23. SOFT-START
12
VIN
75051_PMOS
M1
VOUT
1
0
0
1
2
3
4
5
6
ROCP (kΩ)
FIGURE 24. OCP vs ROCP OVER TEMP
Thermal Guidelines
If the die temperature exceeds typically +175°C, then the LDO
output shuts down to zero until the die temperature cools to
typically +155°C. The level of power combined with the thermal
impedance of the package (θJC of 4°C/W for the 18 Ld CDFP
package) determines whether the junction temperature exceeds
the thermal shutdown temperature specified in the “Electrical
Specifications” table.
The device should be mounted on a high effective thermal
conductivity PCB with thermal vias, per JESD51-7 and JESD51-5.
Place a silpad between package base and PCB copper plane. The
VIN and VOUT ratios should be selected to ensure that dissipation
for the selected VIN range keeps TJ within the recommended
operating level of 150°C for normal operation.
FN7610.1
November 4, 2011
ISL75051SRH
Weight Characteristics
Weight of Packaged Device
K18.D: 1.07 Grams typical with leads clipped
Die Characteristics
Die Dimensions
BACKSIDE FINISH
Silicon
PROCESS
0.6µM BiCMOS Junction Isolated
ASSEMBLY RELATED INFORMATION
Substrate Potential
4555µm x 4555µm (179.3 mils x 179.3 mils)
Thickness: 304.8µm ± 25.4µm (12.0 mils ± 1 mil)
Unbiased
ADDITIONAL INFORMATION
Interface Materials
Worst Case Current Density
GLASSIVATION
< 2 x 105 A/cm2
Type: Silicon Oxide and Silicon Nitride
Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm
TOP METALLIZATION
Type: AlCu (99.5%/0.5%)
Thickness: 2.7µm ±0.4µm
BACKSIDE METALLIZATION
None
Transistor Count
2932
Layout Characteristics
Step and Repeat
4555µm x 4555µm
Metallization Mask Layout
SUBSTRATE
Type: Silicon
PAD X Y COORDIN ATES
PAD NAME X µm Y µm
1
G ND
0
0
2
G ND
-393
0
3
VO UT -711 -710
4
VO UT -711 -1858
5
VO UT -711 -2964
6
ADJ -1680 -3070
7
BYP -1621 -3879
8
EN
2164 -3879
9
O CP 2222 -3131
10
VIN
1078 -2965
11
VIN
1078 -1853
12
VIN
1078 -711
13
PG
420
-25
13
FN7610.1
November 4, 2011
ISL75051SRH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
CHANGE
November 4, 2011
FN7610.1
Removed “Coming Soon” from ISL75051SRHVF, ISL75051SRHQF, ISL75051SRHVX and
ISL75051SRHX/SAMPLE in “Ordering Information” table on page 4.
September 30, 2011
FN7610.0
Initial Release
Products
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14
FN7610.1
November 4, 2011
ISL75051SRH
Package Outline Drawing
K18.D
18 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 2, 3/11
0.015 (0.381)
0.005 (0.127)
PIN NO. 1
ID OPTIONAL
1
2
0.040 (1.016 BSC)
0.476 (12.09)
0.456 (11.58)
PIN NO. 1
ID AREA
0.005 (0.127)
MIN
4
0.020 (0.508)
0.013 (0.330)
0.122 (3.10)
0.100 (2.54) 0.038 (0.97)
0.026 (0.66)
-C-
TOP VIEW
6
0.397 (10.084)
0.377 (9.576)
0.283 (7.19)
MIN
0.010 (0.25)
0.004 (0.10)
-D-
0.350 (8.89)
0.250 (6.35)
-H-
0.03 (0.76) MIN
SEATING AND
BASE PLANE
SIDE VIEW
NOTES:
0.007 (0.178)
0.004 (0.102)
LEAD FINISH
BASE
METAL
0.010 (0.254)
0.004 (0.102)
0.017 (0.432)
0.013 (0.330)
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
4. Measure dimension at all four corners.
0.0015 (0.04)
MAX
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
0.020 (0.508)
0.013 (0.330)
3
SECTION A-A
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Dimensions = INCH (mm). Controlling dimension: INCH.
15
FN7610.1
November 4, 2011