ON AMIS-49200-XTP Fieldbus mau Datasheet

AMIS-492x0
Fieldbus MAU
1.0 Introduction
1.1 Overview
AMIS-492x0 Fieldbus MAU (media access unit) is a transceiver chip for low speed FOUNDATION Fieldbus® and Profibus® PA
devices. The AMIS-49200 was originally designed to be a near pin-for-pin replacement of the Yokogawa μSAA22Q MAU. “Near pinfor-pin” means that associated component values may change, but no board changes are required. A micro-leadframe package option
(NQFP) is also available, the AMIS-49250.
1.2 Definitions, Acronyms and Abbreviations
IC
ESD
FF
LQFP
Manchester
MAU
MDS
NQFP
- Integrated circuit
- Electrostatic discharge
- FOUNDATION Fieldbus
- Low profile quad flat pack
- Communications encoding scheme implemented in FOUNDATION Fieldbus
- Medium attachment unit
- Medium dependent sub-layer
- “Near chip-scale” quad flat pack
μSAA22Q
- Name of Yokogawa’s MAU IC
1.3 References
• Fieldbus Medium Attachment Unit (MAU) Chip, μSAA22Q, Yokogawa Electric Corporation, June 12, 1998, Document No.: SS-96-01
(Rev.3).
• Fieldbus Standard for Use in Industrial Control Systems Part 2: Physical Layer Specification and Service Definition, Amendment to
Clause 22 ISA/SP50 –1996-544B, dS50.02, Part 2, Draft Standard.
• Profibus PA specifications EN 50170 (formerly DIN 19245) covers all of Profibus and includes PA (31.25 kbps Intrinsically Safe
Physical Layer), references IEC 61158-2.
©2008 SCILLC. All rights reserved.
June 2008 – Rev. 6
Publication Order Number:
492x0/D
AMIS-492x0
2.0 AMIS-492x0 Fieldbus MAU Description
2.1 Features
AMIS-492x0 Fieldbus MAU is a transceiver IC for low speed FOUNDATION Fieldbus and Profibus PA devices. It incorporates the
following features:
• All node power can be supplied by the bus, via the AMIS-492x0
• Current consumption 500uA (typ)
• VCC voltage: 6.2V to 4.75V
• VDD voltage: 5.5V to 2.7V
• Compatible to IEC 1158-2 and ISA 50.02
• Shunt regulator
• Voltage reference (internal only)
• Series regulator
• Band-pass filter
• Slew rate control
• Segment current control
• Low voltage detection
• Carrier detect
• Data rate: 31.25kbps voltage mode
• Dual voltage supply 3-6.2V
• 44-pin LQFP/NQFP package
Rev. 6 | Page 2 of 22 | www.onsemi.com
AMIS-492x0
2.2 Block Diagram
33
Receive Block
35
31
VSS
30
FLTOUT
FLT
Zero-Cross
Detector
RXS
HPF
SIGIN
Bandpass Filter
34
32
LPF
Carrier
Detector
RXA
28
27
29
CCD
Transmit Block
26
MDS_CTRL
38
POL
36
TXE
37
TXS
1
41
42
43
VDRV
Tri-Level Modulator
&
Slew Control
MDS
Interface
CRT
VSS
VSS
VSS
CCINP
VSS
CCINM
Current
Driver
VSS
CCOUT
VSS
39
VSS
40
VSS
Power Supply Block
Vmid
Reference
Vmid
19
20
22
23
24
25
3
VCC
VCC
44
VCC
21
VCC
VCC
Bias
Circuitry
18
Vmid
Vref
Bandgap
2
Vref
VDD
17
VCC
13
VO
Series
Regulator
SRSET
VSS
11
SRTR SRAO
15
14
Shunt
Regulator
Low Voltage
Detectors
SRSETIN
12
N_PFail2
5
N_PFail1
4
SHUNT
SHSETIN SHSET SGND
6
7
Figure 1: AMIS-492x0 Fieldbus MAU Block Diagram
Rev. 6 | Page 3 of 22 | www.onsemi.com
9
VSS
16
10
8
AMIS-492x0
2.3 Package Information
The IC is packaged as shown below.
Figure 2: AMIS-49200 Package Dimensions (44-pin LQFP)
Rev. 6 | Page 4 of 22 | www.onsemi.com
AMIS-492x0
Figure 3: AMIS-49250 Package Dimensions (44-pin NQFP)
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AMIS-492x0
Table 1: Pin Numbers and Signal Description
Signal Name
Pin No.
I/O (Note 1)
VSS
1
Ground
VREF
2
AO
Description
Connect to ground
Internal bandgap voltage (1.18V)
VMID
3
AO
2V bias voltage for AC signals
N_PFAIL1
4
AI/O
Power fail alarm at VCC input. This pin is an open-drain output of negative logic.
N_PFAIL2
5
AI/O
Power fail alarm at VDD input. This pin is an open-drain output of negative logic.
SHSETIN
6
AI
Feedback (non-inverting) input for the shunt regulator
SHSET
7
AO
Divided voltage of VCC input. Feeding this voltage to SHSETIN pin results in 5V voltage at
VCC.
SHUNT
8
AI
Control pin of the shunt regulator. Its sink current (25mA max) is controlled so that the voltage
at SHSETIN is equal to VREF (1.18V).
VSS/
SGND
9
Ground
The current absorbed by SHUNT pin (25mA max) is fed to this pin, which must be connected to
the ground level
VSS
10
Ground
Ground
VSS
11
Ground
Ground
SRSETIN
12
AI
Feedback (inverting) input for the series regulator. The series regulator controls its output
(SRAO) to make this input voltage is equal to VREF (1.18V).
SRSET
13
AO
Divided voltage of VO output. Feeding this voltage into SRSETIN pin results in 3V at VO pin.
SRAO
14
AO
Output pin of an operational amplifier for the series regulator
Gate of a PMOS transistor for the series regulator
SRTR
15
AI
VO
16
AO
VDD
17
Digital supply
Supply voltage input for digital block
VCC
18
Analog supply
Analog supply voltage
CRT
19
AI/O
VSS
20
Ground
VDRV
21
AO
VSS
22
Ground
Output pin of the series regulator (20mA max)
Current integration to limit output slew rate
Ground
Output of an operational amplifier for slew rate control. This signal can be fed to current driver.
Ground
CCINP
23
AI
Non-inverting input of an operational amplifier for transmission current driver
CCINM
24
AI
Inverting input of an operational amplifier for transmission current driver
CCOUT
25
AO
Output of an operational amplifier for transmission current driver
MDS_CTRL
26
AI
For POL = VDD MDS_CTRL should = VSS
For POL = VSS MDS_CTRL can be tied to VDD or used as a not reset to control when transmit
communications will be enabled
SIGIN
27
AI
Input pin of the band-pass filter. This pin is connected to VMID bias level with 270K resistor.
HPF
28
AI
Feedback signal of high-pass filter. This pin is connected to the output of an op-amp for high
pass filter with 75K resistor.
LPF
29
AI
Non-inverting input of an operational amplifier for the low-pass filter
FLT
30
AI
Input pin of low-pass filter for feedback. This pin is connected to the output of the high-pass
filter through 20kΩ and the non-inverting input of the low-pass filter through 54kΩ resisters.
FLTOUT
31
AO
Output of the operational amplifier for the low-pass filter. This signal is internally connected to
non-inverting input to form a voltage-follower.
CCD
32
AO
VSS
33
Ground
Current integration (for carrier detect circuit)
Ground
Rev. 6 | Page 6 of 22 | www.onsemi.com
AMIS-492x0
Table 1: Pin Numbers and Signal Description (Continued)
Signal Name
Pin No.
I/O(Note 1)
Description
RXA
34
DO
MDS-MAU interface signal for received signal activity. This pin is a push-pull output.
RXS
35
DO
MDS-MAU interface signal for received signal. This pin is a push-pull
output.
TXE
36
DIS
MDS-MAU interface signal for enable signal transmission (Schmitt Trigger input)
TXS
37
DIS
MDS-MAU interface signal for signal to be transmitted (Schmitt Trigger input)
POL
38
DIS
Selects polarity of TxE input. When this pin is connected to GND, TxE is active high. When
this pin is connected to VDD, TxE is active low.
VSS
39
Ground
Ground
VSS
40
Ground
Ground
Connect to ground
VSS
41
Ground
VSS
42
Ground
Connect to ground
VSS
43
Ground
Connect to ground
VCC
44
Analog supply
Analog supply voltage
Note:
1.
AI = Analog Input, AO = Analog Output, AI/O = Analog Input/Output, DIS = CMOS Digital Input (Schmitt Trigger),
DO = CMOS Digital Output.
3.0 Electrical Characteristics
3.1 Operating Conditions
o
Unless otherwise noted, all block and sub-block specifications apply over the operating temperature (-40 to 85 C).
Table 2: Absolute Maximum Ratings
Parameter
Analog block supply voltage
Digital block supply voltage
Digital input pin voltage
Digital output pin voltage
Input pin current
Output pin current
ESD, Human Body Model
ESD, Machine Model
ESD, Charged Device Model
Storage temperature
Table 3: Normal Operating Conditions
Parameter
Symbol
Analog supply voltage
VCC
Digital supply voltage
VDD
Storage temperature
TOperating
Current consumption
ICC
Symbol
VCC
VDD
VIN
VOUT
IIN
IOUT
Min.
-0.3
-0.3
-0.3
-0.3
-
TStorage
-55
Min.
4.75
2.7
-40
Max.
6.5
6.0
VDD + 0.3
VDD + 0.3
±5
30
2,250
250
1,000
125
Typ.
5
3
Max.
6.2
VCC - 1.1V
85
Units
V
V
°C
500
800
µA
Units
V
V
V
V
mA
mA
V
V
V
°C
Conditions
(TxS, TxE and POL pins)
(RxS and RxA pins)
Not for shunt pin
For shunt, SGND and VO
Conditions
Supply voltages are configurable, or
can be supplied from off-chip
25°C, SHUNT current = 1mA,
No current from series regulator
Rev. 6 | Page 7 of 22 | www.onsemi.com
AMIS-492x0
Table 4: CMOS Input Specifications
Parameter
Input high voltage
Symbol
VIH
Min.
0.7•VDD
Max.
VDD
Units
V
Input low voltage
VIL
0
0.3•VDD
V
Input high current
IIH
1
μA
Input low current
IIL
-1
μA
Schmitt negative threshold
Vt-
Schmitt positive threshold
Vt+
Schmitt hysteresis
Vh
V
0.2•VDD
0.8•VDD
1
V
V
3.2 Power Supply Blocks
Table 5: Regulator Specifications
Parameter
Shunt Regulator
Symbol
Output voltage
VCC
Sink current
Load capacitance
Load regulation
Temperature coefficient
Series Regulator
ISH
CSH
Input voltage
Output voltage
Min.
Typ.
Max.
Units
4.85
4.75
0.001
5
0
5.0
5.15
6.2
25
1.6
4
±200
V
V
mA
μF
%
ppm/°C
6.2
V
Internally tied to VCC pin
3.0
3.09
V
Preset, ISR = 0
3.5
20
V
mA
μF
%
ppm/°C
Internal pass transistor P-ch and pad
For stability use Cap w/ ESR
ISR = 0 to 20mA
95
% Vref
SxSETIN > VTH9 (output: L Æ H)
.038
V
TCVcc
VCC
VO
4.75
2.91
2.85
Output current
ISR
Load capacitance
CSR
5
Load regulation
0
2
Temperature coefficient
TCVo
±200
Low Voltage Detectors (applies to N_PFail1 and N_PFail2)
Threshold
VTH9
85
90
Hysteresis
VHYS5
.012
Output sink current
IOL
30
Output leakage current
IL
Table 6: Voltage Reference Specifications
Parameter
Symbol
Bandgap Voltage Reference
Output voltage tolerance
VREF
Temperature drift
.025
4
μA
μA
VOH = 5V
Typ.
Max.
Units
1.157
1.185
50
1.205
V
ppm/°C
-
100
-
μV
VCCREF
4.75
5
6.2
V
Load current
VMID voltage reference
Output voltage
Output current
Load capacitance
Temperature coefficient
IREFOUT
-
-
0
μA
VMID
IMID
CMID
TCMID
1.95
-30
0.01
2.0
2.05
100
1
± 200
V
μA
μF
ppm/°C
Notes:
1.
External setting and N-JFET
1
Min.
0.1
ISH = 1 to 25mA
No load capacitance
135
VREFHYS
(1)
Preset, ISH = 1 to 5mA
External setting
Internal pass transistor N-ch and pad
SxSETIN < (VTH9 - VHYS5)
(output: H Æ L )
VOL= 0.4V (open drain)
Supply voltage
Hysteresis
Conditions
Conditions
Equates to: +/- 2 percent
Note 1
No load during operation
DVC6000F uses 1uF
Hysteresis is defined as the change in the 25°C reading after 85°C to 25°C cycle and –40°C to 25°C cycle.
Rev. 6 | Page 8 of 22 | www.onsemi.com
AMIS-492x0
3.3 Transmitter Blocks
Table 7: MDS-MAU Interface
Parameter
MDS-MAU Interface
POL input pin
Symbol
Min.
Typ.
Max.
Units
POL
TxE input pin
TxE
TxS input pin
TxS
Conditions
V
See Schmitt Trigger input specs
V
V
Note: The associated MDS chip must handle the jabber detect function.
Table 8: Tri-level Modulator
Parameter
Symbol
Tri-level Modulator and Slew Control
Output voltage
VO
Load current
IO
Output for silence
(1)
Output for high level
Output for low level
(1)
(1)
Asymmetry of VH and VL
Rise and fall times
Notes:
1.
2.
(2)
Min.
Typ.
VMID
-35
Max.
Units
Conditions
(Output is at VDRV)
3.02
+120
V
μA
|∆V| 10mV
VS
VMID+0.485
VMID+0.500
VMID+0.515
V
TXE disabled
VH
VS+0.380
VS+0.400
VS+0.420
V
TXE active
VL
VS-0.420
VS-0.400
VS-0.380
V
TXE active
∆VHL
-0.02
0.02
V
tf, tr
μsec
4.7
Note 2
(CRT= 22pF)
Nominal values are: VS = 2.5V, VH = 2.9V and VL = 2.1V.
By adding an external capacitor between the CRT pin and ground, slew rate at VDRV output can be controlled. The controlling equation is tf or tr = 2us +
(0.123us/pF * CRT). CRT is nominally 22pF, yielding tf = tr =4.7us. The constant comes from an internal capacitor. The hot side of the capacitor and the CRT pin
should have a guard pattern around them to avoid unnecessary interference.
Table 9: Current Control Amplifier
Parameter
Current Control Amplifier
Input common mode voltage
range
Output voltage swing
Load current
Input offset voltage
Slew rate
Gain bandwidth product
Phase margin
Symbol
Min.
VCM
Typ.
Max.
Units
0
VCC – 1
V
VO
1
VCC – 0.5
V
Io
-2300
100
μA
VOS
-3
+3
mV
SR
0.54
V/μs
GBW
1.15
MHz
PM
66
Deg
Rev. 6 | Page 9 of 22 | www.onsemi.com
Conditions
(Output is at CCOUT)
CL= 10pf
RL= 200k
AMIS-492x0
3.4 Receiver Block
Table 10: Receiver Sub-blocks
Parameter
Band Pass Filter
Input voltage
Output voltage swing
Symbol
Min.
Typ.
Max.
Units
VBP
1
4
V
FLTOUT
1
4
V
Output slew rate
SR
Input offset voltage
VOS
0.6
Conditions
SIGIN pin to GND
V/μs
±5
mV
RF1
60
75
90
kΩ
RF2
216
270
324
kΩ
RF3
16
20
24
kΩ
RF4
43
54
65
kΩ
VTH+
40
50
60
mV
VTH-
-60
-50
-40
mV
Output high voltage
VOH
VDD-0.6
Output low voltage
VOL
Output high current
IOH
50
μA
VDD-VO ≤ 0.6V
Output low current
IOL
50
μA
VO ≤ 0.6V
Output rising time
tR
0.3
μs
CL = 10pF
Output leak current
tF
0.3
μs
CL = 10pF
Filter resistors
(1)
Carrier Detector
Threshold voltage
0.3
Relative to VMID
V
IOH = 0mA
V
IOL = 0mA
Zero-cross Detector
VTH+
VMID+0.025
VMID+0.040
VMID+0.058
V
No carrier
VTH-
VMID
VMID
VMID
V
Carrier active
Output high voltage
VOH
VDD-0.6
V
IOH = 0mA
Output low voltage
VOL
V
IOL = 0mA
Output high current
IOH
50
μA
VDD-VO ≤ 0.6V
Output low current
IOL
50
μA
VO ≤ 0.6V
Output rising time
tR
0.3
μs
CL = 10pF
Output leak current
tF
0.3
μs
CL = 10pF
Threshold voltage
0.3
Note:
1.
The band pass filter is made up of a two pole high pass filter in series with a two pole low pass filter. The filter consists of four resistors internal to AMIS-492x0,
and four external capacitors. The active part of each filter is an amplifier connected in a follower configuration.
Rev. 6 | Page 10 of 22 | www.onsemi.com
AMIS-492x0
4.0 Theory of Operation
4.1 Overview
The AMIS-492x0 incorporates two different power supply circuits. Both derive their power from the bus. Using the internal
configuration, the shunt regulator is set for 5V and the series regulator is set for 3V. Users can modify either power supply by adding
external components. The AMIS-492x0 Fieldbus can also monitor these power supply voltages and generate power-fail signals if they
fall below a specified value. Please refer to the AMIS-492x0 Fieldbus MAU Reference Design Application Note for ways to adjust the
shunt and series voltage regulators.
The AMIS-492x0 Fieldbus MAU transmits a Manchester-encoded signal provided from a standard MDS-MAU interface. The output
driver makes it possible to design various signal circuits, which depend on the power requirements of your device. The slew rate of the
signal can be controlled to minimize unnecessary radiation as specified in IEC/ISA standards.
The AMIS-492x0 Fieldbus MAU has a built-in band pass filter which makes it easy to design your own receiver. The receive block
operates on a Manchester-encoded signal. It decodes the signal and verifies proper amplitude with a zero-cross and carrier detect
circuit, respectively. Detected signals are then passed on to a controller with the standard MDS-MAU interface.
4.2 Power Supply Block
The power supply block contains four sub-blocks:
1.
2.
3.
4.
A shunt regulator - for establishing a supply voltage of VCC (typ. = 5V) used by the analog circuitry
A series regulator - for establishing a supply voltage of VDD (typ. = 3V) used for digital circuitry
Two low voltage detectors - for monitoring the two supply voltages
A bandgap voltage reference - which is used internally for generating a bias level for AC signals
4.2.1. Shunt Regulator
The shunt regulator controls its sink current to the SHUNT pin so that the voltage applied to the SHSETIN pin is equal to VREF. The VCC
input is divided by an internal network to provide a voltage equal to Vref at the SHSET pin. If SHSET and SHSETIN pins are tied
together, and VCC and SHUNT pins are connected to a power source of high impedance (e.g., current mirror circuit of signal driver), the
shunt regulator provides 5V power to itself and external circuits. A capacitor of 5μF or larger capacity is necessary to stabilize this
regulator. Figure 13 shows C10 (22μF) connected to Pin 8 to accomplish stabilization.
It is possible to increase the VCC voltage up to 6.2V by dividing VCC with an external network to supply the appropriate voltage to
SHSETIN pin. In this case, SHSET pin must be kept open. The output voltage is determined by the following equation:
VCC = VREF × (1 + R1 / R2)
Shunt Regulator
(Internal Configuration
)
16Meg
VCC
18
6
SHSETIN
9
Cfb
SHUNT
16Meg
8
SGND
7
SHSET
N/C
Figure 4: Shunt Regulator
Rev. 6 | Page 11 of 22 | www.onsemi.com
6
SHSETIN
8
25mA
(Max)
A6
Rsh
R1
SHUNT
50pF
VREF
25mA
(Max)
A6
Rsh
SHSET
VCC
3.25Rsh
50pF
VREF
System
VCC
18
Cfb
3.25Rsh
7
Shunt Regulator
(External Configuration
)
System
VCC
9
SGND
R2
AMIS-492x0
The SHUNT pin is normally connected to VCC. It is possible to insert a resister between VCC and SHUNT to measure the shunt current.
Its value should be small enough to keep VDS (voltage between SHUNT pin and SGND pin) larger than 2.5V (i.e., resistor must be less
than 100Ω.).
Since the internal transistor can sink as much as 25mA, no additional circuit is necessary in most cases. Note that the drain current
must not exceed 25mA because no protection is implemented for the internal transistor. If you do not need the shunt regulator, you
should connect SHUNT and SHSETIN pins to GND and open SHSET pin. Then VCC must be supplied from another source.
4.2.2. Series Regulator
The series regulator produces a regulated voltage at the VO pin from VCC. If you connect SRAO and SRTR pins together, the internal
amplifier will regulate the input voltage at SRSETIN pin to equal VREF. An internal feedback signal is generated to produce a voltage
equal to VREF at pin SRSET. If you connect SRSET and SRSETIN pins, the series regulator supplies 3V at pin VO. A capacitor (CD in
Figure 5) of 5μF or larger capacity is necessary to stabilize this regulator. The capacitor is expected to have an ESR resistor for the
circuit to be stable. If the capacitor is low, a series resistor with the cap load will help stabilize the circuit).
Series Regulator
(Internal Configuration)
May
Supply
VDD
Series Regulator
(External Configuration)
VCC
Cfb1
VO
16
CD
SRSET
20mA (Max)
May
Supply
VDD
VO
40pF
16
Cc2
20pF
CD
1.54Rsr
VREF
A7
R4
SRSET
13
N/C
SRTR
15
14
SRAO
12
20mA (Max)
40pF
Cc2
20pF
1.54Rsr
VREF
A7
13
R5
Rsr
VCC
Cfb1
SRSETIN
Rsr
SRTR
15
14
SRAO
12
SRSETIN
Figure 5: Series Regulator
The supply current must not exceed 20mA because no current limiting is applied to the internal transistor. You can increase VO voltage
up to 3.5V by dividing VO with an external network to supply the appropriate voltage to pin SRSETIN. In this case, pin SRSET must be
kept open. The drain-source voltage of the internal transistor must be larger or equal to 2V. If this condition is not satisfied, you may
need an external P-channel JFET to create the desired low voltage-drop regulator. The output voltage is determined by the following
equation.
VO = VREF × (1 + R4/R5)
4.2.3. Low Voltage Detectors
Low voltage detectors are included to monitor supply voltages and generate “power fail” signals. The low voltage alarms are detected
by sensing the voltage on pins SHSETIN and SRSETIN. These pins also provide feedback for the shunt and series regulators. If the
voltage on the SHSETIN pin is lower than the threshold, VTH9 (90 percent VREF), N_PFAIL1 goes low. Typically SHSETIN monitors
the analog rail voltage VCC. If the voltage on the SRSETIN pin is lower than the threshold, VTH9, N_PFAIL2 goes low. Typically
SRSETIN monitors the digital rail voltage VDD.
Both outputs are open drain, so a resistor will be required. If you do not use one of these pins, it should be connected to GND. You
can also add capacitors to delay these signals. In this case, sink current must not exceed the maximum value.
If you do not wish to use one of the low voltage detectors its corresponding output pin should be connected to GND.
Rev. 6 | Page 12 of 22 | www.onsemi.com
AMIS-492x0
Low Voltage Detectors
VDD
VCC2
0.9*VREF
N_PFail1
R1
4
C3
C1
SHSETIN
VDD
VCC2
0.9*VREF
N_PFail2
R2
5
C4
SRSETIN
C2
Figure 6: Low Voltage Detectors
If you do not use one of the regulators, the corresponding alarm signal can potentially be used to monitor another signal. For example,
if the series regulator is not used, SRAO should be left open, SRTR tied to VCC, VO grounded and SRSET left open. Then SRSETIN
can be the input for monitoring another voltage signal with N_PFAIL2.
4.2.4. Voltage Reference
The voltage reference circuitry generates two voltage signals, VREF and VMID. VREF comes from a bandgap circuit and is used as
the reference voltage for all circuits in the AMIS-492x0 Fieldbus MAU. The typical value for VREF is 1.185V. See Figure 7.
An operational amplifier is regulating VMID to provide a bias (common) level for the AC signals. Its typical voltage is 2V. A capacitor
larger than 0.01μF is necessary on VMID to remove high-frequency ripple.
Figure 7: Bandgap and VMID Voltage Reference
Rev. 6 | Page 13 of 22 | www.onsemi.com
AMIS-492x0
4.3 Transmit Block
The transmit block contains four sub-blocks:
1.
2.
3.
4.
MDS-interface – decodes input signals to generate internal control signals.
Tri-level modulator – generates current signals used as inputs to the slew-rate controller.
Slew rate controller – converts current to three distinct VDRV voltage levels (VS, VH, VL).
Current drive amplifier – op amp designed to drive current drivers for 31.25kbps voltage-mode medium.
4.3.1. MDS-interface
The MDS-interface decodes input signals to generate internal control signals. The POL pin is used to select the polarity of TxE (transmit
enable). The TxE and TxS (transmit signal) are the MDS-MAU interface signals. These three signals are CMOS logic signals powered
by the VDD supply voltage. When POL is connected to GND, TxE is assumed to be active high (positive logic). Likewise, if POL is
connected to VDD, TxE is assumed to be active low (negative logic). See Table 1 on page 7, Table 11, and Figure 8 to see how
MDS_CTRL Pin 26 can be used to control MDS interface operation. Table 11 shows the resulting VDRV output for the various
combinations of interface signals.
Table 11: MDS-interface Logic
POL
TxE
TxS
Low
Low
High
Low
Low
High
High
Low
Low
High
High
Low
High
High
VDRV
VS
VH
VL
VH
VL
VS
Figure 8: MDS Interface
4.3.2. Tri-level Modulator
The tri-level modulator switches current signals into a summing node. The slew rate controller converts the current to a voltage signal,
VDRV. The DC level of silence (VS) is nominally 2.5V. Transmission high (VH ) is nominally 2.9V and transmission low (VL) is nominally
2.1V, yielding an amplitude of 0.8V.
Rev. 6 | Page 14 of 22 | www.onsemi.com
AMIS-492x0
Tri-Level Modulator
&
Slew Control
N_VL
N_Vs
Active Low
Active Low
4R
4R
R
80K
80K
20K
VCC
A3
20R
400K
VDRV
1.2K
21
1.2K
VMID
CRT
1.2K
19
Figure 9: Tri-level Modulator
4.3.3. Slew Rate Controller
Amplifier (A3), shown in the above figure, controls the slew rate. The amplifier converts the current signals from the tri-level modulator
to a voltage signal, VDRV. It controls its slew rate with a capacitor (CRT) connected to the CRT pin. The waveform at the VDRV pin is
symmetric and the fall/rise times are determined by the following equation:
tF, tR = 2.0[μs] + 0.12 [μs/pF] × CRT
The constant part comes from the internal capacitor (not shown). It is recommended to make a guard pattern on your circuit board
around the CRT pin and the hot side of CRT to avoid unnecessary interference.
4.3.4. Current Drive Amplifier
The drive amplifier is an operational amplifier optimized to drive current drivers for 31.25kbps voltage-mode medium. Its input and
output signals are exposed to allow flexible design of the external driver. Note that this amplifier cannot directly sink the necessary
current from the medium. In the following drive circuit the current (IBUS) through the current-detect resister (RF) is determined by the
following equation.
I bus =
[ R3 Vmid (R12 + R11 ) ] - [ Vdrv (R2 R11 + R3 R11 ) ]
- [ RF ( R2 R12 + R3 R12 ) ]
A diode and/or a resistor connected to the emitter are necessary to shift the DC level of CCOUT and to suppress the loop gain. The
resistance value depends on your design (overall gain and emitter current).
Rev. 6 | Page 15 of 22 | www.onsemi.com
AMIS-492x0
Figure 10: Current Control Circuit
4.4 Receive Block
The receive block contains three sub-blocks, which are internally connected:
1.
2.
3.
A band pass filter – to filter the desired incoming communication signal.
Carrier detector – generates the RxA signal by detecting the signal amplitude.
Zero-cross detector generates the RxS signal by detecting the high/low transitions of the Manchester code.
4.4.1. Band Pass Filter
The band pass filter is a series connection of a high-pass and a low-pass filters each having two poles. Each filter is comprised of a
voltage follower and on chip resisters, so only four external capacitors are necessary. The following figure shows an internal circuit and
the connection of external capacitors. Cut-off frequency, fL, of the high-pass filter is determined by C1 and C2 while cut-off frequency, fH,
of the low-pass filter is determined by C3 and C4.
fL =
fH =
1
2π
1
2π
1
R F1 *R F 2 *C1 *C 2
1
R F 3 *R F 4 *C 3 *C 4
QL =
1
2
R F2
R F1
Q L = 0.44 *
=0.95
C3
C4
=0.95
The possible ranges of fL and fH are 1kHz ~ 10kHz and 10kHz ~ 100kHz, respectively.
recommended to obtain 1kHz and 47.6kHz cut-off frequencies.
Rev. 6 | Page 16 of 22 | www.onsemi.com
The values in the following figure are
AMIS-492x0
31
Bandpass Filter
C3=220pf
30 FLT
FLTOUT
HPF
RF1
To
Detectors
28
75K
VCC
VCC
A2
RF4
RF3
54K
20K
C2
SIGIN
A1
C1
Signal
Input
27
RF2
270K
1000pf
1000pf
Vmid
29
C4=47pf
Figure 11: Band Pass Filter
4.4.2. Receive Signal Detection
The carrier detector generates the receive activity (RxA) signal by detecting the input signal amplitude. Minimum amplitude is 100mVpp (TYP). A delay, determined by the capacitor connected between the CCD pin and GND, is added to avoid detection of transient
noise. The recommended value of CCD is 100pF. The output can drive a CMOS input of VDD supply voltage.
The zero-cross detector generates the receive signal (RxS) with minimum phase error (jitter) by detecting the transition between high
and low levels of the incoming Manchester code. Hysteresis of +40mV (TYP) is applied to avoid unnecessary switching by noise.
Once the carrier-detect goes active the hysteresis is removed and the switching point threshold is set to Vmid. The output can drive a
CMOS input of VDD supply voltage.
Zero-Cross Detector
RXS
35
VDD
VCC
Level
Convert
C1
ZC Tript Pt
Vtrip = Vmid
Vhyst = + 40mV
Vmid
R
(1Meg)
Carrier Detector
RxSig
VCC
RXA
34
CCD
VDD
VCC
C2
Level
Convert
CD_Output
VHi50
VHi50 = Vmid + 50mV
VLo50 = Vmid - 50mV
VCC
32
C
(60pF)
VLo50
C2
Figure 12: Receive Signal Detectors
Rev. 6 | Page 17 of 22 | www.onsemi.com
Filtered received signal
from Bandpass Filter
AMIS-492x0
5.0 AMIS-49200 as Replacement for Yokogawa μSAA22Q
The AMIS-49200 is a near pin-for-pin compatible replacement for the Yokogawa μSAA22Q Fieldbus MAU. There are some differences
between the two chips both in the internal operation, the required external connections and the value (or existence) of some of the
external components. These differences are small and those who used the μSAA22Q would most likely be able to use the AMIS-49200
in designs with only some component value changes.
5.1 Functional Differences Between the μSAA22Q and the AMIS-492x0
5.1.1. Jabber Inhibit
The AMIS-492x0 does not implement the Jabber Inhibit function in the μSAA22Q. Typically the AMIS-492x0 will be connected with a
link controller chip such as the UFC100-F1 from Aniotek/Softing. This link controller has a Jabber Inhibit function so the absence of this
function in the AMIS-492x0 should not be a problem.
As can be seen in Table 12, MDS_CTRL is only connected to ground if POL is connected to VDD. See Table 1 for a detailed
description of the interaction between MDS_CTRL and POL.
In Table 12, the μSAA22Q recommends that the JAB/ signal (Pin 39) be connected to ground if the signal is not used. On AMIS-492x0,
Pin 39 must be connected to ground.
5.1.2. Low Power Mode
The low power mode on the μSAA22Q allows the user to have a quiescent current draw of less than 10mA yet still communicate at the
proper IEC 61158-2 signal levels. Very few, if any, Fieldbus devices are capable of operating at such a low current level so this
capability was not included in the AMIS-492x0.
The pins affected by this are 41, 42 and 43. If the low power mode is not being used on the μSAA22Q, these three pins are grounded.
On the AMIS-492x0 it is required that these pins be grounded.
5.2 Pin Differences Between the μSAA22Q and the AMIS-492x0
Table 12: Pin Connection Differences Between the µSAA22Q and the AMIS-492x0
AMIS-492x0
μSAA22Q
Pin No.
Signal Name
Recommended Connection
Signal Name
Required Connection
1
NC
Ground
VSS
Ground
11
22
26
NC
NC
NC
Ground
Ground
Ground
VSS
VSS
MDS_CTRL
Ground
Ground
Ground*
33
NC
Ground
VSS
Ground
39
JAB/
Ground if not used
VSS
Ground
41
CJB
1 μf cap
VSS
Ground
42
VTX
Ground
VSS
Ground
43
VSL
Ground
VSS
Ground
* MDS_CTRL is only connected to ground if POL is connected to VDD. See Table 1 for a detailed description of the interaction between
MDS_CTRL and POL.
Rev. 6 | Page 18 of 22 | www.onsemi.com
AMIS-492x0
5.3 External Circuitry
Figure 13 shows the external circuitry required to connect the AMIS-492x0 to an IEC 61158-2 conformant network. This schematic is
the circuit that was used to pass the FOUNDATION Fieldbus Physical Layer Conformance test as specified in FOUNDATION Fieldbus
specification FF830, Rev 1.5. This circuit is similar but not identical to the circuit recommended by Yokogawa for the μSAA22Q.
Figure 13: AMIS-492x0 Reference Circuit Implementation
Table 13 lists the four external component values that need to be changed with using the AMIS-492x0 in a circuit that previously used
the μSAA22Q.
Table 13: Passive External Component Value Differences Between the µSAA22Q and the AMIS-492x0
Component
AMIS-492x0 Value
μSAA22Q Value
C1
100pf
150pf
C3
100pf
47pf
C4
470pf
220pf
C8
10nf
1μf
C1 connects to signal CCD (Pin 32) and controls the carrier detect assert and drop-out timing. Particular implementations may require
that the value of C1 be changed to accommodate received signal level changes introduced by the addition of intrinsic safety
components added to the external circuitry. C3 and C4 are part of the receive filter and determine the band pass characteristics of the
receive filter. It is unlikely that these would need to be changed. C8 is a noise filter for VMID. It is important that VMID have as little
noise as possible as it is used as a reference for many sub-circuits in the AMIS-492x0. C8 must be a large capacitor with maximum of
100nf. C8 recommended value is 1μf.
Rev. 6 | Page 19 of 22 | www.onsemi.com
AMIS-492x0
There is one other minor difference in the recommended external circuitry between the μSAA22Q and the AMIS-492x0. Figure 14
shows the start-up circuits recommended for the μSAA22Q and the AMIS-492x0. The circuit shown for the AMIS-492x0 is different from
that shown for the μSAA22Q but either one will work. Both are current sources that turn on when power is applied to the H1 segment
terminals so that the AMIS-492x0 can turn on without any turn-on transients on the network.
μSAA 22Q
Startup Circuit
Loop +
AMIS 49200
Startup Circuit
R5
100 k
Loop +
R6
1k
Q1
D3
5.1 V
V Shunt
V Shunt
Figure 14: Recommended Start-up Circuits
5.4 Active Components
Transistors Q1 – Q4 are ordinary small signal transistors. Diodes D1 and D2 are similarly ordinary small signal diodes. Users desiring
to replace a μSAA22Q with the AMIS-49200 in an existing design should be able to use whatever transistors and diodes were used with
the μSAA22Q. For new designs, the specified transistors can be used or other devices may be chosen.
5.5 Alternative Designs
Some users of the Yokogawa μSAA22Q did not use the exact recommended external circuit for the media interface circuit (see Figure
13). Using the AMIS-492x0 without the Yokogawa recommended external circuit may result in some compatibility problems. There are
many alternative designs and it is beyond the scope of this document to identify all possible configurations and their associated design
implications. Please refer to the AMIS-492x0 Fieldbus MAU Reference Design Application Note for a recommended, FOUNDATION
Fieldbus certifiable board design.
5.6 Verification
All designs using the AMIS-492x0 should re-run the entire physical layer conformance test as defined in FOUNDATION Fieldbus
document FF-830, FOUNDATION™ Specification 31.25 kbit/s Physical Layer Conformance Test. Board layout can alter the behavior of
all circuit implementations, even designs that follow the recommended implementation.
Rev. 6 | Page 20 of 22 | www.onsemi.com
AMIS-492x0
6.0 Ordering Information
Part Number
AMIS-49200-XTD
AMIS-49200-XTP
AMIS-49250-XTD
AMIS-49250-XTP
Package
44 LQFP 10x10mm (Green/RoHS Compliant)
44 LQFP 10x10mm (Green/RoHS Compliant)
44 NQFP 7x7mm (Green/RoHS Compliant)
44 NQFP 7x7mm (Green/RoHS Compliant)
Shipping Configuration
Tray
Tape & Reel
Tray
Tape & Reel
Temperature Range
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
7.0 Appendix (A) – Manchester Encoding
All Fieldbus devices transmit the data onto the media as a Manchester-encoded baseband signal. With Manchester encoding, zeros
and ones are represented by transitions that occur in the middle of the bit period (see below). For FOUNDATION Fieldbus H1 and
Profibus PA, the nominal bit time is 32μsec, with the transition occurring at 16μsec. The Manchester encoding rules have been
extended to include two additional symbols, non-data plus (N+) and non-data minus (N-). The symbol encoding rules are shown in
Figure 15.
32 usec
-T
2
T
2
-T
2
Logical "0"
-T
2
T
2
Logical "1"
T
2
-T
2
"N+"
T
2
"N-"
Figure 15: Manchester Encoding
Rev. 6 | Page 21 of 22 | www.onsemi.com
AMIS-492x0
8.0 Revision History
Revision
1
2
3
4
5
6
Date
April 2006
October 2006
January 2007
February 2008
May 2008
June 2008
Modification
Initial release
Update to new AMIS template
Update to new ON Semiconductor template; update OPN table
Added AMIS-49250
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