AD AD9948KCPRL 10-bit ccd signal processor with precision timingâ ¢ core Datasheet

10-Bit CCD Signal Processor with
Precision Timing ™ Core
AD9948
GENERAL DESCRIPTION
FEATURES
Correlated Double Sampler (CDS)
0 dB to 18 dB Pixel Gain Amplifier (PxGA®)
6 dB to 42 dB 10-Bit Variable Gain Amplifier (VGA)
10-Bit 25 MSPS A/D Converter
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Driver
Precision Timing Core with 800 ps Resolution
On-Chip 3 V Horizontal and RG Drivers
40-Lead LFCSP Package
The AD9948 is a highly integrated CCD signal processor for
digital still camera applications. Specified at pixel rates of up to
25 MHz, the AD9948 consists of a complete analog front end
with A/D conversion, combined with a programmable timing
driver. The Precision Timing core allows adjustment of high
speed clocks with 800 ps resolution.
The analog front end includes black level clamping, CDS, PxGA,
VGA, and a 25 MHz 10-bit A/D converter. The timing driver
provides the high speed CCD clock drivers for RG and H1–H4.
Operation is programmed using a 3-wire serial interface.
APPLICATIONS
Digital Still Cameras
High Speed Digital Imaging Applications
Packaged in a space-saving 40-lead LFCSP package, the
AD9948 is specified over an operating temperature range of
–20°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
0dB TO 18dB
6dB TO 42dB
PxGA
VGA
CDS
CCDIN
VREF
10-BIT
ADC
10
DOUT
CLAMP
INTERNAL
CLOCKS
HBLK
CLP/PBLK
RG
H1–H4
4
HORIZONTAL
DRIVERS
AD9948
PRECISION
TIMING
CORE
CLI
SYNC
GENERATOR
HD
VD
INTERNAL
REGISTERS
SL
SCK SDATA
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD9948–SPECIFICATIONS
GENERAL SPECIFICATIONS
Parameter
Min
TEMPERATURE RANGE
Operating
Storage
–20
–65
MAXIMUM CLOCK RATE
25
POWER SUPPLY VOLTAGE
AVDD, TCVDD (AFE, Timing Core)
HVDD (H1–H4 Drivers)
RGVDD (RG Driver)
DRVDD (D0–D9 Drivers)
DVDD (All Other Digital)
2.7
2.7
2.7
2.7
2.7
POWER DISSIPATION
25 MHz, HVDD = RGVDD = 3 V, 100 pF H1–H4 Loading*
Total Shutdown Mode
Typ
Max
Unit
+85
+150
°C
°C
MHz
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
3.6
3.6
220
1
V
V
V
V
V
mW
mW
*The total power dissipated by the HVDD supply may be approximated using the equation
Total HVDD Power = (CLOAD × HVDD × Pixel Frequency) × HVDD × ( Number of H − Outputs Used )
Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will reduce the power dissipation.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(TMIN to TMAX, AVDD = DVDD = DRVDD = HVDD = RGVDD = 2.7 V, CL = 20 pF, unless otherwise noted.)
Parameter
Symbol
Min
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
2.1
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA
Low Level Output Voltage, IOL = 2 mA
VOH
VOL
2.2
CLI INPUT
High Level Input Voltage
(TCVDD/2 + 0.5 V)
Low Level Input Voltage
VIH–CLI
VIL–CLI
1.85
VOH
VOL
2.2
RG AND H-DRIVER OUTPUTS
High Level Output Voltage
(RGVDD – 0.5 V and HVDD – 0.5 V)
Low Level Output Voltage
Maximum Output Current (Programmable)
Maximum Load Capacitance
Typ
Max
0.6
10
10
10
30
V
V
µA
µA
pF
0.5
V
V
0.85
V
V
0.5
100
Unit
V
V
mA
pF
Specifications subject to change without notice.
–2–
REV. 0
AD9948
ANALOG SPECIFICATIONS
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 25 MHz, Typical Timing Specifications,
unless otherwise noted.)
Parameter
Min
CDS
Gain
Allowable CCD Reset Transient*
Max Input Range before Saturation*
Max CCD Black Pixel Amplitude*
Unit
± 50
dB
mV
V p-p
mV
256
Steps
0
18
dB
dB
1.0
1.0
2.0
6
42
dB
dB
256
Steps
0
63.75
LSB
LSB
Measured at ADC output
10
–1.0
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
± 0.5
Guaranteed
2.0
+1.0
Bits
LSB
V
2.0
1.0
V
V
SYSTEM PERFORMANCE
VGA Gain Accuracy
Min Gain (Code 0)
Max Gain (Code 1023)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
Specifications include entire
signal chain
5.0
40.5
5.5
41.5
0.2
0.25
50
*Input signal characteristics defined as follows:
500mV TYP
RESET TRANSIENT
50mV MAX
OPTICAL BLACK PIXEL
1V MAX
INPUT SIGNAL RANGE
Specifications subject to change without notice.
REV. 0
Notes
V p-p
V p-p
Steps
1024
Guaranteed
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Min Clamp Level (0)
Max Clamp Level (255)
A/D CONVERTER
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
Max
0
500
PIXEL GAIN AMPLIFIER (PxGA)
Gain Control Resolution
Gain Monotonicity
Min Gain
Max Gain
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Min Gain (VGA Code 0)
Max Gain (VGA Code 1023)
Typ
–3–
6.0
42.5
dB
dB
%
LSB rms
dB
12 dB gain applied
AC grounded input, 6 dB
gain applied
Measured with step change
on supply
AD9948
TIMING SPECIFICATIONS
(CL = 20 pF, fCLI = 25 MHz, Serial Timing in Figure 3, unless otherwise noted.)
Parameter
MASTER CLOCK (CLI) (See Figure 4)
CLI Clock Period
CLI High/Low Pulsewidth
Delay from CLI to Internal Pixel
Period Position
Symbol
Min
Typ
Max
Unit
tCLI
tADC
40
16
20
24
ns
ns
tCLIDLY
6
ns
CLPOB Pulsewidth (Programmable)*
tCOB
2
20
Pixels
SAMPLE CLOCKS (See Figure 6)
SHP Rising Edge to SHD Rising Edge
tS1
17
20
ns
6
11
ns
Cycles
DATA OUTPUTS (See Figures 7a and 7b)
Output Delay From Programmed Edge
Pipeline Delay
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
tOD
10
10
10
10
10
10
fSCLK
tLS
tLH
tDS
tDH
tDV
MHz
ns
ns
ns
ns
ns
*Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Parameter
AVDD, TCVDD
HVDD, RGVDD
DVDD, DRVDD
Any VSS
Digital Outputs
CLPOB/PBLK, HBLK
SCK, SL, SDATA
RG
H1–H4
REFT, REFB, CCDIN
Junction Temperature
Lead Temperature (10 sec)
With
Respect To
Min
Max
Unit
AVSS
HVSS, RGVSS
DVSS, DRVSS
Any VSS
DRVSS
DVSS
DVSS
RGVSS
HVSS
AVSS
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
+3.9
+3.9
+3.9
+0.3
DRVDD + 0.3
DVDD + 0.3
DVDD + 0.3
RGVDD + 0.3
HVDD + 0.3
AVDD + 0.3
150
300
V
V
V
V
V
V
V
V
V
V
°C
°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
ORDERING GUIDE
THERMAL CHARACTERISTICS
Temperature
Range
Package
Package
Description Option
Thermal Resistance
Model
AD9948KCP
AD9948KCPRL
AD9948KCPZ*
AD9948KCPZRL*
–20°C to +85°C
–20°C to +85°C
–20°C to +85°C
–20°C to +85°C
LFCSP
LFCSP
LFCSP
LFCSP
*␪JA is measured using a 4-layer PCB with the exposed paddle
soldered to the board.
CP-40
CP-40
CP-40
CP-40
40-Lead LFCSP Package
␪JA = 27°C/W*
*This is a lead free product.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9948 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
REV. 0
AD9948
1
2
3
D2
4
DRVSS
5
DRVDD
D3
6
7
31 SL
33 SCK
32 SDI
35 HD
34 VD
38 HBLK
37 DVDD
36 DVSS
40 NC
NC
(LSB) D0
D1
39 CLP/PBLK
PIN CONFIGURATION
PIN 1
IDENTIFIER
AD9948
TOP VIEW
30
REFB
29
REFT
28
27
AVSS
CCDIN
26
AVDD
25
24
CLI
TCVDD
RGVSS 20
RG
H4 19
21
H3 18
D6 10
HVSS 16
TCVSS
RGVDD
HVDD 17
23
22
(MSB) D9 13
H1 14
H2 15
8
9
D7 11
D8 12
D4
D5
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Type*
Description
2–4
5
6
7–13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
1, 40
D0–D2
DRVSS
DRVDD
D3–D9
H1
H2
HVSS
HVDD
H3
H4
RGVSS
RG
RGVDD
TCVSS
TCVDD
CLI
AVDD
CCDIN
AVSS
REFT
REFB
SL
SDI
SCK
VD
HD
DVSS
DVDD
HBLK
CLP/PBLK
NC
DO
P
P
DO
DO
DO
P
P
DO
DO
P
DO
P
P
P
DI
P
AI
P
AO
AO
DI
DI
DI
DI
DI
P
P
DI
DO
Data Outputs (D0 is LSB)
Digital Driver Ground
Digital Driver Supply
Data Outputs (D9 is MSB)
CCD Horizontal Clock 1
CCD Horizontal Clock 2
H1–H4 Driver Ground
H1–H4 Driver Supply
CCD Horizontal Clock 3
CCD Horizontal Clock 4
RG Driver Ground
CCD Reset Gate Clock
RG Driver Supply
Analog Ground for Timing Core
Analog Supply for Timing Core
Master Clock Input
Analog Supply for AFE
Analog Input for CCD Signal (Connect through Series 0.1 µF Capacitor)
Analog Ground for AFE
Reference Top Decoupling (Decouple with 1.0 µF to AVSS)
Reference Bottom Decoupling (Decouple with 1.0 µF to AVSS)
3-Wire Serial Load
3-Wire Serial Data Input
3-Wire Serial Clock
Vertical Sync Pulse
Horizontal Sync Pulse
Digital Ground
Digital Supply
Optional HBLK Input
CLPOB or PBLK Output
Not Internally Connected
*Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV. 0
–5–
AD9948
TERMINOLOGY
Differential Nonlinearity (DNL)
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated in
LSB, and represents the rms noise level of the total signal chain
at the specified gain setting. The output noise can be converted
to an equivalent voltage, using the relationship
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. No missing codes guaranteed to
10-bit resolution indicates that all 1024 codes, respectively,
must be present over all operating conditions.
1 LSB = (ADC full scale/ 2n codes)
Peak Nonlinearity
where n is the bit resolution of the ADC. For the AD9948,
1 LSB is approximately 1.95 mV.
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9948 from a true straight
line. The point used as zero scale occurs 0.5 LSB before the
first code transition. Positive full scale is defined as a level 1 LSB
and 0.5 LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of
the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC’s full-scale range.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
EQUIVALENT CIRCUITS
AVDD
DVDD
R
330
AVSS
AVSS
Circuit 1. CCDIN (Pin 27)
DVSS
AVDD
Circuit 4. Digital Inputs (Pins 31–35, 38)
330
25k
HVDD or RGVDD
CLI
1.4V
DATA
AVSS
Circuit 2. CLI (Pin 25)
DVSS
ENABLE
OUTPUT
DRVDD
DATA
HVSS or RGVSS
THREESTATE
Circuit 5. H1–H4 and RG (Pins 14, 15, 18, 19, 21)
DOUT
DVSS
DRVSS
Circuit 3. Data Outputs D0–D9 (Pins 2–4, 7–13)
–6–
REV. 0
Typical Performance Characteristics–AD9948
1.0
DNL (LSB)
0.5
0
–0.5
–1.0
0
200
400
600
ADC OUTPUT CODE
800
1000
800
1000
TPC 1. Typical DNL
10
OUTPUT NOISE (LSB)
7.5
5.0
2.5
0
0
200
400
600
VGA GAIN CODE (LSB)
TPC 2. Output Noise vs. VGA Gain
275
POWER DISSIPATION (mW)
250
225
VDD = 3.3V
200
VDD = 3.0V
175
VDD = 2.7V
150
125
100
10
15
20
SAMPLE RATE (MHz)
25
TPC 3. Power Curves
REV. 0
–7–
AD9948
generates the high speed CCD clocks and all internal AFE clocks.
All AD9948 clocks are synchronized with VD and HD. All of
the AD9948’s horizontal pulses (CLPOB, PBLK, and HBLK)
are programmed and generated internally.
SYSTEM OVERVIEW
V-DRIVER
V1–Vx, VSG1–VSGx, SUBCK
The H-drivers for H1–H4 and RG are included in the AD9948,
allowing these clocks to be connected directly to the CCD.
H-drive voltage of 3 V is supported in the AD9948.
H1–H4, RG
DOUT
CCDIN
CCD
AD9948
INTEGRATED
AFE + TD
HD, VD
Figure 2a shows the horizontal and vertical counter dimensions
for the AD9948. All internal horizontal clocking is programmed
using these dimensions to specify line and pixel locations.
DIGITAL IMAGE
PROCESSING
ASIC
MAXIMUM FIELD DIMENSIONS
CLI
SERIAL
INTERFACE
Figure 1. Typical Application
12-BIT HORIZONTAL = 4096 PIXELS MAX
Figure 1 shows the typical system application diagram for the
AD9948. The CCD output is processed by the AD9948’s AFE
circuitry, which consists of a CDS, a PxGA, a VGA, a black level
clamp, and an A/D converter. The digitized pixel information is
sent to the digital image processor chip, where all postprocessing
and compression occurs. To operate the CCD, CCD timing
parameters are programmed into the AD9948 from the image
processor through the 3-wire serial interface. From the system
master clock, CLI, provided by the image processor, the AD9948
12-BIT VERTICAL = 4096 LINES MAX
Figure 2a. Vertical and Horizontal Counters
MAX VD LENGTH IS 4095 LINES
VD
MAX HD LENGTH IS 4095 PIXELS
HD
CLI
Figure 2b. Maximum VD/HD Dimensions
–8–
REV. 0
AD9948
SERIAL INTERFACE TIMING
COMPLETE REGISTER LISTING
All of the internal registers of the AD9948 are accessed through
a 3-wire serial interface. Each register consists of an 8-bit address
and a 24-bit data-word. Both the 8-bit address and 24-bit dataword are written starting with the LSB. To write to each register,
a 32-bit operation is required, as shown in Figure 3a. Although
many registers are less than 24 bits wide, all 24 bits must be
written for each register. If the register is only 16 bits wide, then
the upper eight bits are don’t cares and may be filled with zeros
during the serial write operation. If fewer than 24 bits are written,
the register will not be updated with new data.
All addresses and default values are expressed in hexadecimal.
All registers are VD/HD updated as shown in Figure 3a, except
for the registers indicated in Table I, which are SL updated.
Table I. SL-Updated Registers
Figure 3b shows a more efficient way to write to the registers by
using the AD9948’s address auto-increment capability. Using
this method, the lowest desired address is written first, followed
by multiple 24-bit data-words. Each new 24-bit data-word will
be written automatically to the next highest register address. By
eliminating the need to write each 8-bit address, faster register
loading is achieved. Address auto-increment may be used starting with any register location, and may be used to write to as
few as two registers or as many as the entire register space.
Register
Description
OPRMODE
CTLMODE
SW_RESET
TGCORE _RSTB
PREVENTUPDATE
VDHDEDGE
FIELDVAL
HBLKRETIME
CLPBLKOUT
CLPBLKEN
H1CONTROL
RGCONTROL
DRVCONTROL
SAMPCONTROL
DOUTPHASE
AFE Operation Modes
AFE Control Modes
Software Reset Bit
Reset Bar Signal for Internal TG Core
Prevents Update of Registers
VD/HD Active Edge
Resets Internal Field Pulse
Retimes the HBLK to Internal Clock
CLP/BLK Output Pin Select
Enables CLP/BLK Output Pin
H1/H2 Polarity Control
H1 Positive Edge Location
H1 Negative Edge Location
H1 Drive Current
H2 Drive Current
8-BIT ADDRESS
A0
SDATA
A1
A2
A3
tDS
SCK
A4
24-BIT DATA
A5
A6
A7
D0
D1
D2
D3
tDH
1
2
3
4
5
6
7
8
9
10
11
12
...
D21
...
30
D22
D23
31
32
tLH
tLS
...
...
SL
VD
SL UPDATED
VD/HD UPDATED
...
HD
NOTES
1. INDIVIDUAL SDATA BITS ARE LATCHED ON SCK RISING EDGES.
2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA.
3. IF THE REGISTER LENGTH IS <24 BITS, THEN DON’T CARE BITS MUST BE USED TO COMPLETE THE 24-BIT DATA LENGTH.
4. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
Figure 3a. Serial Write Operation
DATA FOR STARTING
REGISTER ADDRESS
SDATA
SCK
SL
A0
1
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
D0
9
D1
10
...
...
...
D22
31
DATA FOR NEXT
REGISTER ADDRESS
D23
32
D0
33
D1
34
...
...
D22 D23
55
56
D0
D1
57
...
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
Figure 3b. Continuous Serial Write Operation
REV. 0
–9–
58
D2
59
...
...
...
AD9948
Table II. AFE Register Map
Address
Data Bit
Content
Default
Value
Name
Description
00
[11:0]
4
OPRMODE
AFE Operation Modes. (See Table VIII.)
01
[9:0]
0
VGAGAIN
VGA Gain.
02
[7:0]
80
CLAMP LEVEL
Optical Black Clamp Level.
03
[11:0]
4
CTLMODE
AFE Control Modes. (See Table IX.)
04
[17:0]
0
PxGA GAIN01
PxGA Gain Registers for Color 0 [8:0] and Color 1 [17:9].
05
[17:0]
0
PxGA GAIN23
PxGA Gain Registers for Color 2 [8:0] and Color 3 [17:9].
Table III. Miscellaneous Register Map
Address
Data Bit
Content
Default
Value
Name
Description
10
[0]
0
SW_RST
Software Reset.
1 = Reset all registers to default, then self-clear back to 0.
11
[0]
0
OUT_CONTROL
Output Control.
0 = Make all dc outputs inactive.
12
[0]
0
TGCORE_RSTB
Timing Core Reset Bar.
0 = Reset TG core.
1 = Resume operation.
13
[11:0]
0
UPDATE
Serial Update.
Sets the line (HD) within the field to update serial data.
14
[0]
0
PREVENTUPDATE
Prevents the update of the VD-Updated Registers.
1 = Prevent update.
15
[0]
0
VDHDEDGE
VD/HD Active Edge.
0 = Falling edge triggered.
1 = Rising edge triggered.
16
[1:0]
0
FIELDVAL
Field Value Sync.
0 = Next Field 0.
1 = Next Field 1.
2/3 = Next Field 2.
17
[0]
0
HBLKRETIME
Retime HBLK to Internal H1 Clock.
Preferred setting is 1. Setting to 1 will add one cycle delay to HBLK
toggle positions.
18
[1:0]
0
CLPBLKOUT
CLP/BLK Pin Output Select.
0 = CLPOB.
1 = PBLK.
2 = HBLK.
3 = Low.
19
[0]
1
CLPBLKEN
Enable CLP/BLK Output.
1 = Enable.
1A
[0]
0
TEST MODE
Internal Test Mode.
Should always be set low.
–10–
REV. 0
AD9948
Table IV. CLPOB Register Map
Address
Data Bit
Content
Default
Value (Hex)
Name
Description
20
[3:0]
F
CLPOBPOL
Start Polarities for CLPOB Sequences 0, 1, 2, and 3.
21
[23:0]
FFFFFF
CLPOBTOG_0
Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
22
[23:0]
FFFFFF
CLPOBTOG_1
Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
23
[23:0]
FFFFFF
CLPOBTOG_2
Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
24
[23:0]
FFFFFF
0
CLPOBTOG_3
CLPOBSCP0
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
CLPOB Sequence-Change-Position 0 (Hard-Coded to 0).
25
[7:0]
0
CLPOBSPTR
CLPOB Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6].
26
[11:0]
FFF
CLPOBSCP1
CLPOB Sequence-Change-Position 1.
27
[11:0]
FFF
CLPOBSCP2
CLPOB Sequence-Change-Position 2.
28
[11:0]
FFF
CLPOBSCP3
CLPOB Sequence-Change-Position 3.
Table V. PBLK Register Map
Address
Data Bit
Content
Default
Value (Hex)
Name
Description
30
[3:0]
F
PBLKPOL
Start Polarities for PBLK Sequences 0, 1, 2, and 3.
31
[23:0]
FFFFFF
PBLKTOG_0
Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
32
[23:0]
FFFFFF
PBLKTOG_1
Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
33
[23:0]
FFFFFF
PBLKTOG_2
Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
34
[23:0]
FFFFFF
0
PBLKTOG_3
PBLKSCP0
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
PBLK Sequence-Change-Position 0 (Hard-Coded to 0).
35
[7:0]
0
PBLKSPTR
PBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6].
36
[11:0]
FFF
PBLKSCP1
PBLK Sequence-Change-Position 1.
37
[11:0]
FFF
PBLKSCP2
PBLK Sequence-Change-Position 2.
38
[11:0]
FFF
PBLKSCP3
PBLK Sequence-Change-Position 3.
REV. 0
–11–
AD9948
Table VI. HBLK Register Map
Address
Data Bit
Content
Default
Value (Hex)
Name
Description
40
[0]
0
HBLKDIR
HBLK Internal/External.
0 = Internal.
1 = External.
41
[0]
0
HBLKPOL
HBLK External Active Polarity.
0 = Active Low.
1 = Active High.
42
[0]
1
HBLKEXTMASK
HBLK External Masking Polarity.
0 = Mask H1 Low.
1 = Mask H1High.
43
[3:0]
F
HBLKMASK
HBLK Internal Masking Polarity.
0 = Mask H1 Low.
1 = Mask H1 High.
44
[23:0]
FFFFFF
HBLKTOG12_0
Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
45
[23:0]
FFFFFF
HBLKTOG34_0
Sequence 0. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
46
[23:0]
FFFFFF
HBLKTOG56_0
Sequence 0. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
47
[23:0]
FFFFFF
HBLKTOG12_1
Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
48
[23:0]
FFFFFF
HBLKTOG34_1
Sequence 1. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
49
[23:0]
FFFFFF
HBLKTOG56_1
Sequence 1. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
4A
[23:0]
FFFFFF
HBLKTOG12_2
Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
4B
[23:0]
FFFFFF
HBLKTOG34_2
Sequence 2. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
4C
[23:0]
FFFFFF
HBLKTOG56_2
Sequence 2. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
4D
[23:0]
FFFFFF
HBLKTOG12_3
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
4E
[23:0]
FFFFFF
HBLKTOG34_3
Sequence 3. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
4F
[23:0]
FFFFFF
0
HBLKTOG56_3
HBLKSCP0
Sequence 3. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
HBLK Sequence-Change-Position 0 (Hard-coded to 0).
50
[7:0]
0
HBLKSPTR
HBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6].
51
[11:0]
FFF
HBLKSCP1
HBLK Sequence-Change-Position 1.
52
[11:0]
FFF
HBLKSCP2
HBLK Sequence-Change-Position 2.
53
[11:0]
FFF
HBLKSCP3
HBLK Sequence-Change-Position 3.
Table VII. H1–H2, RG, SHP, SHD Register Map
Address
Data Bit
Content
Default
Value
Name
Description
60
[12:0]
01001
H1CONTROL
H1 Signal Control. Polarity [0] (0 = Inversion, 1 = No Inversion).
H1 Positive Edge Location [6:1].
H1 Negative Edge Location [12:7].
61
[12:0]
00801
RGCONTROL
RG Signal Control. Polarity [0] (0 = Inversion, 1 = No Inversion).
RG Positive Edge Location [6:1].
RG Negative Edge Location [12:7].
62
[14:0]
0
DRVCONTROL
Drive Strength Control for H1 [2:0], H2 [5:3], H3 [8:6], H4 [11:9], and
RG [14:12].
Drive Current Values: 0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA.
63
[11:0]
00024
SAMPCONTROL
SHP/SHD Sample Control. SHP Sampling Location [5:0].
SHD Sampling Location [11:6].
64
[5:0]
0
DOUTPHASE
DOUT Phase Control.
–12–
REV. 0
AD9948
Table VIII. AFE Operation Register Detail
Address
Data Bit
Content
Default
Value
Name
Description
00
[1:0]
0
PWRDOWN
[2]
1
CLPENABLE
[3]
0
CLPSPEED
[4]
0
FASTUPDATE
[5]
0
PBLK_LVL
[7:6]
[8]
0
0
TEST MODE
DCBYP
[9]
[11:10]
0
0
TESTMODE
CDSGAIN
0 = Normal Operation.
1 = Reference Standby.
2/3 = Total Power-Down.
0 = Disable OB Clamp.
1 = Enable OB Clamp.
0 = Select Normal OB Clamp Settling.
1 = Select Fast OB Clamp Settling.
0 = Ignore VGA Update.
1 = Very Fast Clamping when VGA Is Updated.
DOUT Value during PBLK.
0 = Blank to Zero.
1 = Blank to Clamp Level.
Test Operation Only. Set to zero.
0 = Enable DC Restore Circuit.
1 = Bypass DC Restore Circuit during PBLK.
Test Operation Only. Set to zero.
Adjustment of CDS Gain.
0 = 0 dB.
01= –2 dB.
10 = –4 dB.
11 = 0 dB.
Table IX. AFE Control Register Detail
Address
Data Bit
Content
Default
Value
Name
Description
04
[1:0]
0
COLORSTEER
[2]
1
PXGAENABLE
[3]
0
DOUTDISABLE
[4]
0
DOUTLATCH
[5]
0
GRAYENCODE
0 = Off.
1 = Progressive.
2 = Interlaced.
3 = Three Field.
0 = Disable PxGA.
1 = Enable PxGA.
0 = Data Outputs Are Driven.
1 = Data Outputs Are Three-Stated.
0 = Latch Data Outputs with DOUT Phase.
1 = Output Latch Transparent.
0 = Binary Encode Data Outputs.
1= Gray Encode Data Outputs.
REV. 0
–13–
AD9948
PRECISION TIMING HIGH SPEED TIMING GENERATION
High Speed Clock Programmability
The AD9948 generates flexible high speed timing signals using
the Precision Timing core. This core is the foundation for generating the timing used for both the CCD and the AFE; the reset
gate RG, horizontal drivers H1–H4, and the SHP/SHD sample
clocks. A unique architecture makes it routine for the system
designer to optimize image quality by providing precise control
over the horizontal CCD readout and the AFE correlated
double sampling.
Figure 5 shows how the high speed clocks, RG, H1–H4, SHP,
and SHD, are generated. The RG pulse has programmable rising
and falling edges, and may be inverted using the polarity control.
The horizontal clocks H1 and H3 have programmable rising and
falling edges, and polarity control. The H2 and H4 clocks are
always inverses of H1 and H3, respectively. Table X summarizes
the high speed timing registers and their parameters.
Timing Resolution
The Precision Timing core uses a 1× master clock input (CLI)
as a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 4 illustrates how the internal timing core
divides the master clock period into 48 steps or edge positions.
Therefore, the edge resolution of the Precision Timing core is
(tCLI/48). For more information on using the CLI input, refer to
the Applications Information section.
POSITION
Each edge location setting is 6 bits wide, but only 48 valid edge
locations are available. Therefore, the register values are mapped
into four quadrants, with each quadrant containing 12 edge
locations. Table XI shows the correct register values for the
corresponding edge locations.
P[12]
P[0]
P[24]
P[36]
P[48] = P[0]
CLI
...
tCLIDLY
...
1 PIXEL
PERIOD
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6 ns TYP).
Figure 4. High Speed Clock Resolution From CLI Master Clock Input
(3)
(4)
CCD SIGNAL
(1)
(2)
RG
(5)
(6)
H1/H3
H2/H4
PROGRAMMABLE CLOCK POSITIONS:
1. RG RISING EDGE
2. RG FALLING EDGE
3. SHP SAMPLE LOCATION
4. SHD SAMPLE LOCATION
5. H1/H3 RISING EDGE POSITION
6. H1/H3 FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3)
Figure 5. High Speed Clock Programmable Locations
Table X. H1CONTROL, RGCONTROL, DRVCONTROL, and SAMPCONTROL Register Parameters
Parameter
Length
Range
Description
Polarity
Positive Edge
Negative Edge
Sample Location
Drive Control
DOUT Phase
1b
6b
6b
6b
3b
6b
High/Low
0–47 Edge Location
0–47 Edge Location
0–47 Sample Location
0–7 Current Steps
0–47 Edge Location
Polarity Control for H1/H3 and RG (0 = No Inversion, 1 = Inversion).
Positive Edge Location for H1/H3 and RG.
Negative Edge Location for H1/H3 and RG.
Sampling Location for SHP and SHD.
Drive Current for H1–H4 and RG Outputs, 0–7 Steps of 4.1 mA Each.
Phase Location of Data Outputs with Respect to Pixel Period.
–14–
REV. 0
AD9948
Table XI. Precision Timing Edge Locations
Quadrant
Edge Location (Decimal)
Register Value (Decimal)
Register Value (Binary)
I
II
III
IV
0 to 11
12 to 23
24 to 35
36 to 47
0 to 11
16 to 27
32 to 43
48 to 59
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9948
features on-chip output drivers for the RG and H1–H4 outputs.
These drivers are powerful enough to directly drive the CCD
inputs. The H-driver and RG driver current can be adjusted
for optimum rise/fall time into a particular load by using the
DRVCONTROL register (Address x062). The DRVCONTROL
register is divided into five different 3-bit values, each one being
adjustable in 4.1 mA increments. The minimum setting of 0 is
equal to OFF or three-state, and the maximum setting of 7 is
equal to 30.1 mA.
As shown in Figure 6, the H2/H4 outputs are inverses of H1/H3.
The internal propagation delay resulting from the signal inversion
is less than l ns, which is significantly less than the typical rise
time driving the CCD load. This results in a H1/H2 crossover
voltage at approximately 50% of the output swing. The crossover
voltage is not programmable.
Digital Data Outputs
The AD9948 data output phase is programmable using the
DOUTPHASE register (Address x064). Any edge from 0 to 47
may be programmed, as shown in Figure 7a. The pipeline delay
for the digital data output is shown in Figure 7b.
tRISE
H1/H3
H2/H4
tPD << tRISE
tPD
H1/H3
H2/H4
FIXED CROSSOVER VOLTAGE
Figure 6. H-Clock Inverse Phase Relationship
P[12]
P[0]
P[24]
P[48] = P[0]
P[36]
CLI
1 PIXEL PERIOD
tOD
DOUT
NOTES
1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.
Figure 7a. Digital Output Phase Adjustment
CLI
tCLIDLY
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N+10
N+11
N–3
N–2
N–1
N+12
N+13
CCDIN
SAMPLE PIXEL N
SHD
(INTERNAL)
PIPELINE LATENCY = 11 CYCLES
DOUT
N–13
N–12
N–11
N–10
N–9
N–8
N–7
N–6
N–5
N–4
N
NOTES
DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0.
HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
REV. 0
Figure 7b. Pipeline Delay for Digital Data Output
–15–
N+1
AD9948
HORIZONTAL CLAMPING AND BLANKING
The AD9948’s horizontal clamping and blanking pulses are
fully programmable to suit a variety of applications. Individual
sequences are defined for each signal, which are then organized
into multiple regions during image readout. This allows the dark
pixel clamping and blanking patterns to be changed at each
stage of the readout to accommodate different image transfer
timing and high speed line shifts.
Individual CLPOB and PBLK Sequences
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 8. These two signals are independently programmed using the parameters shown in Table XII. The start
polarity, first toggle position, and second toggle position are
fully programmable for each signal. The CLPOB and PBLK
signals are active low, and should be programmed accordingly.
Up to four individual sequences can be created for each signal.
Individual HBLK Sequences
The HBLK programmable timing shown in Figure 9 is similar
to CLPOB and PBLK. However, there is no start polarity control. Only the toggle positions are used to designate the start and
the stop positions of the blanking period. Additionally, there is a
polarity control, HBLKMASK, which designates the polarity of
the horizontal clock signals H1–H4 during the blanking period.
Setting HBLKMASK high will set H1 = H3 = low and H2 =
H4 = high during the blanking, as shown in Figure 10. Up to
four individual sequences are available for HBLK.
...
HD
(2)
CLPOB (1)
PBLK
...
(3)
ACTIVE
ACTIVE
PROGRAMMABLE SETTINGS:
1. START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)
2. FIRST TOGGLE POSITION
3. SECOND TOGGLE POSITION
Figure 8. Clamp and Preblank Pulse Placement
...
HD
...
(2)
(1)
BLANK
HBLK
BLANK
PROGRAMMABLE SETTINGS:
1. FIRST TOGGLE POSITION = START OF BLANKING
2. SECOND TOGGLE POSITION = END OF BLANKING
Figure 9. Horizontal Blanking (HBLK) Pulse Placement
Table XII. CLPOB and PBLK Individual Sequence Parameters
Parameter
Length
Range
Description
Polarity
Toggle Position 1
Toggle Position 2
1b
12b
12b
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
Starting Polarity of Clamp and PBLK Pulses for Sequences 0–3.
First Toggle Position within the Line for Sequences 0–3.
Second Toggle Position within the Line for Sequences 0–3.
Table XIII. HBLK Individual Sequence Parameters
Parameter
Length
Range
Description
HBLKMASK
Toggle Position 1
Toggle Position 2
Toggle Position 3
Toggle Position 4
Toggle Position 5
Toggle Position 6
1b
12b
12b
12b
12b
12b
12b
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
Masking Polarity for H1 for Sequences 0–3 (0 = H1 Low, 1 = H1 High).
First Toggle Position within the Line for Sequences 0–3.
Second Toggle Position within the Line for Sequences 0–3.
Third Toggle Position within the Line for Sequences 0–3.
Fourth Toggle Position within the Line for Sequences 0–3.
Fifth Toggle Position within the Line for Sequences 0–3.
Sixth Toggle Position within the Line for Sequences 0–3.
–16–
REV. 0
AD9948
...
HD
...
HBLK
H1/H3
THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1).
...
H1/H3
H2/H4
...
Figure 10. HBLK Masking Control
TOG2
TOG1
TOG3
TOG4
TOG5
TOG6
HBLK
H1/H3
H2/H4
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS.
Figure 11. Generating Special HBLK Patterns
Table XIV. Horizontal Sequence Control Parameters for CLPOB, PBLK, and HBLK
Register
Length
Range
Description
SCP
12b
0–4095 Line Number
CLOB/PBLK/HBLK SCP to Define Horizontal Regions 0–3.
SPTR
2b
0–3 Sequence Number
Sequence Pointer for Horizontal Regions 0–3.
GENERATING SPECIAL HBLK PATTERNS
Six toggle positions are available for HBLK. Normally, only
two of the toggle positions are used to generate the standard
HBLK interval. However, the additional toggle positions may be
used to generate special HBLK patterns, as shown in Figure 11.
The pattern in this example uses all six toggle positions to
generate two extra groups of pulses during the HBLK interval. By changing the toggle positions, different patterns can
be created.
Horizontal Sequence Control
The AD9948 uses sequence change positions (SCPs) and sequence
pointers (SPTRs) to organize the individual horizontal sequences.
Up to four SCPs are available to divide the readout into four
separate regions, as shown in Figure 12. The SCP 0 is always hardcoded to Line 0, and SCP1–SCP3 are register programmable.
During each region bounded by the SCP, the SPTR registers
REV. 0
designate which sequence is used by each signal. CLPOB, PBLK,
and HBLK each have a separate set of SCPs. For example,
CLPOBSCP1 will define Region 0 for CLPOB, and in that region,
any of the four individual CLPOB sequences may be selected with
the CLPOBSPTR register. The next SCP defines a new region,
and in that region each signal can be assigned to a different
individual sequence. The sequence control registers are summarized in Table XIV.
External HBLK Signal
The AD9948 can also be used with an external HBLK signal. Setting the HBLKDIR register (Address x040) to high will disable the
internal HBLK signal generation. The polarity of the external
signal is specified using the HBLKPOL register, and the masking polarity of H1 is specified using the HBLKMASK register.
Table XV summarizes the register values when using an external
HBLK signal.
–17–
AD9948
SINGLE FIELD (1 VD INTERVAL)
SEQUENCE CHANGE OF POSITION 0
(V-COUNTER = 0)
CLAMP AND PBLK SEQUENCE REGION 0
SEQUENCE CHANGE OF POSITION 1
CLAMP AND PBLK SEQUENCE REGION 1
SEQUENCE CHANGE OF POSITION 2
CLAMP AND PBLK SEQUENCE REGION 2
SEQUENCE CHANGE OF POSITION 3
CLAMP AND PBLK SEQUENCE REGION 3
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE
PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
Figure 12. Clamp and Blanking Sequence Flexibility
Table XV. External HBLK Register Parameters
Register
Length
Range
Description
HBLKDIR
1b
High/Low
HBLKPOL
1b
High/Low
HBLKEXTMASK
1b
High/Low
Specifies HBLK Internally Generated or Externally Supplied.
1 = External.
External HBLK Active Polarity.
0 = Active Low.
1 = Active High.
External HBLK Masking Polarity.
0 = Mask H1 Low.
1 = Mask H1 High.
VD
HD
H-COUNTER
RESET
CLI
H-COUNTER X
(PIXEL COUNTER)
X
X
X
X
X
X
X
X
X
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
0
1
2
3
PxGA GAIN
REGISTER X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
2
3
2
3
NOTES
1. INTERNAL H-COUNTER IS RESET SEVEN CLI CYCLES AFTER THE HD FALLING EDGE (WHEN USING VDHDEDGE = 0).
2. TYPICAL TIMING RELATIONSHIP: CLI RISING EDGE COINCIDES WITH HD FALLING EDGE.
3. PxGA STEERING IS SYNCHRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).
Figure 13. H-Counter Synchronization
H-COUNTER SYNCHRONIZATION
The H-Counter reset occurs seven CLI cycles following the HD
falling edge. The PxGA steering is synchronized with the reset
of the internal H-Counter (see Figure 13).
–18–
REV. 0
AD9948
POWER-UP PROCEDURE
VDD
(INPUT)
CLI
(INPUT)
tPWR
SERIAL
WRITES
1V
...
...
VD
(OUTPUT)
ODD FIELD
EVEN FIELD
1H
...
...
HD
(OUTPUT)
H2/H4
DIGITAL
OUTPUTS
H1/H3, RG
CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER IS
UPDATED AT VD/HD EDGE
Figure 14. Recommended Power-Up Sequence
Recommended Power-Up Sequence
5. Write a 1 to the PREVENTUPDATE register (Address x014).
This will prevent the updating of the serial register data.
When the AD9948 is powered up, the following sequence is
recommended (refer to Figure 14 for each step):
6. Write to the desired registers to configure high speed timing
and horizontal timing.
1. Turn on the power supplies for the AD9948.
2. Apply the master clock input, CLI, VD, and HD.
3. Although the AD9948 contains an on-chip power-on reset, a
software reset of the internal registers is recommended. Write
a 1 to the SW_RST register (Address x010), which will reset
all the internal registers to their default values. This bit is
self-clearing and will automatically be reset back to 0.
4. The Precision Timing core must be reset by writing a 0 to the
TGCORE_RSTB register (Address x012) followed by writing
a l to the TGCORE_RSTB register. This will start the internal
timing core operation.
REV. 0
7. Write a 1 to the OUT_CONTROL register (Address x011).
This will allow the outputs to become active after the next
VD/HD rising edge.
8. Write a 0 to the PREVENTUPDATE register (Address x014).
This will allow the serial information to be updated at next
VD/HD falling edge.
The next VD/HD falling edge allows register updates to occur,
including OUT_CONTROL, which enables all clock outputs.
–19–
AD9948
1.0F 1.0F
DC RESTORE
AD9948
DOUT
PHASE
SHD
CCDIN
10
OUTPUT
DATA
LATCH
10-BIT
ADC
VGA
PxGA
CDS
2V FULL SCALE
6dB ~ 42dB
0dB ~ 18dB
1.0F
REFT
2.0V
INTERNAL
VREF
1.5V
SHP
REFB
1.0V
DOUT
0dB, –2dB, –4dB
DAC
VGA GAIN
REGISTER
PxGA GAIN
REGISTERS
OPTICAL BLACK
CLAMP
CLPOB PBLK
DIGITAL
FILTER
8
DOUT
SHP SHD PHASE
PRECISION
TIMING
GENERATION
CLPOB
CLAMP LEVEL
REGISTER
PBLK
V-H
TIMING
GENERATION
Figure 15. Analog Front End Functional Block Diagram
ANALOG FRONT END DESCRIPTION AND OPERATION
PxGA
The AD9948 signal processing chain is shown in Figure 15. Each
processing step is essential in achieving a high quality image from
the raw CCD pixel data.
The PxGA provides separate gain adjustment for the individual
color pixels. A programmable gain amplifier with four separate
values, the PxGA has the capability to multiplex its gain value on
a pixel-to-pixel basis (see Figure 16). This allows lower output
color pixels to be gained up to match higher output color pixels.
Also, the PxGA may be used to adjust the colors for white balance, reducing the amount of digital processing that is needed.
The four different gain values are switched according to the color
steering circuitry. Three different color steering modes for different types of CCD color filter arrays are programmable in the AFE
CTLMODE register at Address 0x03 (see Figures 18a to 18c for
timing examples). For example, progressive steering mode accommodates the popular Bayer arrangement of red, green, and blue
filters (see Figure 17a).
DC Restore
To reduce the large dc offset of the CCD output signal,
a dc restore circuit is used with an external 0.1 µF series coupling capacitor. This restores the dc level of the CCD signal to
approximately 1.5 V to be compatible with the 3 V supply voltage
of the AD9948.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
shown in Figure 5 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference
level and the CCD signal level, respectively. The placement of
the SHP and SHD sampling edges is determined by the setting
of the SAMPCONTROL register located at Address 0x63.
Placement of these two clock signals is critical in achieving the
best performance from the CCD.
VD
SHP/SHD
Max CDS Input
0
0
1
1
0 dB
–2 dB
–4 dB
0 dB
1.0 V p-p
1.2 V p-p
1.6 V p-p
1.0 V p-p
0
1
0
1
PxGA STEERING
MODE
SELECTION
CONTROL
REGISTER
BITS D0–D1
GAIN0
4:1
MUX
PxGA
GAIN1
GAIN2
PxGA GAIN
REGISTERS
GAIN3
8
CDS
Table XVI. Adjustable CDS Gain
CDS Gain
3
2
The gain in the CDS is fixed at 0 dB by default. Using Bits D10
and D11 in the AFE operation register, the gain may be reduced
to –2 dB or –4 dB. This will allow the AD9948 to accept an input
signal of greater than 1 V p-p. See Table VIII for register details.
Operation Register Bits
D11
D10
COLOR
STEERING
CONTROL
HD
VGA
Figure 16. PxGA Block Diagram
–20–
REV. 0
AD9948
CCD: PROGRESSIVE BAYER
A third type of readout uses the Bayer pattern divided into three
different readout fields. The three-field mode should be used
with this type of CCD (see Figure 17c). The color steering
performs the proper multiplexing of the R, G, and B gain values
(loaded into the PxGA gain registers), and is synchronized by
the user with vertical (VD) and horizontal (HD) sync pulses.
For timing information, see Figure 18c.
COLOR STEERING MODE:
PROGRESSIVE
R
Gr
R
Gr
LINE0
GAIN0, GAIN1, GAIN0, GAIN1, ...
Gb
B
Gb
B
LINE1
GAIN2, GAIN3, GAIN2, GAIN3, ...
R
Gr
R
Gr
LINE2
GAIN0, GAIN1, GAIN0, GAIN1, ...
Gb
B
Gb
B
CCD: 3-FIELD READOUT
COLOR STEERING MODE:
THREE FIELD
FIRST FIELD
Figure 17a. CCD Color Filter Example—Progressive Scan
The same Bayer pattern can also be interlaced, and the interlaced
mode should be used with this type of CCD (see Figure 17b).
The color steering performs the proper multiplexing of the R,
G, and B gain values (loaded into the PxGA gain registers), and
is synchronized by the user with vertical (VD) and horizontal
(HD) sync pulses. For timing information, see Figure 18b.
R
Gr
R
Gr
LINE0
GAIN0, GAIN1, GAIN0, GAIN1, ...
Gb
B
Gb
B
LINE1
GAIN2, GAIN3, GAIN2, GAIN3, ...
R
Gr
R
Gr
LINE2
GAIN0, GAIN1, GAIN0, GAIN1, ...
Gb
B
Gb
B
SECOND FIELD
CCD: INTERLACED BAYER
EVEN FIELD
COLOR STEERING MODE:
INTERLACED
Gb
B
Gb
B
LINE0
GAIN2, GAIN3, GAIN2, GAIN3, ...
R
Gr
R
Gr
LINE0
GAIN0, GAIN1, GAIN0, GAIN1, ...
R
Gr
R
Gr
LINE1
GAIN0, GAIN1, GAIN0, GAIN1, ...
R
Gr
R
Gr
LINE1
GAIN0, GAIN1, GAIN0, GAIN1, ...
Gb
B
Gb
B
LINE2
GAIN2, GAIN3, GAIN2, GAIN3, ...
R
Gr
R
Gr
LINE2
GAIN0, GAIN1, GAIN0, GAIN1, ...
R
Gr
R
Gr
R
Gr
R
Gr
THIRD FIELD
ODD FIELD
R
Gr
R
Gr
LINE0
GAIN0, GAIN1, GAIN0, GAIN1, ...
Gb
B
Gb
B
LINE0
GAIN2, GAIN3, GAIN2, GAIN3, ...
Gb
B
Gb
B
LINE1
GAIN2, GAIN3, GAIN2, GAIN3, ...
Gb
B
Gb
B
LINE1
GAIN2, GAIN3, GAIN2, GAIN3, ...
R
Gr
R
Gr
LINE2
GAIN0, GAIN1, GAIN0, GAIN1, ...
Gb
B
Gb
B
LINE2
GAIN2, GAIN3, GAIN2, GAIN3, ...
Gb
B
Gb
B
Gb
B
Gb
B
Figure 17c. CCD Color Filter Example—Three-Field Readout
Figure 17b. CCD Color Filter Example—Interlaced Readout
REV. 0
–21–
AD9948
FIELDVAL = 0
FIELDVAL
FIELDVAL = 0
VD
HD
PxGA GAIN
REGISTER X
X
0
1
0
1
2
3
2
3
0
1
0
1
0
1
0
1
2
3
2
3
0
1
0
1
0
1
0
1
3
2
3
0
NOTES
1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.
2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN 0101 AND 2323 LINES.
3. FIELDVAL IS ALWAYS RESET TO 0 ON VD FALLING EDGES.
Figure 18a. PxGA Color Steering—Progressive Mode
FIELDVAL = 0
FIELDVAL
FIELDVAL = 1
FIELDVAL = 0
VD
HD
PxGA GAIN
REGISTER X
X
0
1
0
1
0
1
0
1
2
3
2
3
2
3
2
3
0
1
0
1
NOTES
1. FIELDVAL = 0 (START OF FIRST FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.
2. FIELDVAL = 1 (START OF SECOND FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 2323 LINE.
3. HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO EITHER 0 (FIELDVAL = 0) OR 2 (FIELDVAL = 1).
4. FIELDVAL WILL TOGGLE BETWEEN 0 AND 1 ON EACH VD FALLING EDGE.
Figure 18b. PxGA Color Steering—Interlaced Mode
FIELDVAL = 0
FIELDVAL
FIELDVAL = 1
FIELDVAL = 2
VD
HD
PxGA GAIN
REGISTER X
X
0
1
0
1
2
3
2
3
2
3
2
3
1
0
1
0
0
1
0
1
2
NOTES
1. FIELDVAL = 0 (START OF FIRST FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.
2. FIELDVAL = 1 (START OF SECOND FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 2323 LINE.
2. FIELDVAL = 2 (START OF THIRD FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.
3. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN 0101 AND 2323 LINES.
4. FIELDVAL WILL INCREMENT AT EACH VD FALLING EDGE, REPEATING THE 0...1...2...0...1...2 PATTERN.
Figure 18c. PxGA Color Steering—Three-Field Mode
–22–
REV. 0
AD9948
The PxGA gain for each of the four channels is variable from 0 dB
to 18 dB in 512 steps, specified using the PxGA GAIN01 and
PxGA GAIN23 registers. The PxGA gain curve is shown in
Figure 19. The PxGA GAIN01 registers contains nine bits each
for PxGA Gain0 and Gain1, and the PxGA GAIN23 registers
contains nine bits each for PxGA Gain2 and Gain3.
A/D Converter
The AD9948 uses a high performance ADC architecture, optimized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB. The ADC
uses a 2 V input range. See TPC 1 and TPC 2 for typical linearity
and noise performance plots for the AD9948.
Optical Black Clamp
18
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the clamp level register.
The value can be programmed between 0 LSB and 63.75 LSB
in 256 steps. The resulting error signal is filtered to reduce noise,
and the correction value is applied to the ADC input through a
D/A converter. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital clamping
is used during the postprocessing, the AD9948 optical black
clamping may be disabled using Bit D2 in the OPRMODE register.
When the loop is disabled, the clamp level register may still be
used to provide programmable offset adjustment.
15
PxGA GAIN (dB)
12
9
6
3
0
0
64
128
192
256
320
384
448
511
PxGA GAIN REGISTER CODE
Figure 19. PxGA Gain Curve
Variable Gain Amplifier
The VGA stage provides a gain range of 6 dB to 42 dB, programmable with 10-bit resolution through the serial digital interface.
The minimum gain of 6 dB is needed to match a 1 V input signal
with the ADC full-scale range of 2 V. When compared to 1 V
full-scale systems, the equivalent gain range is 0 dB to 36 dB.
The VGA gain curve follows a linear-in-dB characteristic. The
exact VGA gain can be calculated for any gain register value by
using the equation
Gain ( dB ) = (0.0351 × Code) + 6 dB
where the code range is 0 to 1023.
There is a restriction on the maximum amount of gain that can
be applied to the signal. The PxGA can add as much as 18 dB,
and the VGA is capable of providing up to 42 dB. However, the
maximum total gain from the PxGA and VGA is restricted to
42 dB. If the registers are programmed to specify a total gain
higher than 42 dB, the total gain will be clipped at 42 dB.
The CLPOB pulse should be placed during the CCD’s optical
black pixels. It is recommended that the CLPOB pulse duration
be at least 20 pixels wide to minimize clamp noise. Shorter
pulsewidths may be used, but clamp noise may increase and the
ability to track low frequency variations in the black level will be
reduced. See the Horizontal Clamping and Blanking and the
Applications Information sections for timing examples.
Digital Data Outputs
The AD9948 digital output data is latched using the DOUT
phase register value, as shown in Figure 15. Output data timing is
shown in Figure 7. It is also possible to leave the output latches
transparent, so that the data outputs are valid immediately from
the A/D converter. Programming the AFE control register Bit D4
to a 1 will set the output latches transparent. The data outputs
can also be disabled (three-stated) by setting the AFE control
register Bit D3 to a 1.
The data output coding is normally straight binary, but the
coding my be changed to gray coding by setting the AFE
control register Bit D5 to a 1.
42
36
VGA GAIN (dB)
30
24
18
12
6
0
127
255
383
511
639
767
VGA GAIN REGISTER CODE
895
1023
Figure 20. VGA Gain Curve (PxGA Not Included)
REV. 0
–23–
AD9948
APPLICATIONS INFORMATION
Circuit Configuration
Grounding and Decoupling Recommendations
As shown in Figure 21, a single ground plane is recommended
for the AD9948. This ground plane should be as continuous as
possible, particularly around Pins 23 to 30. This will ensure that
all analog decoupling capacitors provide the lowest possible
impedance path between the power and bypass pins and their
respective ground pins. All high frequency decoupling capacitors
should be located as close as possible to the package pins. It is
recommended that the exposed paddle on the bottom of the
package be soldered to a large pad, with multiple vias connecting the pad to the ground plane.
The AD9948 recommended circuit configuration is shown in
Figure 21. Achieving good image quality from the AD9948
requires careful attention to PCB layout. All signals should be
routed to maintain low noise performance. The CCD output
signal should be directly routed to Pin 27 through a 0.1 µF
capacitor. The master clock CLI should be carefully routed to
Pin 25 to minimize interference with the CCDIN, REFT, and
REFB signals.
The digital outputs and clock inputs are located on Pins 2 to 13
and Pins 31 to 39, and should be connected to the digital ASIC
away from the analog and CCD clock signals. Placing series
resistors close to the digital output pins may help to reduce
digital code transition noise. If the digital outputs must drive a
load larger than 20 pF, buffering is recommended to minimize
additional noise. If the digital ASIC can accept gray code, the
AD9948’s outputs can be selected to output data in gray code
format using the control register Bit D5. Gray coding will
help reduce potential digital transition noise compared with
binary coding.
All the supply pins must be decoupled to ground with good
quality, high frequency chip capacitors. There should also be a
4.7 µF or larger bypass capacitor for each main supply—AVDD,
RGVDD, HVDD, and DRVDD—although this is not necessary
for each individual pin. In most applications, it is easier to share
the supply for RGVDD and HVDD, which may be done as long
as the individual supply pins are separately bypassed. A separate
3 V supply may be used for DRVDD, but this supply pin should
still be decoupled to the same ground plane as the rest of the
chip. A separate ground for DRVSS is not recommended.
The H1–H4 and RG traces should have low inductance to
avoid excessive distortion of the signals. Heavier traces are
recommended because of the large transient current demand
on H1–H4 from the capacitive load of the CCD. If possible,
physically locating the AD9948 closer to the CCD will reduce
the inductance on these lines. As always, the routing path
should be as direct as possible from the AD9948 to the CCD.
3V
ANALOG
SUPPLY
4
5
31 SL
33 SCK
32 SDI
35 HD
34 VD
30
REFB
1F
29
REFT
1F
28
27
AVSS
CCDIN
AD9948
26
AVDD
TOP VIEW
25
24
CLI
TCVDD
TCVSS
RGVDD
RG
9
D6 10
21
0.1F
CCD SIGNAL
MASTER CLOCK INPUT
0.1F
+
4.7F
0.1F
3V
ANALOG
SUPPLY
RG OUTPUT
RGVSS 20
D5
23
22
H4 19
8
H3 18
D4
HVSS 16
6
7
HVDD 17
DRVDD
D3
(MSB) D9 13
H1 14
H2 15
DATA
OUTPUTS
10
D2
DRVSS
SERIAL
INTERFACE
3
PIN 1
IDENTIFIER
D7 11
D8 12
+
4.7F 0.1F
1
2
3
38 HBLK
37 DVDD
36 DVSS
40 NC
4
NC
(LSB) D0
D1
3V
DRIVER
SUPPLY
0.1F
39 CLP/PBLK
VD/HD/HBLK INPUTS
CLP/BLK OUTPUT
The reference bypass pins (REFT, REFB) should be decoupled
to ground as close as possible to their respective pins. The analog
input (CCDIN) capacitor should also be located close to the pin.
0.1F
RG DRIVER
SUPPLY
+
4.7F
H DRIVER
SUPPLY
0.1F
+
4.7F
4
H1–H4
Figure 21. Recommended Circuit Configuration
–24–
REV. 0
AD9948
Driving the CLI Input
The AD9948’s master clock input (CLI) may be used in two
different configurations, depending on the application. Figure 23a
shows a typical dc-coupled input from the master clock source.
When the dc-coupled technique is used, the master clock signal
should be at standard 3 V CMOS logic levels. As shown in
Figure 23b, a 1000 pF ac coupling capacitor may be used
between the clock source and the CLI input. In this configuration, the CLI input will self-bias to the proper dc voltage level
of approximately 1.4 V. When the ac-coupled technique is
used, the master clock signal can be as low as ± 500 mV in
amplitude.
CCDIN
AD9948
18
H3
19
H4
14
H1
AD9948
27
15
H2
25
21
ASIC
CLI
RG
SIGNAL
OUT
MASTER CLOCK
Figure 23a. CLI Connection, DC-Coupled
H2
H1
RG
CCD IMAGER
Figure 22a. CCD Connections (2 H-Clock)
AD9948
25
CCDIN
27
AD9948
ASIC
CLI
LPF
1nF
14
H1
15
H2
18
H3
19
H4
MASTER CLOCK
21
RG
Figure 23b. CLI Connection, AC-Coupled
SIGNAL
OUT
H1
H2
RG
CCD IMAGER
H2
H1
Figure 22b. CCD Connections (4 H-Clock)
REV. 0
–25–
AD9948
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 24 shows an example CCD layout. The horizontal register contains 28 dummy pixels, which will occur on each line
clocked from the CCD. In the vertical direction, there are 10
optical black (OB) lines at the front of the readout and two at
the back of the readout. The horizontal direction has four OB
pixels in the front and 48 in the back.
To configure the AD9948 horizontal signals for this CCD, three
sequences can be used. Figure 25 shows the first sequence, to be
used during vertical blanking. During this time, there are no
valid OB pixels from the sensor, so the CLPOB signal is not
used. PBLK may be enabled during this time, because no valid
data is available.
Figure 26 shows the recommended sequence for the vertical OB
interval. The clamp signals are used across the whole lines in
order to stabilize the clamp loop of the AD9948.
Figure 27 shows the recommended sequence for the effective
pixel readout. The 48 OB pixels at the end of each line are used
for the CLPOB signal.
SEQUENCE 2 (OPTIONAL)
2 VERTICAL OB LINES
USE SEQUENCE 3
EFFECTIVE IMAGE AREA
V
10 VERTICAL OB LINES
USE SEQUENCE 2
H
48 OB PIXELS
4 OB PIXELS
HORIZONTAL CCD REGISTER
28 DUMMY PIXELS
Figure 24. Example CCD Configuration
SEQUENCE 1: VERTICAL BLANKING
CCDIN
INVALID PIX
VERTICAL SHIFT
DUMMY
INVALID PIXELS
VERT SHIFT
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
Figure 25. Horizontal Sequence during Vertical Blanking
–26–
REV. 0
AD9948
SEQUENCE 2: VERTICAL OPTICAL BLACK LINES
CCDIN
OPTICAL BLACK
VERTICAL SHIFT
OPTICAL BLACK
DUMMY
VERT SHIFT
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
Figure 26. Horizontal Sequences during Vertical Optical Black Pixels
SEQUENCE 3: EFFECTIVE PIXEL LINES
OB
CCDIN
OPTICAL BLACK
VERTICAL SHIFT
EFFECTIVE PIXELS
DUMMY
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
Figure 27. Horizontal Sequences during Effective Pixels
REV. 0
–27–
OPTICAL BLACK
VERT SHIFT
AD9948
OUTLINE DIMENSIONS
40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm 6 mm Body
(CP-40)
6.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
31
30
PIN 1
INDICATOR
0.50
BSC
5.75
BSC SQ
TOP
VIEW
0.50
0.40
0.30
12 MAX
1.00
0.90
0.80
C03752–0–5/03(0)
Dimensions shown in millimeters
40
1
4.25
3.70 SQ
1.75
BOTTOM
VIEW
21
20
10
11
4.50
REF
0.80 MAX
0.65 NOM
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
–28–
REV. 0