AD ADM802L Microprocessor supervisory circuit Datasheet

Microprocessor
Supervisory Circuits
ADM690A/ADM692A/ADM802L/M/ADM805L/M
a
FEATURES
Precision Supply Voltage Monitor
4.65 V ADM690A/ADM802L/ADM805L
4.40 V ADM692A/ADM802M/ADM805M
Reset Assertion Down to 1 V V CC
Reset Timeout—200 ms
Watchdog Timer—1.6 s
100 mA Quiescent Supply Current
Automatic Battery Backup Power Switching
Voltage Monitor for Power Fail
62% Power Fail Accuracy on ADM802L/M
Space-Saving MicroSOIC Package (ADM690A)
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
FUNCTIONAL BLOCK DIAGRAM
VBATT
BATTERY
SWITCHOVER
VOUT
VCC
4.65V*
WATCHDOG
INPUT (WDI)
RESET
GENERATOR
WATCHDOG
TRANSITION DETECTOR
(1.6s)
POWER FAIL
INPUT (PFI)
RESET
(RESET)
ADM690A
ADM692A
ADM802L
ADM802M
ADM805L
ADM805M
POWER FAIL
OUTPUT (PFO)
1.25V
*4.4V FOR ADM692A/ADM802M/ADM805M
( ) = ADM805L/M ONLY
GENERAL DESCRIPTION
The ADM690A/ADM692A/ADM802L/M/ADM805L/M
family of supervisory circuits offers complete single chip
solutions for power supply monitoring and battery control
functions in microprocessor systems. These functions include
µP reset, backup battery switchover, watchdog timer, and power
failure warning.
The ADM805L/M provides an active high reset output, RESET
instead of RESET.
The ADM690A/ADM692A/ADM802L/M/ADM805L/M are
available in 8-pin packages and provide:
They provide a pin-compatible upgrade for the MAX690A/
MAX692A/MAX802L/MAX802M/MAX805L
1. Power-on reset output during power-up, power-down and
brownout conditions. The RESET output remains operational with VCC as low as 1 V.
All parts are available in 8-pin DIP and SOIC packages. The
ADM690A is also available in a new space-saving microSOIC
package.
The family of products is fabricated using an advanced epitaxial
CMOS process combining low power consumption and high
reliability. RESET assertion is guaranteed with VCC as low as 1 V.
2. Battery backup switching for CMOS RAM, CMOS
microprocessor or other low power devices.
3. A reset pulse if the optional watchdog timer has not been
toggled within 1.6 seconds.
4. A 1.25 V threshold detector for power fail warning, low battery
detection, or to monitor a power supply other than +5 V.
On the ADM690A/ADM802L/ADM805L the reset voltage
threshold is 4.65 V. On the ADM692A/ADM802M/
ADM805M, the reset voltage threshold is 4.40 V.
The ADM802L/ADM802M guarantee power fail accuracies to
± 2%.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
ADM690A/ADM692A/ADM802L/M/ADM805L/M–SPECIFICATIONS
(VCC = 4.75 V to 5.5 V (ADM690A/ADM802L/ADM805L), VCC = 4.5 V to 5.5 V, (ADM692A/ADM802M/ADM805M), VBATT = +2.8 V, TA = TMIN to TMAX
unless otherwise noted)
Parameter
Min
Typ
Max
Units
70
0.05
5.5
100
1.0
V
µA
µA
+0.02
VCC – 0.01
VCC – 0.05
VCC – 0.02
VBATT – 0.002
µA
V
V
V
V
20
–20
40
mV
mV
mV
Test Conditions/Comments
1
VCC/VBATT OPERATION
VCC Operating Voltage Range
1.0
Supply Current (Excludes IOUT)
Supply Current in Battery Backup Mode
Battery Standby Current
(+ = Discharge, – = Charge)
–0.1
VOUT Output Voltage
VCC – 0.02
VCC – 0.5
VOUT in Battery Backup Mode
VBATT – 0.05
Battery Switchover Threshold
Battery Switchover Hysteresis
RESET THRESHOLD
Reset Voltage Threshold
ADM690A, ADM802L, ADM805L
ADM692A, ADM802M, ADM805M
ADM802L
ADM802M
Reset Threshold Hysteresis
Reset Timeout Delay
RESET Output Voltage
4.5
4.25
4.55
4.30
140
VCC – 1.5
4.65
4.4
4.75
4.5
4.7
4.45
40
200
280
0.4
0.3
RESET Output Voltage
0.8
VCC – 1.5
0.4
WATCHDOG TIMER
Watchdog Timeout Period
WDI Input Pulse Width
WDI Input Threshold
Logic Low
Logic High
WDI Input Current
1.0
50
1.6
2.25
0.8
3.5
10
–10
POWER FAIL DETECTOR
PFI Input Threshold
PFI Input Current
PFO Output Voltage
1.20
1.225
–25
VCC – 1.5
1.25
1.25
0.01
1.30
1.275
+25
0.4
V
V
V
V
mV
ms
V
V
V
V
V
V
VCC = 0 V, VBATT = 2.8 V
5.5 V > VCC > VBATT + 0.2 V
IOUT = 5 mA
IOUT = 50 mA
IOUT = 250 mA
IOUT = 250 µA, VCC < VBATT – 0.2 V
Power Up
Power Down
TA = 25°C, VCC Falling
TA = 25°C, VCC Falling
ISOURCE = 800 µA
ISINK = 3.2 mA
ISINK = 100 µA, VCC = 1 V
ISOURCE = 4 µA, VCC = 1.1 V
ADM805L/M, ISOURCE = 800 µA
ADM805L/M, ISINK = 3.2 mA
s
ns
VIL = 0.4, VIH = 0.8 (VCC)
V
V
µA
µA
WDI = VCC
WDI = 0 V
V
V
nA
V
V
ADM690A, ADM692A, ADM805L/M
ADM802L/M
ISOURCE = 800 µA
ISINK = 3.2 mA
NOTES
1
Either VCC or VBATT can be 0 V if the other > +2.0 V.
Specifications subject to change without notice.
–2–
REV. 0
ADM690A/ADM692A/ADM802L/M/ADM805L/M
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Input Current
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . 400 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 120°C/W
Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . . 500 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4 kV
Model
Temperature
Range
Package
Option
ADM690AAN
ADM690AARN
ADM690AARM
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-8
SO-8
RM-8
ADM692AAN
ADM692AARN
–40°C to +85°C
–40°C to +85°C
N-8
SO-8
ADM802LAN
ADM802LARN
–40°C to +85°C
–40°C to +85°C
N-8
SO-8
ADM802MAN
ADM802MARN
–40°C to +85°C
–40°C to +85°C
N-8
SO-8
ADM805LAN
ADM805LARN
–40°C to +85°C
–40°C to +85°C
N-8
SO-8
ADM805MAN
ADM805MARN
–40°C to +85°C
–40°C to +85°C
N-8
SO-8
PIN CONFIGURATIONS
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods of time may affect device reliability.
VOUT 1
VCC 2
GND 3
PFI 4
ADM690A
ADM692A
ADM802L
ADM802M
ADM805L
ADM805M
TOP VIEW
(Not to Scale)
8 VBATT
7 RESET (RESET)
6 WDI
5 PFO
PIN FUNCTION DESCRIPTION
Mnemonic
Function
VCC
VBATT
Power Supply Input: +5 V Nominal.
Backup Battery Input. As VCC falls below the reset threshold and below VBATT by 20 mV, VBATT will be switched
to VOUT. On power-up as VCC rises to 20 mV above VBATT, VOUT will be switched back to VCC.
Output Voltage. When VCC is above the reset threshold, VOUT is connected to VCC through an on chip switch.
When VCC is below the reset threshold, the higher of VCC or VBATT is connected to VOUT.
0 V. Ground reference for all signals.
Power Fail Comparator Input. If PFI is less than 1.25 V, the power fail output PFO goes low. If unused, PFI
should be connected to VCC or GND.
Power Fail Comparator Output. If PFI is less than 1.25 V, the power fail output PFO goes low.
Logic Output. RESET goes low if
1. VCC falls below the Reset Threshold
2. The watchdog timer is not serviced within its timeout period (1.6 seconds)
The reset threshold is typically 4.65 V for the ADM690A/ADM802L/ADM805L and 4.4 V for the ADM692A/
ADM802M/ADM805M. RESET remains low for 200 ms after VCC returns above the threshold. RESET also
goes low for 200 ms if the watchdog timer is enabled but not serviced within its timeout period.
Active high RESET output (ADM805L/M only). This is the inverse of RESET. The asserted (high) level is VCC
or VBATT whichever is higher.
Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than 1.6 s, (RESET)
(RESET) is activated. The timer resets with each transition on the WDI line. The watchdog timer may be
disabled if WDI is left floating or is connected to a high impedance three stated logic output.
VOUT
GND
PFI
PFO
RESET
RESET
WDI
REV. 0
–3–
ADM690A/ADM692A/ADM802L/M/ADM805L/M
Typical Performance Curves
3
5.00
4.98
2.75
4.96
ROUT = 0.53Ω
4.88
VOUT – V
VOUT – V
ROUT = 9.3Ω
2.5
4.92
4.9
2.25
4.88
4.86
2
4.84
10
20
30
40
IOUT – mA
50
60
20
70
50
100
IOUT – mA
150
200
Figure 4. Output Voltage vs. Load Current in Normal
Operation
Figure 1. Output Voltage vs. Load Current in Battery
Backup
TA = +258C
5V
100
100
90
90
PFO
1.3V
PFI
1.2V
PFO
0V
10
10
0%
0%
200mV
1.3V
PFI
2µs
1.2V
200mV
2µs
Figure 5. Power Fail Comparator Response Time H ➝ L
Figure 2. Power Fail Comparator Response Time L ➝ H
TA = +258C
5V
VCC
100
100
90
4V
90
RESET
10
10
0%
0%
1V
1V
10µs
400ms
Figure 6. RESET Output Voltage vs. VCC
Figure 3. ADM690A RESET Response Time
–4–
REV. 0
ADM690A/ADM692A/ADM802L/M/ADM805L/M
+5V
VBATT
VCC
BATTERY
SWITCHOVER
VOUT
0V
VOUT
VCC
4.65V*
RESET
GENERATOR
0V
+5V
RESET
(RESET)
3.0V
tRS
RESET
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION DETECTOR
(1.6s)
POWER FAIL
INPUT (PFI)
ADM690A
ADM692A
ADM802L
ADM802M
ADM805L
ADM805M
0V
+5V
RESET
3.0V
0V
+5V
POWER FAIL
OUTPUT (PFO)
1.25V
PFO
VBATT = PFI = 3.0V
0V
*4.4V FOR ADM692A/ADM802M/ADM805M
( ) = ADM805L/M ONLY
Figure 7. Functional Block Diagram
Figure 8. Timing Diagram
POWER FAIL RESET, RESET
BATTERY SWITCHOVER SECTION
RESET is an active low output which provides a RESET signal
to the microprocessor whenever VCC is at an invalid level. When
VCC falls below the reset threshold, the RESET output is forced
low. The nominal reset voltage threshold is 4.65 V (ADM690A/
ADM802L/ADM805L or 4.4 V ADM692A/ADM802M/
ADM805M.
During normal operation with VCC higher than the reset
threshold, VCC is internally switched to VOUT via an internal
PMOS transistor switch. This switch has a typical on-resistance
of less than 1 Ω and can supply up to 100 mA at the VOUT
terminal. Once VCC falls below the reset threshold, the higher of
VCC or VBATT is switched to VOUT. This means that VBATT
connects to VOUT only when VCC is below the reset threshold
and VBATT is greater than VCC.
On power-up RESET will remain low for 200 ms after VCC rises
above the reset threshold. This allows time for the power supply
and microprocessor to stabilize. On power-down, the RESET
output remains low with VCC as low as 1 V. This ensures that
the microprocessor is held in a stable shutdown condition.
The guaranteed minimum and maximum thresholds are as follows:
ADM690A/ADM802L/ADM805L: 4.5 V and 4.75 V
ADM692A: 4.25 V and 4.5 V.
ADM802L: 4.55 V and 4.7 V
ADM802M: 4.3 V and 4.45 V
The ADM805L and ADM805M contain an active high reset
output. This is the complement of RESET and is intended for
processors requiring an active high RESET signal.
The guaranteed minimum and maximum thresholds for the
ADM805 are:
ADM805L: 4.5 V and 4.75 V
ADM805M: 4.25 V and 4.5 V.
Watchdog Timer RESET, RESET
The watchdog timer circuit monitors the activity of the microprocessor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within
1.6 seconds, a RESET pulse is generated. The watchdog
timeout period restarts with each transition on the WDI pin. To
ensure that the watchdog timer does not time out, either a
high-to-low or low-to-high transition on the WDI pin must
occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be
issued after each timeout period (1.6 s). The watchdog monitor
can be deactivated by floating the Watchdog Input (WDI) or by
connecting it to midsupply.
REV. 0
VOUT is normally used to drive a RAM memory bank which
may require instantaneous currents of greater than 100 mA. If
this is the case, then a bypass capacitor should be connected to
VOUT. The capacitor will provide the peak current transients to the
RAM. A capacitance value of 0.1 µF or greater may be used.
A 9 Ω MOSFET switch connects the VBATT input to VOUT
during battery backup. This MOSFET has very low input-tooutput differential (dropout voltage) at the low current levels
required for battery backup of CMOS RAM or other low power
CMOS circuitry. The supply current in battery backup is
typically 0.05 µA.
Typically 3 V batteries are used as the backup supply. High
value capacitors, either standard electrolytic or the farad size
double layer capacitors, can also be used for short-term memory
back up. A small charging current of typically 10 nA (0.1 µA
max) flows out of the VBATT terminal. This current is useful for
maintaining rechargeable batteries in a fully charged condition.
This extends the life of the back up battery by compensating for
its self discharge current. Also note that this current poses no
problem when lithium batteries are used for back up since the
maximum charging current (0.1 µA) is safe for even the smallest
lithium cells.
If the battery-switchover section is not used, VBATT should be
connected to GND and VOUT should be connected to VCC.
–5–
ADM690A/ADM692A/ADM802L/M/ADM805L/M
INPUT
POWER
Table I. Input and Output Status in Battery Backup Mode
Signal
Status
VOUT
RESET
RESET
PFI
PFO
WDI
R1
VOUT is connected to VBATT via an internal
PMOS switch.
Logic low.
Logic high (ADM805L, ADM805M). The open
circuit output voltage is equal to VOUT.
The power fail comparator is disabled
Logic low.
The watchdog timer is disabled
(PFO)
1.25V
TO
µP NMI
PFI
R2
R3
5V
PFO
Power Fail Comparator
The power fail comparator is an independent comparator
that may be used to monitor the input power supply. The
comparator’s inverting input is internally connected to a 1.25
V reference voltage. The noninverting input is available at the
PFI input. This input may be used to monitor the input power
supply via a resistive divider network. When the voltage on the
PFI input drops below 1.25 V, the comparator output (PFO)
goes low indicating a power failure. For early warning of power
failure the comparator may be used to monitor the preregulator
input simply by choosing an appropriate resistive divider
network. The PFO output can be used to interrupt the
processor so that a shutdown procedure is implemented before
the power is lost.
0V
0V
VH
VL
VIN
VH = 1.25 1+
VL = 1.25+R1
R2+R3
R2 × R3
1.25
–
R2
VMID= 1.25
R1
VCC–1.25
R3
R1+R2
R2
Figure 10. Adding Hysteresis to the Power Fail
Comparator
INPUT
POWER
TYPICAL APPLICATIONS
R1
R2
1.25V
(PFO)
Figure 11 shows a typical power monitoring, battery backup
application. VOUT powers the CMOS RAM. Under normal
operating conditions with VCC present, VOUT is internally
connected to VCC. If a power failure occurs, VCC will decay and
VOUT will be switched to VBATT thereby maintaining power for
the CMOS RAM. A RESET pulse is also generated when VCC
falls below the reset threshold.
POWER FAIL
OUTPUT
POWER
FAIL
INPUT
Figure 9. Power Fail Comparator
Adding Hysteresis to the Power Fail Comparator
UNREGULATED
DC
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is noninverting, hysteresis can be added simply by connecting a
resistor between the PFO output and the PFI input as shown in
Figure 10. When PFO is low, resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, resistor
R3 sources current into the PFI summing junction. This results
in differing trip levels for the comparator. Further noise
immunity may be achieved by connecting a capacitor between
PFI and GND.
+5V
VCC
µP POWER
R1
VOUT
PFI
µP SYSTEM
R2
RESET
VBATT
+
BATTERY
CMOS RAM
POWER
GND
µP RESET
PFO
µP NMI
WDI
I/O LINE
Figure 11. Typical Application Circuit
The watchdog timer input (WDI) monitors an I/O line from the
µP system. This line must be toggled once every 1.6 seconds to
verify correct software execution. Failure to toggle the line
indicates that the µP system is not correctly executing its
program and may be tied up in an endless loop. If this happens,
a reset pulse is generated to initialize the processor.
–6–
REV. 0
ADM690A/ADM692A/ADM802L/M/ADM805L/M
If the watchdog timer is not needed, the WDI input should be
left floating.
The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network. The voltage on the PFI input is
compared with a precision 1.25 V internal reference. If the input
voltage drops below 1.25 V, a power fail output (PFO) signal is
generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold
voltage VT.
VT = (1.25 R1/R2) + 1.25 V
R1/R2 = (VT/1.25) – 1
Alternate Watchdog Input Drive Circuits
The watchdog feature can be enabled and disabled under
program control by driving WDI with a 3-state buffer. When
three-stated, the WDI input will float thereby disabling the
watchdog timer.
Operation Without a Backup Supply
If a backup power source is not used, VBATT should be connected to GND and VOUT should be connected to VCC.
Replacing the Backup Battery
The backup battery may be replaced without any danger of
spurious resetting when VCC is present. Since VCC is above the
reset threshold, a reset will not occur even if VBATT is floating
while a replacement battery is being inserted. This differs from
older generation products where leakage currents flowing out
VBATT could cause spurious resetting during battery replacement.
mPs With Bidirectional RESET
In order to prevent contention for microprocessors with a
bidirectional reset line, a current limiting resistor should be
inserted between the ADM69xA/ADM80xx RESET output pin
and the µP reset pin. This will limit the current to a safe level if
there are conflicting output reset levels. A suitable resistor value
is 4.7 kΩ. If the reset output is required for other uses, then it
should be buffered as shown in Figure 13.
BUFFERED
RESET
High Capacity Backup Capacitors
High capacity (0.1 µF or greater) capacitors may be used as a
backup power source. A typical application is shown in Figure 12.
+5V
VCC
ADM690A
ADM692A
ADM802L
ADM802M
+5V
VOUT
VCC
RESET
GND
VBATT
0.1F
RESET
RESET*
RESET
GND
TO µP
+
Figure 13. Bidirectional Reset
GND
*FOR ADM805L/ADM805M ONLY
Figure 12. High Capacity Capacitor
REV. 0
µP
TO STATIC RAM
–7–
ADM690A/ADM692A/ADM802L/M/ADM805L/M
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C2197–12–10/96
8-Pin Plastic DIP
(N-8)
0.430 (10.92)
0.348 (8.84)
8
5
1
0.280 (7.11)
0.240 (6.10)
4
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
PIN 1
0.015 (0.38)
0.210 (5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.130
0.160 (4.06)
(3.30)
MIN
0.115 (2.93)
0.022 (0.558) 0.100 0.070 (1.77) SEATING
PLANE
0.014 (0.356) (2.54) 0.045 (1.15)
BSC
0.015 (0.381)
0.008 (0.204)
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
PIN 1
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0500 0.0192 (0.49)
(1.27) 0.0138 (0.35)
BSC
0.0196 (0.50)
x 45°
0.0099 (0.25)
0.0098 (0.25)
0.0075 (0.19)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
8-Lead MicroSOIC
(RM-8)
0.122 (3.10)
0.114 (2.90)
8
5
0.199 (5.05)
0.122 (3.10)
0.187 (4.75)
0.114 (2.90)
4
PRINTED IN U.S.A.
1
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.120 (3.05)
0.112 (2.84)
0.002 (0.05)
SEATING
PLANE
0.112 (2.84)
0.043 (1.09)
0.037 (0.938)
0.006 (0.15)
0.018 (0.46)
0.011 (0.28)
0.008 (0.20)
0.003 (0.08)
–8–
33°
27°
0.027 (0.68)
0.015 (0.38)
REV. 0