MCNIX MX29LA321MBXCC-70R 32m-bit [4m x 8/2m x 16] single voltage 3v only flash memory Datasheet

MX29LA32xMT/B
FEATURES
32M-BIT [4M x 8/2M x 16] SINGLE VOLTAGE 3V
ONLY FLASH MEMORY
GENERAL FEATURES
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• 4,194,304 x 8 / 2,097,152 x 16 switchable
• Sector structure
- 8KB (4KW) x 8 and 64KB(32KW) x 63
• Latch-up protected to 250mA from -1V to VCC + 1V
• Low VCC write inhibit is equal to or less than 1.5V
• Compatible with JEDEC standard
- Pin-out and software compatible to single power supply Flash
- Data# polling & Toggle bits provide detection of program and erase operation completion
HARDWARE FEATURES
• Ready/Busy (RY/BY#) Output
- Provides a hardware method of detecting program
and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal
state machine to read mode
• WP#/ACC input
- Write protect (WP#) function allows protection of all
sectors, regardless of sector protect status
- ACC (high voltage) accelerates programming time
for higher throughput during system
PERFORMANCE
• High Performance
- Fast access time: 70R/90ns
- Page read time: 25ns
- Sector erase time: 0.5s (typ.)
- Effective write buffer word programming time: 22us
- 4 word/8 byte page read buffer
- 16 word/ 32 byte write buffer: reduces programming
time for multiple-word/byte updates
• Low Power Consumption
- Active read current: 18mA(typ.)
- Active write current: 50mA(typ.)
- Standby current: 20uA(typ.)
• Minimum 100,000 erase/program cycle
• 20-years data retention
SECURITY
• Sector Protection/Chip Unprotect
- Provides sector group protect function to prevent program or erase operation in the protected sector group
- Provides chip unprotect function to allow code
changes
• Sector Permanent Lock
- A unique lock bit feature allows the content to be
permanently locked
(Please contact Macronix sales for specific information regarding this permanent lock feature)
• Secured Silicon Sector
- Provides a 128-word OTP area for permanent, secure identification
- Can be programmed and locked at factory or by customer
SOFTWARE FEATURES
• Support Common Flash Interface (CFI)
- Flash device parameters stored on the device and
provide the host system to access
• Program Suspend/Resume
- Suspend program operation to read other sectors
• Erase Suspend/Erase Resume
- Suspends sector erase operation to read data from or
program data to another sector which is not being
erased
• Status Reply
PACKAGE
• 48-pin TSOP (for MX29LA320MT/B)
• 48-ball CSP (for MX29LA320MT/B)
• 56-pin TSOP (for MX29LA321MT/B)
• 64-ball CSP (for MX29LA321MT/B)
• All Pb-free devices are RoHS Compliant
GENERAL DESCRIPTION
to be reprogrammed and erased in system or in standard
EPROM programmers.
The MX29LA32xMT/B is a 32-mega bit Flash memory
organized as 4M bytes of 8 bits or 2M words of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29LA32xMT/B is packaged in 48-pin TSOP, 48ball CSP, 56-pin TSOP and 64-ball CSP. It is designed
The standard MX29LA32xMT/B offers access time as
fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LA32xMT/B has separate chip enable
(CE#) and output enable (OE#) controls.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
1
MX29LA32xMT/B
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LA32xMT/B uses a command register to manage
this functionality.
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and program
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and programming operations produces reliable
cycling. The MX29LA32xMT/B uses a 2.7V to 3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
AUTOMATIC SECTOR ERASE
The MX29LA32xMT/B is sector(s) erasable using
MXIC's Auto Sector Erase algorithm. Sector erase modes
allow sectors of the array to be erased in one erase cycle.
The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are controlled internally within the device.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the
status of the programming operation.
AUTOMATIC PROGRAMMING
The MX29LA32xMT/B is byte/word/page programmable
using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify
the data programmed. The typical chip programming time
at room temperature of the MX29LA32xMT/B is less than
31.5 seconds.
Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE# .
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the user
to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times
the programming pulse width, provides the program verification, and counts the number of sequences. A status
bit similar to DATA# polling and a status bit toggling between consecutive read cycles, provide feedback to the
user as to the status of the programming operation.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29LA32xMT/B
electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command register to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 50 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 32 seconds. The Automatic Erase algorithm
P/N:PM1144
REV. 1.3, NOV. 15, 2005
2
MX29LA32xMT/B
PIN CONFIGURATION
48 TSOP (for MX29LA320MT/B)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
NC
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX29LA320MT/B
48 Ball CSP (Top View, Ball Down) (for MX29LA320MT/B)
8.0 mm
6
A13
A12
A14
A15
A16
BYTE#
Q15/
A-1
GND
5
A9
A8
A10
A11
Q7
Q14
Q13
Q6
4
WE#
RESET#
NC
A19
Q5
Q12
VCC
Q4
6.0 mm
3
RY/
BY#
WP#/
ACC
A18
A20
Q2
Q10
Q11
Q3
2
A7
A17
A6
A5
Q0
Q8
Q9
Q1
1
A3
A4
A2
A1
A0
CE#
OE#
GND
A
B
C
D
E
F
G
H
P/N:PM1144
REV. 1.3, NOV. 15, 2005
3
MX29LA32xMT/B
56 TSOP (for MX29LA321MT/B)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NC
CE1
A20
A21
A18
A17
A16
A15
VDD
A14
A13
A12
A11
CE0
WP#/ACC
RESET#
A10
A9
A8
A7
VSS
A6
A5
A4
A3
A2
A1
A0
NC
WE#
OE#
RY/BY#
Q15
Q7
Q14
Q6
VSS
S13
Q5
Q12
Q4
VCC
GND
Q11
Q3
Q10
Q2
VDD
Q9
Q1
Q8
Q0
A-1
BYTE#
NC
CE2
64 CSP (for MX29LA321MT/B)
1
2
3
4
5
6
7
8
A
A0
A5
A7
WP#/
ACC
A12
VCC
A17
NC
B
A1
GND
A8
CE0
A13
NC
A18
CE1
C
A2
A6
A9
A11
A14
NC
A19
A20
D
A3
A4
A10
RESET#
NC
NC
A15
A16
E
Q8
Q1
Q9
Q3
Q4
NC
Q15
RY/
BY#
F
BYTE#
Q0
Q10
Q11
Q12
NC
NC
OE#
G
NC
A-1
Q2
VCC
Q5
Q6
Q14
WE#
H
CE2
NC
VDD
GND
Q13
GND
Q7
NC
P/N:PM1144
REV. 1.3, NOV. 15, 2005
4
MX29LA32xMT/B
LOGIC SYMBOL
PIN DESCRIPTION
SYMBOL
PIN NAME
A0~A20
Address Input
Q0~Q14
Data Inputs/Outputs
Q15/A-1
Q15(Word Mode)/LSB addr(Byte Mode)
CE#
Chip Enable Input
WE#
Write Enable Input
OE#
Output Enable Input
RESET#
Hardware Reset Pin, Active Low
21
A0-A20
CE#
OE#
WP#/ACC Hardware Write Protect/Programming
WE#
Acceleration input
RY/BY#
16 or 8
Q0-Q15
(A-1)
RESET#
Read/Busy Output
RY/BY#
BYTE#
Selects 8 bit or 16 bit mode
WP#/ACC
VCC
+3.0V single power supply
BYTE#
GND
Device Ground
NC
Pin Not Connected Internally
Chip Enable Truth Table (for MX29LA321MT/B
Only)
CE2
CE1
CE0
DEVICE
VIL
VIL
VIL
Enabled
VIL
VIL
VIH
Disabled
VIL
VIH
VIL
Disabled
VIL
VIH
VIH
Disabled
VIH
VIL
VIL
Enabled
VIH
VIL
VIH
Enabled
VIH
VIH
VIL
Enabled
VIH
VIH
VIH
Disabled
Note: For Single-chip applications, CE2 and CE1 can be
strapped to GND.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
5
MX29LA32xMT/B
BLOCK DIAGRAM
CE#
OE#
WE#
WP#
BYTE#
RESET#
WRITE
CONTROL
STATE
INPUT
LOGIC
HIGH VOLTAGE
MACHINE
(WSM)
LATCH
BUFFER
STATE
FLASH
REGISTER
ARRAY
ARRAY
Y-DECODER
AND
X-DECODER
ADDRESS
A0-A20
PROGRAM/ERASE
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15
I/O BUFFER
P/N:PM1144
REV. 1.3, NOV. 15, 2005
6
MX29LA32xMT/B
Table 1.a: MX29LA32xMT SECTOR GROUP ARCHITECTURE
Sector
Group
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
10
10
10
10
Sector Sector Address
A20-A12
SA0
000000xxx
SA1
000001xxx
SA2
000010xxx
SA3
000011xxx
SA4
000100xxx
SA5
000101xxx
SA6
000110xxx
SA7
000111xxx
SA8
001000xxx
SA9
001001xxx
SA10
001010xxx
SA11
001011xxx
SA12
001100xxx
SA13
001101xxx
SA14
001110xxx
SA15
001111xxx
SA16
010000xxx
SA17
010001xxx
SA18
010010xxx
SA19
010011xxx
SA20
010100xxx
SA21
010101xxx
SA22
010110xxx
SA23
010111xxx
SA24
011000xxx
SA25
011001xxx
SA26
011010xxx
SA27
011011xxx
SA28
011100xxx
SA29
011101xxx
SA30
011110xxx
SA31
011111xxx
SA32
100000xxx
SA33
100001xxx
SA34
100010xxx
SA35
100011xxx
SA36
100100xxx
SA37
100101xxx
SA38
100110xxx
SA39
100111xxx
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
P/N:PM1144
(x8)
Address Range
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
(x16)
Address Range
000000h-07FFFh
008000h-0FFFFh
010000h-17FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
REV. 1.3, NOV. 15, 2005
7
MX29LA32xMT/B
Sector
Group
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
17
18
19
20
21
22
23
24
Sector Sector Address
A20-A12
SA40
101000xxx
SA41
101001xxx
SA42
101010xxx
SA43
101011xxx
SA44
101100xxx
SA45
101101xxx
SA46
101110xxx
SA47
101111xxx
SA48
110000xxx
SA49
110001xxx
SA50
110010xxx
SA51
110011xxx
SA52
110100xxx
SA53
110101xxx
SA54
110110xxx
SA55
110111xxx
SA56
111000xxx
SA57
111001xxx
SA58
111010xxx
SA59
111011xxx
SA60
111100xxx
SA61
111101xxx
SA62
111110xxx
SA63
111111000
SA64
111111001
SA65
111111010
SA66
111111011
SA67
111111100
SA68
111111101
SA69
111111110
SA70
111111111
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
(x8)
Address Range
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3F1FFFh
3F2000h-3F3FFFh
3F4000h-3F5FFFh
3F6000h-3F7FFFh
3F8000h-3F9FFFh
3FA000h-3FBFFFh
3FC000h-3FDFFFh
3FE000h-3FFFFFh
(x16)
Address Range
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-147FFFh
168000h-14FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1F8FFFh
1F9000h-1F9FFFh
1FA000h-1FAFFFh
1FB000h-1FBFFFh
1FC000h-1FCFFFh
1FD000h-1FDFFFh
1FE000h-1FEFFFh
1FF000h-1FFFFFh
Note:The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH)
P/N:PM1144
REV. 1.3, NOV. 15, 2005
8
MX29LA32xMT/B
Table 1.b: MX29LA32xMB SECTOR GROUP ARCHITECTURE
Sector
Group
1
2
3
4
5
6
7
8
9
9
9
10
10
10
10
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
16
Sector Sector Address
A20-A12
SA0
000000000
SA1
000000001
SA2
000000010
SA3
000000011
SA4
000000100
SA5
000000101
SA6
000000110
SA7
000000111
SA8
000001xxx
SA9
000010xxx
SA10
000011xxx
SA11
000100xxx
SA12
000101xxx
SA13
000110xxx
SA14
000111xxx
SA15
001000xxx
SA16
001001xxx
SA17
001010xxx
SA18
001011xxx
SA19
001100xxx
SA20
001101xxx
SA21
001110xxx
SA22
001111xxx
SA23
010000xxx
SA24
010001xxx
SA25
010010xxx
SA26
010011xxx
SA27
010100xxx
SA28
010101xxx
SA29
010110xxx
SA30
010111xxx
SA31
011000xxx
SA32
011001xxx
SA33
011010xxx
SA34
011011xxx
SA35
011100xxx
SA36
011101xxx
SA37
011110xxx
SA38
011111xxx
Sector Size
(Kbytes/Kwords)
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
P/N:PM1144
(x8)
Address Range
000000h-001FFFh
002000h-003FFFh
004000h-005FFFh
006000h-007FFFh
008000h-009FFFh
00A000h-00BFFFh
00C000h-00DFFFh
00E000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
(x16)
Address Range
000000h-000FFFh
001000h-001FFFh
002000h-002FFFh
003000h-003FFFh
004000h-004FFFh
005000h-005FFFh
006000h-006FFFh
007000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
REV. 1.3, NOV. 15, 2005
9
MX29LA32xMT/B
Sector
Group
17
17
17
17
18
18
18
18
19
19
19
19
20
20
20
20
21
21
21
21
22
22
22
22
23
23
23
23
24
24
24
24
Sector Sector Address
A20-A12
SA39
100000xxx
SA40
100001xxx
SA41
100010xxx
SA42
100011xxx
SA43
100100xxx
SA44
100101xxx
SA45
100110xxx
SA46
100111xxx
SA47
101000xxx
SA48
101001xxx
SA49
101010xxx
SA50
101011xxx
SA51
101100xxx
SA52
101101xxx
SA53
101110xxx
SA54
101111xxx
SA55
110000xxx
SA56
110001xxx
SA57
110010xxx
SA58
110011xxx
SA59
110100xxx
SA60
110101xxx
SA61
110110xxx
SA62
110111xxx
SA63
111000xxx
SA64
111001xxx
SA65
111010xxx
SA66
111011xxx
SA67
111100xxx
SA68
111101xxx
SA69
111110xxx
SA70
111111xxx
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
(x8)
Address Range
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
(x16)
Address Range
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
Note:The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH)
P/N:PM1144
REV. 1.3, NOV. 15, 2005
10
MX29LA32xMT/B
Table 1. BUS OPERATION (1)
Q8~Q15
Operation
CE# OE# WE#
RE-
WP#
ACC
Address
Q0~Q7 BYTE#
SET#
Read
L
L
H
H
X
X
AIN
DOUT
BYTE#
=VIH
=VIL
DOUT
Q8-Q14=
High Z
Q15=A-1
Write (Program/Erase)
L
H
L
H
(Note 3)
X
AIN
(Note 4) (Note 4) Q8-Q14=
High Z
Q15=A-1
Accelerated Program
L
H
L
H
(Note 3)
VHH
AIN
(Note 4) (Note 4) Q8-Q14=
High Z
Q15=A-1
Standby
VCC±
X
X
0.3V
VCC±
X
H
X
High-Z
High-Z
High-Z
0.3V
Output Disable
L
H
H
H
X
X
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
X
X
High-Z
High-Z
High-Z
Sector Group Protect
L
H
L
VID
H
X
X
X
X
X
(Note 2)
Sector Addresses, (Note 4)
A6=L,A3=L, A2=L,
A1=H,A0=L
Chip unprotect
L
H
L
VID
H
X
(Note 2)
Sector Addresses, (Note 4)
A6=H, A3=L, A2=L,
A1=H, A0=L
Legend:
L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0±0.5V, VHH=12.0±0.5V, X=Don't Care, AIN=Address IN, DIN=Data IN,
DOUT=Data OUT
Notes:
1. Addresses are Amax:A0 in word mode; Amax:A-1 in byte mode. Sector address are Amax:A15 in both modes.
2. The sector group protect and chip unprotect functions may also be implemented via programming equipment. See
the "Sector Group Protection and Chip Unprotect" section.
3. If WP#=VIL, all the sectors remain protected. If WP#=VIH, all sector's protection depends on whether they were last
protected or unprotect using the method described in "Sector/ Sector Block Protection and Unprotect".
4. DIN or DOUT as required by command sequence, Data# polling or sector protect algorithm (see Figure 15).
P/N:PM1144
REV. 1.3, NOV. 15, 2005
11
MX29LA32xMT/B
Table 2. AUTOSELECT CODES (High Voltage Method)
A20 A14
Description
CE# OE# WE# to
to
A8
A9
A15 A10
Manufacturer ID
L
L
H
X
X
to
A6
A7
VID
X
L
A5
A3
to
to
A1 A0 BYTE# BYTE#
A4
A2
=VIH
=VIL
X
L
L
L
00
X
C2h
L
L
H
22
X
7Eh
H
H
L
22
X
1Ah
H
H
H
22
X
00(bottom boot)
Device ID
Cycle 1
Cycle 2
L
L
H
X
X
VID
X
L
X
Cycle 3
Q8 to Q15
Q7 to Q0
01h(top boot)
Sector Protection
L
L
H
SA
X
VID
X
L
X
L
H
L
X
X
Verification
01h (protected),
00h (unprotected)
Secured Silicon
Sector Indicator
Bit (Q7), WP#
98h
L
L
H
X
X
VID
X
L
X
L
H
H
X
X
(factory locked),
protects top two
18h
address sector
(not factory locked)
Secured Silicon
Sector
88h
Indicator Bit (Q7),
WP# protects
(factory locked),
L
L
H
X
X
VID
X
L
X
L
H
H
X
bottom two
X
08h
address sector
(not factory locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
12
MX29LA32xMT/B
consists of the address bits required to uniquely select a
sector. The "Writing specific address and data commands
or sequences into the command register initiates device
operations. Table 1 defines the valid register command
sequences. Writing incorrect address and data values or
writing them in the improper sequence resets the device
to reading array data. Section has details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.
REQUIREMENTS FOR READING ARRAY
DATA
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid address on
the device address inputs produce valid data on the device data outputs. The device remains enabled for read
access until the command register contents are altered.
After the system writes the Automatic Select command
sequence, the device enters the Automatic Select mode.
The system can then read Automatic Select codes from
the internal register (which is separate from the memory
array) on Q7-Q0. Standard read cycle timings apply in
this mode. Refer to the Automatic Select Mode and Automatic Select Command Sequence section for more
information.
PAGE MODE READ
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC
Characteristics" section contains timing specification
table and timing diagrams for write operations.
The MX29LA32xMT/B offers "fast page mode read" function. This mode provides faster read access speed for
random locations within a page. The page size of the
device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A0~A1(Word Mode)/A1~A1(Byte Mode) This is an asynchronous operation; the
microprocessor supplies the specific word location.
WRITE BUFFER
Write Buffer Programming allows the system to write a
maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time
than the standard programming algorithms. See "Write
Buffer" for more information.
The system performance could be enhanced by initiating
1 normal read and 3 fast page read (for word mode A0A1) or 7 fast page read (for byte mode A-1~A1). When
CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode
accesses are obtained by keeping the "read-page addresses" constant and changing the "intra-read page"
addresses.
WRITING COMMANDS/COMMAND
QUENCES
ACCELERATED PROGRAM OPERATION
The device offers accelerated program operations through
the ACC function. This is one of two functions provided
by the ACC pin. This function is primarily intended to
allow faster manufacturing throughput at the factory.
SE-
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors, and
uses the higher voltage on the pin to reduce the time
required for program operations. The system would use
a two-cycle program command sequence as required by
the Unlock Bypass mode. Removing VHH from the ACC
pin must not be at VHH for operations other than accelerated programming, or device damage may result.
To program data to the device or erase sectors of memory,
the system must drive WE# and CE# to VIL, and OE# to
VIH.
An erase operation can erase one sector, multiple sectors, or the entire device. Table indicates the address
space that each sector occupies. A "sector address"
P/N:PM1144
REV. 1.3, NOV. 15, 2005
13
MX29LA32xMT/B
but not within VSS±0.3V, the standby current will be
greater.
STANDBY MODE
When using both pins of CE# and RESET#, the device
enter CMOS Standby with both pins held at VCC ± 0.3V.
If CE# and RESET# are held at VIH, but not within the
range of VCC ± 0.3V, the device will still be in the standby
mode, but the standby current will be larger. During Auto
Algorithm operation, VCC active current (ICC2) is required
even CE# = "H" until the operation is completed. The
device can be read with standard access time (tCE) from
either of these standby modes, before it is ready to read
data.
The RESET# pin may be tied to system reset circuitry.
A system reset would that also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase
operation, the RY/BY# pin remains a "0" (busy) until the
internal reset operation is complete, which requires a time
of tREADY (during Embedded Algorithms). The system
can thus monitor RY/BY# to determine whether the reset
operation is complete. If RESET# is asserted when a
program or erase operation is completed within a time of
tREADY (not during Embedded Algorithms). The system
can read data tRH after the RESET# pin returns to VIH.
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this
mode when address remain stable for tACC+30ns. The
automatic sleep mode is independent of the CE#, WE#,
and OE# control signals. Standard address access timings provide new data when addresses are changed. While
in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table
represents the automatic sleep mode current specification.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 3 for the timing diagram.
SECTOR GROUP PROTECT OPERATION
The MX29LA32xMT/B features hardware sector group
protection. This feature will disable both program and
erase operations for these sector group protected. In this
device, a sector group consists of four adjacent sectors
which are protected or unprotected at the same time. To
activate this mode, the programming equipment must force
VID on address pin A9 and control pin OE#, (suggest
VID = 12V) A6 = VIL and CE# = VIL. (see Table 2) Programming of the protection circuitry begins on the falling
edge of the WE# pulse and is terminated on the rising
edge. Please refer to sector group protect algorithm and
waveform.
OUTPUT DISABLE
With the OE# input at a logic high level (VIH), output
from the devices are disabled. This will cause the output
pins to be in a high impedance state.
RESET# OPERATION
MX29LA32xMT/B also provides another method. Which
requires VID on the RESET# only. This method can be
implemented either in-system or via programming equipment. This method uses standard microprocessor bus
cycle timing.
The RESET# pin provides a hardware method of resetting
the device to reading array data. When the RESET# pin
is driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write
commands for the duration of the RESET# pulse. The
device also resets the internal state machine to reading
array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another
command sequence, to ensure data integrity
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
(with CE# and OE# at VIL and WE# at VIH). When A1=1,
it will produce a logical "1" code at device output Q0 for a
protected sector. Otherwise the device will produce 00H
for the unprotected sector. In this mode, the addresses,
except for A1, are don't care. Address locations with A1
= VIL are reserved to read manufacturer and device codes.
(Read Silicon ID)
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at VSS±0.3V, the device draws
CMOS standby current (ICC4). If RESET# is held at VIL
P/N:PM1144
REV. 1.3, NOV. 15, 2005
14
MX29LA32xMT/B
or unprotect using the method described in "Sector/Sector Group Protection and Chip Unprotect".
It is also possible to determine if the group is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
Note that the WP# pin must not be left floating or unconnected; inconsistent behavior of the device may result.
CHIP UNPROTECT OPERATION
SILICON ID READ OPERATION
The MX29LA32xMT/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in
the code. It is recommended to protect all sectors before
activating chip unprotect mode.
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the
device resides in the target system. PROM programmers typically access signature codes by raising A9 to
a high voltage. However, multiplexing high voltage onto
address lines is not generally desired system design practice.
To activate this mode, the programming equipment must
force VID on control pin OE# and address pin A9. The
CE# pins must be set at VIL. Pins A6 must be set to
VIH. (see Table 2) Refer to chip unprotect algorithm and
waveform for the chip unprotect algorithm. The unprotect
mechanism begins on the falling edge of the WE# pulse
and is terminated on the rising edge.
MX29LA32xMT/B provides hardware method to access
the silicon ID read operation. Which method requires VID
on A9 pin, VIL on CE#, OE#, A6, and A1 pins. Which
apply VIL on A0 pin, the device will output MXIC's manufacture code.. Which apply VIH on A0 pin, the device will
output MX29LA32xMT/B device code.
MX29LA32xMT/B also provides another method. Which
requires VID on the RESET# only. This method can be
implemented either in-system or via programming equipment. This method uses standard microprocessor bus
cycle timing.
VERIFY SECTOR GROUP PROTECT STATUS
OPERATION
It is also possible to determine if the chip is unprotect in
the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs (Q0-Q7) for an unprotect sector. It is
noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
MX29LA32xMT/B provides hardware method for sector
group protect status verify. Which method requires VID
on A9 pin, VIH on WE# and A1 pins, VIL on CE#, OE#,
A6, and A0 pins, and sector address on A16 to A20 pins.
Which the identified sector is protected, the device will
output 01H. Which the identified sector is not protect, the
device will output 00H.
WRITE PROTECT (WP#)
The write protect function provides a hardware method
to protect all sectors without using VID.
DATA PROTECTION
The MX29LA32xMT/B is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during power
transition. During power up the device automatically resets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific command sequences. The device also
incorporates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down transition or system noise.
If the system asserts VIL on the WP# pin, the device
disables program and erase functions in all sectors independently of whether those sectors were protected or
unprotect using the method described in Sector "Sector
Group Protection and Chip Unprotect".
If the system asserts VIH on the WP# pin, the device
reverts to whether sectors were last set to be protected
or unprotect. That is, sector protection or unprotection for
the sectors depends on whether they were last protected
P/N:PM1144
REV. 1.3, NOV. 15, 2005
15
MX29LA32xMT/B
SECURED SILICON SECTOR
FACTORY LOCKED:Secured Silicon Sector
Programmed and Protected At the Factory
The MX29LA32xMT/B features a OTP memory region
where the system may access through a command sequence to create a permanent part identification as so
called Electronic Serial Number (ESN) in the device.
Once this region is programmed, any further modification on the region is impossible. The secured silicon sector is a 128 words in length, and uses a Secured Silicon
Sector Indicator Bit (Q7) to indicate whether or not the
Secured Silicon Sector is locked when shipped from the
factory. This bit is permanently set at the factory and
cannot be changed, which prevent duplication of a factory locked part. This ensures the security of the ESN
once the product is shipped to the field.
In device with an ESN, the Secured Silicon Sector is
protected when the device is shipped from the factory.
The Secured Silicon Sector cannot be modified in any
way. A factory locked device has an 8-word random ESN
at address 000000h-000007h.
CUSTOMER LOCKABLE:Secured Silicon
Sector NOT Programmed or Protected At the
Factory
As an alternative to the factory-locked version, the device
may be ordered such that the customer may program
and protect the 128-word Secured Silicon Sector.
Programming and protecting the Secured Silicon Sector
must be used with caution since, once protected, there
is no procedure available for unprotected the Secured
Silicon Sector area and none of the bits in the Secured
Silicon Sector memory space can be modified in any
way.
The MX29LA32xMT/B offers the device with Secured
Silicon Sector either factory locked or customer lockable. The factory-locked version is always protected when
shipped from the factory , and has the Secured Silicon
Sector Indicator Bit permanently set to a "1". The customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to utilize that
sector in any form they prefer. The customer-lockable
version has the secured sector Indicator Bit permanently
set to a "0". Therefore, the Secured Silicon Sector Indicator Bit prevents customer, lockable device from being
used to replace devices that are factory locked.
The Secured Silicon Sector area can be protected using
one of the following procedures:
Write the three-cycle Enter Secured Silicon Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 15, except
that RESET# may be at either VIH or VID. This allows insystem protection of the Secured Silicon Sector without
raising any device pin to a high voltage. Note that method
is only applicable to the Secured Silicon Sector.
The system access the Secured Silicon Sector through
a command sequence (refer to "Enter Secured Silicon/
Exit Secured Silicon Sector command Sequence). After
the system has written the Enter Secured Silicon Sector
command sequence, it may read the Secured Silicon
Sector by using the address normally occupied by the
first sector SA0. Once entry the Secured Silicon Sector
the operation of boot sectors is disabled but the operation
of main sectors is as normally. This mode of operation
continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed
from the device. On power-up, or following a hardware
reset, the device reverts to sending command to sector
SA0.
Secured Silicon
ESN factory
Customer
Sector address
locked
lockable
Write the three-cycle Enter Secured Silicon Sector Region
command sequence, and then alternate method of sector
protection described in the :Sector Group Protection and
Unprotect" section.
Once the Secured Silicon Sector is programmed, locked
and verified, the system must write the Exit Secured
Silicon Sector Region command sequence to return to
reading and writing the remainder of the array.
LOW VCC WRITE INHIBIT
range
000000h-000007h
ESN
Determined by
000008h-00007Fh
Unavailable
Customer
When VCC is less than VLKO the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and all
P/N:PM1144
REV. 1.3, NOV. 15, 2005
16
MX29LA32xMT/B
internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is
greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional write
when VCC is greater than VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns (typical) on CE# or WE#
will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE# = VIL,
CE# = VIH or WE# = VIH. To initiate a write cycle CE#
and WE# must be a logical zero while OE# is a logical
one.
POWER-UP SEQUENCE
The MX29LA32xMT/B powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.
POWER-UP WRITE INHIBIT
If WE#=CE#=VIL and OE#=VIH during power up, the
device does not accept commands on the rising edge of
WE#. The internal state machine is automatically reset
to the read mode on power-up.
POWER SUPPLY DE COUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected between its VCC and GND.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
17
MX29LA32xMT/B
Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress. Either of the two
reset command sequences will reset the device (when
applicable).
SOFTWARE COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them
in the improper sequence will reset the device to the
read mode. Table 3 defines the valid register command
sequences. Note that the Erase Suspend (B0H) and
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data are latched on
rising edge of WE# or CE#, whichever happens first.
TABLE 3. MX29LA32xMT/B COMMAND DEFINITIONS
First Bus
Command
Bus
Cycle
Second Bus Third Bus
Cycle
Cycles Addr Data Addr
Read (Note 5)
1
RA
RD
Reset (Note 6)
1
XXX
F0
Fourth Bus
Cycle
Cycle
Data Addr Data Addr
Data
Fifth Bus
Sixth Bus
Cycle
Cycle
Addr Data Addr Data
Automatic Select (Note 7)
Manufacturer ID
Device ID
Word
4
555
AA
2AA
55
555
90
X00
C2H
Byte
4
AAA
AA
555
55
AAA 90
X00
C2H
Word
4
555
AA
2AA
55
555
X01
227EH X0E 221A X0F 2200/
90
(Note 8)
2201
Byte
4
AAA
AA
555
55
AAA 90
X02
7E
Secured Sector Fact-
Word
4
555
AA
2AA
55
555
90
X03
see
Note 9
ory Protect (Note 9)
Byte
4
AAA
AA
555
55
AAA 90
X06
Sector Group Protect
Word
4
555
AA
2AA
55
555
90
(SA)X02 XX00/
Verify (Note 10)
(SA)X04 XX01
Byte
4
AAA
AA
555
55
AAA 90
Enter Secured Silicon
Word
3
555
AA
2AA
55
555
Sector
Byte
3
AAA
AA
555
55
AAA 88
Exit Secured Silicon
Word
4
555
AA
2AA
55
555
90
XXX
00
Sector
Byte
4
AAA
AA
555
55
AAA 90
XXX
00
Program
Word
4
555
AA
2AA
55
555
PA
PD
Write to Buffer (Note 11)
Program Buffer to Flash
X1E 00/01
88
A0
Byte
4
AAA
AA
555
55
AAA A0
PA
PD
Word
6
555
AA
2AA
55
SA
25
SA
WC
PA
PD
WBL PD
Byte
6
AAA
AA
555
55
SA
25
SA
BC
PA
PD
WBL PD
Word
1
SA
29
2AA
55
555
F0
555
AA
2AA 55
555 10
Byte
1
SA
29
Write to Buffer Abort
Word
3
555
AA
Reset (Note 12)
Byte
3
AAA
AA
555
55
AAA F0
Chip Erase
Word
6
555
AA
2AA
55
555
Sector Erase
X1C 1A
80
Byte
6
AAA
AA
555
55
AAA 80
AAA
AA
555 55
AAA 10
Word
6
555
AA
2AA
55
555
80
555
AA
2AA 55
SA
30
555
55
AAA 80
AAA
AA
555 55
SA
30
Byte
6
AAA
AA
Program/Erase Suspend (Note 13)
1
XXX
B0
Program/Erase Resume (Note 14)
1
XXX
30
CFI Query (Note 15)
Word
1
55
98
Byte
1
AA
98
P/N:PM1144
REV. 1.3, NOV. 15, 2005
18
MX29LA32xMT/B
Legend:
X=Don't care
RA=Address of the memory location to be read.
RD=Data read from location RA during read operation.
PA=Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# or
CE# pulse, whichever happen later.
DDI=Data of device identifier
C2H for manufacture code
PD=Data to be programmed at location PA. Data is
latched on the rising edge of WE# or CE# pulse.
SA=Address of the sector to be erase or verified (in
autoselect mode).
Address bits A20-A12 uniquely select any sector.
WBL=Write Buffer Location. Address must be within the
same write buffer page as PA.
WC=Word Count. Number of write buffer locations to load
minus 1.
BC=Byte Count. Number of write buffer locations to load
minus 1.
Notes:
1. See Table 1 for descriptions of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or automatic select data, all bus cycles are write operation.
4. Address bits are don't care for unlock and command cycles, except when PA or SA is required.
5. No unlock or command cycles required when device is in read mode.
6. The Reset command is required to return to the read mode when the device is in the automatic select mode or if
Q5 goes high.
7. The fourth cycle of the automatic select command sequence is a read cycle.
8. The device ID must be read in three cycles. The data is 01h for top boot and 00h for bottom boot.
9. If WP# protects the top two address sectors, the data is 98h for factory locked and 18h for not factory locked. If
WP# protects the bottom two address sectors, the data is 88h for factory locked and 08h for not factor locked.
10. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.
11. The total number of cycles in the command sequence is determined by the number of words written to the write
buffer. The maximum number of cycles in the command sequence is 21(Word Mode) / 37(Byte Mode).
12. Command sequence resets device for next command after aborted write-to-buffer operation.
13. The system may read and program functions in non-erasing sectors, or enter the automatic select mode, when in
the erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
14. The Erase Resume command is valid only during the Erase Suspend mode.
15. Command is valid when device is ready to read array data or when device is in automatic select mode.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
19
MX29LA32xMT/B
array data (also applies during Erase Suspend).
READING ARRAY DATA
The device is automatically set to reading array data
after device power-up. No commands are required to retrieve data. The device is also ready to read array data
after completing an Automatic Program or Automatic
Erase algorithm.
SILICON ID READ COMMAND SEQUENCE
The SILICON ID READ command sequence allows the
host system to access the manufacturer and devices
codes, and determine whether or not a sector is protected. Table 2 shows the address and data requirements.
This method is an alternative to that shown in Table 1,
which is intended for PROM programmers and requires
VID on address bit A9.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See Erase Suspend/Erase
Resume Commands for more information on this mode.
The system must issue the reset command to re-enable the device for reading array data if Q5 goes high, or
while in the automatic select mode. See the "Reset Command" section, next.
The SILICON ID READ command sequence is initiated
by writing two unlock cycles, followed by the SILICON
ID READ command. The device then enters the SILICON ID READ mode, and the system may read at any
address any number of times, without initiating another
command sequence. A read cycle at address XX00h
retrieves the manufacturer code. A read cycle at address
XX01h returns the device code. A read cycle containing
a sector address (SA) and the address 02h returns 01h if
that sector is protected, or 00h if it is unprotected. Refer
to Table for valid sector addresses.
RESET COMMAND
Writing the reset command to the device resets the device to reading array data. Address bits are don't care for
this command.
The system must write the reset command to exit the
automatic select mode and return to reading array data.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores
reset commands until the operation is complete.
BYTE/WORD PROGRAM COMMAND SEQUENCE
The reset command may be written between the sequence cycles in a program command sequence before
programming begins. This resets the device to reading
array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the
device ignores reset commands until the operation is
complete.
The command sequence requires four bus cycles, and
is initiated by writing two unlock write cycles, followed
by the program set-up command. The program address
and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required
to provide further controls or timings. The device automatically generates the program pulses and verifies the
programmed cell margin. Table 3 shows the address and
data requirements for the byte program command sequence.
The reset command may be written between the sequence cycles in an SILICON ID READ command sequence. Once in the SILICON ID READ mode, the reset
command must be written to return to reading array data
(also applies to SILICON ID READ during Erase Suspend).
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses
are no longer latched. The system can determine the
status of the program operation by using Q7, Q6, or RY/
BY#. See "Write Operation Status" for information on
these status bits.
If Q5 goes high during a program or erase operation,
writing the reset command returns the device to reading
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hard-
P/N:PM1144
REV. 1.3, NOV. 15, 2005
20
MX29LA32xMT/B
multiple times, the address/data pair counter will be
decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter decrements for each
data load operation, not for each unique write-buffer-address location. Note also that if an address location is
loaded more than once into the buffer, the final data loaded
for that address will be programmed.
ware reset immediately terminates the programming operation. The Byte/Word Program command sequence
should be reinitiated once the device has reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may halt the operation and set Q5 to "1", or cause the Data# Polling
algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still
"0". Only erase operations can convert a "0" to a "1".
Once the specified number of write buffer locations have
been loaded, the system must then write the Program
Buffer to Flash command at the sector address. Any
other address and data combination aborts the Write
Buffer Programming operation. The device then begins
programming. Data polling should be used while monitoring the last address location loaded into the write buffer.
Q7, Q6, Q5, and Q1 should be monitored to determine
the device status during Write Buffer Programming.
Write Buffer Programming
Write Buffer Programming allows the system write to a
maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time
than the standard programming algorithms. The Write
Buffer Programming command sequence is initiated by
first writing two unlock cycles. This is followed by a third
write cycle containing the Write Buffer Load command
written at the Sector Address in which programming will
occur. The fourth cycle writes the sector address and
the number of word locations, minus one, to be programmed. For example, if the system will program 6
unique address locations, then 05h should be written to
the device. This tells the device how many write buffer
addresses will be loaded with data and therefore when to
expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of
the write buffer or the operation will abort.
The write-buffer programming operation can be suspended
using the standard program suspend/resume commands.
Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next
command.
The Write Buffer Programming Sequence can be aborted
in the following ways:
• Load a value that is greater than the page buffer size
during the Number of Locations to Program step.
• Write to an address in a sector different than the one
specified during the Write-Buffer-Load command.
• Write an Address/Data pair to a different write-bufferpage than the one selected by the Starting Address
during the write buffer data loading stage of the operation.
• Write data other than the Confirm Command after the
specified number of data load cycles.
The fifth cycle writes the first address location and data
to be programmed. The write-buffer-page is selected by
address bits AMAX-4. All subsequent address/data pairs
must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into
the write buffer. Write buffer locations may be loaded in
any order.
The abort condition is indicated by Q1 = 1, Q7 = DATA#
(for the last address location loaded), Q6 = toggle, and
Q5=0. A Write-to-Buffer-Abort Reset command sequence
must be written to reset the device for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required when using WriteBuffer-Programming features in Unlock Bypass mode.
The write-buffer-page address must be the same for all
address/data pairs loaded into the write buffer. (This
means Write Buffer Programming cannot be performed
across multiple write-buffer pages. This also means that
Write Buffer Programming cannot be performed across
multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the
operation will abort.
Program Suspend/Program Resume Command
Sequence
The Program Suspend command allows the system to
interrupt a programming operation or a Write to Buffer
Note that if a Write Buffer address location is loaded
P/N:PM1144
REV. 1.3, NOV. 15, 2005
21
MX29LA32xMT/B
programming operation so that data can be read from any
non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 15us maximum
(5 us typical) and updates the status bits. Addresses are
not required when writing the Program Suspend command.
AUTOMATIC CHIP/SECTOR ERASE COMMAND
The device does not require the system to preprogram
prior to erase. The Automatic Erase algorithm automatically pre-program and verifies the entire memory for an
all zero data pattern prior to electrical erase. The system
is not required to provide any controls or timings during
these operations. Table 3 shows the address and data
requirements for the chip erase command sequence.
After the programming operation has been suspended,
the system can read array data from any non-suspended
sector. The Program Suspend command may also be
issued during a programming operation while an erase is
suspended. In this case, data may be read from any
addresses not in Erase Suspend or Program Suspend. If
a read is needed from the Secured Silicon Sector area
(One-time Program area), then user must use the proper
command sequences to enter and exit this region.
Any commands written to the chip during the Automatic
Erase algorithm are ignored. Note that a hardware reset
during the chip erase operation immediately terminates
the operation. The Chip Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
The system may also write the autoselect command
sequence when the device is in the Program Suspend
mode. The system can read as many autoselect codes
as required. When the device exits the autoselect mode,
the device reverts to the Program Suspend mode, and
is ready for another valid operation. See Autoselect Command Sequence for more information.
The system can determine the status of the erase operation by using Q7, Q6, Q2, or RY/BY#. See "Write Operation Status" for information on these status bits. When
the Automatic Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Figure 10 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC
Characteristics" for parameters, and to Figure 9 for timing diagrams.
After the Program Resume command is written, the device reverts to programming. The system can determine
the status of the program operation using the Q7 or Q6
status bits, just as in the standard program operation.
See Write Operation Status for more information.
SETUP AUTOMATIC CHIP/SECTOR ERASE
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H, or
the sector erase command 30H.
The MX29LA32xMT/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read
silicon ID command sequence into the command register. Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
22
MX29LA32xMT/B
device requires a maximum 20us to suspend the sector
erase operation. However, When the Erase Suspend command is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation. After this command has
been executed, the command register will initiate erase
suspend mode. The state machine will return to read
mode automatically after suspend is ready. At this time,
state machine only allows the command register to respond to the Erase Resume, program data to, or read
data from any sector not selected for erasure.
SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the device
to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic
Sector Erase command. Upon executing the Automatic
Sector Erase command, the device will automatically
program and verify the sector(s) memory for an all-zero
data pattern. The system is not required to provide any
control or timing during these operations.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend program operation is complete, the system can once again
read array data within non-suspended blocks.
ERASE RESUME
When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector erase
is a six-bus cycle operation. There are two "unlock" write
cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector
address is latched on the falling edge of WE# or CE#,
whichever happens later , while the command (data) is
latched on the rising edge of WE# or CE#, whichever
happens first. Sector addresses selected are loaded
into internal register on the sixth falling edge of WE# or
CE#, whichever happens later. Each successive sector
load cycle started by the falling edge of WE# or CE#,
whichever happens later must begin within 50us from
the rising edge of the preceding WE# or CE#, whichever
happens first. Otherwise, the loading period ends and
internal auto sector erase cycle starts. (Monitor Q3 to
determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command other
than Sector Erase(30H) or Erase Suspend(B0H) during
the time-out period resets the device to read mode.
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the chip has resumed erasing.
ERASE SUSPEND
This command only has meaning while the state machine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Sector Erase operation. When the Erase Suspend command is issued during the sector erase operation, the
P/N:PM1144
REV. 1.3, NOV. 15, 2005
23
MX29LA32xMT/B
The single cycle Query command is valid only when the
device is in the Read mode, including Erase Suspend,
Standby mode, and Read ID mode; however, it is ignored
otherwise.
QUERY COMMAND AND COMMON FLASH
INTERFACE (CFI) MODE
MX29LA32xMT/B is capable of operating in the CFI mode.
This mode all the host system to determine the manufacturer of the device such as operating parameters and
configuration. Two commands are required in CFI mode.
Query command of CFI mode is placed first, then the
Reset command exits CFI mode. These are described in
Table 4.
The Reset command exits from the CFI mode to the
Read mode, or Erase Suspend mode, or read ID mode.
The command is valid only when the device is in the CFI
mode.
Table 4-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description
Query-unique ASCII string "QRY"
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code (none)
Address for secondary algorithm extended query table (none)
Address h Address h
(x16)
(x8)
10
20
11
22
12
24
13
26
14
28
15
2A
16
2C
17
2E
18
30
19
32
1A
34
Data h
Address h Address h
(x16)
(x8)
1B
36
1C
38
1D
3A
1E
3C
1F
3E
20
40
21
42
22
44
23
46
24
48
25
4A
26
4C
Data h
0051
0052
0059
0002
0000
0040
0000
0000
0000
0000
0000
Table 4-2. CFI Mode: System Interface Data Values
Description
VCC supply, minimum (2.7V)
VCC supply, maximum (3.6V)
VPP supply, minimum (none)
VPP supply, maximum (none)
Typical timeout for single word/byte write (2N us)
Typical timeout for maximum size buffer write (2N us)
Typical timeout for individual block erase (2N ms)
Typical timeout for full chip erase (2N ms)
Maximum timeout for single word/byte write times (2N X Typ)
Maximum timeout for maximum size buffer write times (2N X Typ)
Maximum timeout for individual block erase times (2N X Typ)
Maximum timeout for full chip erase times (not supported)
P/N:PM1144
0027
0036
0000
0000
0007
0007
000A
0000
0001
0005
0004
0000
REV. 1.3, NOV. 15, 2005
24
MX29LA32xMT/B
Table 4-3. CFI Mode: Device Geometry Data Values
Description
Device size (2n bytes)
Flash device interface code (02=asynchronous x8/x16)
Maximum number of bytes in multi-byte write = 2n
Number of erase block regions
Erase block region 1 information
[2E,2D] = # of blocks in region -1
[30, 2F] = size in multiples of 256-bytes
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
P/N:PM1144
Address h Address h
(x16)
(x8)
27
4E
28
50
29
52
2A
54
2B
56
2C
58
2D
5A
2E
5C
2F
5E
30
60
31
62
32
64
33
66
34
68
35
6A
36
6C
37
6E
38
70
39
72
3A
74
3B
76
3C
78
Data h
0016
0002
0000
0005
0000
0002
0007
0000
0020
0000
003E
0000
0000
0001
0000
0000
0000
0000
0000
0000
0000
0000
REV. 1.3, NOV. 15, 2005
25
MX29LA32xMT/B
Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Description
Query-unique ASCII string "PRI"
Major version number, ASCII
Minor version number, ASCII
Address sensitive unlock (0=required, 1= not required)
Erase suspend (2= to read and write)
Sector protect (N= # of sectors/group)
Temporary sector unprotect (1=supported)
Sector protect/unprotect scheme
Simultaneous R/W operation (0=not supported)
Burst mode type (0=not supported)
Page mode type (1= 4 word page)
ACC (Acceleration) Supply Minimum
00h=Not Supported, D7-D4: Volt, D3-D0:100mV
ACC (Acceleration) Supply Maximum
00h=Not Supported, D7-D4: Volt, D3-D0:100mV
Top/Bottom Boot Sector Flag
02h=Bottom Boot Device, 03h=Top Boot Device
Program Suspend
00h=Not Supported, 01h=Supported
P/N:PM1144
Address h Address h
(x16)
(x8)
40
80
41
82
42
84
43
86
44
88
45
8A
46
8C
47
8E
48
90
49
92
4A
94
4B
96
4C
98
4D
9A
Data h
0050
0052
0049
0031
0033
0000
0002
0001
0000
0004
0000
0000
0001
00B5
4E
9C
00C5
4F
9E
50
A0
0002/
0003
0001
REV. 1.3, NOV. 15, 2005
26
MX29LA32xMT/B
WRITE OPERATION STATUS
The device provides several bits to determine the status
of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY#.
Table 5 and the following subsections describe the functions of these bits. Q7, RY/BY#, and Q6 each offer a
method for determining whether a program or erase operation is complete or in progress. These three bits are
discussed first.
Table 5. Write Operation Status
Status
Q7
Q6
Q5
Q3
Q2
Q1
RY/BY#
Byte/Word Program in Auto Program Algorithm
Q7#
Toggle
0
N/A
No
0
0
Toggle
Auto Erase Algorithm
Erase Suspend Read
Erase
(Erase Suspended Sector)
Suspended
Erase Suspend Read
Mode
(Non-Erase Suspended Sector)
Erase Suspend Program
0
Toggle
0
1
Toggle
N/A
0
1
No
0
N/A
Toggle
N/A
1
Toggle
Data
Data
Data
Data
Data
Data
1
Q7#
Toggle
0
N/A
N/A
N/A
0
Program-Suspended Read
Program
(Program-Suspended Sector)
Suspend
Program-Suspended Read
Invalid (not allowed)
1
Data
1
(Non-Program-Suspended Sector)
Write-to-Buffer
Busy
Q7#
Toggle
0
N/A
N/A
0
0
Abort
Q7#
Toggle
0
N/A
N/A
1
0
Notes:
1. Q5 switches to "1" when an Word/Byte Program, Erase, or Write-to-Buffer operation has exceeded the maximum
timing limits. Refer to the section on Q5 for more information.
2. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. Q1 switches to "1" when the device has aborted the write-to-buffer operation.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
27
MX29LA32xMT/B
happens first pulse in the command sequence (prior to
the program or erase operation), and during the sector
time-out.
Q7: Data# Polling
The Data# Polling bit, Q7, indicates to the host system
whether an Automatic Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data#
Polling is valid after the rising edge of the final WE# pulse
in the program or erase command sequence.
During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6
to toggle. The system may use either OE# or CE# to
control the read cycles. When the operation is complete,
Q6 stops toggling.
During the Automatic Program algorithm, the device outputs on Q7 the complement of the datum programmed
to Q7. This Q7 status also applies to programming during Erase Suspend. When the Automatic Program algorithm is complete, the device outputs the datum programmed to Q7. The system must provide the program
address to read valid status information on Q7. If a program address falls within a protected sector, Data# Polling on Q7 is active for approximately 1 us, then the device returns to reading array data.
After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles for
100us and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase suspended.
When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When
the device enters the Erase Suspend mode, Q6 stops
toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended.
Alternatively, the system can use Q7.
During the Automatic Erase algorithm, Data# Polling produces a "0" on Q7. When the Automatic Erase algorithm
is complete, or if the device enters the Erase Suspend
mode, Data# Polling produces a "1" on Q7. This is analogous to the complement/true datum output described for
the Automatic Program algorithm: the erase function
changes all the bits in a sector to "1" prior to this, the
device outputs the "complement," or "0". The system
must provide an address within any of the sectors selected for erasure to read valid status information on Q7.
If a program address falls within a protected sector, Q6
toggles for approximately 2us after the program command sequence is written, then returns to reading array
data.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on
Q7 is active for approximately 100 us, then the device
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algorithm is complete.
Table 5 shows the outputs for Toggle Bit I on Q6.
When the system detects Q7 has changed from the
complement to true data, it can read valid data at Q7-Q0
on the following read cycles. This is because Q7 may
change asynchronously with Q0-Q6 while Output Enable
(OE#) is asserted low.
Q2:Toggle Bit II
Q6:Toggle BIT I
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is,
the Automatic Erase algorithm is in process), or whether
that sector is erase-suspended. Toggle Bit II is valid
after the rising edge of the final WE# or CE#, whichever
happens first pulse in the command sequence.
Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE# or CE#, whichever
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE# or CE# to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com-
P/N:PM1144
REV. 1.3, NOV. 15, 2005
28
MX29LA32xMT/B
If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it
may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence. This
allows the system to continue to use the other active
sectors in the device.
parison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sectors and mode information. Refer to
Table 5 to compare outputs for Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read cycle.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or combination of sectors are bad.
If this time-out condition occurs during the byte/word programming operation, it specifies that the entire sector
containing that byte is bad and this sector may not be
reused, (other sectors are still functional and can be reused).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase operation. If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops toggling.
Once the Device has exceeded timing limits, the Q5 bit
will indicate a "1". Please note that this is not a device
failure condition since the device was incorrectly used.
The Q5 failure condition may appear if the system tries
to program a to a "1" location that is previously programmed to "0". Only an erase operation can change a
"0" back to a "1". Under this condition, the device halts
the operation, and when the operation has exceeded the
timing limits, Q5 produces a "1".
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively,
it may choose to perform other system tasks. In this
case, the system must start at the beginning of the algorithm when it returns to determine the status of the
operation.
Q3:Sector Erase Timer
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data# Polling
and Toggle Bit are valid after the initial sector erase command sequence.
Q5:Program/Erase Timing
Q5 will indicate if the program or erase time has exceeded
the specified limits (internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
indicates that the program or erase cycle was not successfully completed. Data# Polling and Toggle Bit are
the only operating functions of the device under this condition.
If Data# Polling or the Toggle Bit indicates the device
has been written with a valid erase command, Q3 may
be used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data# Polling or
P/N:PM1144
REV. 1.3, NOV. 15, 2005
29
MX29LA32xMT/B
Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command
has been accepted, the system software should check
the status of Q3 prior to and following each subsequent
sector erase command. If Q3 were high on the second
status check, the command may not have been accepted.
If the time between additional erase commands from the
system can be less than 50us, the system need not to
monitor Q3.
Q1: Write-to-Buffer Abort
Q1 indicates whether a Write-to-Buffer operation was
aborted. Under these conditions Q1 produces a "1". The
system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data.
See Write Buffer section for more details.
RY/BY#:READY/BUSY OUTPUT
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in progress
or complete. The RY/BY# status is valid after the rising
edge of the final WE# pulse in the command sequence.
Since RY/BY# is an open-drain output, several RY/BY#
pins can be tied together in parallel with a pull-up resistor
to VCC .
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device
is ready to read array data (including during the Erase
Suspend mode), or is in the standby mode.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
30
MX29LA32xMT/B
ABSOLUTE MAXIMUM RATINGS
OPERATING RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
A9, OE#, and
RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Commercial (C) Devices
Ambient Temperature (TA ). . . . . . . . . . . . . 0° C to +70° C
Industrial (I) Devices
Ambient Temperature (TA ). . . . . . . . . . . -40° C to +85° C
VCC Supply Voltages
VCC for full voltage range. . . . . . . . . . . . +2.7 V to 3.6 V
VCC for regulated voltage range. . . . . . . +3.0 V to 3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.
During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20ns.
2. Minimum DC input voltage on pins A9, OE#, and
RESET# is -0.5 V. During voltage transitions, A9, OE#,
and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at
a time. Duration of the short circuit should not be
greater than one second.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect
device reliability.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
31
MX29LA32xMT/B
DC CHARACTERISTICS
for 70R)
TA=-40°° C to 85°° C, VCC=2.7V~3.6V (TA=0°° C to 70°° C, VCC=3.0V~3.6V
Parameter Description
I LI
Input Load Current (Note 1)
I LIT
I LO
A9 Input Leakage Current
Output Leakage Current
ICC1 VCC Initial Read Current
(Notes 2,3)
ICC2 VCC Intra-Page Read
Current (Notes 2,3)
ICC3 VCC Active Write Current
(Notes 2,4,6)
ICC4 VCC Standby Current
(Note 2)
ICC5 VCC Reset Current
(Note 2)
ICC6 Automatic Sleep Mode
(Notes 2,5)
VIL
VIH
VHH
VID
Input Low Voltage
Input High Voltage
Voltage for ACC Program
Acceleration
Voltage for Autoselect
VOL Output Low Voltage
VOH1 Output High Voltage
VOH2
VLKO Low VCC Lock-Out Voltage
(Note 4)
Test Conditions
VIN = VSS to VCC ,
VCC = VCC max
VCC=VCC max; A9 = 12.5V
VOUT = VSS to VCC ,
VCC= VCC max
CE#= VIL,
10 MHz
OE# = VIH
5 MHz
1 MHz
CE#= VIL ,
10 MHz
OE# = VIH
40 MHz
CE#= VIL , OE# = VIH
WE#=VIL
CE#,RESET#=VCC±0.3V
WP#=VIH
RESET#=VSS±0.3V
WP#=VIH
VIL = V SS ± 0.3 V,
VIH = VCC ± 0.3 V,
WP#=VIH
Min.
Max.
±1.0
Unit
uA
35
±1.0
uA
uA
35
18
5
5
10
50
50
25
20
20
40
60
mA
mA
mA
mA
mA
mA
20
50
uA
20
50
uA
20
50
uA
VCC = 2.7V ~ 3.6V
-0.5
0.7xVCC
11.5
12.0
0.8
VCC+0.5
12.5
V
V
V
VCC = 3.0 V ± 10%
11.5
12.0
12.5
V
0.45
V
V
V
V
IOL= 4.0mA,VCC=VCC min
IOH=-2.0mA,VCC=VCC min 0.85VCC
IOH=-100uA,VCC=VCC min VCC-0.4
2.3
Typ.
2.5
Notes:
1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0uA.
2. Maximum ICC specifications are tested with VCC = VCC max.
3. The ICC current listed is typically is less than 2 mA/MHz, with OE# at VIH. Typical specifications are for VCC =
3.0V.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns.
6. Not 100% tested.
7. A9=12.5V when TA=0° C to 85° C, A9=12V when when TA=-40° C to 0° C.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
32
MX29LA32xMT/B
SWITCHING TEST CIRCUITS
TEST SPECIFICATIONS
Test Condition
Output Load
Output Load Capacitance, CL
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
Input timing measurement
reference levels
Output timing measurement
reference levels
2.7K ohm
DEVICE UNDER
TEST
3.3V
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
All Speeds
1 TTL gate
30
Unit
5
0.0-3.0
1.5
ns
V
V
1.5
V
pF
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State(High Z)
SWITCHING TEST WAVEFORMS
3.0V
1.5
Measurement Level
1.5
0.0V
INPUT
OUTPUT
P/N:PM1144
REV. 1.3, NOV. 15, 2005
33
MX29LA32xMT/B
AC CHARACTERISTICS
Read-Only Operations TA=-40°° C to 85°° C, VCC=2.7V~3.6V (TA=0°° C to 70°° C, VCC=3.0V~3.6V for
70R)
Parameter
Speed Options
Std.
Description
Test Setup
70R
90
Unit
tRC
Read Cycle Time (Note 1)
Min
70
90
ns
tACC
Address to Output Delay
CE#, OE#=VIL
Max
70
90
ns
tCE
Chip Enable to Output Delay
OE#=VIL
Max
70
90
ns
tPACC
Page Access Time
Max
25
25
ns
tOE
Output Enable to Output Delay
Max
35
35
ns
tDF
Chip Enable to Output High Z (Note 1)
Max
16
ns
tDF
Output Enable to Output High Z (Note 1)
Max
16
ns
tOH
Output Hold Time From Address, CE#
Min
0
ns
Read
Min
35
ns
Output Enable Hold Time
Toggle and
Min
10
ns
(Note 1)
Data# Polling
or OE#, whichever Occurs First
tOEH
Notes:
1. Not 100% tested.
2. See SWITCHING TEST CIRCUITS and TEST SPECIFICATIONS TABLE for test specifications.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
34
MX29LA32xMT/B
Figure 1. READ TIMING WAVEFORMS
tRC
VIH
ADD Valid
Addresses
VIL
tCE
VIH
CE#
tRH
VIL
tRH
VIH
WE#
VIL
OE#
VIH
VIL
Outputs
tDF
tOE
tOEH
VOH
tOH
tACC
HIGH Z
HIGH Z
DATA Valid
VOL
VIH
RESET#
VIL
RY/BY#
0V
Figure 2. PAGE READ TIMING WAVEFORMS
Same Page
A2-A20
(A-1), A0~A2
tACC
CE#
tPACC
Output
tPACC
tPACC
OE#
Qa
Qb
P/N:PM1144
Qc
Qd
REV. 1.3, NOV. 15, 2005
35
MX29LA32xMT/B
AC CHARACTERISTICS
Parameter
Description
Test Setup All Speed Options Unit
tREADY1
RESET# PIN Low (During Automatic Algorithms)
MAX
20
us
MAX
500
ns
to Read or Write (See Note)
tREADY2
RESET# PIN Low (NOT During Automatic Algorithms)
to Read or Write (See Note)
tRP
RESET# Pulse Width (NOT During Automatic Algorithms)
MIN
500
ns
tRH
RESET# High Time Before Read (See Note)
MIN
50
ns
tRB
RY/BY# Recovery Time(to CE#, OE# go low)
MIN
0
ns
tRPD
RESET# Low to Standby Mode
MIN
20
us
Note:Not 100% tested
Figure 3. RESET# TIMING WAVEFORM
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady2
Reset Timing NOT during Automatic Algorithms
tReady1
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Reset Timing during Automatic Algorithms
P/N:PM1144
REV. 1.3, NOV. 15, 2005
36
MX29LA32xMT/B
AC CHARACTERISTICS
Erase and Program Operations
3.0V~3.6V for 70R)
Parameter
Std.
tWC
tAS
tASO
tAH
tAHT
tDS
tDH
tCEPH
tOEPH
tGHWL
tGHEL
tCS
tCH
tWP
tWPH
tWHWH1
tWHWH2
tVCS
tRB
tBUSY
tVHH
tPOLL
TA=-40°° C to 85°° C, VCC=2.7V~3.6V (TA=0°° C to 70°° C, VCC=
Description
Write Cycle Time (Note 1)
Address Setup Time
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
Address Hold Time From CE# or OE# high during toggle
bit polling
Data Setup Time
Data Hold Time
CE# High During Toggle Bit Polling
Output Enable High during toggle bit polling
Read Recovery Time Before Write
(OE# High to WE# Low)
Read Recovery Time Before Write
CE# Setup Time
CE# Hold Time
Write Pulse Width
Write Pulse Width High
Write Buffer Program Operation (Notes 2,3)
Single Word/Byte Program
Byte
Operation (Notes 2,5)
Word
Accelerated Single Word/Byte
Byte
Programming Operation (Notes 2,5)
Word
Sector Erase Operation (Note 2)
VCC Setup Time (Note 1)
Write Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
VHH Rise and Fall Time (Note 1)
Program Valid Before Status Polling (Note 6)
Min
Min
Min
Min
Min
Speed Options
70R
90
70
90
0
15
45
0
Unit
ns
ns
ns
ns
ns
Min
Min
Min
Min
Min
35
0
20
20
0
ns
ns
ns
ns
ns
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Typ
Typ
Min
Min
Min
Min
Max
0
0
0
35
30
240
60
60
54
54
0.5
50
0
ns
ns
ns
ns
ns
us
us
us
us
us
sec
us
ns
ns
ns
us
70
90
250
4
Notes:
1. Not 100% tested.
2. See the "Erase And Programming Performance" section for more information.
3. For 1-16 words/1-32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the
write buffer.
6. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be
fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL
is not required again prior to reading the status bits upon resuming.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
37
MX29LA32xMT/B
ERASE/PROGRAM OPERATION
Figure 4. AUTOMATIC PROGRAM TIMING WAVEFORMS
Program Command Sequence(last two cycle)
tWC
XXXh
Address
Read Status Data (last two cycle)
tAS
PA
PA
PA
tAH
CE#
tCH
OE#
tWP
WE#
tWHWH1
tCS
tWPH
tDS
tDH
A0h
Status
PD
DOUT
Data
tBUSY
tRB
RY/BY#
tVCS
VCC
Note :
1.PA=Program Address, PD=Program Data, DOUT is the true data the program address
Figure 5. ACCELERATED PROGRAM TIMING DIAGRAM
VHH
ACC
VIL or VIH
VIL or VIH
tVHH
tVHH
P/N:PM1144
REV. 1.3, NOV. 15, 2005
38
MX29LA32xMT/B
Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Data Poll
from system
Increment
Address
No
Verify Word Ok ?
YES
No
Last Address ?
YES
Auto Program Completed
P/N:PM1144
REV. 1.3, NOV. 15, 2005
39
MX29LA32xMT/B
Figure 7. WRITE BUFFER PROGRAMMING ALGORITHM FLOWCHART
Write "Write to Buffer"
command and
Sector Address
Write number of addresses
to program minus 1(WC)
and Sector Address
Part of "Write to Buffer"
Command Sequence
Write first address/data
Yes
WC = 0 ?
No
Abort Write to
Buffer Operation ?
Yes
Write to a different
sector address
No
Write to buffer ABORTED.
Must write "Write-to-buffer
Abort Reset" command sequence
to return to read mode.
Write next address/data pair
(Note 1)
WC = WC - 1
Write program buffer
to flash sector address
Notes:
1. When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations with data, all
addresses must fall within the selected Write-Buffer
Page.
2. Q7 may change simultaneously with Q5.
Therefore, Q7 should be verified.
3. If this flowchart location was reached because Q5=
"1" then the device FAILED. If this flowchart location
was reached because Q1="1", then the Write to
Buffer operation was ABORTED. In either case, the
proper reset command must be written before the
device can begin another operation. If Q1=1, write
the Write-Buffer-Programming-Abort-Reset command. If Q5=1, write the Reset command.
4. See Table 3 for command sequences required for
write buffer programming.
Read Q7~Q0 at Last
Loaded Address
Yes
Q7 = Data ?
No
No
No
Q5 = 1 ?
Q1 = 1 ?
Yes
Yes
Read Q7~Q0 with address
= Last Loaded Address
(Note 2)
Q7 and Q15 = Data ?
Yes
No
(Note 3)
FAIL or ABORT
PASS
P/N:PM1144
REV. 1.3, NOV. 15, 2005
40
MX29LA32xMT/B
Figure 8. PROGRAM SUSPEND/RESUME FLOWCHART
Program Operation
or Write-to-Buffer
Sequence in Progress
Write address/data
XXXh/B0h
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Wait 15us
Autoselect and Secured Sector
read operations are also allowed
Data cannot be read from erase-or
program-suspended sectors
Read data as
required
No
Done reading ?
Yes
Write address/data
XXXh/30h
Write Program Resume
Command Sequence
Device reverts to
operation prior to
Program Suspend
P/N:PM1144
REV. 1.3, NOV. 15, 2005
41
MX29LA32xMT/B
Figure 9. AUTOMATIC CHIP/SECTOR ERASE TIMING WAVEFORM
Erase Command Sequence(last two cycle)
tWC
2AAh
Address
Read Status Data
tAS
VA
SA
555h for chip erase
VA
tAH
CE#
tCH
OE#
tWHWH2
tWP
WE#
tCS
tWPH
tDS
tDH
55h
Data
In
Progress Complete
30h
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Note :
1. SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
P/N:PM1144
REV. 1.3, NOV. 15, 2005
42
MX29LA32xMT/B
Figure 10. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Data Poll
from system
YES
No
DATA = FFh ?
YES
Auto Erase Completed
P/N:PM1144
REV. 1.3, NOV. 15, 2005
43
MX29LA32xMT/B
Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
NO
Last Sector
to Erase ?
YES
Data Poll from System
NO
Data=FFh?
YES
Auto Sector Erase Completed
P/N:PM1144
REV. 1.3, NOV. 15, 2005
44
MX29LA32xMT/B
Figure 12. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
NO
ERASE SUSPEND
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
Programming End
NO
YES
Write Data 30H
ERASE RESUME
Continue Erase
Another
Erase Suspend ?
NO
YES
P/N:PM1144
REV. 1.3, NOV. 15, 2005
45
MX29LA32xMT/B
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
TA=-40°° C to 85°° C, VCC=2.7V~3.6V (TA=0°° C to 70°° C, VCC=3.0V~3.6V for 70R)
Parameter
Speed Options
Std.
Description
70R
90
Unit
tWC
Write Cycle Time (Note 1)
Min
70
90
ns
tAS
Address Setup Time
Min
0
ns
tAH
Address Hold Time
Min
45
ns
tDS
Data Setup Time
Min
35
ns
tDH
Data Hold Time
Min
0
ns
tGHEL
Read Recovery Time Before Write
Min
0
ns
(OE# High to WE# Low)
tWS
WE# Setup Time
Min
0
ns
tWH
WE# Hold Time
Min
0
ns
tCP
CE# Pulse Width
Min
35
ns
tCPH
CE# Pulse Width High
Min
25
ns
Write Buffer Program Operation (Notes 2,3)
Typ
240
us
tWHWH1
Single Word/Byte Program
Byte
Typ
60
us
Operation (Notes 2,5)
Word
Typ
60
us
Accelerated Single Word/Byte
Byte
Typ
54
us
Programming Operation (Notes 2,5)
Word
Typ
54
us
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
tRH
RESET HIGH Time Before Write (Note 1)
Min
50
ns
tPOLL
Program Valid Before Status Polling (Note 6)
Max
4
us
Notes:
1. Not 100% tested.
2. See the "Erase And Programming Performance" section for more information.
3. For 1-16 words/1-32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the
write buffer.
6. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be
fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL
is not required again prior to reading the status bits upon resuming.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
46
MX29LA32xMT/B
Figure 13. CE# CONTROLLED PROGRAM TIMING WAVEFORM
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Address
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tCP
tWHWH1 or 2
CE#
tWS
tCPH
tDS
tBUSY
tDH
Q7
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes :
1. PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.
2. Figure indicates the last two bus cycles of the command sequence.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
47
MX29LA32xMT/B
SECTOR GROUP PROTECT/CHIP UNPROTECT
Figure 14. Sector Group Protect / Chip Unprotect Waveform (RESET# Control)
VID
VIH
RESET#
SA, A6
A1, A0
Valid*
Valid*
Sector Group Protect or Chip Unprotect
Data
60h
1us
60h
Valid*
Verify
40h
Status
Sector Group Protect:150us
Chip Unprotect:15ms
CE#
WE#
OE#
Note: For sector group protect A6=0, A1=1, A0=0. For chip unprotect A6=1, A1=1, A0=0
P/N:PM1144
REV. 1.3, NOV. 15, 2005
48
MX29LA32xMT/B
Figure 15. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH
RESET#=VID
START
START
Protect all sectors:
The indicated portion of
the sector protect algorithm
must be performed
for all unprotected sectors
prior to issuing the first
sector unprotect address
PLSCNT=1
RESET#=VID
PLSCNT=1
RESET#=VID
Wait 1us
Wait 1us
First Write
Cycle=60h
First Write
Cycle=60h
Yes
Yes
Set up sector address
No
Sector Protect:
Write 60h to sector
address with
A6=0, A1=1, A0=0
All sectors
protected?
Yes
Set up first sector address
Wait 150us
Verify Sector Protect:
Write 40h to sector
address with
A6=0, A1=1, A0=0
Sector Unprotect:
Write 60h to sector
address with
A6=1, A1=1, A0=0
Reset
PLSCNT=1
Increment PLSCNT
Wait 15 ms
Read from
sector address
with
A6=0, A1=1, A0=0
Verify Sector Unprotect:
Write 40h to sector
address with
A6=1, A1=1, A0=0
No
Increment PLSCNT
No
PLSCNT=25?
Yes
Data=01h?
Read from
sector address
with
A6=1, A1=1, A0=0
Yes
No
Device failed
Protect another
sector?
Sector Protect
Algorithm
Reset
PLSCNT=1
Yes
No
PLSCNT=1000?
Data=00h?
No
Yes
Remove VID from RESET#
Yes
Device failed
Last sector
verified?
Write reset command
Chip Unprotect
Algorithm
Sector Protect complete
No
Yes
Remove VID from RESET#
Write reset command
Sector Unprotect complete
P/N:PM1144
REV. 1.3, NOV. 15, 2005
49
MX29LA32xMT/B
AC CHARACTERISTICS
Parameter
Description
Test Setup
All Speed Options
Unit
tVLHT
Voltage transition time
Min.
4
us
tWPP1
Write pulse width for sector group protect
Min.
100
ns
tOESP
OE# setup time to WE# active
Min.
4
us
Figure 16. SECTOR GROUP PROTECT TIMING WAVEFORM (A9, OE# Control)
A1
A6
12V
3V
A9
tVLHT
Verify
12V
3V
OE#
tVLHT
tVLHT
tWPP 1
WE#
tOESP
CE#
Data
01H
F0H
tOE
A20-A16
Sector Address
P/N:PM1144
REV. 1.3, NOV. 15, 2005
50
MX29LA32xMT/B
Figure 17. SECTOR GROUP PROTECTION ALGORITHM (A9, OE# Control)
START
Set Up Sector Addr
PLSCNT=1
OE#=VID, A9=VID, CE#=VIL
A6=VIL
Activate WE# Pulse
Time Out 150us
Set WE#=VIH, CE#=OE#=VIL
A9 should remain VID
Read from Sector
Addr=SA, A1=1
No
PLSCNT=32?
.
No
Data=01H?
Yes
Device Failed
Protect Another
Sector?
Yes
Remove VID from A9
Write Reset Command
Sector Protection
Complete
P/N:PM1144
REV. 1.3, NOV. 15, 2005
51
MX29LA32xMT/B
Figure 18. CHIP UNPROTECT TIMING WAVEFORM (A9, OE# Control)
A1
12V
3V
A9
tVLHT
A6
Verify
12V
3V
OE#
tVLHT
tVLHT
tWPP 2
WE#
tOESP
CE#
Data
00H
F0H
tOE
P/N:PM1144
REV. 1.3, NOV. 15, 2005
52
MX29LA32xMT/B
Figure 19. CHIP UNPROTECT FLOWCHART (A9, OE# Control)
START
Protect All Sectors
PLSCNT=1
Set OE#=A9=VID
CE#=VIL, A6=1
Activate WE# Pulse
Time Out 15ms
Increment
PLSCNT
Set OE#=CE#=VIL
A9=VID, A1=1
Set Up First Sector Addr
Read Data from Device
No
Data=00H?
Increment
Sector Addr
Yes
No
All sectors have
No
PLSCNT=1000?
Yes
Device Failed
been verified?
Yes
Remove VID from A9
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
53
MX29LA32xMT/B
Figure 20. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART
START
Enter Secured Silicon Sector
Wait 1us
First Wait Cycle Data=60h
Second Wait Cycle Data=60h
A6=0, A1=1, A0=0
Wait 300us
No
Data = 01h ?
Yes
Device Failed
Write Reset Command
Secured Sector Protect Complete
P/N:PM1144
REV. 1.3, NOV. 15, 2005
54
MX29LA32xMT/B
Figure 21. SILICON ID READ TIMING WAVEFORM
VCC
3V
VID
VIH
VIL
ADD
A9
ADD
A0
VIH
VIL
tACC
A1
tACC
tACC
tACC
VIH
VIL
A2
VIH
VIL
ADD
VIH
VIL
CE#
VIH
VIL
tCE
WE#
VIH
VIL
OE#
VIH
tOE
tDF
VIL
tOH
tOH
tOH
tOH
VIH
DATA
Q0-Q15
VIL
DATA OUT
DATA OUT
DATA OUT
DATA OUT
Manufacturer ID
Device ID
Cycle 1
Device ID
Cycle 2
Device ID
Cycle 3
P/N:PM1144
REV. 1.3, NOV. 15, 2005
55
MX29LA32xMT/B
WRITE OPERATION STATUS
Figure 22. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
tRC
Address
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
Q7
Status Data
Q0-Q6
Status Data
Complement
Status Data
True
True
Valid Data
Valid Data
High Z
High Z
tBUSY
RY/BY#
Note :
VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
56
MX29LA32xMT/B
Figure 23. DATA# POLLING ALGORITHM
Start
Read Q7~Q0
Add.=VA(1)
Yes
Q7 = Data ?
No
No
Q5 = 1 ?
Yes
Read Q7~Q0
Add.=VA
Yes
Q7 = Data ?
(2)
No
FAIL
Pass
Notes :
1.VA=valid address for programming.
2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
57
MX29LA32xMT/B
Figure 24. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
tRC
Address
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tDH
Q6/Q2
Valid Status
tOH
Valid Status
Valid Data
(second read)
(stops toggling)
Valid Status
(first read)
Valid Data
RY/BY#
Note :
VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
58
MX29LA32xMT/B
Figure 25. TOGGLE BIT ALGORITHM
START
Read Q7~Q0
Read Q7~Q0
(Note 1)
NO
Toggle Bit Q6
=Toggle?
YES
NO
Q5=1?
YES
Read Q7~Q0 Twice
(Note 1,2)
Toggle Bit Q6=
Toggle?
YES
Program/Erase Operation Not
Complete, Write Reset Command
Program/Erase Operation Complete
Notes :
1. Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
P/N:PM1144
REV. 1.3, NOV. 15, 2005
59
MX29LA32xMT/B
Figure 26. Q6 versus Q2
Enter Embedded
Erasing
Erase
Suspend
Erase
WE#
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Resume
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
Q6
Q2
Note :
The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended
P/N:PM1144
REV. 1.3, NOV. 15, 2005
60
MX29LA32xMT/B
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
tVR
tACC
tR or tF
VIH
ADDRESS
tR or tF
Valid
Address
VIL
tF
tCE
tR
VIH
CE#
VIL
VIH
WE#
VIL
tF
tOE
tR
VIH
OE#
VIL
VIH
WP#/ACC
VIL
VOH
DATA
High Z
Valid
Ouput
VOL
Figure A. AC Timing at Device Power-Up
Symbol
Parameter
tVR
VCC Rise Time
tR
Input Signal Rise Time
tF
Input Signal Fall Time
Notes
Min.
Max.
Unit
1
20
500000
us/V
1,2
20
us/V
1,2
20
us/V
Notes :
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
P/N:PM1144
REV. 1.3, NOV. 15, 2005
61
MX29LA32xMT/B
ERASE AND PROGRAMMING PERFORMANCE (1)
PARAMETER
Sector Erase Time
Typ (Note 1)
Max (Note 2)
Unit
Comments
0.5
3.5
sec
Excludes 00h
programming
Chip Erase Time
32
sec
prior to erasure
Note 6
Total Write Buffer Program Time (Note 4)
240
us
Excludes
Total Accelerated Effective Write Buffer
200
us
system level
Program Time (Note 4)
Chip Program Time
overhead
31.5
sec
Note 7
Notes:
1. Typical program and erase times assume the following conditions: 25° C, 3.0 V VCC. Programming specifications
assume that all bits are programmed to 00h.
2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and
including 100,000 program/erase cycles.
3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the
write buffer.
4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation.
5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer
operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence(s) for the program command. See
Tables 3 for further information on command definitions.
8. The device has a minimum erase and program cycle endurance of 100,000 cycles.
LATCH-UP CHARACTERISTICS
MIN.
MAX.
Input Voltage with respect to GND on all pins except I/O pins
-1.0V
13.5V
Input Voltage with respect to GND on all I/O pins
-1.0V
VCC + 1.0V
-100mA
+100mA
Current
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
DATA RETENTION
Parameter
Minimum Pattern Data Retention Time
P/N:PM1144
Min
Unit
20
Years
REV. 1.3, NOV. 15, 2005
62
MX29LA32xMT/B
TSOP PIN AND CSP PACKAGE CAPACITANCE
Parameter Symbol
Parameter Description
CIN
Input Capacitance
COUT
CIN2
Output Capacitance
Control Pin Capacitance
Test Set
VIN=0
VOUT=0
VIN=0
TYP
MAX
UNIT
6
7.5
pF
CSP
4.2
5.0
pF
TSOP
8.5
12
pF
CSP
5.4
6.5
pF
TSOP
7.5
9
pF
CSP
3.9
4.7
pF
TSOP
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA=25° C, f=1.0MHz
P/N:PM1144
REV. 1.3, NOV. 15, 2005
63
MX29LA32xMT/B
ORDERING INFORMATION
PART NO.
ACCESS TIME
(ns)
MX29LA320MTTC-70R
70
MX29LA320MTTC-90
90
MX29LA320MBTC-70R
70
MX29LA320MBTC-90
90
MX29LA320MTTI-90
90
MX29LA320MBTI-90
90
MX29LA320MTXBC-70R
MX29LA320MTXBC-90
MX29LA320MBXBC-70R
MX29LA320MBXBC-90
MX29LA320MTXBI-90
MX29LA320MBXBI-90
MX29LA320MTXEC-70R
MX29LA320MTXEC-90
MX29LA320MBXEC-70R
MX29LA320MBXEC-90
MX29LA320MTXEI-90
MX29LA320MBXEI-90
MX29LA320MTTC-90G
70
90
70
90
90
90
70
90
70
90
90
90
90
MX29LA320MBTC-90G
90
MX29LA320MTTI-90G
90
MX29LA320MBTI-90G
90
MX29LA320MTXBC-90G
MX29LA320MBXBC-90G
MX29LA320MTXBI-90G
MX29LA320MBXBI-90G
MX29LA320MTXEC-90G
MX29LA320MBXEC-90G
MX29LA320MTXEI-90G
MX29LA320MBXEI-90G
90
90
90
90
90
90
90
90
Ball Pitch/
Ball size
0.8mm/0.3mm
0.8mm/0.3mm
0.8mm/0.3mm
0.8mm/0.3mm
0.8mm/0.3mm
0.8mm/0.3mm
0.8mm/0.4mm
0.8mm/0.4mm
0.8mm/0.4mm
0.8mm/0.4mm
0.8mm/0.4mm
0.8mm/0.4mm
0.8mm/0.3mm
0.8mm/0.3mm
0.8mm/0.3mm
0.8mm/0.3mm
0.8mm/0.4mm
0.8mm/0.4mm
0.8mm/0.4mm
0.8mm/0.4mm
P/N:PM1144
PACKAGE
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
Remark
PB-free
PB-free
PB-free
PB-free
PB-free
PB-free
PB-free
PB-free
PB-free
PB-free
PB-free
PB-free
REV. 1.3, NOV. 15, 2005
64
MX29LA32xMT/B
PART NO.
ACCESS TIME
(ns)
MX29LA321MTTC-70R
70
MX29LA321MTTC-90
90
MX29LA321MBTC-70R
70
MX29LA321MBTC-90
90
MX29LA321MTTI-90
90
MX29LA321MBTI-90
90
MX29LA321MTXCC-70R
MX29LA321MTXCC-90
MX29LA321MBXCC-70R
MX29LA321MBXCC-90
MX29LA321MTXCI-90
MX29LA321MBXCI-90
MX29LA321MTTC-90G
70
90
70
90
90
90
90
MX29LA321MBTC-90G
90
MX29LA321MTTI-90G
90
MX29LA321MBTI-90G
90
MX29LA321MTXCC-90G
MX29LA321MBXCC-90G
MX29LA321MTXCI-90G
MX29LA321MBXCI-90G
90
90
90
90
Ball Pitch/
Ball size
1.0mm/0.4mm
1.0mm/0.4mm
1.0mm/0.4mm
1.0mm/0.4mm
1.0mm/0.4mm
1.0mm/0.4mm
1.0mm/0.4mm
1.0mm/0.4mm
1.0mm/0.4mm
1.0mm/0.4mm
P/N:PM1144
PACKAGE
56 Pin TSOP
(Normal Type)
56 Pin TSOP
(Normal Type)
56 Pin TSOP
(Normal Type)
56 Pin TSOP
(Normal Type)
56 Pin TSOP
(Normal Type)
56 Pin TSOP
(Normal Type)
64 Ball CSP
64 Ball CSP
64 Ball CSP
64 Ball CSP
64 Ball CSP
64 Ball CSP
56 Pin TSOP
(Normal Type)
56 Pin TSOP
(Normal Type)
56 Pin TSOP
(Normal Type)
56 Pin TSOP
(Normal Type)
64 Ball CSP
64 Ball CSP
64 Ball CSP
64 Ball CSP
Remark
PB-free
PB-free
PB-free
PB-free
PB-free
PB-free
PB-free
PB-free
REV. 1.3, NOV. 15, 2005
65
MX29LA32xMT/B
PACKAGE INFORMATION
P/N:PM1144
REV. 1.3, NOV. 15, 2005
66
MX29LA32xMT/B
P/N:PM1144
REV. 1.3, NOV. 15, 2005
67
MX29LA32xMT/B
P/N:PM1144
REV. 1.3, NOV. 15, 2005
68
MX29LA32xMT/B
P/N:PM1144
REV. 1.3, NOV. 15, 2005
69
MX29LA32xMT/B
P/N:PM1144
REV. 1.3, NOV. 15, 2005
70
MX29LA32xMT/B
REVISION HISTORY
Revision No.
1.0
1.1
1.2
1.3
Description
1. Removed "Advanced Information" on title
1. To modify WP# protect function
1. To add note 7 for ILIT parameter in DC Characteristics table
2. To add comments into performance table
1. To add "Chip Enable Truth" table for MX29LA321 option
2. Removed "Temporary Sector Group Unprotect" function
P/N:PM1144
Page
P1
P1,11,15
P32
P63
P5
All
Date
MAR/22/2005
JUN/10/2005
JUL/11/2005
NOV/15/2005
REV. 1.3, NOV. 15, 2005
71
MX29LA32xMT/B
MACRONIX INTERNATIONAL CO., LTD.
Headquarters:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
Europe Office :
TEL:+32-2-456-8020
FAX:+32-2-456-8021
Hong Kong Office :
TEL:+86-755-834-335-79
FAX:+86-755-834-380-78
Japan Office :
Kawasaki Office :
TEL:+81-44-246-9100
FAX:+81-44-246-9105
Osaka Office :
TEL:+81-6-4807-5460
FAX:+81-6-4807-5461
Singapore Office :
TEL:+65-6346-5505
FAX:+65-6348-8096
Taipei Office :
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-262-8887
FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.