CY7C65642 HX2VL – Very Low Power USB 2.0 TetraHub™ Controller Features ■ High-performance, low-power USB 2.0 hub, optimized for low- cost designs with minimum bill-of-material (BOM). ■ USB 2.0 hub controller ❐ Compliant with USB2.0 specification ❐ Up to four downstream ports support ❐ Downstream ports are backward compatible with FS, LS ❐ Multiple translator (TT), one per downstream port for maximum performance. ■ ■ 12-MHz +/-500 ppm external crystal with drive level 600 W (integrated PLL) clock input with optional 27/48-MHz oscillator clock input. ❐ Internal power failure detection for ESD recovery ❐ Very low-power consumption ❐ Supports bus-powered and self-powered modes ❐ Auto switching between bus-powered and self-powered ❐ Single MCU with 2 K ROM and 64 byte RAM ❐ Lowest power consumption. Highly integrated solution for reduced BOM cost ❐ Internal regulator - single power supply 5 V required. ❐ Provision of connecting 3.3 V with external regulator. ❐ Integrated upstream pull-up resistor ❐ Integrated pull-down resistors for all downstream ports ❐ Integrated upstream/downstream termination resistors ❐ Integrated port status indicator control ■ Downstream port management ❐ Support individual and ganged mode power management ❐ Overcurrent detection within 8 mS. ❐ Two status indicators per downstream port ❐ Slew rate control for EMI management ■ Maximum configurability ❐ VID and PID are configurable through external EEPROM ❐ Number of ports, removable/non-removable ports are configurable through EEPROM and I/O pin configuration ❐ I/O pins can configure gang/individual mode power switching, reference clock source and polarity of power switch enable pin ❐ Configuration options also available through mask ROM ■ Available in space saving 48-pin (7 × 7 mm) TQFP and 28-pin (5 × 5 mm) QFN packages ■ Supports 0 C to +70 C temperature range Block Diagram D+ 12/27/48 MHz OSC-in OR 12 MHz Crystal I2C / SPI MCU D- RAM USB 2.0 PHY Serial Interface Engine PLL ROM HS USB Control Logic USB Upstream Port 5 V i/p (for internal regulator) NC (for external regulator) Transaction Translator x 4 1.8 V Regulator Hub Repeater 3.3 V 3.3 V i/p (with ext. reg. & 28-QFN NC (with ext. reg. & 48-TQFP) 3.3 V o/p (for int. reg.) Routing Logic USB Downstream Port 2 USB Downstream Port 3 USB Downstream Port 4 USB 2.0 PHY USB 2.0 PHY USB 2.0 PHY USB 2.0 PHY Cypress Semiconductor Corporation Document Number: 001-65659 Rev. *B • 198 Champion Court LED • D+ D- Port Control O V R # [4] D+ D- O V R # [3] LED Port Control P W R # [3] D+ D- O V R # [2] LED Port Control P W R # [2] O V R # [1] P W R # [1] D+ D- Port Control P W R # [4] USB Downstream Port 1 LED San Jose, CA 95134-1709 • 408-943-2600 Revised July 27, 2011 CY7C65642 Contents Introduction ....................................................................... 3 n USB Serial Interface Engine ..................................... 3 n HS USB Control Logic .............................................. 3 n Hub Repeater ........................................................... 3 n MCU ......................................................................... 3 n Transaction Translator ............................................. 3 n Port Control .............................................................. 3 n Applications ................................................................... 3 n Functional Overview ..................................................... 4 n System Initialization .................................................. 4 n Upstream Port .......................................................... 4 n Downstream Ports .................................................... 4 n Power Switching ....................................................... 4 Figure 2. Pin Description for 48-Pin TQFP Package ..... 8 1. Pin Description for 28-Pin QFN Package ................. 10 Table 2. EEPROM Configuration Options .................... 12 Table 2. Pin Configuration Options .............................. 13 Table 2. Power ON Reset ......................................... 13 Table 2. Gang/Individual Power Switching Mode ...... 13 Table 2. Power Switch Enable Pin Polarity ............... 13 Document Number: 001-65659 Rev. *B Table 2. Port Number Configuration .......................... 13 Table 2. Non Removable Ports Configuration ........... 13 Table 2. Reference Clock Configuration ................... 13 Table 2. Electrical Characteristics ................................ 14 Table 2. Absolute Maximum Ratings ......................... 14 Table 2. Operating Conditions ................................... 14 Table 2. .................................................................... 14 Table 2. DC Electrical Characteristics ....................... 14 Table 2. AC Electrical Characteristics ....................... 15 Table 4. Ordering Information ....................................... 16 Table 4. Ordering Code Definition ............................. 16 Table 4. Package Diagram ............................................. 17 Figure 4. Acronyms ........................................................ 19 Table 5. Document Conventions ................................... 19 Table 5. Units of Measure ......................................... 19 Table 6. Document History Page ................................... 20 Table 6. Sales, Solutions, and Legal Information ........ 21 Table 6. Worldwide Sales and Design Support ......... 21 Table 6. Products ...................................................... 21 Table 6. PSoC Solutions ........................................... 21 Page 2 of 21 CY7C65642 Introduction ■ Ensures orderly entry into and out of ‘Suspend’ state, including proper handling of remote wakeups. HX2VL is Cypress’s next generation family of high- performance, very low-power USB 2.0 hub controllers. HX2VL has integrated upstream and downstream transceivers; a USB serial interface engine (SIE); USB hub control and repeater logic; and transaction translator (TT) logic. Cypress has also integrated external components such as voltage regulator and pull-up/pull-down resistors, reducing the overall BOM required to implement a USB hub system. MCU The CY7C65642 is a part of the HX2VL portfolio with four downstream ports and an independent TT dedicated for each downstream port. This device option is for low-power but high- performance applications that require up to four downstream ports. The CY7C65642 is available in 48-pin TQFP and 28-pin QFN package options. Transaction Translator The HX2VL has MCU with 2 K ROM and 64 byte RAM. The MCU operates with a 12 MHz clock to decode USB commands from host and respond to the host. It can also handle GPIO settings to provide higher flexibility to the customers and control the read interface to the EEPROM which has extended configuration options. ■ Bit stuffing and unstuffing The TT translates data from one speed to another. A TT takes high-speed split transactions and translates them to full or low-speed transactions when the hub is operating at high-speed (the upstream port is connected to a high speed host controller) and has full or low- speed devices attached. The operating speed of a device attached on a downstream port determines whether the routing logic connects a port to the TT or to hub repeater. When the upstream host and downstream device are functioning at different speeds, the data is routed through the TT. In all other cases, the data is routed through the repeater. For example, If a full or low-speed device is connected to the high-speed host upstream through the hub, then the data transfer route includes TT. If a high-speed device is connected to the high-speed host upstream through the hub, the transfer route includes the repeater. When the hub is connected to a full-speed host controller upstream, then high-speed peripheral does not operate at its full capability. These devices only work at full speed. Full and low-speed devices connected to this hub operate at their normal speed. ■ Checksum generation and checking Port Control ■ TOKEN type identification ■ Address checking. The downstream ‘Port Control’ block handles the connect/disconnect and over current detection as well as the power enable and LED control. It also generates the control signals for the downstream transceivers. All device options are supported by Cypress’s world class reference design kits, which include board schematics, BOM, Gerber files, Orcad files, and thorough design documentation. HX2VL Architecture The “Block Diagram” on page 1 shows the HX2VL TetraHub™ architecture. USB Serial Interface Engine The SIE allows HX2VL to communicate with the USB host. The SIE handles the following USB activities independently of the Hub Control Block. HS USB Control Logic ‘Hub Control’ block co-ordinates enumeration, suspend and resume. It generates status and control signals for host access to the hub. It also includes the frame timer that synchronizes the hub to the host. It has status/control registers which function as the interface to the firmware in the MCU. Hub Repeater The hub repeater manages the connectivity between upstream and downstream facing ports that are operating at the same speed. It supports full or low-speed connectivity and high-speed connectivity. According to the USB 2.0 specification, the hub repeater provides the following functions: ■ Applications Typical applications for the HX2VL device family are: ■ Docking stations ■ Standalone hubs ■ Monitor hubs ■ Multi-function printers ■ Digital televisions ■ Advanced port replicators ■ Keyboard hubs Sets up and tears down connectivity on packet boundaries Document Number: 001-65659 Rev. *B Page 3 of 21 CY7C65642 Functional Overview The Cypress CY7C65642 USB 2.0 Hubs are low-power hub solutions for USB which provide maximum transfer efficiency with no TT multiplexing between downstream ports. The CY7C65642 USB 2.0 Hubs integrate 1.5 k upstream pull-up resistors for full speed operation and all downstream 15 k pull-down resistors and series termination resistors on all upstream and downstream D+ and D– pins. This results in optimization of system costs by providing built-in support for the USB 2.0 specification. System Initialization On power up, CY7C65642 has an option to enumerate from the default settings in the mask ROM or from reading an external EEPROM for configuration information. At the most basic level, this EEPROM has the Vendor ID (VID) and the Product ID (PID), for the customer's application. For more specialized applications, other configuration options can be specified. See EEPROM Configuration Options for more details. CY7C65642 verifies the checksum before loading the EEPROM contents as the descriptors. Enumeration The device checks if VBUSPOWER (connected to up-stream VBUS) is high, CY7C65642 enables the pull-up resistor on D+ to indicate its presence to the upstream hub, after which a USB Bus Reset is expected. After a USB Bus Reset, CY7C65642 is in an unaddressed, unconfigured state (configuration value set to’0’). During the enumeration process, the host sets the hub's address and configuration. After the hub is configured, the full hub functionality is available. Multiple Transaction Translator Support After TetraHub is configured in a high speed system, it is in single TT mode. The host may then set the hub into multiple TT mode by sending a SetInterface command. In multiple TT mode, each full speed port is handled independently and thus has a full 12 Mbps bandwidth available. In Single TT mode, all traffic from the host destined for full or low-speed ports are forwarded to all of those ports. This means that the 12 Mbps bandwidth is shared by all full and low-speed ports. Upstream Port The upstream port includes the transmitter and the receiver state machine. The transmitter and receiver operate in high speed and full speed depending on the current hub configuration. The transmitter state machine monitors the upstream facing port while the Hub Repeater has connectivity in the upstream direction. This machine prevents babble and disconnect events on the downstream facing ports of this hub from propagating and causing the hub to be disabled or disconnected by the hub to which it is attached. Downstream Ports The CY7C65642 supports a maximum of four downstream ports, each of which may be marked as usable or removable in the EEPROM configuration, see EEPROM Configuration Options. Additionally, number of downstream ports can also be configured by pin strapping, see Pin Configuration Options. Document Number: 001-65659 Rev. *B Downstream D+ and D– pull-down resistors are incorporated in CY7C65642 for each port. Before the hubs are configured, the ports are driven Single Ended Zero, ((SE0) where both D+ and D– are driven low) and are set to the unpowered state. When the hub is configured, the ports are not driven and the host may power the ports by sending a SetPortPower command for each port. After a port is powered, any connect or disconnect event is detected by the hub. Any change in the port state is reported by the hubs back to the host through the Status Change Endpoint (endpoint 1). On receipt of SetPortReset request for a port with a device connected, the hub does as follows: ■ Performs a USB Reset on the corresponding port ■ Puts the port in an enabled state ■ Enables babble detection after the port is enabled. Babble consists of a non idle condition on the port after EOF2. If babble is detected on an enabled port, that port is disabled. A ClearPortEnable request from the host also disables the specified port. Downstream ports can be individually suspended by the host with the SetPortSuspend request. If the hub is not suspended, a remote wakeup event on that port is reflected to the host through a port change indication in the Hub Status Change Endpoint. If the hub is suspended, a remote wakeup event on this port is forwarded to the host. The host may resume the port by sending a ClearPortSuspend command. Power Switching The CY7C65642 includes interface signals for external port power switches. Both ganged and individual (per-port) configurations are supported by pin strapping, see “Pin Configuration Options” on page 13. After enumerating, the host may power each port by sending a SetPortPower request for that port. Power switching and overcurrent detection are managed using respective control signals (PWR#[n] and OVR#[n]) which are connected to an external power switch device. Both High/Low enabled power switches are supported and the polarity is configured through GPIO setting, see “Pin Configuration Options” on page 13. Overcurrent Detection The OVR#[n] pins of the CY7C65642 series are connected to the respective external power switch's port overcurrent indication (output) signals. After detecting an overcurrent condition, hub reports overcurrent condition to the host and disables the PWR#[n] output to the external power device. Port Indicators The USB 2.0 port indicators are also supported directly by CY7C65642. According to the specification, each downstream port of the hub optionally supports a status indicator. The presence of indicators for downstream facing ports is specified by bit 7 of the wHubCharacteristics field of the hub class descriptor. The default CY7C65642 descriptor specifies that the port indicators are supported. The CY7C65642 port indicators has two modes of operation: automatic and manual. Page 4 of 21 CY7C65642 On power up the CY7C65642 defaults to automatic mode, where the color of the Port Indicator (green, amber, off) indicates the functional status of the CY7C65642 port. The LEDs are turned off when the device is suspended. 5 V to 3.3 V Regulator 5 V to 3.3 V Regulator Port Status Indicator LED NC NC NC VCC VREG VREG CY7C65642 48 Pin Note Pin-strapping GREEN#[1] and GREEN#[2] enables proprietary function that may affect the normal functionality of HX2VL. Configuring Port #1 and #2 as non-removable by pin-strapping should be avoided Power Regulator CY7C65642 requires 3.3 V source power for normal operation of internal core logic and USB physical layer (PHY). The integrated low-drop power regulator converts 5 V power input from USB cable (Vbus) to 3.3 V source power. The 3.3 V power output is guaranteed by an internal voltage reference circuit when the input voltage is within the 4 V - 5.5 V range. The regulator’s maximum current loading is 150 mA, which provides tolerance margin over CY7C65642’s normal power consumption of below 100 mA. The on chip regulator has a quiescent current of 28 uA. External Regulation Scheme CY7C65642 supports both external regulation and internal regulation schemes. When an external regulation is chosen, then for the 48-pin package, VCC and VREG are to be left open with no connection. The external regulator output 3.3 V has to be connected to VCC_A and VCC_D pins. This connection has to be done externally, on board. For the 28-Pin package, the 3.3 V output from the external regulator has to be connected to VREG, VCC_A and VCC_D. The VCC pin has to be left open with no connection. From the external input 3.3 V, 1.8 V is internally generated for the chip’s internal usage. Document Number: 001-65659 Rev. *B CY7C65642 28 Pin VCC_D VCC_A VCC VCC_A VCC_D External Regulation Scheme Internal Regulation Scheme When the built-in internal regulator is chosen, then the VCC pin has to be connected to a 5 V, in both 48-pin and 28-pin packages. Internally, the built-in regulator generates a 3.3 V and 1.8 V for the chip’s internal usage. Also a 3.3 V output is available at VREG pin, that has to be connected externally to VCC_A and VCC_D. 3.3 V VREG 5V VCC CY7C65642 48 Pin VCC_A 3.3 V VREG 5V VCC CY7C65642 28 Pin VCC_D VCC_A VCC_D Internal Regulation Scheme Page 5 of 21 CY7C65642 Figure 1. 48-pin TQFP Pin Configuration PWR#[1] / I2C_SDA OVR#[1] PWR#[2] OVR#[2] GANG VCC_D SELFPWR 44 43 42 41 40 39 38 37 45 SEL27 GREEN[1] / SPI_SK / 47 46 VCC 48 FIXED_PORT 1 AMBER[1] / SPI_CS VREG AMBER[2] / SPI_DI / PWR_PIN_POL GREEN[2] / SPI_DO / FIXED_PORT2 VCC_A 1 36 GND 2 35 D- 3 34 VCC_D D+ 4 33 AMBER[3] / SET_PORT_NUM2 DD-[1] 5 32 GREEN[3] / FIXED_PORT3 DD+[1] 5 31 PWR#[3] VCC_A 7 30 OVR#[3] GND 8 29 PWR#[4] DD-[2] 9 28 OVR#[4] DD+[2] 10 27 TEST / SCL RREF 11 26 RESET# VCC_A 12 25 SEL48 CY7C65642 48 TQFP 13 14 15 16 17 18 19 20 21 22 23 24 GND XIN XOUT VCC_A DD-[3] DD+[3] VCC_A GND DD-[4] DD+[4] GREEN[4] / FIXED_PORT 4 AMBER[4] / SET_PORT_NUM1 Document Number: 001-65659 Rev. *B Page 6 of 21 CY7C65642 Figure 2. 28-pin QFN Pin Configuration VREG VCC SDA OVR # [1] O V R # [2] GANG SELFPWR 28 27 26 25 24 23 22 1 21 VC C_ D D+ 2 20 O V R # [3] D D - [1] 3 19 O V R # [4] DD + [1] 4 18 T E S T/S C L V C C_ A 5 17 RESET# DD - [2] 6 CY7C65642 16 DD + [4] DD + [2] 7 28 QFN 15 DD - [4] - D - 9 10 11 12 13 14 RREF V C C_ A XIN XOUT DD D D + [3] V C C_ A - [3] 8 Document Number: 001-65659 Rev. *B Page 7 of 21 CY7C65642 Pin Description for 48-Pin TQFP Package Pin Types: I = Input, O = Output, P = Power/ground, Z = High Impedance, RDN = Pad internal Pull-Down Resistor, RUP = Pad internal Pull-Up Resistor. Table 1. Pin Assignments 48-pin TQFP pin no. Power and Clock VCC_A 1 VCC_A 7 VCC_A 12 VCC_A 16 VCC_A 19 VCC_D 34 VCC_D 38 Name Type P P P P P P P VCC_A. 3.3 V analog power to the chip. VCC_A. 3.3 V analog power to the chip. VCC_A. 3.3 V analog power to the chip. VCC_A. 3.3 V analog power to the chip. VCC_A. 3.3 V analog power to the chip. VCC_D. 3.3 V digital power to the chip. VCC_D. 3.3 V digital power to the chip. VCC. 5 V input to the internal regulator; NC if using external regulator VCC. 5 - 3.3 V regulator o/p during internal regulation; NC if using external regulator. GND. Connect to ground with as short a path as possible. GND. Connect to ground with as short a path as possible. GND. Connect to ground with as short a path as possible. GND. Connect to ground with as short a path as possible. 12-MHz crystal clock input, or 12/27/48MHz clock input 12-MHz Crystal OUT. (NC if external clock is used). 00: Reserved 01: 48-MHz OSC-in 10: 27-MHz OSC-in 11: 12-MHz Crystal or OSC-in Active LOW Reset. External reset input, default pull high 10 K; When RESET = low, whole chip is reset to the initial state Self Power. Input for selecting self/bus power. 0 is bus powered, 1 is self powered. GANG Default is input mode after power-on-reset. Gang Mode: Input:1 -> Output is 0 for normal operation and 1 for suspend Individual Mode: Input:0 -> Output is 1 for normal operation and 0 for suspend refer to gang/individual power switching modes in “Pin Configuration Options” on page 13 for details 650 resistor must be connected between RREF and Ground VCC VREG GND GND GND GND XIN XOUT SEL48/SEL27 47 48 2 8 13 20 14 15 25/44 P P P P P P I O I RESET# 26 I SELFPWR GANG 37 39 I I/O 11 I/O RREF System Interface Test I2C_SCL Upstream Port D– D+ 27 3 4 Description I(RDN) Test: 0: Normal Operation and 1: Chip will be put in test mode I/O(RDN) I2C_SCL: Can be used as I2C clock pin to access I2C EEPROM I/O/Z I/O/Z Document Number: 001-65659 Rev. *B Upstream D– Signal. Upstream D+ Signal. Page 8 of 21 CY7C65642 Pin Types: I = Input, O = Output, P = Power/ground, Z = High Impedance, RDN = Pad internal Pull-Down Resistor, RUP = Pad internal Pull-Up Resistor. Table 1. Pin Assignments 48-pin TQFP pin no. Downstream Port 1 DD–[1] 5 DD+[1] 6 AMBER[1] 46 SPI_CS 45 GREEN[1][1] SPI_SK FIXED_PORT1 Name Type Description I/O/Z I/O/Z O(RDN) O(RDN) O(RDN) O(RDN) I(RDN) Downstream D– Signal. Downstream D+ Signal. LED. Driver output for amber LED. port indicator support. SPI_CS. Can be used as chip select to access external SPI EEPROM. LED. Driver output for green LED. Port indicator support. SPI_SK. Can be used as SPI Clock to access external SPI EEPROM. FIXED_PORT1. At POR used to set Port1 as non removable port. Refer “Pin Configuration Options” on page 13 42 I(RUP) Overcurrent Condition Detection Input. Active LOW Overcurrent Condition Detection Input. PWR#[1] I2C_SDA Downstream Port 2 DD–[2] DD+[2] AMBER[2] SPI_DI PWR_PIN_POL 43 O/Z I/O 9 10 36 I/O/Z I/O/Z O(RDN) O(RDN) I(RDN) GREEN[2][1] SPI_DO FIXED_PORT2 35 OVR#[2] 40 O(RDN) LED. Driver output for Green LED. Port Indicator Support. I(RDN) SPI_DO. Can be used as Data In (MISO) to access external SPI EEPROM. I(RDN) FIXED_PORT2. At POR used to set Port2 as non removable port. Refer “Pin Configuration Options” on page 13 I(RUP) Overcurrent Condition Detection Input. Active LOW Overcurrent Condition Detection Input. O/Z Power Switch Driver Output. Default is Active LOW OVR#[1] PWR#[2] Downstream Port 3 DD–[3] DD+[3] AMBER[3] SET_PORT_ NUM2 GREEN[3] FIXED_PORT3 41 17 18 33 32 OVR#[3] 30 PWR#[3] 31 Power Switch Driver Output. Default is Active LOW. I2C_SDA. Can be used as I2C Data pin, connected with I2C EEPROM. Downstream D– Signal. Downstream D+ Signal. LED. Driver output for Amber LED. Port Indicator Support. SPI_DI. Can be used as Data Out (MOSI) to access external SPI EEPROM. PWR_PIN_POL. Used for power switch enable pin polarity setting. Refer “Pin Configuration Options” on page 13 I/O/Z I/O/Z Downstream D– Signal. Downstream D+ Signal. O(RDN) LED. Driver output for Amber LED. Port indicator support. SET_PORT_NUM2. Used to set port numbering along with SET_PORT_NUM1. Refer “Pin I(RDN) Configuration Options” on page 13 O(RDN) LED. Driver output for Green LED. Port indicator support. I(RDN) FIXED_PORT3. At POR used to set Port3 as non removable port. Refer “Pin Configuration Options” on page 13 I(RUP) Overcurrent Condition Detection Input. Active LOW Overcurrent Condition Detection Input. O/Z Power Switch Driver Output. Default is Active LOW. Note 1. Pin-strapping GREEN#[1] and GREEN#[2] enables proprietary function that may affect the normal functionality of HX2VL. Configuring Port #1 and #2 as non-removable by pin-strapping should be avoided. Document Number: 001-65659 Rev. *B Page 9 of 21 CY7C65642 Pin Types: I = Input, O = Output, P = Power/ground, Z = High Impedance, RDN = Pad internal Pull-Down Resistor, RUP = Pad internal Pull-Up Resistor. Table 1. Pin Assignments 48-pin TQFP Type Description pin no. Downstream Port 4 DD–[4] 21 I/O/Z Downstream D– Signal. DD+[4] 22 I/O/Z Downstream D+ Signal. AMBER[4] 24 O(RDN) LED. Driver output for Amber LED. Port Indicator Support. SET_PORT_ I(RDN) SET_PORT_NUM1. Used to set port numbering along with SET_PORT_NUM2. Refer “Pin Configuration Options” on page 13 NUM1 GREEN[4] 23 O(RDN) LED. Driver output for Green LED. Port Indicator Support. FIXED_PORT4 I(RDN) FIXED_PORT4. At POR used to set Port4 as non removable port. Refer “Pin Configuration Options” on page 13 OVR#[4] 28 I(RUP) Overcurrent Condition Detection Input. Active LOW Overcurrent Condition Detection Input. PWR#[4] 29 O/Z Power Switch Driver Output. Default is Active LOW. Name Pin Description for 28-Pin QFN Package Pin Types: I = Input, O = Output, P = Power/ground, Z = High Impedance, RDN = Pad internal Pull-Down Resistor, RUP = Pad internal Pull-Up Resistor. Table 2. Pin Assignments 28-QFN pin no. Power and Clock VCC_A 5 VCC_A 9 VCC_A 14 VCC_D 21 VCC 27 VREG 28 XIN 10 XOUT 11 RESET# 17 Name SELFPWR GANG Type Description P P P P P P I O I VCC_A. 3.3 V analog power to the chip. VCC_A. 3.3 V analog power to the chip. VCC_A. 3.3 V analog power to the chip. VCC_D. 3.3 V digital power to the chip. VCC. 5 V input to the internal regulator; NC if using external regulator VCC. 5 - 3.3 V regulator o/p during internal regulation; 3.3 V i/p if using external regulator. 12-MHz crystal clock input, or 12-MHz clock input 12-MHz Crystal OUT. (NC if external clock is used). Active LOW Reset. External reset input, default pull high 10K Ohm; When RESET = low, whole chip is reset to the initial state Self Power. Input for selecting self/bus power. 0 is bus powered, 1 is self powered. GANG Default is input mode after power-on-reset. Gang Mode: Input:1 -> Output is 0 for normal operation and 1 for suspend Individual Mode: Input:0 -> Output is 1 for normal operation and 0 for suspend refer to gang/individual power switching modes in “Pin Configuration Options” on page 13 for details 650- resistor must be connected between RREF and Ground 22 23 I I/O RREF 8 System Interface Test 18 SCL I/O SDA Upstream Port D– D+ 26 1 2 O(RDN) Test: 0: Normal Operation & 1: Chip will be put in test mode I/O(RDN SCL: I2C Clock pin. ) I/O SDA: I2C Data pin. I/O/Z I/O/Z Document Number: 001-65659 Rev. *B Upstream D– Signal. Upstream D+ Signal. Page 10 of 21 CY7C65642 Pin Types: I = Input, O = Output, P = Power/ground, Z = High Impedance, RDN = Pad internal Pull-Down Resistor, RUP = Pad internal Pull-Up Resistor. Table 2. Pin Assignments 28-QFN pin no. Downstream Port 1 DD–[1] 3 DD+[1] 4 OVR#[1] 25 Name Downstream Port 2 DD–[2] 6 DD+[2] 7 OVR#[2] 24 Downstream Port 3 DD–[3] 12 DD+[3] 13 OVR#[3] 20 Downstream Port 4 DD–[4] 15 DD+[4] 16 OVR#[4] 19 GND PAD Type Description I/O/Z Downstream D– Signal. I/O/Z Downstream D+ Signal. I(RUP) Overcurrent Condition Detection Input. Active LOW Overcurrent Condition Detection Input. I/O/Z Downstream D– Signal. I/O/Z Downstream D+ Signal. I(RUP) Overcurrent Condition Detection Input. Active LOW Overcurrent Condition Detection Input. I/O/Z Downstream D– Signal. I/O/Z Downstream D+ Signal. I(RUP) Overcurrent Condition Detection Input. Active LOW Overcurrent Condition Detection Input. I/O/Z Downstream D– Signal. I/O/Z Downstream D+ Signal. I(RUP) Overcurrent Condition Detection Input. Active LOW Overcurrent Condition Detection Input. P Ground pin for the chip. It is the solderable exposed pad beneath the chip. Refer to the Figure 4 on page 18. Document Number: 001-65659 Rev. *B Page 11 of 21 CY7C65642 EEPROM Configuration Options Systems using CY7C65642 have the option of using the default descriptors to configure the hub. Otherwise, it must have an external EEPROM for the device to have a unique VID, and PID. The CY7C65642 can communicate with an SPI (microwire) EEPROM like 93C46 or I2C EEPROM like 24C02. Example EEPROM connections are shown as follows: Byte 11h - 3Fh 40h 41h - 6Fh 70 h 71 h to 80 h Value Vendor string (ASCII code) Product string length Product string (ASCII code) Serial number length Serial number string Byte 0: VID (LSB) S P I E E P R O M C o n n e ctio n A M B E R # [1 ] CS VCC G R E E N # [1 ] SK NC1 A M B E R # [2 ] DI NC2 G R E E N # [2 ] DO GND VDD Least Significant Byte of Vendor ID Byte 1: VID (MSB) Most Significant Byte of Vendor ID Byte2: PID (LSB) Least Significant Byte of Product ID AT93C 46 Byte 3: PID (MSB)] I2 C E E P R O M C o n n e ctio n Most Significant Byte of Product ID VDD Byte 4: ChkSum A0 VCC A1 WP CY7C65642 will ignore the EEPROM settings if ChkSum is not equal to VID_LSB + VID_MSB + PID_LSB + PID_MSB +1 A2 SCL TEST GND SDA P W R # [1 ] Byte 5: Reserved Set to FF AT24C 02 Byte 6: RemovablePorts I2C Note The 28 pin QFN package includes only support for EEPROM like ATMEL/24C02N_SU27 D, MICROCHIP/4LC028 SN0509, SEIKO/S24CS02AVH9. The 48-pin TQFP package includes both I2C and SPI EEPROM connectivity options. In this case, user can use either SPI or I2C connectivity at a time for communicating to EEPROM. The 48-pin package supports ATMEL/AT93C46DN-SH-T, in addition to the above mentioned families. HX2VL can only read from SPI EEPROM. So field programming of EEPROM will be supported only for I2C EEPROM. The default VID and PID are 0x04B4 and 0x6572. CY7C65642 verifies the check sum after power on reset and if validated loads the configuration from the EEPROM. To prevent this configuration from being overwritten, amber LED is disabled when the SPI EEPROM is present. Byte 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h - 0Fh 10h Value VID_LSB VID_MSB PID_LSB PID_MSB ChkSum Reserved - FE Removable ports Port number Maximum power Reserved – FF (except 0Bh which is FE) Vendor string length Document Number: 001-65659 Rev. *B RemovablePorts[4:1] are the bits that indicate whether the device attached to the corresponding downstream port is removable (set to 0). Bit 1 corresponds to Port 1, Bit 2 to Port 2 and so on. These bit values are reported appropriately in the HubDescriptor:DeviceRemovable field. Bits 0,5,6,7 are set to 0. Byte 7: Port Number Port Number values must be 1 to 4 Byte 8: Maximum Power This value is reported in the Configuration Descriptor: bMax-Power field and is the current in 2 mA increments that is required from the upstream hubs. The allowed range is 00h (0mA) to FAh(500mA) Byte 9 - 15: Reserved Set to FF Byte 16: Vendor String Length Length of the Vendor String Byte 17 - 63: Vendor String Value of Vendor String. Strings must comply with the USB specification. The first byte (Byte 16) must be the length of the string in bytes, the second must be 0x03, and the string must be in ASCII code. Byte 64: Product String Length Length of the Product String Byte 65- 111: Product String Value of Product String in ASCII code Page 12 of 21 CY7C65642 Features supported in 48 pin and 28 pin packages Byte 112: Serial Number Length Length of the Serial Number Supported Features 48 Pin 28 Pin Port number configuration Yes No Non-removable port configuration Yes No Reference clock configuration Yes No Power switch enable polarity Yes No LED Indicator Yes No Byte 113 onwards: Serial Number String Serial Number String in ASCII code. Pin Configuration Options Power-on Reset The power-on reset (POR) can be triggered by external reset or internal circuitry. The internal reset is initiated, when there is an unstable power event for silicon’s internal core power (3.3 V). The internal reset is released after approximately 2.7 micro-seconds of stable internal core voltage. The external reset pin, continuously senses the voltage level (5 V) on the upstream VBUS as shown in the figure. In the event of USB plug/unplug or drop in voltage, the external reset is triggered. This reset trigger can be configured using the resistors R1 and R2. Cypress recommends that the reset time applied in external reset circuit should be longer than that of the internal reset time. PCB VBUS (External 5V) Silicon Ext. VBUS power-good detection circuit input (Pin"RESET#") R1 EXT Global Reset# INT R2 Power Switch Enable Pin Polarity The pin polarity is set active-high by pin-strapping the PWR_PIN_POL pin to 1 and Active-Low by pin-strapping the PWR_PIN_POL pin to 0. Thus, both kinds of power switches are supported. This feature is not supported in 28-pin QFN package. Port Number Configuration In addition to the EEPROM configuration, as described above, configuring the hub for 2/3/4 ports is also supported using pin-strapping SET_PORT_NUM1 and SET_PORT_NUM2, as shown in following table.Pin strapping option is not supported in the 28-QFN package. SET_PORT_NUM2 SET_PORT_NUM1 1 1 1 (Port 1) 1 0 2 (Port 1/2) 0 1 3 (Port 1/2/3) 0 0 4 (All ports) Int. 3.3V power-good detection circuit input (USB PHY reset) # Ports Gang/Individual Power Switching Mode Non Removable Ports Configuration A single pin is used to set individual / gang mode as well as output the suspend flag. This is done to reduce the pin count. The individual or gang mode is decided within 20 us after power on reset. 50ms after reset, this pin is changed to output mode. CY7C65642 outputs the suspend flag, once it is globally suspended. Pull-down resistor of greater than 100K is needed for Individual mode and a pull-up resistor greater than 100K is needed for Gang mode. Figure below shows the suspend LED indicator schematics. The polarity of LED must be followed, otherwise the suspend current will be over the spec limitation (2.5 mA). In embedded systems, downstream ports that are always connected inside the system, can be set as non-removable (always connected) ports, by pin-strapping the corresponding FIXED_PORT# pins 1~4 to High, before power on reset. At POR, if the pin is pull high, the corresponding port is set to non-removable. This is not supported in the 28-pin QFN package. VDD (3.3V) VDD (3.3V) PCB Silicon GANG MODE 100K GANG/SUSPND SUSPEND OUT SUSPEND INDICATOR Reference Clock Configuration This hub can support, optional 27/48-MHz clock source. When on-board 27/48-MHz clock is present, then using this feature, system integrator can further reduce the BOM cost by eliminating the external crystal. This is available through GPIO pin configuration shown below. This is not supported in the 28-pin QFN package SEL48 SEL27 Clock Source 0 1 48-MHz OSC-in 1 0 27-MHz OSC-in 1 1 12-MHz X’tal/OSC-in 100K INDIVIDUAL MODE Document Number: 001-65659 Rev. *B 0 : INDIVIDUAL MODE 1: GANG MODE Page 13 of 21 CY7C65642 Electrical Characteristics Absolute Maximum Ratings Operating Conditions Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Ambient temperature ..................................... 0 °C to +70 °C Storage temperature ................................ –60 °C to +100 °C Ambient temperature ..................................... 0 °C to +70 °C 5 V supply voltage to ground potential ........–0.5 V to +6.0 V 3.3 V supply voltage to ground potential .....–0.5 V to +3.6 V Voltage at open drain input pins (OVR#1-4, SELFPWR, RESET#) ......................................................–0.5 V to +5.5 V 3.3 V Input Voltage for digital I/O ..................–0.5 V to +3.6 V Ambient max junction temperature .............. 0 °C to +125 °C 5 V supply voltage to ground potential ......4.75 V to +5.25 V 3.3 V supply voltage to ground potential .....3.15 V to +3.6 V Input voltage for USB signal pins ..................0.5 V to +3.6 V Voltage at open drain input pins ..................–0.5 V to +5.0 V Thermal characteristics 48 TQFP ......................... 75.8 °C/W Thermal characteristics 28 QFN ........................... 32.4 °C/W FOSC (oscillator or crystal frequency)......... 12 MHz ± 0.05% DC Electrical Characteristics Parameter Description Conditions Min Typ Max Unit PD Power dissipation Excluding USB signals – – 432 mW VIH Input high voltage – 2 – – V VIL Input low voltage – Il Input leakage current Full speed/ low speed (0 < VIN < VCC) VOH Output voltage high – – 0.8 V –10 – +10 A High speed mode (0 < VIN < VCC) –5 0 +5 A IOH = 8 mA 2.4 – – V VOL Output low voltage IOL= 8 mA – – 0.4 V RDN Pad internal pull-down resistor – 81 103 181 RUP Pad internal pull-up resistor – 81 103 181 CIN Input pin capacitance Full speed / low speed mode – – 20 pF high speed mode 4 4.5 5 pF ISUSP Suspend current – – 786 903 A ICC Supply Current Full speed host, full speed devices – 88.7 99.78 mA 4 Active ports 3 Active ports 2 Active ports 1 Active ports No Active ports High speed host, high speed devices – 81.9 91.44 mA High speed host, full speed devices – 88.2 97.23 mA Full speed host, full speed devices – 79.1 94.6 mA High speed host, high speed devices – 72.9 80.92 mA High speed host, full speed devices – 75.9 92.02 mA Full speed host, full speed devices – 68.1 80.53 mA High speed host, high speed devices – 61.9 70.55 mA High speed host, full speed devices – 64.9 77.46 mA Full speed host, full speed devices – 57.1 66.66 mA High speed host, high speed devices – 51.9 60.32 mA High speed host, full speed devices – 54.7 63.81 mA Full speed host – 42.8 49.02 mA High speed host – 44.2 49.78 mA USB Transceiver is USB 2.0 certified in low, full and high speed modes. Document Number: 001-65659 Rev. *B Page 14 of 21 CY7C65642 AC Electrical Characteristics Both the upstream USB transceiver and all four downstream transceivers have passed the USB-IF USB 2.0 Electrical Certification Testing. The 48 pin TQFP package can support communication to EEPROM using either I2C or SPI. The 28 pin QFN package can support only I2C communication to EEPROM. AC characteristics of these two interfaces to EEPROM are summarized in tables below: Table 3. Table: AC characteristics of SPI EEPROM interface Symbol Parameter Min Typ Max Units us tCSS CS setup time 3.0 – – tCSH CS hold time 3.0 – – tSKH SK high time 1.0 – – tSKL SK low time 2.2 – – tDIS DI setup time 1.8 – – tDIH DI hold time 2.4 – – tPD1 Output delay to '1' – – 1.8 tPD0 Output delay to '0' – – 1.8 Table 4. Table: AC characteristics of I2C EEPROM interface Symbol 1.8 V - 5.5 V 2.5 V - 5.5 V Min Max Min Max Parameter Units fSCL SCL clock frequency 0.0 100 0.0 400 KHz tLOW Clock LOW Period 4.7 – 1.2 – us tHIGH Clock HIGH Period 4.0 – 0.6 – us tSU:STA Start condition setup time 4.7 – 0.6 – us tSU:STO Stop condition setup time 4.7 – 0.6 – us tHD:STA Start condition hold time 4.0 – 0.6 – us tHD:STO Stop condition hold time 4.0 – 0.6 – us tSU:DAT Data in setup time 200.0 – 100.0 – ns tHD:DAT Data in hold time 0 – 0 – ns tDH Data out hold time 100 – 50 – ns tAA Clock to output 0.1 4.5 0.1 – us tWR Write cycle time – –10 – – ns Document Number: 001-65659 Rev. *B Page 15 of 21 CY7C65642 Ordering Information Ordering Code Package Type CY7C65642-48AXC 48-Pin TQFP Bulk CY7C65642-48AXCT 48-Pin TQFP Tape and Reel Ordering Code Definition CY 7C XXX XX - XX XXX C X X = blank or T (blank = Bulk, T = Tape and Reel) Temperature grades : C = Commercial Package type : AX: TQFP ( Pb- free) : Pin count 48 = 48 pins Specific product identifier Base part number Marketing code :7 C Company ID : CY = Cypress Document Number: 001-65659 Rev. *B Page 16 of 21 CY7C65642 Package Diagram The CY7C65642 is available in following packages: Figure 3. 48-Pin TQFP Package Diagram 51-85135 *B Document Number: 001-65659 Rev. *B Page 17 of 21 CY7C65642 Figure 4. 28-Pin QFN Package Diagram GND 001-64621 ** Document Number: 001-65659 Rev. *B Page 18 of 21 CY7C65642 Acronyms The following table lists the acronyms that are used in this document. Table 5. Acronyms Used in this Datasheet Acronym Description Acronym Description AC alternating current PC program counter ADC analog-to-digital converter PLL phase-locked loop API application programming interface POR power on reset CPU central processing unit PPOR precision power on reset CT continuous time PSoC® Programmable System-on-Chip™ ECO external crystal oscillator PWM pulse-width modulator EEPROM electrically erasable programmable read-only memory SC switched capacitor FSR full scale range SRAM static random access memory GPIO general purpose I/O ICE in-circuit emulator GUI graphical user interface ILO internal low speed oscillator HBM human body model IMO internal main oscillator LSb least-significant bit I/O input/output LVD low-voltage detect IPOR imprecise power on reset MSb most-significant bit Document Conventions Units of Measure The following table lists the units of measure that are used in this document. Table 6. Units of Measure Symbol Unit of Measure Symbol Unit of Measure °C degree Celsius W microwatts dB decibels mA milliampere fF femto farad ms millisecond Hz hertz mV millivolts KB 1024 bytes nA nanoampere Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts kilohm ohm MHz megahertz pA picoampere M megaohm pF picofarad A microampere pp peak-to-peak k F microfarad ppm H microhenry ps picosecond s microsecond sps samples per second V microvolts s sigma: one standard deviation microvolts root-mean-square V volts Vrms Document Number: 001-65659 Rev. *B parts per million Page 19 of 21 CY7C65642 Document History Page Document Title: CY7C65642 HX2VL - Very Low Power USB 2.0 TetraHub™ Controller Document Number: 001-65659 Revision ECN Orig. of Change ** 3176751 SWAK *A 3250883 SWAK/AASI *B 3327505 AASI Submission Date Description of Change 02/18/2011 New datasheet 06/29/2011 1. In page 6, the pin of the 48-pin TQFP package was named SELF_PWR. It is changed to SELFPWR. 2. In page 9, 10 and 11 the entry against OVR# in the pin assignment table is changed to "Active LOW Overcurrent Condition Detection Input" as it should not say "Default is Active LOW" since the polarity is not configurable. 3. In page 8 and 11, in page assignment table, entry against XOUT is changed to "12-MHz Crystal OUT. (NC if external clock is used)" 4. In page 11, under pin assignment table, entry against XIN is changed to "12-MHz crystal clock input, or 12-MHz clock input" since 28-pin package does not support 27 and 48 MHz. 5. In page 9, all seven occurrences of "Refer "48-pin TQFP Pin Configuration" on page 5" is changed to "Refer "Pin Configuration Options" on page 13". 6. In page 4, under "Port indicators" section added the following as a note "pin-strapping GREEN#[1] and GREEN#[2] enables proprietary function that may affect the normal functionality of HX2VL. Configuring Port #1 and #2 as non-removable by pin-strapping should be avoided". 7. Added note # 1 on page 9 and is referred to GREEN#[1] and GREEN#[2] under ”Pin Description for 48-Pin TQFP Package” on page 8. 8. In section ”Power Switch Enable Pin Polarity” on page 13 replaced first two occurrences of the word “setting” with “pin-strapping”. 9. RREF changed from 680ohm to 650ohm 10. Maximum load current for internal regulator changed from 200mA to 150mA 11. Maximum operating voltage for 5V supply changed from 5.5 V to 5.25 V 12. Supply current values in DC Electrical characteristics table updated 13. Maximum suspend current value updated to 903uA. 07/27/2011 Datasheet moved from Preliminary to Final Updated Ordering Information, Ordering Code Definition Updated *A revision history in Document History Page. Minor edits in Pin Description for 48-Pin TQFP Package table. Document Number: 001-65659 Rev. *B Page 20 of 21 CY7C65642 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-65659 Rev. *B Revised July 27, 2011 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 21 of 21