IK Semicon IN16C554TQ Quad-uart asynchronous communications element Datasheet

IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
1. General Description
IN16C554
is an enhanced quadruple version of the 16C550 UART (Universal Asynchronous Receiver
Transmitter). Each channel can be put into FIFO mode to relieve the CPU of excessive software overhead. In this
mode, internal FIFOs are activated and 16 bytes plus 3 bit of error data per byte can be stored in both receive
and transmit modes.
Each channel performs serial-to-parallel conversion on data characters received from a peripheral device or a
MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the
complete status of the UART at any time during the functional operation. The Status information includes the
type and condition of the transfer operations being performed by the UART, as well as any error conditions such
as parity, overrun, framing, and break interrupt.
IN16C554
includes a programmable baud rate generator which is capable of dividing the timing reference
16
clock input by divisors of 1 to 2 -1, and producing a 16x clock for driving the internal transmitter logic.
Provisions are also included to use this clock to drive the receiver logic.
IN16C554
has complete MODEM-control capability and an interrupt system that can be programmed to the
user’s requirements, minimizing the computing required to handle the communication links.
2. Features
z
In the FIFO mode, Each channel’s transmitter and receiver is buffered with 16-byte FIFO to reduce
the number of interrupts to CPU.
z
Adds or deletes standard asynchronous communication bits (start, stop, parity) to or from the serial
data.
z
Holding Register and Shift Register eliminate need for precise synchronization between the CPU and
serial data.
z
Independently controlled transmit, receive, line status and data interrupts.
z
Programmable Baud Rate Generators which allow division of any input reference clock by 1 to 2 -1
16
and generate an internal 16X clock.
z
Independent receiver clock input
z
Modem control functions (CTS#, RTS#, DSR#, DTR#, RI#, and DCD#).
z
Fully programmable serial interface characteristics.
- 5-, 6-, 7-, or 8-bit characters
- Even-, Odd-, or No-Parity bit
- 1-, 1.5-, 2-Stop bit generation. ( Like other general UARTs, IN16C554 checks only one stop bit,
no matter how many they are)
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
z
False start bit detection
z
Generates or Detects Line Break
z
Internal diagnostic capabilities : Loopback controls for communications link fault isolation.
z
Full prioritized interrupt system controls
z
The transmitter outputs and receiver inputs are protected to ±15kV Air ESD.
z
5V and 3.3V Operation
3. Signal Description
NAME
PIN NO.
A0
34 (48)
A1
33 (47)
A2
32 (46)
I/O
†
CS0#, CS1#
16,20 (28, 33)
CS2#, CS3#
50,54 (68, 73)
CTS0#, CTS1#
11,25 (23, 38)
CTS2, CTS3#
45,59 (63, 78)
DESCRIPTION
Register select pins. A0, A1, and A2 three inputs are used to select the
I
I
register of the UART during read and write operations.
Chip Select. Each CSx# enables read and write operations to its respective
channel.
I
Clear to send. CTSx# is a modem status signal. Its status can be known by
reading bit 4 of the modem status register. CTS# does not affect the transmit
or receive operation.
Data Bus. Eight data lines with 3-state outputs provide a bidirectional path
D7~D3,
66~68(15~11)
D2~D0
1~ 5 (9~7)
I/O
for data, control, and status information between the IN16C554
and the
CPU. D0 is the LSB.
Data Carrier Detect. A low on DCDx# indicates the carrier has been
DCD0#, DCD1#
9,27 (19, 42)
DCD2#, DCD3#
43, 61 (59, 2)
DSR0#, DSR1#
10,26 (22, 39)
DSR2#, DSR3#
44,60 (62, 79)
I
detected by the modem. Its condition can be known by reading bit 7 of the
modem status register.
I
Data set ready. DSRx# is a modem status signal. The condition of DSRx# can
be checked by reading the Bit 5 of the modem status register. DSR# does not
affect the transmit or receive operation.
Data Terminal Ready. DTRx# is an output that indicates to a modem or
DTR0#, DTR1#
12, 24(24, 37)
DTR2#, DTR3#
46, 58(64,77)
O
data set that the UART is ready to establish communications. Setting the
DTR bit of the modem control register activates it. DTRx# is placed in
inactive state either as a result of the master reset during loop mode
operation or clearing bit 0 of the modem control register.
GND
6, 23 (16,36)
signal and power ground
40, 57 (56,76)
Interrupt normal. INTN# in conjunction with bit 3 of the modem status
register and affects operation of the four interrupts (INT0~INT3).
INTN#
Operation Of Interrupts
Interrupts are enabled according to the state of
INTN#
65 (6)
OUT2 (MCR bit 3). When the MCR bit 3 is cleared, the
I
Low or Float
3-state interrupt output of that UART is in the high Z
state. When MCR bit 3 is set, the interrupt output of
the UART is enabled.
High
INT0, INT1
15,21(27,34)
INT2, INT3
19,55(67,74)
IOR#
52 (70)
Interrupts are always activated.
External interrupt output. When activated, INTx output informs CPU that
UART has an interrupt to be serviced.
I
Read strobe. A low level on IOR# transfers the contents of the IN16C554
data bus to the external CPU bus.
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
PIN NO.
I/O
DESCRIPTION
IOW#
NAME
18 (31)
I
Write strobe. IOW# allows the CPU to write into the selected address by the
RESET
37 (53)
I
address register.
Master reset. When active, RESET clears most UART registers and sets the
state of various signals. The transmitter output and he receiver input is
disabled during reset time.
RI0#, RI1#
8, 28 (18,43)
RI2#, RI3#
42, 62 (58, 3)
RTS0#, RTS1#
14, 22 (26,35)
RTS2#, RTS3#
48, 56 (66,75)
I
Ring detect indicator. A low on Rix# indicates the modem has received a
ring signal from the telephone line. The condition of this signal can be
checked by reading bit 6 of the modem status register.
O
Request to Send. When active, RTSx# informs the modem or data set that
the UART is ready to receive data. Writing a 1 in the modem control
register sets this bit to a low state. After reset, this terminal is set high.
These terminals have no affect on the transmit or receive operation.
RXD0, RXD1
7, 29 (17, 44)
RXD2, RXD3
41, 63 (57, 4)
I
Serial Input. RXDx is a serial data input from a connected communications
device. During loopback mode, the RXDx input is disabled from external
connection and connected to the TXDx output internally.
RXRDY#
38 (54)
O
Receive ready. RXRDY# goes low when the receive FIFO is full. It can be
used as a single transfer or multi transfer.
Transmit output. TXDx is a composite serial data output that is connected
TXD0, TXD1
17, 19 (29,32)
TXD2, TXD3
51, 53 (69,72)
TXRDY#
39 (55)
O
to a communications device. TXD1, TXD2, TXD3, and TXD4 are set to the
high state as a result of reset.
O
Transmit Ready. TXRDY# goes low when the transmit FIFO is full. It can be
used as a single transfer of multi transfer.
VCC
13, 30 (5, 25)
Power supply.
47, 64 (45,65)
XTAL1
35 (50)
I
Crystal input 1 or external clock input. A crystal can be connected to XTAL1
and XTAL2 to utilize the internal oscillator circuit. An external clock can be
connected to drive the internal clock circuits.
XTAL2
36 (51)
O
Crystal output 2 or buffered clock output.
† At the PIN NO, the number outside the parenthesis means the pin number of the IN16C554 PL, and the number inside the parenthesis
means the pin number of the IN16C554 TQ.
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
4. Functional Block Diagram
SB16C554
D[7:0]
IOR#/IOW#
RESET
DATA AND
CONTROL
LOGIC
A[2:0]
CS#[3:0]
REGISTER
CONTROL
LOGIC
INT[3:0]
TXRDY #/RXRDY #
INTRRUPT
CONTROL
LOGIC
TRANSMIT
16-by te FIFO
REGISTER
TRANSMIT
SHIFT
REGISTER
TXD0
RECEIVE
16-by te FIFO
REGISTER
RECEIVE
SHIFT
REGISTER
RXD0
MODEM
SIGNAL
CONTROL
LOGIC
RTS0#/DTR0#
CTS0#/DSR0#/DCD0#/RI0#
TXRDY 0#/RXRDY 0#
UART 0
TXD1
RXD1
RTS1#/DTR1#
CTS1#/DSR1#/DCD1#/RI1#
TXRDY 1#/RXRDY 1#
UART 1
TXD2
RXD2
RTS2#/DTR2#
CTS2#/DSR2#/DCD2#/RI2#
TXRDY 2#/RXRDY 2#
UART 2
TXD3
RXD3
RTS3#/DTR3#
CTS3#/DSR3#/DCD3#/RI3#
TXRDY 3#/RXRDY 3#
UART 3
CLOCK AND
BAUD RATE
GENERATOR
XTAL1
XTAL2
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
5. Register Description
ADDRESS
REGISTER
REGISTER ADDRESS
MNEMONIC
0
0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RBR
Data bit 7
Data bit 6
Data bit 5
Data bit 4
Data bit 3
Data bit 2
Data bit 1
Data bit 0
(read only)
(MSB)
THR
Data bit 7
Data bit 6
Data bit 5
Data bit 4
Data bit 3
Data bit 2
Data bit 1
Data bit 0
Bit 2
Bit 1
Bit 0
(LSB)
(write only)
0
†
DLL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
1
†
DLM
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
(EDSSI)
(ERLSI)
(ETBEI)
(ERBI)
Enable
Enable
Enable
Enable
modem
receiver
Transmitter
received
status
line status
Holding
data
interrupt
interrupt
register
available
empty
interrupt
1
IER
0
0
0
0
interrupt
2
FCR
(write only)
2
IIR
(read only)
3
LCR
Receiver
Receiver
Trigger
Trigger
(MSB)
(LSB)
FIFOs
‡
FIFOs
‡
Enabled
Enabled
(DLAB)
Set break
Reserved
0
Reserved
0
DMA mode
Transmit
Receiver
FIFO
select
FIFO reset
FIFO reset
enable
Interrupt
Interrupt ID
Interrupt
0 if interrupt
ID Bit (3)
Bit (2)
ID Bit (1)
pending
‡
(EPS)
(PEN)
(STB)
(WLSB1)
(WLSB0)
Divisor
Even parity
Parity
Number of
Word
Word
latch
select
Enable
Stop bits
length
length
Stick Parity
access bit
4
MCR
0
0
0
Loop
select bit 1
select bit 0
(RTS)
(DTR)
Enable
Request to
Data
external
Send
terminal
OUT2
Reserved
interrupt
ready
(INT)
5
LSR
Error in
(TEMT)
(THRE)
(BI)
(FE)
(PE)
(OE)
(DR)
receiver
Transmitter
Transmitter
Break
Framing
Parity Error
Overrun
Data ready
FIFO
registers
holding
interrupt
Error
empty
register
error
empty
6
MSR
(DCD)
(RI)
(DSR)
(CTS)
(∆DCD)
(TERI)
(∆DSR)
(∆CTS)
Data
Ring
Data set
Clear to
Delta data
Trailing
Delta data
Delta clear
carrier
indicator
Ready
Send
carrier
Edge
set ready
to send
detect
indicator
Bit 3
Bit 2
Bit 1
Bit 0
detect
7
SCR
Bit 7
Bit 6
Bit 5
Bit 4
ring
† DLAB = 1
‡ This bit is always in a low state when FIFO is disabled.
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
5.1. FIFO control register(FCR)
The FCR is a write-only register at the same address as the IIR. FCR enables FIFO, sets the trigger level of
the receiver FIFO, and selects the type of DMA signaling.
z
Bit 0 : FCR0 enables transmit and receiver FIFOs. All bytes in both FIFOs can be cleared by clearing
this bit. Data is cleared automatically from the FIFOs when changing from the FIFO mode to the
16C450 mode and vice versa. Programming of other FCR bits is enabled by setting this bit.
z
Bit 1 : When set, FCR1 clears all bytes in the receiver FIFO and resets its counter. This does not clear
the shift register.
z
Bit 2 : When set, FRC2 clears all bytes in the transmitter FIFO and resets its counter. This does not
clear the shift register.
z
Bit 3 : When set, FRC3 changes RXRDY# and TXRDY# from mode 0 to mode 1 if FCR0 is set.
z
Bit 4, 5 : Reserved for the future use.
z
Bit 6, 7 : FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt. (see Table 1).
Table 1. Receiver FIFO Trigger Level
Receiver FIFO
BIT
7
6
Trigger Level
0
0
01
0
1
04
1
0
08
1
1
14
* FIFO interrupt mode operation
The following receiver status occurs when the receiver FIFO and receiver interrupts are enabled.
1.
2.
3.
4.
LSR0 is set when a character is transferred from the shift register to the receiver FIFO. When the
FIFO is empty, it is reset.
Receiver line status interrupt(IIR = 06) has higher priority than the receive data available interrupt(IIR
= 04).
Receive data available interrupt is issued to the CPU when the programmed trigger level is reached
by the FIFO. As soon as the FIFO drops below its programmed trigger level, it is cleared.
Receive data available indicator(IIR=04) also occurs when the FIFO reaches its trigger level. It is
cleared when the FIFO drops below the programmed trigger level.
The following receiver FIFO character time-out status occurs when receiver FIFO and receiver interrupts are
enabled.
1.
When the following conditions exist, a FIFO character time-out interrupt occurs.
a.
b.
c.
2.
Minimum of one character in FIFO.
Last received serial character is longer than four continuous previous character times ago. (If two
stop bits are programmed, the second one is included in the time delay. Only the first stop bit is
checked by the UART.)
The last CPU of the FIFO read is more than four continuous character times earlier.
By using the XTAL1 input for a clock signal, the character times can be calculated. The delay is
proportional to the baud rate.
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
3.
4.
The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received. This
occurs when there has been no time-out interrupt.
A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver
FIFO.
Transmit interrupts occurs as follows when the transmitter and transmit FIFO interrupts are enabled (FCR=0,
IER=1).
1.
2.
When the transmitter FIFO is empty, the transmitter holding register interrupt (IIR=02) occurs. The interrupt
is cleared when the transmitter holding register is written to or the IIR is read. 1 to 16 characters can be
written to the transmit FIFO when servicing this interrupt.
The transmitter FIFO empty indicators are delayed one character time minus the last stop bit time
whenever the following occurs.
THRE=1, and there has not been a minimum of two bytes at the same time in transmit FIFO since the last
THRE=1. The first transmitter interrupt after changing FCR0 is immediate, however, assuming it is enabled.
Receiver FIFO trigger level and character time-out interrupts have the same priority as the receive data
available interrupt. The transmitter holding register empty interrupt has the same priority as the transmitter FIFO
empty interrupt.
5.2. Line Control Register
The format of the data character is controlled by the LCR.
z
Bit 0, 1 : LCR0 and LCR1 are word length select bits. (see Figure 1)
z
Bit 2 : LCR2 is the stop bit select bit. The receiver always checks for one stop bit.
z
Bit 3 : LCR3 is the parity enable bit. When LCR3 is set, a parity bit is generated and checked.
z
Bit 4 : LCR4 is the even parity select bit. When LCR3 and this bit is set, even parity is generated and
checked. When LCR3 is set and this bit is cleared, odd parity is selected.
z
Bit 5 : LCR5 is the stick parity select bit. When LCR3 and this bit is set, the transmission and the
reception of a parity bit is forced to an opposite state from the value of LCR4. Clearing this bit
disenables the stick parity.
z
Bit 6 : LCR6 is a break control bit. When this bit is set, the serial outputs TXDxs are forced to ‘0’. The
break control bit acts only on the serial output and does not affect the transmitter logic. If the
following sequence is used, no invalid characters are transmitted because of the break.
z
1.
Load a zero byte in response to the transmitter holding register empty(THRE) status indicator.
2.
The next THRE signal in the response of the set the break.
3.
Wait for the transmitter to be idle, when transmitter empty status signal is set (TEMT=1) and
then clear the break, and start the normal transmission.
Bit 7 : LCR7 is the divisor latch access bit(DLAB). This bit must be set to access the divisor latches
DLL and DLM of the baud rate generator during a read or write operation. LCR7 must be cleared to
access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register.
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
Figure 1. Line Control Register
LCR
0
LCR
0
LCR
0
LCR
0
LCR
0
LCR
0
LCR
0
LCR
0
Word Length
Select
0
0
1
1
0
1
0
1
=
=
=
=
5
6
7
8
Data
Data
Data
Data
Bits
Bits
Bits
Bits
Stop Bit
Select
0 = 1 Stop Bit
1 = 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6,7,8 Data Bits Selected
0 = Parity Disabled
Parity Enable 1 = Parity Enabled
Even Parity
0 = Odd Parity
1 = Even Parity
Stick Parity
0 = Stick Parity Disabled
1 = Stick Parity Enabled
Break Control
0 = Break Disabled
1 = Break Enabled
Divisor Latch 0 = Access Receiver Buffer
1 = Access Divisor Latches
Access Bit
* Programmable Baud Generator
The UART contains a programmable Baud Generator that is capable of taking any clock input from DC to
16
14.7456MHz and dividing it by any divisor from 2 to 2 -1. 4MHz is the highest clock input recommended
when the divisor = 1. The output frequency of the baud generator is 16 x baud [divisor # = (frequency
input)/(baud rate X 16)]. Two 8-bit latches store the divisor in a 16-bit binary format. These Divisor Latches
must be loaded during initialization to ensure proper operation of the Baud Generator. (see Table 2.)
Table 2. Baud rates
This table provides decimal divisors to use with crystal frequencies of 1.8432MHz, 3.6864MHz, 7.3728MHz and 14.7456MHz. For baud
rates of 38400 and below, the error obtained is minimal. The accuracy of the desired baud rate is dependent on the frequency of the crystal. It
is not recommended using a divisor of zero.
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
Desired baud rate
50
75
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19.2K
38.4K
57.6K
115.2K
230.4K
460.8K
921.6K
1.8432MHz
2304
1536
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
-
Decimal divisor to generate 16 x Clock
3.6864MHz
7.3728MHz
4608
9216
3072
6144
1714
3428
1536
3072
768
1536
384
768
192
384
128
256
116
232
96
192
64
128
48
96
32
64
24
48
12
24
6
12
4
8
2
4
1
2
1
-
14.7456MHz
18432
12288
6856
6144
3072
1536
768
512
464
384
256
192
128
96
48
24
16
8
4
2
1
5.3. Line Status Register
This register provides status information to the CPU concerning the data transfer.
z
Bit 0 : Data Ready(DR) indicator. Bit 0 is set to a logic 1 whenever a complete incoming character has
been received and transferred into the Receiver Buffer Register or the FIFO. This bit is cleared by
reading all of the data in the Receiver Buffer Register of the FIFO.
z
Bit 1 : Overrun Error(OE) indicator. Bit 1 indicates that data in the Receiver Buffer Register was not
read by the CPU before the next character was transferred into the Receiver Buffer Register, thereby
destroying the previous character. This bit is set to a logic 1 when overrun occurs and cleared
whenever the CPU reads the contents of the Line Status Register. If the FIFO mode data continues to
fill the FIFO beyond the trigger level, an overrun error will occur only after the FIFO is full and the next
character has been completely received in the shift register. OE is indicated to the CPU as soon as it
happens. The character in the shift register is overwritten, but it is not transferred to the FIFO.
z
Bit 2 : Parity Error indicator. Bit 2 is set to a logic 1 upon detection of a parity error and is reset to a
logic 0 whenever CPU reads the contents of the Line Status Register. In the FIFO mode, this error is
revealed to CPU when its associated character is at the top of the FIFO.
z
Bit 3 : Framing Error indicator. Bit 3 indicates that the received character did not have a valid stop bit.
This bit is set to a logic 1 whenever the stop bit following the last data bit or parity bit is detected as a
logic 0 bit. It is reset to a logic 0 whenever CPU reads the contents of the Line Status Register. In the
FIFO mode, this error is revealed to CPU when its associated character is at the top of the FIFO.
When this error has been detected, CPU assumes it due to a next start bit, so it samples this start bit
twice and the take the data.
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
z
Bit 4 : Break Interrupt indicator. Bit 4 is set to a logic 1 when the received data input is held in the
spacing state for longer than a full word transmission time (start bit + data bits + parity bit + stop bits).
The BI indicator is reset to a logic 0 whenever the CPU reads the contents of the Line Status Register.
In the FIFO mode, this error is revealed to CPU when its associated character is at the top of the FIFO.
When break occurs, only one zero character is loaded into the FIFO. The next character transfer is
enabled after SIN goes HIGH and receives the next start bit.
z
Bit 5 : Transmitter holding register empty(THRE) indicator. Bit 5 indicates that the UART is ready to
take a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the
CPU when the Transmit Holding Register Empty interrupt enable is set to HIGH. This bit is set to a
logic 1 when a character is transferred from the Transmitter Holding Register into the Transmitter shift
register. And it is reset to a logic 0 when the CPU transfers data to the Transmitter Holding Register.
In the FIFO mode, this bit is set to a logic 1 when the XMIT FIFO is empty, and is reset to a logic 0
when at least one byte is written to the XMIT FIFO.
z
Bit 6 : Transmitter Empty indicator. This bit is set when the Transmitter Holding Register and
Transmitter Shift Register are both empty, and reset to a logic 0 when the THR contains a data
character. In the FIFO mode, it is set to a logic 1 when the both the Transmitter FIFO and the
Transmitter Shift Register are empty.
z
Bit 7 : In the 16450 mode, this bit is a 0. In the FIFO mode it is set to a logic 1 when it contains at
least one error such as parity error, framing error or break error. This bit is reset to a logic 0 when the
CPU reads the Line Status Register and there exists no error.
5.4. Interrupt Identification Register
In order to provide minimum software overhead during data transfer, the UART prioritizes interrupts into 4
levels and record these in the Interrupt Identification Register. The four levels of interrupt conditions are, in order
of priority:
z
Receiver Line Status
z
Received Data Ready
z
Transmitter Holding Register Empty
z
MODEM Status
When the CPU accesses the IIR, the UART freezes all interrupts and indicates the highest priority pending
interrupt to the CPU. While this CPU access is occurring, the UART records new interrupts, but does not change
its current indication until the access is complete.
Bit 0 : This bit can be used in a prioritized interrupt environment to indicate whether an interrupt is pending.
When bit 0 is a logic 0, an interrupt is pending and the IIR contents may be used as a pointer to the
appropriate interrupt service routine. When bit 0 is a logic 1, no interrupt is pending.
Bit 1, 2 : These two bits of the IIR are used to identify the highest priority interrupt pending as indicated in
Table 3.
Bit 3 : In the 16450 mode, this bit is 0. In the FIFO mode, this bit is set along with bit 2 when a time-out
interrupt is pending.
Bit 4, 5 : These two bits are always logic 0.
Bit 6, 7 : These two bits are set whenever FCR0 is a logic 1.
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
Table 3. Interrupt Control Function
FIFO
Interrupt Identification
mode
Register
Interrupt set / reset Function
only
Bit 3
Bit 2
Bit 1
Bit 0
Priority
Interrupt Type
Interrupt Source
Interrupt Reset Control
Level
0
0
0
1
-
-
-
-
0
1
1
0
1
Receiver Line
OE, PE, FE, BI
Reading the LSR
Status
0
1
0
0
2
Receiver Data
Receiver
Available
Trigger level reached
Character
No
Timeout
removed since the last transfer
Indication
and there was no transfer at
Data
Available
or
Reading the RBR or
the FIFO drops below
the trigger level
1
1
0
0
2
the
character
FIFO
has
during
been
the
Reading the RBR
4
character time.
0
0
1
0
3
Transmitter
Transmitter Holding Register
Reading
Holding
Empty
source
Register
0
0
0
0
4
of
IIR
(if
the
interrupt ) or writing
Empty
Modem Status
the
the THR
CTS, DSR, RI, DCD
Reading the MSR
5.5. Interrupt Enable Register
The IER independently enables the four serial channel interrupt sources that activate the interrupt( INT0, INT1,
INT2, INT3) output. All interrupts are disabled by clearing IER0-IER3 of the IER. Interrupts are enabled by setting
the appropriate bits of the IER. Disabling the interrupt system inhibits the IIR and the active high interrupt output.
All other system functions operate in their normal manner, including the setting of the LSR and MSR. The
contents of the IER are described in the following bulleted list.
z
Bit 0 : When IER0 is set, IER0 enables the received data available interrupt and the timeout interrupts
z
Bit 1 : When IER1 is set, the transmitter holding register empty interrupt is enabled.
z
Bit 2 : When IER2 is set, the receiver line status interrupt is enabled.
z
Bit 3 : When IER3 is set, the modem status interrupt is enabled.
z
Bit 4~7 : These bits are cleared.
in the FIFO mode.
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
5.6. Modem Control Register
The MCR controls the interface with the modem or data set as described in Figure 2. MCR can be written and
read. The RTS# and DTR# outputs are directly controlled by their control bits in this register. A high input
asserts a low signal at the output terminals. MCR bits 0-4 are shown as follows.
z
Bit 0 : When MCR0 is set, the DTR# output is forced low. When MCR0 is cleared, the DTR# output is
forced high. The DTR# output of the serial channel may be input into an inverting line driver in order
to obtain the proper polarity input at the modem or data set.
z
Bit 1 : When MCR1 is set, the RTS# output is forced to 0. When MCR1 is cleared, the RTS# output is
forced high. The DTR# output of the serial channel may be input into an inverting line driver in order
to obtain the proper polarity input at the modem or data set.
z
Bit 2 : MCR2 has no affect on operation.
z
Bit 3 : When MCR3 is set, the external serial channel interrupt is enabled.
z
Bit 4 : MCR4 provides a local loopback feature for diagnostic testing of the channel. When MCR4 is
set, serial output TXDx is set to the high state and SIN is disconnected. The output of the TSR is
looped back into the RSR input. The four modem control inputs (CTS#, DSR#, DCD#, RI#) are
disconnected. The modem control outputs (DTR#, RTS#) are internally connected to the four modem
control inputs. The modem control output terminals are forced to their inactive state on the IN16C554 .
In the diagnostic mode, data transmitted is immediately received. This allows the processor to verify
the transmit and receive data path of the selected serial channel. Interrupt control is fully operational;
however, interrupts are generated by controlling the lower four MCR bits internally. Interrupts are not
generated by activity on the external terminals represented by those four bits.
z
Bit 5~7 : These bits are permanently cleared.
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
5.7. Modem Status Register
The MSR provides the CPU with status of the modem input lines for the modem or peripheral devices. The
MSR allows the CPU to read the serial channel modem signal inputs by accessing the data bus interface of the
UART. It also reads the current status of four bits of the MSR that indicate whether the modem inputs have
changed since the last reading of the MSR. The delta status bits are set when a control input from the modem
changes states and are cleared when the CPU reads the MSR. The contents of the MSR are shown as follows.
z
Bit 0 : Delta Clear to Send(DCTS) indicator. DCTS indicates that the CTS# input to the serial channel
z
Bit 1 : Delta Data Set Ready(DDSR) indicator. DDSR indicates that the DSR# input to the serial
z
Bit 2 : Trailing Edge of Ring Indicator(TERI) indicator. TERI indicates that the RI# input to the serial
has changed state since it was last read by the CPU.
channel has changed state since it was last read by the CPU.
channel has changed states from low to high since the last time it was read by the CPU. High to low
transitions on RI do not activate TERI.
z
Bit 3 : Delta Data Carrier Detect(DDCD) indicator. DDCD indicates that the DCD# input to the serial
channel has changed state since it was last read by the CPU.
* note : An interrupt is generated whenever the bit0~3 of the MSR is set to a logic 1.
z
Bit 4 : Clear to Send bit. CTS is the complement of the CTS# input from the modem indicating to the
serial channel that the modem is ready to provice received data from the serial channel receiver
circuitry. When the channel is in the loop mode, MSR4 reflects the value of RTS in the MCR.
z
Bit 5 : Data Set Ready bit. DSR is the complement of the DSR# input from the modem to the serial
channel that indicates that the modem is ready to provide received data from the serial channel
receiver circuitry. When the channel is in the loop mode, MSR5 reflects the value of DTR in the MCR.
z
Bit 6 : Ring indicator bit. RI is the complement of the Rix# inputs. When the channel is in the loop
z
Bit 7 : Data Carrier Detect bit. Data carrier detect indicates the status of the data carrier detect input.
mode, MSR6 reflects the value of OUT1# in the MCR.
When the channel is In the loop mode, MSR7 reflects the value of OUT2# in the MCR.
5.8. Scratch Register
This 8-bit read/write register has no affect on either channel of the UART. It is intended to be used by the
programmer to hold data temporarily.
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
6. Package Diagram
DSR0#
10
11
CTS0#
DCD3#
RI3#
RXD3
INTN#
VCC
D0
D1
D2
D3
D4
D5
D6
D7
GND
RXD0
RI0#
DCD0#
IN16C554 PL PACKAGE (Top)
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60
DSR3#
59
CTS3#
58
DTR3#
VCC
12
13
57
GND
RTS0#
14
56
RTS3#
INT0
15
55
INT3
CS0#
16
17
54
CS3#
DTR0#
TXD0
47
VCC
24
46
DTR2#
CTS1#
25
45
CTS2#
DSR1#
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DSR2#
DCD1#
RI2#
GND
DTR1#
DCD2#
RTS2#
RXD2
48
23
GND
RTS1#
TXRDY#
INT2
RXRDY#
CS2#
49
XTAL2
50
21
22
RESET
20
INT1
XTAL1
CS1#
A1
A0
TXD2
A2
51
NC
TXD1
VCC
IOR#
RXD1
TXD3
52
RI1#
53
18
19
IOW#
NC - No internal connection
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
NC
DCD1#
RI1#
RXD1
VCC
A2
A0
A1
NC
XTAL1
XTAL2
NC
RESET
TXRDY#
RXRDY#
GND
RXD2
RI2#
DCD2#
NC
IN16C554 TQ PACKAGE (Top)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61
40
62
39
NC
DSR2#
CTS2#
NC
DSR1#
63
64
38
CTS1#
DTR2#
37
DTR1#
VCC
65
36
GND
RTS2#
66
35
RTS1#
INT2
67
68
34
INT1
33
CS1#
32
TXD1
IOR#
69
70
31
IOW#
NC
71
30
NC
TXD3
29
TXD0
CS3#
72
73
28
CS0#
INT3
74
27
INT0
RTS3#
75
26
RTS0#
GND
76
25
VCC
CS2#
TXD2
RI0#
NC
DCD0#
NC
GND
RXD0
D7
D6
D5
D4
21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
D3
80
D2
NC
NC
DSR0#
D0
D1
22
INTN#
79
VCC
CTS0#
DSR3#
RXD3
DTR0#
23
RI3#
24
78
DCD3#
77
CTS3#
NC
DTR3#
NC - No internal connection
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
7. Operating Conditions
7.1. General Operating Conditions, Standard Voltage (5V)
Supply Voltage, Vcc
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Clock high-level input voltage at XTAL1, VIH(CLK)
2
Vcc
V
Clock low-level input voltage at XTAL1, VIL(CLK)
-0.5
0.8
V
High-level input voltage, VIH
2.0
Vcc+0.5
V
Low-level input Voltage, VIL
-0.5
0.8
V
16
MHz
85
o
Clock frequency, fCLOCK
Operating free-air temperature, TA
-20
C
7.2. General Operating Conditions, Low Voltage (3.3V)
MIN
NOM
MAX
Supply Voltage, Vcc
3
3.3
3.6
UNIT
V
Clock high-level input voltage at XTAL1, VIH(CLK)
2
Vcc
V
Clock low-level input voltage at XTAL1, VIL(CLK)
-0.5
0.8
V
High-level input voltage, VIH
2.0
Vcc+0.5
V
Low-level input Voltage, VIL
-0.5
0.8
V
16
MHz
85
o
Clock frequency, fCLOCK
Operating free-air temperature, TA
7.3.
-20
C
Read cycle timing requirements over recommended ranges of operating free-air temperature and supply
voltage (See Fig 1.)
MIN
MAX
UNIT
trd
Pulse duration, IOR# low
75
ns
tcsr
Set up time, CSx# valid before IOR# low †
10
ns
tar
Set up time, A2~A0 valid before IOR# low †
15
ns
tra
Hold time, A2~A0 valid after IOR# high †
0
ns
trcs
Hold time, CSx# valid after IOR# high †
0
ns
tfrc
Delay time, tar+trd+trc ‡
140
ns
trc
Delay time, IOR# high to IOR# or IOW# low
50
ns
† The internal address strobe is always in active state.
‡ In the FIFO mode, td1=425ns (min) between reads of the FIFO and the status register.
7.4. Write cycle timing requirements over recommended ranges of operating free-air temperature and supply
voltage (See Fig 2.)
MIN
MAX
UNIT
twr
Pulse duration, IOW#↓
50
ns
tcsw
Setup time, CSx# valid before IOW#↓
10
ns
taw
Setup time, A2~A0 valid before IOW#↓
15
ns
tds
Setup time, D7~D0 valid before IOW#↑
10
ns
twa
Hold time, A2~A0 valid after IOW#↑
5
ns
twcs
Hold time, CSx# valid after IOW#↑
5
ns
tdh
Hold time, D7~D0 valid after IOW#↑
25
ns
tfwc
Delay time, taw+twr+twc
120
ns
twc
Delay time, IOW#↑ to IOW# or IOR#↓
55
ns
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
7.5. Read cycle switching characteristics over recommended ranges of operating free-air temperature and supply
voltage ( See Fig 1.)
MIN
trvd
Enable time, IOR#↓ to D7~D0 valid
thz
Disable time, IOR# to D7~D0 released
0
MAX
UNIT
30
ns
20
ns
7.6. Transmitter switching characteristics over recommended ranges of operating free-air temperature and supply
voltage (See Fig 3~5.)
MIN
MAX
UNIT
tirs
Delay time, INTx↓ to TXDx↓ at start
8
24
RCLK cycles
tsti
Delay time, TXDx↓ at start to INTx↑
8
8
RCLK cycles
tsi
Delay time, IOW# high or low (WR THR) to INTx↑
16
32
RCLK cycles
tsxa
Delay time, TXDx↓ at start to TXRDY#↓
8
RCLK cycles
thr
Propagation delay time, IOW#(WR THR)↓ to INTx↓
35
ns
tir
Propagation delay time, IOR#(RD IIR)↑ to INTx↓
30
ns
twxi
Propagation delay time, IOW#(WR THR)↑ to TXRDY#↑
50
ns
7.7. Receiver switching characteristics over recommended ranges of operating free-air temperature and supply
voltage (Fig 6~9.)
MAX
UNIT
1
RCLK cycle
Propagation delay time, Read RBR/LSR to INTx↓/LSR interrupt↓
40
ns
Propagation delay time, IOR# RCLK↓ to RXRDY#↑
40
ns
MIN
tsint
Delay time, stop bit to INTx↑ or stop bit to RXRDY# or read RBR to set interrupt
trint
trint
7.8. Modem control switching characteristics over recommended ranges of operating free-air temperature and
supply voltage (See Fig 10.)
MIN
MAX
UNIT
tmdo
Propagation delay time, IOW#(WR MCR)↑ to RTSx#, DTRx#↑
50
ns
tsim
Propagation delay time, modem input CTSx#, DSRx#, and DCDx#↓↑ to INTx↑
30
ns
trim
Propagation delay time, IOR#(RD MSR)↑ to interrupt↓
35
ns
tsim
Propagation delay time, Rix#↑ to INTx#↓
30
ns
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
A[2:0]
VALID ADDRESS
t ra
CSx#
t csr
t rcs
t frc
t ar
IOR#
ACTIVE
t rd
t rc
IOW#
t rvd
t hz
D[7:0]
VALID DATA
Fig 1. Read Cycle Timing
A[2:0]
VALID ADDRESS
t wa
CSx#
t csw
t wcs
t fwc
t aw
IOR#
t wr
t wc
IOW#
ACTIVE
t ds
D[7:0]
t dh
VALID DATA
Fig 2. Write Cycle Timing Waveforms
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
TXDx
START
DATA(5-8)
PARITY
STOP(1-2)
START
t irs
t sti
INTx
t hr
t si
t hr
IOW#
(WR THR)
t ir
IOR#
(RD IIR)
Fig 3. Transmitter Timing Waveforms
IOW#
(WR THR)
TXDx
BYTE #1
DATA
PARITY
STOP
START
TXRDY#
t wxi
t sxa
Fig 4. Transmitter Ready Mode 0 Timing Waveforms
IOW#
(WR THR)
TXDx
BYTE #16
DATA
PARITY
TXRDY#
STOP
START
FIFO FULL
t wxi
t sxa
Fig 5. Transmitter Ready Mode 1 Timing Waveforms
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
RXDx
START
DATA(5-8)
PARITY
STOP
Sample
Clock
(FIFO AT OR ABOVE
TRIGGER LEVEL)
INTx(TRIGGER
LEVEL INTERRUPT
(FCR6, 7 = 0, 0)
t sint
t rint
(FIFO BELOW
TRIGGER LEVEL)
LSI INTERRUPT
t rint
IOR#
(RD LSR)
IOR#
(RD RBR)
Fig 6. Receiver FIFO First Byte (Sets RDR) Waveforms
RXDx
STOP
Sample
Clock
(FIFO AT OR ABOVE
TRIGGER LEVEL)
TIMEOUT OR
TRIGGER LEVEL
INTERRUPT
t sint
LSI INTERRUPT
t rint
(FIFO BELOW
TRIGGER LEVEL)
TOP BYTE OF FIFO
t sint
IOR#
(RD LSR)
t rint
IOR#
(RD RBR)
PREVIOUS BYTE
READ FROM FIFO
Fig 7. Receiver FIFO After First Byte (After RDR Set) Waveforms
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
IOR#
(RD RBR)
RXDx
(FIRST BYTE)
STOP
Sample
Clock
RXRDY#
t sint
t rint
Fig 8. Receiver Ready Mode 0 Timing Waveforms
IOR#
(RD RBR)
RXDx
(FIRST BYTE THAT
REACHES THE
TRIGGER LEVEL)
STOP
Sample
Clock
RXRDY#
t sint
t rint
Fig 9. Receiver Ready Mode 1 Timing Waveforms
IOW#
(WR MCR)
t mdo
t mdo
RTSx#, DTRx#
CTSx#, DSRx#, DCDx#
INTx
t sim
t rim
t sim
t rim
t sim
IOR#
(RD MSR)
RIx#
Fig 10. Modem Control Timing Waveforms
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
* Typical Clock Circuits
XTAL1
External
Clock
XTAL1
R1
CRYSTAL
SB16C554
SB16C554
R2
XTAL2
Optional
Clock
Output
XTAL2
C1
Frequency Range (MHz)
C1 (pF)
1.8~8
8~16
C2
C2 (pF)
R1 (Ω)
R2(Ω)
10~30
40~60
1M
1.5K
10~22
33 ~ 47
1M
1.5K
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
8. Mechanical Data
PLCC(Plastic Leaded Chip Carrier) Package
0.469 (11,913)
0.441 (11,201)
0.18 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
0.02 (0,51) MIN
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
0.469 (11,913)
0.441 (11,201)
0.956 (24,282)
0.950 (24,130)
0.995 (25,273)
0.985 (25,019)
0.956 (24,282)
0.950 (24,130)
0.032 (0.081)
0.026 (0,66)
0.995 (25,273)
0.985 (25,019)
Note
1.
All dimensions are in inches (millimeters).
2.
Falls within ANSI Y14.5-1982
Rev. 01
IN16C554PL/IN16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NOVEMBER 2002-REVISED AUG 2006
TQFP(Thin Quad Flat Pack) Package
0,27
0,17
9,50
12,00
14,00
1,05
0,95
1,20 MAX
0,10
0,50
0,75
0,45
0-7
1.00
Note
1. All dimensions are in millimeters.
2. Falls within ANSI Y14.5-1982.
Rev. 01