ON MC33174D Low power, single supply operational amplifier Datasheet

Order this document by MC33171/D
DUAL
Quality bipolar fabrication with innovative design concepts are employed
for the MC33171/72/74 series of monolithic operational amplifiers. These
devices operate at 180 µA per amplifier and offer 1.8 MHz of gain bandwidth
product and 2.1 V/µs slew rate without the use of JFET device technology.
Although this series can be operated from split supplies, it is particularly
suited for single supply operation, since the common mode input voltage
includes ground potential (VEE). With a Darlington input stage, these devices
exhibit high input resistance, low input offset voltage and high gain. The all
NPN output stage, characterized by no deadband crossover distortion and
large output voltage swing, provides high capacitance drive capability,
excellent phase and gain margins, low open loop high frequency output
impedance and symmetrical source/sink AC frequency response.
The MC33171/72/74 are specified over the industrial/ automotive
temperature ranges. The complete series of single, dual and quad
operational amplifiers are available in plastic as well as the surface mount
packages.
• Low Supply Current: 180 µA (Per Amplifier)
•
•
•
•
•
•
•
•
•
•
•
•
8
8
1
1
P SUFFIX
PLASTIC PACKAGE
CASE 626
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
PIN CONNECTIONS
Offset Null
1
Inv. Input
2
Noninv. Input
3
VEE
4
Wide Supply Operating Range: 3.0 V to 44 V or ±1.5 V to ±22 V
–
+
8
NC
7
VCC
6
Output
5
Offset Null
(Single, Top View)
Wide Input Common Mode Range, Including Ground (VEE)
Output 1
Wide Bandwidth: 1.8 MHz
1
Inputs 1
High Slew Rate: 2.1 V/µs
8
2
–
+
3
Low Input Offset Voltage: 2.0 mV
VEE
Large Output Voltage Swing: –14.2 V to +14.2 V (with ±15 V Supplies)
1
7
2
6
–
+
4
VCC
Output 2
Inputs 2
5
(Top View)
Large Capacitance Drive Capability: 0 pF to 500 pF
Low Total Harmonic Distortion: 0.03%
Excellent Phase Margin: 60°C
Excellent Gain Margin: 15 dB
QUAD
Output Short Circuit Protection
ESD Diodes Provide Input Protection for Dual and Quad
14
14
1
1
P SUFFIX
PLASTIC PACKAGE
CASE 646
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
PIN CONNECTIONS
ORDERING INFORMATION
Op Amp
Function
Single
Dual
Quad
Device
MC33171D
MC33171P
Operating
Temperature Range
TA = –40° to +85°C
TA = –40° to +85°C
Output 1
Package
SO–8
Plastic DIP
MC33172D
MC33172P
TA = –40° to +85°C
TA = –40° to +85°C
SO–8
Plastic DIP
MC33174D
MC33174P
TA = –40° to +85°C
TA = –40° to +85°C
SO–14
Plastic DIP
Inputs 1
VCC
Inputs 2
Output 2
1
14
2
13
3
–
+
1
4
–
+
Inputs 4
12
4
11
5
10
6
+
2
–
3
7
+
–
Output 4
9
8
VEE
Inputs 3
Output 3
(Top View)
 Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
Rev 0
1
MC33171 MC33172 MC33174
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC/VEE
±22
V
VIDR
(Note 1)
V
Input Voltage Range
VIR
(Note 1)
V
Output Short Circuit Duration (Note 2)
tSC
Indefinite
sec
Operating Ambient Temperature Range
TA
–40 to +85
°C
TJ
+150
°C
Tstg
–65 to +150
°C
Supply Voltage
Input Differential Voltage Range
Operating Junction Temperature
Storage Temperature Range
NOTES: 1. Either or both input voltages must not exceed the magnitude of VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ)
is not exceeded.
Representative Schematic Diagram
(Each Amplifier)
VCC
Q3
Q4
Q5
Q6
Q7
Q1
Q17
Q2
R1
R2
C1
D2
Bias
–
Q8
Q9
Q10
Q18
R6
Q11
Inputs
R7
Output
R8
+
C2
D3
Q19
Q13
Q14
Q15
Q12
Q16
Current
Limit
D1
R5
R3
R4
VEE/Gnd
Offset Null
(MC33171)
2
MOTOROLA ANALOG IC DEVICE DATA
MC33171 MC33172 MC33174
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, RL connected to ground, TA = Tlow to Thigh [Note 3],
unless otherwise noted.)
Characteristics
Symbol
Input Offset Voltage (VCM = 0 V)
VCC = +15 V, VEE = –15 V, TA = +25°C
VCC = +5.0 V, VEE = 0 V, TA = +25°C
VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh
VIO
Average Temperature Coefficient of Offset Voltage
∆VIO/∆T
Input Bias Current (VCM = 0 V)
TA = +25°C
TA = Tlow to Thigh
IIB
Input Offset Current (VCM = 0 V)
TA = +25°C
TA = Tlow to Thigh
IIO
Large Signal Voltage Gain (VO = ±10 V< RL = 10 k)
TA = +25°C
TA = Tlow to Thigh
AVOL
Output Voltage Swing
VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = –15 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = –15 V, RL = 10 k, TA = Tlow to Thigh
VOH
VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = –15 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = –15 V, RL = 10 k, TA = Tlow to Thigh
VOL
Output Short Circuit (TA = +25°C)
Input Overdrive = 1.0 V, Output to Ground
Source
Sink
Input Common Mode Voltage Range
TA = +25°C
TA = Tlow to Thigh
Min
Typ
Max
—
—
—
2.0
2.5
—
4.5
5.0
6.5
—
10
—
—
—
20
—
100
200
—
—
5.0
—
20
40
50
25
500
—
—
—
3.5
13.6
13.3
4.3
14.2
—
—
—
—
—
—
—
0.05
–14.2
—
0.15
–13.6
–13.3
Unit
mV
µV/°C
nA
nA
V/mV
V
ISC
mA
3.0
15
5.0
27
—
—
VICR
V
VEE to (VCC –1.8)
VEE to (VCC –2.2)
Common Mode Rejection Ratio (RS ≤ 10 k) TA = +25°C
CMRR
80
90
—
dB
Power Supply Rejection Ratio (RS = 100 Ω) TA = +25°C
PSRR
80
100
—
dB
—
—
—
180
220
—
250
250
300
Power Supply Current (Per Amplifier)
VCC = +5.0 V, VEE = 0 V, TA = +25°C
VCC = +15 V, VEE = –15 V, TA = +25°C
VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh
NOTE: 3. Tlow = –40°C
µA
ID
Thigh = +85°C
MOTOROLA ANALOG IC DEVICE DATA
3
MC33171 MC33172 MC33174
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, RL connected to ground, TA = +25°C, unless otherwise noted.)
Symbol
Characteristics
Slew Rate (Vin = –10 V to +10 V, RL = 10 k, CL = 100 pF)
AV +1
AV –1
Min
Typ
Max
SR
Unit
V/µs
1.6
—
2.1
2.1
—
—
Gain Bandwidth Product (f = 100 kHz)
GBW
1.4
1.8
—
MHz
Power Bandwidth
AV = +1.0 RL = 10 k, VO = 20 Vpp, THD = 5%
BWp
—
35
—
kHz
—
—
60
45
—
—
—
—
15
5.0
—
—
Phase Margin
RL = 10 k
RL = 10 k, CL = 100 pF
φm
Gain Margin
RL = 10 k
RL = 10 k, CL = 100 pF
Am
Equivalent Input Noise Voltage
RS = 100 Ω, f = 1.0 kHz
en
—
32
—
nV/ √ Hz
Equivalent Input Noise Current (f = 1.0 kHz)
In
—
0.2
—
pA/ √ Hz
Rin
—
300
—
MΩ
Differential Input Resistance
Vcm = 0 V
Input Capacitance
Degree
s
dB
Ci
—
0.8
—
pF
THD
—
0.03
—
%
Channel Separation (f = 10 kHz)
CS
—
120
—
dB
Open Loop Output Impedance (f = 1.0 MHz)
zo
—
100
—
Ω
Figure 1. Input Common Mode Voltage Range
versus Temperature
0
Figure 2. Split Supply Output Saturation
versus Load Current
VCC/VEE = ±1.5 V to ± 22 V
∆VIO = 5.0 mV
VCC
Vsat , OUTPUT SATURATION VOLTAGE (V)
V ICR , INPUT COMMON MODE VOLTAGE RANGE (V)
Total Harmonic Distortion
AV = +10, RL = 10 k, 2.0 Vpp ≤ VO ≤ 20 Vpp, f = 10 kHz
–0.8
–1.6
–2.4
0.1
VEE
0
–55
4
–25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
0
VCC/VEE = ± 5.0 V to ± 22 V
TA = 25°C
VCC
–1.0
Source
1.0
Sink
0
VEE
0
1.0
2.0
3.0
IL, LOAD CURRENT (±mA)
4.0
MOTOROLA ANALOG IC DEVICE DATA
MC33171 MC33172 MC33174
20
Gain
1 Margin
= 15 dB
Phase
Margin
= 58°
10
2
VCC/VEE = ±15 V
RL = 10 k
Vout = 0 V
3
–10 TA = 25°C
1 — Phase
–20 2 — Phase, CL = 100 pF
3 — Gain
4 — Gain, CL = 100 pF
–30
100 k
1.0 M
f, FREQUENCY (Hz)
0
4
140
160
180
200
φ m, PHASE MARGIN (DEGREES)
70
120
70
60
50
40
30
%
20
10
10
0
10 M
10
20
50
100
200
CL, LOAD CAPACITANCE (pF)
500
0
1.0 k
Figure 6. Small and Large Signal
Transient Response
5.0 µs/DIV
GBW
1.1
50 mV/DIV
VCC/VEE = ±15 V
RL = 10 k
1.2
0
10 V/DIV
1.3
GBW AND SR (NORMALIZED)
20
220
Figure 5. Normalized Gain Bandwidth Product
and Slew Rate versus Temperature
0
VCC/VEE = ±15 V
VCM = 0 V
VO = 0 V
∆IO = ±0.5 mA
TA = 25°C
1.0
SR
0.9
0.8
0.7
–55
–25
0
25
50
75
100
125
5.0 µs/DIV
TA, AMBIENT TEMPERATURE (°C)
120
100
VCC/VEE = ±15 V
AV = +1.0
RL = 10 k
CL = 100 pF
TA = 25°C
80
Figure 8. Supply Current versus Supply Voltage
I D , I CC , POWER SUPPLY CURRENT (mA)
Figure 7. Output Impedance and Frequency
140
zo , OUTPUT IMPEDANCE (Ω )
60
VCC/VEE = ±15 V
50
AVOL = +1.0
RL = 10 k
∆VO = 20 mVpp
40
TA = 25°C
30
φm
%, PERCENT OVERSHOOT
3
0
Figure 4. Phase Margin and Percent
Overshoot versus Load Capacitance
φ , EXCESS PAHSE (DEGREES)
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
Figure 3. Open Loop Voltage Gain and
Phase versus Frequency
AV = 1000
AV = 100
60
40
AV = 10
AV = 1.0
20
0
200
2.0 k
20 k
f, FREQUENCY (Hz)
200 k
MOTOROLA ANALOG IC DEVICE DATA
2.0 M
1.1
1. TA = –55°C
2. TA = 25°C
0.9 3. TA = 125°C
1
Quad
2
3
0.7
Dual
1
2
3
Single
1
2
3
0.5
0.3
0.1
0
5.0
10
15
VCC/VEE, SUPPLY VOLTAGE (±V)
20
25
5
MC33171 MC33172 MC33174
APPLICATIONS INFORMATION – CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the
voltage to approach within millivolts of VEE. For sink currents
MC33171/72/74 amplifier family is similar to low power op
(> 0.4 mA), diode D3 clamps the voltage across R4. Thus the
amp products utilizing JFET input devices, these amplifiers
negative swing is limited by the saturation voltage of Q15,
offer additional advantages as a result of the PNP transistor
plus the forward diode drop of D3 (≈VEE +1.0 V). Therefore
differential inputs and an all NPN transistor output stage.
an unprecedented peak–to–peak output voltage swing is
Because the input common mode voltage range of this
possible for a given supply voltage as indicated by the output
input stage includes the VEE potential, single supply
swing specifications.
operation is feasible to as low as 3.0 V with the common
If the load resistance is referenced to VCC instead of
mode input voltage at ground potential.
ground for single supply applications, the maximum possible
The input stage also allows differential input voltages up to
output swing can be achieved for a given supply voltage. For
±44 V, provided the maximum input voltage range is not
light load currents, the load resistance will pull the output to
exceeded. Specifically, the input voltages must range
VCC during the positive swing and the output will pull the load
between VCC and VEE supply voltages as shown by the
resistance near ground during the negative swing. The load
maximum rating table. In practice, although not
resistance value should be much less than that of the
recommended, the input voltages can exceed the VCC
feedback resistance to maximize pull–up capability.
voltage by approximately 3.0 V and decrease below the VEE
Because the PNP output emitter–follower transistor has
voltage by 0.3 V without causing product damage, although
been eliminated, the MC33171/72/74 family offers a 15 mA
output phase reversal may occur. It is also possible to source
minimum current sink capability, typically to an output voltage
up to 5.0 mA of current from VEE through either inputs’
of (VEE +1.8 V). In single supply applications the output can
clamping diode without damage or latching, but phase
directly source or sink base current from a common emitter
reversal may again occur. If at least one input is within the
NPN transistor for current switching applications.
common mode input voltage range and the other input is
In addition, the all NPN transistor output stage is inherently
within the maximum input voltage range, no phase reversal
faster than PNP types, contributing to the bipolar amplifier’s
will occur. If both inputs exceed the upper common mode
improved gain bandwidth product. The associated high
input voltage limit, the output will be forced to its lowest
frequency low output impedance (200 Ω typ @ 1.0 MHz)
voltage state.
allows capacitive drive capability from 0 pF to 400 pF without
Since the input capacitance associated with the small
oscillation in the noninverting unity gain configuration. The
geometry input device is substantially lower (0.8 pF) than that
60°C phase margin and 15 dB gain margin, as well as the
of a typical JFET (3.0 pF), the frequency response for a given
general gain and phase characteristics, are virtually
input source resistance is greatly enhanced. This becomes
independent of the source/sink output swing conditions. This
evident in D–to–A current to voltage conversion applications
allows easier system phase compensation, since output
where the feedback resistance can form a pole with the input
swing will not be a phase consideration. The AC
capacitance of the op amp. This input pole creates a 2nd
characteristics of the MC33171/72/74 family also allow
Order system with the single pole op amp and is therefore
excellent active filter capability, especially for low voltage
detrimental to its settling time. In this context, lower input
single supply applications.
capacitance is desirable especially for higher values of
Although the single supply specification is defined at 5.0 V,
feedback resistances (lower current DACs). This input pole
these amplifiers are functional to at least 3.0 V @ 25°C.
can be compensated for by creating a feedback zero with a
However slight changes in parametrics such as bandwidth,
capacitance across the feedback resistance, if necessary, to
slew rate, and DC gain may occur.
reduce overshoot. For 10 kΩ of feedback resistance, the
If power to this integrated circuit is applied in reverse
MC33171/72/74 family can typically settle to within 1/2 LSB
polarity, or if the IC is installed backwards in a socket, large
of 8 bits in 4.2 µs, and within 1/2 LSB of 12 bits in 4.8 µs for
unlimited current surges will occur through the device that
a 10 V step. In a standard inverting unity gain fast settling
may result in device destruction.
configuration, the symmetrical slew rate is typically
As usual with most high frequency amplifiers, proper lead
± 2.1 V/µs. In the classic noninverting unity gain
dress, component placement and PC board layout should
configuration the typical output positive slew rate is also
be exercised for optimum frequency performance. For
2.1 V/µs, and the corresponding negative slew rate will
example, long unshielded input or output leads may result in
usually exceed the positive slew rate as a function of the fall
unwanted input/output coupling. In order to preserve the
time of the input waveform.
relatively low input capacitance associated with these
The all NPN output stage, shown in its basic form on the
amplifiers, resistors connected to the inputs should be
equivalent circuit schematic, offers unique advantages over
immediately adjacent to the input pin to minimize additional
the more conventional NPN/PNP transistor Class AB output
stray input capacitance. This not only minimizes the input
stage. A 10 kΩ load resistance can typically swing within 0.8 V
pole for optimum frequency response, but also minimizes
of the positive rail (VCC) and negative rail (VEE), providing a
extraneous “pick up” at this node. Supply decoupling with
28.4 Vpp swing from ±15 V supplies. This large output swing
adequate capacitance immediately adjacent to the supply pin
becomes most noticeable at lower supply voltages.
is also important, particularly over temperature, since many
The positive swing is limited by the saturation voltage of
types of decoupling capacitors exhibit great impedance
the current source transistor Q7, the VBE of the NPN pull–up
changes over temperature.
transistor Q17, and the voltage drop associated with the
The output of any one amplifier is current limited and thus
short circuit resistance, R5. For sink currents less than
protected from a direct short to ground. However, under such
0.4 mA, the negative swing is limited by the saturation
conditions, it is important not to allow the device to exceed
voltage of the pull–down transistor Q15, and the voltage drop
the maximum junction temperature rating. Typically for ±15 V
across R4 and R5. For small valued sink currents, the above
supplies, any one output can be shorted continuously to
voltage drops are negligible, allowing the negative swing
ground without exceeding the maximum temperature rating.
6
MOTOROLA ANALOG IC DEVICE DATA
MC33171 MC33172 MC33174
Figure 9. AC Coupled Noninverting Amplifier
with Single +5.0 V Supply
2.2 k
Figure 10. AC Coupled Inverting Amplifier
with Single +5.0 V Supply
VCC
510 k
VCC
3.8 Vpp
VO 0
CO
+
100 k
VO
–
RL
VO
–
100 k
10 k
Cin
1.0 k
CO
+
10 k
100 k
Vin
100 k
3.6 Vpp
VO 0
100 k
Cin
RL
100 k
Vin
AV = 101
BW ( –3.0 dB) = 20 kHz
AV = 10
BW ( –3.0 dB) = 200 kHz
Figure 11. DC Coupled Inverting Amplifier
Maximum Output Swing with Single
+5.0 V Supply
VCC
100 k
4.7 k
Figure 12. Offset Nulling Circuit
VCC
50 k
RL
+
3
2
VO
–
7
+
6
5
–
1
4
10 k
1.0 M
100 k
VEE
4.2 Vpp
V 2.5 V
Vin O
Offset Nulling range is approximately ±80 mV with
a 10 k potentiometer, MC33171 only.
AV = 10
BW ( –3.0 dB) = 200 kHz
Figure 13. Active High–Q Notch Filter
Figure 14. Active Bandpass Filter
VCC
fo = 30 kHz
Q = 10
HO = 1.0
Vin ≥ 0.2 Vdc
16 k
Vin
R
0.01
16 k
–
R1
1.1 k
VO
+
R
Vin
C
R2
5.6 k
2C
0.02
2R
32 k
2C
0.02
fo = 1.0 kHz
1
fo =
4 π RC
C
0.047
R3
2.2 k
–
C
0.047
VO
+
0.4
VCC
Then: R1 =
R3
2 HO
R2 =
R1 R3
4Q2R1 –R3
Qo fo
Q
Given fo = center frequency
R3 =
< 0.1
Ao = Gain at center frequency
π foC
GBW
Choose Value fo, Q, Ao, C
For less than 10% error for operational amplifier, where fo and GBW are expressed in Hz.
MOTOROLA ANALOG IC DEVICE DATA
7
MC33171 MC33172 MC33174
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
–B–
1
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
–A–
NOTE 2
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
–––
10_
0.76
1.01
4
L
C
J
–T–
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
–––
10_
0.030
0.040
N
SEATING
PLANE
D
M
K
G
H
0.13 (0.005)
M
T A
M
B
M
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE R
D
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
8
5
0.25
H
E
M
B
M
1
4
h
B
e
X 45 _
q
A
C
SEATING
PLANE
L
0.10
A1
B
0.25
8
M
C B
S
A
S
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.18
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
MOTOROLA ANALOG IC DEVICE DATA
MC33171 MC33172 MC33174
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
14
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
8
B
1
7
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
J
N
H
G
D
SEATING
PLANE
K
M
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14)
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
14
8
–B–
1
P 7 PL
0.25 (0.010)
7
G
M
F
–T–
D 14 PL
0.25 (0.010)
M
K
M
T B
S
MOTOROLA ANALOG IC DEVICE DATA
M
R X 45 _
C
SEATING
PLANE
B
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
9
MC33171 MC33172 MC33174
NOTES
10
MOTOROLA ANALOG IC DEVICE DATA
MC33171 MC33172 MC33174
NOTES
MOTOROLA ANALOG IC DEVICE DATA
11
MC33171 MC33172 MC33174
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51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
12
◊
*MC33171/D*
MOTOROLA ANALOG IC DEVICE
DATA
MC33171/D