Cypress CY7C1313BV18-200BZC 18-mbit qdr-ii sram 4-word burst architecture Datasheet

CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
PRELIMINARY
18-Mbit QDR™-II SRAM 4-Word Burst
Architecture
Features
Functional Description
• Separate Independent Read and Write data ports
— Supports concurrent transactions
• 250-MHz clock for high bandwidth
• 4-Word Burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 500 MHz) at 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in ×8, x9, ×18, and ×36 configurations
• Full data coherency providing most current data
• Core VDD = 1.8(+/-0.1V); I/O VDDQ = 1.4V to VDD)
• 15 × 17 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball
(11 × 15 matrix)
• Variable drive HSTL output buffers
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and
CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write port has dedicated Data Inputs to
support Write operations. QDR-II architecture has separate
data inputs and data outputs to completely eliminate the need
to “turn-around” the data bus required with common I/O
devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR-II Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 8-bit words (CY7C1311BV18) or 9-bit
words (CY7C1911BV18) or 18-bit words (CY7C1313BV18) or
36-bit words (CY7C1315BV18) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K and
K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
CY7C1311BV18–2M x 8
CY7C1911BV18–2M x 9
CY7C1313BV18–1M x 18
CY7C1315BV18–512K x 36
Cypress Semiconductor Corporation
Document Number: 38-05620 Rev. **
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised July 23, 2004
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
PRELIMINARY
Logic Block Diagram (CY7C1311BV18)
8
DOFF
Address
Register
Read Add. Decode
CLK
Gen.
512K x 8 Array
K
K
512K x 8 Array
19
512K x 8 Array
A(18:0)
Write Write Write Write
Reg
Reg
Reg Reg
512K x 8 Array
Address
Register
Write Add. Decode
D[7:0]
RPS
Control
Logic
C
C
Read Data Reg.
32
VREF
WPS
NWS[1:0]
CQ
CQ
16
Reg.
Control
Logic
A(18:0)
19
16
Reg.
Reg.
8
Q[7:0]
8
Logic Block Diagram (CY7C1911BV18)
DOFF
VREF
WPS
BWS[0]
Address
Register
Read Add. Decode
CLK
Gen.
512K x 9 Array
K
K
512K x 9 Array
19
Write Write Write Write
Reg
Reg
Reg Reg
512K x 9 Array
Address
Register
512K x 9 Array
A(18:0)
9
Write Add. Decode
D[8:0]
RPS
Control
Logic
C
C
Read Data Reg.
36
Control
Logic
CQ
CQ
18
Reg.
18
Reg.
Reg.
9
9
Document Number: 38-05620 Rev. **
A(18:0)
19
Q[8:0]
Page 2 of 23
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
PRELIMINARY
Logic Block Diagram (CY7C1313BV18)
DOFF
Address
Register
Read Add. Decode
CLK
Gen.
256K x 18 Array
K
K
256K x 18 Array
18
Write Write Write Write
Reg
Reg
Reg Reg
256K x 18 Array
Address
Register
256K x 18 Array
A(17:0)
18
Write Add. Decode
D[17:0]
18
RPS
Control
Logic
C
C
Read Data Reg.
72
VREF
WPS
CQ
CQ
36
Reg.
Control
Logic
BWS[1:0]
A(17:0)
36
Reg.
Reg.
18
18
Q[17:0]
Logic Block Diagram (CY7C1315BV18)
DOFF
VREF
WPS
BWS[3:0]
Address
Register
Read Add. Decode
CLK
Gen.
128K x 36 Array
K
K
128K x 36 Array
17
Write Write Write Write
Reg
Reg
Reg Reg
128K x 36 Array
Address
Register
128K x 36 Array
A(16:0)
36
Write Add. Decode
D[35:0]
17
RPS
Control
Logic
C
C
Read Data Reg.
144
Control
Logic
CQ
CQ
72
Reg.
72
A(16:0)
Reg.
Reg.
36
36 Q
[35:0]
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
250
200
167
MHz
Maximum Operating Current
TBD
TBD
TBD
mA
Document Number: 38-05620 Rev. **
Page 3 of 23
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
PRELIMINARY
Pin Configurations
CY7C1311BV18 (2M × 8)–15 × 17 FBGA
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/72M
A
WPS
NWS1
K
NC/144M
RPS
A
NC/36M
CQ
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
NC
NC
NC
NC
D4
NC
NC
NC/288M
A
VSS
K
NC
VSS
NWS0
A
VSS
A
VSS
VSS
NC
NC
NC
A
VSS
VSS
NC
NC
NC
Q3
D3
NC
R
NC
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
Q2
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
DOFF
NC
D5
VREF
NC
Q5
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
VDDQ
NC
NC
VREF
Q1
NC
ZQ
D1
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q0
NC
NC
NC
D7
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
D0
NC
NC
NC
Q7
A
A
C
A
A
NC
NC
NC
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
CY7C1911BV18 (2M × 9)–15 × 17 FBGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
7
8
9
10
11
CQ
NC/72M
A
WPS
NC
K
NC/144M
RPS
A
NC/36M
CQ
NC
NC
NC
A
NC/288M
K
BWS0
A
NC
NC
Q4
NC
NC
NC
D5
NC
VSS
VSS
A
VSS
NC
VSS
A
VSS
VSS
VSS
NC
NC
NC
NC
D4
NC
NC
NC
NC
Q5
VDDQ
VSS
VSS
VSS
VDDQ
NC
D3
Q3
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
DOFF
NC
D6
VREF
NC
Q6
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
VDDQ
NC
NC
VREF
Q2
NC
ZQ
D2
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
Q7
D7
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q1
NC
NC
NC
D8
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
D1
NC
NC
NC
Q8
A
A
C
A
A
NC
D0
Q0
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Document Number: 38-05620 Rev. **
Page 4 of 23
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
PRELIMINARY
Pin Configurations (continued)
CY7C1313V18 (1M × 18)–15 × 17 FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
2
3
NC/144M NC/36M
4
5
WPS
A
NC
Q9
D9
NC
NC
D10
NC
D11
Q10
VSS
VSS
NC
NC
Q11
VDDQ
9
10
11
RPS
A
NC/72M
CQ
A
NC
NC
Q8
Q7
D8
VSS
VSS
VSS
NC
NC
NC
D7
VSS
VDDQ
NC
D6
Q6
6
7
8
BWS1
K
NC/288M
NC
K
BWS0
A
NC
A
VSS
VSS
VSS
VSS
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
D5
DOFF
NC
VREF
NC
VDDQ
D14
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
NC
VREF
Q4
ZQ
D4
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
NC
NC
NC
D17
D16
Q16
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
Q1
NC
D2
D1
NC
NC
Q17
A
A
C
A
A
NC
D0
Q0
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
9
10
CY7C1315AV18 (512K × 36)–15 × 17FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
2
3
NC/288M NC/72M
4
5
6
7
8
WPS
BWS2
K
BWS1
RPS
BWS3
A
K
D17
Q17
Q8
VSS
VSS
D16
VSS
BWS0
A
VSS
A
NC
VSS
Q16
Q7
D15
D8
D7
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
11
NC/36M NC/144M
CQ
Q27
Q18
D18
A
D27
D28
Q28
D20
D19
Q19
VSS
VSS
Q29
D29
Q20
VDDQ
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
D30
D22
VREF
Q31
Q22
VDDQ
D23
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
Q13
VDDQ
D12
D13
VREF
Q4
D5
ZQ
D4
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
D33
D34
Q34
D26
D25
Q25
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
D10
Q10
Q1
D9
D2
D1
Q35
D35
Q26
A
A
C
A
A
Q9
D0
Q0
A
A
A
A
TMS
TDI
DOFF
D31
TDO
TCK
A
Document Number: 38-05620 Rev. **
C
A
Page 5 of 23
PRELIMINARY
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
InputData input signals, sampled on the rising edge of K and K clocks during valid write operaSynchronous tions.
CY7C1311BV18 − D[7:0]
CY7C1911BV18 − D[8:0]
CY7C1313BV18 − D[17:0]
CY7C1315BV18 − D[35:0]
WPS
InputWrite Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,
Synchronous a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port
will cause D[x:0] to be ignored.
NWS0,
NWS1,
InputNibble Write Select 0, 1 − active LOW.(CY7C1311BV18 Only) Sampled on the rising edge of
Synchronous the K and K clocks during Write operations. Used to select which nibble is written into the device
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select will cause the corresponding nibble of data to be ignored and not written into the
device.
BWS0, BWS1,
InputByte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocks
BWS2, BWS3 Synchronous during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1911BV18 − BWS0 controls D[8:0]
CY7C1313BV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1315BV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A
InputAddress Inputs. Sampled on the rising edge of the K clock during active Read and Write operaSynchronous tions. These address inputs are multiplexed for both Read and Write operations. Internally, the
device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1311BV18, 2M x 9 (4 arrays
each of 512K x 9) for CY7C1911BV18,1M x 18 (4 arrays each of 256K x 18) for CY7C1313BV18
and 512K x 36 (4 arrays each of 128K x 36) for CY7C1315BV18. Therefore, only 19 address
inputs are needed to access the entire memory array of CY7C1311BV18 and CY7C1911BV18,
18 address inputs for CY7C1313BV18 and 17 address inputs for CY7C1315BV18. These inputs
are ignored when the appropriate port is deselected.
Q[x:0]
OutputsData Output signals. These pins drive out the requested data during a Read operation. Valid
Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K and
K. when in single clock mode. When the Read port is deselected, Q[x:0] are automatically
tri-stated.
CY7C1311BV18 − Q[7:0]
CY7C1911BV18 − Q[8:0]
CY7C1313BV18 − Q[17:0]
CY7C1315BV18 − Q[35:0]
RPS
InputRead Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When
Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
tri-stated following the next rising edge of the C clock. Each Read access consists of a burst of
four sequential transfers.
C
InputClock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
C
InputClock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
K
InputClock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
InputClock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[x:0] when in single clock mode.
Document Number: 38-05620 Rev. **
Page 6 of 23
PRELIMINARY
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Pin Definitions (continued)
I/O
Pin Description
CQ
Pin Name
Echo Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized to the
output clock (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
CQ
Echo Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized to the
output clock (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
VDD, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DOFF
Input
DLL Turn Off - active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
More details on this operation can be found in the application note, “DLL Operation in the QDR-II.”
TDO
Output
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/36M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/72M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/144M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/288M
VREF
VDD
VSS
VDDQ
N/A
InputReference
TDO for JTAG.
Not connected to the die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and outputs
as well as AC measurement points.
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
Functional Overview
The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18,
CY7C1315BV18 are synchronous pipelined Burst SRAMs
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-II completely eliminates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design. Each access
consists of four 8-bit data transfers in the case of
CY7C1311BV18, four 9-bit data transfers in the case of
CY7C1911BV18, four 18-bit data transfers in the case of
CY7C1313BV18, and four 36-bit data in the case of
CY7C1315BV18 transfers in two clock cycles.
Accesses for both ports are initiated on the Positive Input
Clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the output clocks (C and C or K and K when
in single clock mode).
Document Number: 38-05620 Rev. **
All synchronous data inputs (D[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q[x:0]) outputs pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single-clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C1313BV18 is described in the following sections. The
same basic descriptions apply to CY7C1311BV18,
CY7C1911BV18, and CY7C1315BV18.
Read Operations
The CY7C1313BV18 is organized internally as 4 arrays of
256K x 18. Accesses are completed in a burst of four
sequential 18-bit data words. Read operations are initiated by
asserting RPS active at the rising edge of the Positive Input
Clock (K). The address presented to Address inputs are stored
in the Read address register. Following the next K clock rise,
the corresponding lowest order 18-bit word of data is driven
onto the Q[17:0] using C as the output timing reference. On the
subsequent rising edge of C the next 18-bit data word is driven
onto the Q[17:0]. This process continues until all four 18-bit data
Page 7 of 23
PRELIMINARY
words have been driven out onto Q[17:0]. The requested data
will be valid 0.45 ns from the rising edge of the output clock (C
or C or (K or K when in single-clock mode)). In order to
maintain the internal logic, each read access must be allowed
to complete. Each Read access consists of four 18-bit data
words and takes 2 clock cycles to complete. Therefore, Read
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Read request. Read accesses can be initiated on
every other K clock rise. Doing so will pipeline the data flow
such that data is transferred out of the device on every rising
edge of the output clocks (C and C or K and K when in
single-clock mode).
When the read port is deselected, the CY7C1313BV18 will first
complete the pending Read transactions. Synchronous
internal circuitry will automatically tri-state the outputs
following the next rising edge of the Positive Output Clock (C).
This will allow for a seamless transition between devices
without the insertion of wait states in a depth expanded
memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored
into the lower 18-bit Write Data register, provided BWS[1:0] are
both asserted active. On the subsequent rising edge of the
Negative Input Clock (K) the information presented to D[17:0]
is also stored into the Write Data register, provided BWS[1:0]
are both asserted active. This process continues for one more
cycle until four 18-bit words (a total of 72 bits) of data are
stored in the SRAM. The 72 bits of data are then written into
the memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Write request. Write accesses can be initiated on
every other rising edge of the Positive Input Clock (K). Doing
so will pipeline the data flow such that 18 bits of data can be
transferred into the device on every rising edge of the input
clocks (K and K).
When deselected, the Write port will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1313BV18.
A Write operation is initiated as described in the Write Operations section above. The bytes that are written are determined
by BWS0 and BWS1, which are sampled with each set of 18-bit
data words. Asserting the appropriate Byte Write Select input
during the data portion of a Write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1313BV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
Document Number: 38-05620 Rev. **
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
the user must tie C and C HIGH at power on. This function is
a strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1313BV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the transaction on the other port. If the ports access the same location
when a Read follows a Write in successive clock cycles, the
SRAM will deliver the most recent information associated with
the specified address location. This includes forwarding data
from a Write cycle that was initiated on the previous K clock
rise.
Read accesses and Write access must be scheduled such that
one transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on
the previous state of the SRAM. If both ports were deselected,
the Read port will take priority. If a Read was initiated on the
previous cycle, the Write port will assume priority (since Read
operations can not be initiated on consecutive cycles). If a
Write was initiated on the previous cycle, the Read port will
assume priority (since Write operations can not be initiated on
consecutive cycles). Therefore, asserting both port selects
active from a deselected state will result in alternating
Read/Write operations being initiated, with the first access
being a Read.
Depth Expansion
The CY7C1313BV18 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the QDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are free running
clocks and are synchronized to the output clock of the QDR-II.
In the single clock mode, CQ is generated with respect to K
and CQ is generated with respect to K. The timings for the
echo clocks are shown in the AC Timing table.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. The DLL can also be reset by slowing the cycle time
of input clocks K and K to greater than 30 ns.
Page 8 of 23
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
PRELIMINARY
Application Example[1]
SRAM #1
R
P
S
#
Vt
D
A
R
W
P
S
#
B
W
S
#
R = 250ohms
SRAM #4
ZQ
CQ/CQ#
Q
C C# K K#
R
P
S
#
D
A
DATA IN
DATA OUT
Address
RPS#
BUS
WPS#
MASTER
BWS#
(CPU CLKIN/CLKIN#
or
Source K
ASIC)
Source K#
R
W
P
S
#
B
W
S
#
ZQ R = 250ohms
CQ/CQ#
Q
C C# K K#
Vt
Vt
Delayed K
Delayed K#
R
R = 50ohms Vt = Vddq/2
Truth Table[2, 3, 4, 5, 6, 7]
Operation
K
L-H
Write Cycle:
Load address on the rising
edge of K; input write data on
two consecutive K and K
rising edges.
L-H
Read Cycle:
Load address on the rising
edge of K; wait one and a
half cycle; read data on two
consecutive C and C rising
edges.
NOP: No Operation
L-H
Standby: Clock Stopped
Stopped
RPS
H[8]
WPS
L[9]
DQ
D(A) at
K(t+1) ↑
DQ
D(A + 1) at
K(t+1) ↑
DQ
DQ
D(A + 2) at K(t + D(A + 3) at
2) ↑
K(t +2) ↑
L[9]
X
Q(A) at
C(t +1)↑
Q(A + 1) at
C(t + 2) ↑
Q(A + 2) at C(t Q(A + 3) at C(t
+ 2)↑
+ 3) ↑
H
H
X
X
D=X
D=X
D=X
D=X
Q = High-Z
Q = High-Z
Q = High-Z
Q = High-Z
Previous State Previous State Previous State Previous State
Write Cycle Descriptions CY7C1311BV18 and CY7C1313BV18)
BWS0/NWS0 BWS1/NWS1 K
L
L
L–H
L
L
–
[2, 10]
K
–
Comments
During the Data portion of a Write sequence:
CY7C1311BV18 − both nibbles (D[7:0]) are written into the device,
CY7C1313BV18 − both bytes (D[17:0]) are written into the device.
L-H During the Data portion of a Write sequence:
CY7C1311BV18 − both nibbles (D[7:0]) are written into the device,
CY7C1313BV18 − both bytes (D[17:0]) are written into the device.
Notes:
1. The above application shows four QDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. “t” represents the cycle at which a Read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the
“t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will
ignore the second Read or Write request.
10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS0, NWS1, BWS0, BWS1, BWS2 and BWS3 can be altered on different
portions of a Write cycle, as long as the set-up and hold requirements are achieved.
Document Number: 38-05620 Rev. **
Page 9 of 23
PRELIMINARY
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Write Cycle Descriptions CY7C1311BV18 and CY7C1313BV18) (continued)[2, 10]
BWS0/NWS0 BWS1/NWS1 K
L
H
L–H
L
H
H
L
H
L
H
H
H
H
K
–
Comments
During the Data portion of a Write sequence :
CY7C1311BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will
remain unaltered,
CY7C1313BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will
remain unaltered.
– L–H During the Data portion of a Write sequence :
CY7C1311BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will
remain unaltered,
CY7C1313BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will
remain unaltered.
L–H – During the Data portion of a Write sequence :
CY7C1311BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will
remain unaltered,
CY7C1313BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will
remain unaltered.
– L–H During the Data portion of a Write sequence :
CY7C1311BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will
remain unaltered,
CY7C1313BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will
remain unaltered.
L–H – No data is written into the devices during this portion of a write operation.
– L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions[2, 10](CY7C1315BV18)
BWS0 BWS1 BWS2 BWS3
L
L
L
L
K
L–H
K
–
L
L
L
L
–
L–H
L
H
H
H
L–H
–
L
H
H
H
–
L–H
H
L
H
H
L–H
–
H
L
H
H
–
L–H
H
H
L
H
L–H
–
H
H
L
H
–
L–H
H
H
H
L
L–H
H
H
H
L
–
L–H
H
H
H
H
H
H
H
H
L–H
–
–
L–H
Comments
During the Data portion of a Write sequence, all four bytes (D[35:0]) are written
into the device.
During the Data portion of a Write sequence, all four bytes (D[35:0]) are written
into the device.
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] will remain unaltered.
No data is written into the device during this portion of a write operation.
No data is written into the device during this portion of a write operation.
Write Cycle Descriptions[2, 10] (CY7C1911BV18)
BWS0
L
L
H
H
K
L–H
–
L–H
–
K
–
L–H
–
L–H
During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device.
During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device.
No data is written into the device during this portion of a write operation.
No data is written into the device during this portion of a write operation.
Document Number: 38-05620 Rev. **
Page 10 of 23
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
PRELIMINARY
Maximum Ratings
Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V
(Above which the useful life may be impaired.)
Latch-up Current..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with Power Applied .... –10°C to +85°C
Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V
DC Applied to Outputs in High-Z .........–0.5V to VDDQ + 0.3V
Range
Ambient
Temperature (TA)
VDD[15]
VDDQ[15]
0°C to +70°C
1.8 ± 0.1V
1.4V to VDD
Com’l
DC Input Voltage[14] ............................ –0.5V to VDDQ + 0.3V
Current into Outputs (LOW) .........................................20 mA
DC Electrical Characteristics Over the Operating Range[11]
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Power Supply Voltage
1.7
1.8
1.9
V
VDDQ
I/O Supply Voltage
1.4
1.5
VDD
V
VOH
Output HIGH Voltage
Note 12
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
Output LOW Voltage
Note 13
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOH(LOW)
Output HIGH Voltage
IOH = −0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
VOL(LOW)
Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VSS
0.2
V
VIH
Input HIGH Voltage[14]
VREF + 0.1
VDDQ + 0.3
V
VIL
Input LOW Voltage[14]
–0.3
VREF – 0.1
V
IX
Input Load Current
GND ≤ VI ≤ VDDQ
−5
5
µA
IOZ
Output Leakage Current
GND ≤ VI ≤ VDDQ, Output Disabled
−5
5
µA
VREF
Input Reference Voltage[16]
Typical Value = 0.75V
0.95
V
IDD
VDD Operating Supply
VDD = Max., IOUT = 0 mA, 167 MHz
f = fMAX = 1/tCYC
200 MHz
TBD
mA
TBD
mA
250 MHz
TBD
mA
167 MHz
Max. VDD, Both Ports
Deselected, VIN ≥ VIH or 200 MHz
VIN ≤ VIL
250 MHz
f = fMAX = 1/tCYC,
Inputs Static
TBD
mA
TBD
mA
TBD
mA
ISB1
Automatic
Power-down
Current
0.68
0.75
Notes:
11. All Voltage referenced to Ground.
12. Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.
13. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.
14. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2).
15. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
16. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.
Document Number: 38-05620 Rev. **
Page 11 of 23
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
PRELIMINARY
AC Electrical Characteristics Over the Operating Range
Min.
Typ.
Max.
Unit
VIH
Parameter
Input High (Logic 1) Voltage
Description
Test Conditions
VREF + 0.2
–
–
V
VIL
Input Low (Logic 0) Voltage
–
–
VREF – 0.2
V
Switching Characteristics Over the Operating Range[17, 18]
250 MHz
Cypress Consortium
Parameter Parameter
Description
Min.
[21]
200 MHz
Max.
Min.
167 MHz
Max.
Min.
6.3
6.0
8.4
ns
1
Unit
VDD(Typical) to the First Access
1
tCYC
tKHKH
K Clock and C Clock Cycle Time
4.0
5.25
5.0
tKH
tKHKL
Input Clock (K/K; C/C) HIGH
1.6
–
2.0
2.4
–
ns
tKL
tKLKH
Input Clock (K/K; C/C) LOW
1.6
–
2.0
–
2.4
–
ns
tKHKH
tKHKH
K Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge)
1.8
–
2.2
–
2.7
–
ns
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to
rising edge)
0.0
1.8
0.0
2.2
0.0
2.7
ns
tPOWER
1
Max.
ms
Set-up Times
tSA
tSA
Address Set-up to K Clock Rise
0.5
–
0.6
–
0.7
–
ns
tSC
tSC
Control Set-up to Clock (K, K) Rise (RPS, WPS)
0.5
–
0.6
–
0.7
–
ns
tSCDDR
tSC
Double Data Rate Control Set-up to Clock (K, K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.35
–
0.4
–
0.5
–
ns
tSD
tSD
D[X:0] Set-up to Clock (K/K) Rise
0.35
–
0.4
–
0.5
–
ns
tHA
tHA
Address Hold after Clock (K/K) Rise
0.5
–
0.6
–
0.7
–
ns
tHC
tHC
Control Hold after Clock (K /K) Rise (RPS, WPS)
0.5
–
0.6
–
0.7
–
ns
tHCDDR
tHC
Double Data Rate Control Hold after Clock (K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.35
–
0.4
–
0.5
–
ns
tHD
tHD
D[X:0] Hold after Clock (K/K) Rise
0.35
–
0.4
–
0.5
–
ns
Hold Times
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to
Data Valid
–
0.45
–
0.45
–
0.50
ns
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise
(Active to Active)
–0.45
–
-0.45
–
-0.50
–
ns
tCCQO
tCHCQV
C/C Clock Rise to Echo Clock Valid
–
0.45
–
0.45
–
0.50
ns
tCQOH
tCHCQX
Echo Clock Hold after C/C Clock Rise
–0.45
–
–0.45
–
–0.50
–
ns
tCQD
tCQHQV
Echo Clock High to Data Valid
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
tCHZ
tCHZ
Clock (C and C) Rise to High-Z (Active to
High-Z)[19, 20]
tCLZ
tCLZ
Clock (C and C) Rise to Low-Z[19, 20]
–
0.30
–
0.35
–
0.40
ns
–0.30
–
–0.35
–
–0.40
–
ns
–
0.45
–
0.45
–
0.50
ns
–0.45
–
–0.45
–
–0.50
–
ns
Notes:
17. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
18. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
19. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
20. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
21. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation
can be initiated.
Document Number: 38-05620 Rev. **
Page 12 of 23
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
PRELIMINARY
Switching Characteristics Over the Operating Range[17, 18] (continued)
250 MHz
Cypress Consortium
Parameter Parameter
Description
200 MHz
167 MHz
Min.
Max.
Min.
Max.
Min.
Max.
Unit
–
0.20
–
0.20
–
0.20
ns
–
1024
–
1024
–
cycles
DLL Timing
tKC Var
tKC Var
Clock Phase Jitter
tKC lock
tKC lock
DLL Lock Time (K, C)
1024
tKC Reset
tKC Reset
K Static to DLL Reset
30
30
30
ns
Thermal Resistance[22]
Parameter
Description
Test Conditions
165 FBGA
Package
Unit
ΘJA
Thermal Resistance
Test conditions follow standard test methods and procedures for
(Junction to Ambient) measuring thermal impedance, per EIA/JESD51.
TBD
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
TBD
°C/W
Capacitance[22]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CO
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 1.8V
VDDQ = 1.5V
Max.
Unit
TBD
pF
TBD
pF
TBD
pF
AC Test Loads and Waveforms
VREF = 0.75V
VREF
0.75V
VREF
OUTPUT
Z0 = 50Ω
Device
Under
Test
VREF = 0.75V
ZQ
RQ =
250Ω
(a)
RL = 50Ω
0.75V
R = 50Ω
ALL INPUT PULSES
1.25V
0.75V
OUTPUT
Device
Under ZQ
Test
Including jig
and scope
5 pF
RQ =
250 Ω
[14]
0.25V
Slew Rate = 2V / ns
(b)
Note:
22. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05620 Rev. **
Page 13 of 23
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
PRELIMINARY
Switching Waveforms[23, 24, 25]
Read/Write/Deselect Sequence
NOP
1
READ
2
WRITE
3
READ
4
WRITE
5
NOP
6
7
K
tKH
t KL
t CYC
tKHKH
K
RPS
tSC
tSC
tHC
tHC
WPS
A0
A
t SA
A1
A2
A3
t HD
t HA
t HD
t SD
D
Q
Qx2
Qx3
t SD
D10
D11
D12
D13
D30
D31
D32
D33
Q00
Q01
Q02
Q03
Q20
Q21
Q22
Q23
tCO
tKHCH
t CLZ
tDOH
t CO
tDOH
t CHZ
tCQDOH
tCQD
C
tKHCH
tCYC
tKH
tKHKH
t KL
C
t CCQO
t CQOH
CQ
t CCQO
t CQOH
CQ
DON’T CARE
UNDEFINED
Notes:
23. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
24. Output are disabled (High-Z) one clock cycle after a NOP.
25. In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 38-05620 Rev. **
Page 14 of 23
PRELIMINARY
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 1.8V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
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TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port—Test Clock
Boundary Scan Register
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document Number: 38-05620 Rev. **
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
Page 15 of 23
PRELIMINARY
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.
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The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tristate”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 38-05620 Rev. **
Page 16 of 23
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PRELIMINARY
TAP Controller State Diagram[26]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
SHIFT-IR
0
1
0
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-IR
EXIT2-DR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Note:
26. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 38-05620 Rev. **
Page 17 of 23
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PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
TDI
2
1
0
1
0
Selection
Circuitry
Instruction Register
31 30 29
.
.
2
TDO
Identification Register
106 .
.
.
.
2
1
0
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[11, 14, 27]
Parameter
Description
Test Conditions
Min.
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.4
VOH2
Output HIGH Voltage
IOH = −100 µA
1.6
VOL1
Output LOW Voltage
IOL = 2.0 mA
IOL = 100 µA
Max.
Unit
V
V
0.4
V
VOL2
Output LOW Voltage
0.2
V
VIH
Input HIGH Voltage
0.65VDD
VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
0.35VDD
V
IX
Input and Output Load Current
–5
5
µA
GND ≤ VI ≤ VDD
TAP AC Switching Characteristics Over the Operating Range [28, 29]
Parameter
Description
Min.
Max.
Unit
20
MHz
tTCYC
TCK Clock Cycle Time
50
tTF
TCK Clock Frequency
ns
tTH
TCK Clock HIGH
40
ns
tTL
TCK Clock LOW
40
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
10
ns
tTDIS
TDI Set-up to TCK Clock Rise
10
ns
tCS
Capture Set-up to TCK Rise
10
ns
tTMSH
TMS Hold after TCK Clock Rise
10
ns
tTDIH
TDI Hold after Clock Rise
10
ns
tCH
Capture Hold after Clock Rise
10
ns
Hold Times
Notes:
27. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
28. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
29. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document Number: 38-05620 Rev. **
Page 18 of 23
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PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range [28, 29] (continued)
Parameter
Description
Min.
Max.
Unit
20
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
0
ns
TAP Timing and Test Conditions[29]
0.9V
ALL INPUT PULSES
1.8V
0.9V
50Ω
0V
TDO
Z0 = 50Ω
CL = 20 pF
GND
tTH
(a)
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Identification Register Definitions
Value
Instruction Field
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Revision Number
(31:29)
000
000
000
000
Description
Version
number.
Cypress Device ID 11010011011000101 11010011011001101 11010011011010101 11010011011100101 Defines the
(28:12)
type of SRAM.
Cypress JEDEC
ID (11:1)
ID Register
Presence (0)
00000110100
00000110100
00000110100
00000110100
Allows unique
identification of
SRAM vendor.
1
1
1
1
Indicates the
presence of an
ID register.
Document Number: 38-05620 Rev. **
Page 19 of 23
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PRELIMINARY
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
107
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register
between TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register
between TDI and TDO. Forces all SRAM output drivers to a High-Z
state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output ring contents. Places the boundary scan
register between TDI and TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does
not affect SRAM operation.
Boundary Scan Order
Boundary Scan Order (continued)
Bit #
Bump ID
Bit #
Bump ID
0
6R
23
9J
1
6P
24
9K
2
6N
25
10J
3
7P
26
11J
4
7N
27
11H
5
7R
28
10G
6
8R
29
9G
7
8P
30
11F
8
9R
31
11G
9
11P
32
9F
10
10P
33
10F
11
10N
34
11E
12
9P
35
10E
13
10M
36
10D
14
11N
37
9E
15
9M
38
10C
16
9N
39
11D
17
11L
40
9C
18
11M
41
9D
19
9L
42
11B
20
10L
43
11C
21
11K
44
9B
22
10K
45
10B
Document Number: 38-05620 Rev. **
Page 20 of 23
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PRELIMINARY
Boundary Scan Order (continued)
Boundary Scan Order (continued)
Bit #
Bump ID
Bit #
Bump ID
46
11A
90
3L
47
Internal
91
1M
48
9A
92
1L
49
8B
93
3N
50
7C
94
3M
51
6C
95
1N
52
8A
96
2M
53
7A
97
3P
54
7B
98
2N
55
6B
99
2P
56
6A
100
1P
57
5B
101
3R
58
5A
102
4R
59
4A
103
4P
60
5C
104
5P
61
4B
105
5N
62
3A
106
5R
63
1H
64
1A
65
2B
66
3B
67
1C
68
1B
69
3D
70
3C
71
1D
72
2C
73
3E
74
2D
75
2E
76
1E
77
2F
78
3F
79
1G
80
1F
81
3G
82
2G
83
1J
84
2J
85
3K
86
3J
87
2K
88
1K
89
2L
Document Number: 38-05620 Rev. **
Page 21 of 23
CY7C1311BV18
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PRELIMINARY
Ordering Information
Speed
(MHz)
Package
Name
Ordering Code
250
CY7C1311BV18-250BZC
Operating
Range
Package Type
BB165E
15 x 17 x 1.4 mm FBGA
Commercial
BB165E
15 x 17x 1.4 mm FBGA
Commercial
BB165E
15 x 17 x 1.4 mm FBGA
Commercial
CY7C1911BV18-250BZC
CY7C1313BV18-250BZC
CY7C1315BV18-250BZC
200
CY7C1311BV18-200BZC
CY7C1911BV18-200BZC
CY7C1313BV18-200BZC
CY7C1315BV18-200BZC
167
CY7C1311BV18-167BZC
CY7C1911BV18-167BZC
CY7C1313BV18-167BZC
CY7C1315BV18-167BZC
Package Diagram
165-Ball FBGA (15 x 17 x 1.40 mm) Pkg. Outline (0.50 Ball Dia.) BB165E
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
+0.14
(165X)
-0.06
Ø0.50
1
2
3
4
5
6
7
8
9
10
11
11
10
9
8
7
6
4
3
2
1
A
B
B
C
C
1.00
A
D
D
F
F
G
G
J
14.00
E
17.00±0.10
E
H
H
J
K
L
L
7.00
K
M
M
N
N
P
P
R
R
A
1.00
10.00
0.15 C
0.41±0.05
0.53±0.05
5.00
0.25 C
5
B
15.00±0.10
0.15(4X)
SEATING PLANE
1.40 MAX.
0.36
C
51-85195-**
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT,NEC, and Samsung
technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document Number: 38-05620 Rev. **
Page 22 of 23
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress.
PRELIMINARY
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Document History Page
Document Title: CY7C1311BV18/CY7C1911BV18/CY7C1313BV18/CY7C1315BV18 18-Mbit QDR™-II SRAM 4-Word
Burst Architecture
Document Number: 38-05620
REV.
ECN NO.
ISSUE
DATE
**
252474
See ECN
Document Number: 38-05620 Rev. **
ORIG. OF
CHANGE DESCRIPTION OF CHANGE
SYT
New Data Sheet
Page 23 of 23

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