A5979 Microstepping DMOS Driver with Translator FEATURES AND BENEFITS • • • • • • • • • • • • ±2.8 A, 40 V output rating Low RDS(on) outputs, 0.22 Ω source, 0.15 Ω sink typical Automatic current decay mode detection/selection 3 to 5.5 V logic supply voltage range Mixed, fast, and slow current decay modes Home output Synchronous rectification for low power dissipation Internal UVLO and thermal shutdown circuitry Crossover-current protection Short-to-ground protection Short-to-VBB protection Shorted load protection Package: 28-lead TSSOP (suffix LP) with exposed thermal pad DESCRIPTION The A5979 is a complete microstepping motor driver with built-in translator. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step modes, with output drive capability of 40 V and ±2.8 A. The A5979 includes a fixed off-time current regulator that has the ability to operate in slow-, fast-, or mixed-decay modes. This current-decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. The translator is the key to the easy implementation of the A5979. Simply inputting one pulse on the STEP input drives the motor one step (two logic inputs determine if it is a full-, half-, quarter-, or sixteenth-step). There are no phase sequence tables, high-frequency control lines, or complex interfaces to program. The A5979 interface is an ideal fit for applications where a complex microprocessor is unavailable or overburdened. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover-current protection. Special power-up sequencing is not required. The A5979 is supplied in a thin (<1.2 mm) 28-pin TSSOP with an exposed thermal pad (suffix LP). The package is lead (Pb) free (suffix -T), with 100% matte-tin leadframe plating. Not to scale Typical Application Logic Supply CP1 VDD CP2 VCP REF PFD Load Supply VBB1 VBB2 Microcontroller or Controller Logic HOMEn STEP DIR RESETn SLEEPn ENABLEn MS1 MS2 SR RC1 RC2 VREG A5979-DS, Rev. 2 A5979 OUT1A OUT1B SENSE1 SENSE2 OUT2A OUT2B GND PGND 100 µF A5979 Microstepping DMOS Driver with Translator SELECTION GUIDE Part Number Package Packing A5979GLPTR-T 28-pin TSSOP 4000 pieces per reel SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Load Supply Voltage VBB Logic Supply Voltage VDD Logic Input Voltage Range SENSEx Voltage (DC) VIN 40 V 7 V Pulsed, tW > 30 ns –0.3 to VDD + 0.3 V Pulsed, tW < 30 ns –1 to VDD + 1 V VSENSE 0.5 V Reference Voltage VREF VDD V Output Current IOUT ±2.8 A –40 to 105 °C Operating Ambient Temperature TA Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Range G Junction Temperature TJ(max) 150 °C Storage Temperature Tstg –55 to 150 °C THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information Characteristic Symbol Package Thermal Resistance RθJA Test Conditions* Package LP, on 4-layer PCB based on JEDEC standard Value Units 28 ºC/W *Additional thermal information available on Allegro website. Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A5979 Microstepping DMOS Driver with Translator PINOUT DIAGRAM AND TERMINAL LIST TABLE Terminal List Table Number Name 1 SENSE1 Sense resistor for bridge 1 25 OUT1B 2 HOMEn Logic output PFD 5 24 CP2 3 DIR RC1 6 23 CP1 4 OUT1A 28 VBB1 SENSE1 1 27 SLEEPn HOMEn 2 26 ENABLEn DIR 3 OUT1A 4 AGND 7 PAD 22 VCP Description Logic input DMOS full-bridge 1, output A REF 8 21 PGND 5 PFD Analog input for mixed-decay setting RC2 9 20 VREG 6 RC1 Analog input for fixed off-time, bridge 1 VDD 10 19 STEP 7 AGND* 8 REF Gm reference input Analog input for fixed off-time, bridge 2 OUT2A 11 18 OUT2B MS2 12 17 RESETn MS1 13 16 SR SENSE2 14 15 VBB2 Package LP, 28-Pin TSSOP Analog ground 9 RC2 10 VDD 11 OUT2A 12 MS2 Logic input 13 MS1 Logic input 14 SENSE2 15 VBB2 Logic supply voltage DMOS full-bridge 2, output A Sense resistor for bridge 2 Load supply for bridge 2 16 SR Logic input 17 RESETn Logic input 18 OUT2B DMOS full-bridge 2, output B 19 STEP Logic input 20 VREG Regulator decoupling 21 PGND* Power ground 22 VCP Reservoir capacitor 23 CP1 Charge pump capacitor 24 CP2 Charge pump capacitor 25 OUT1B 26 ENABLEn DMOS full-bridge 1, output B Logic input 27 SLEEPn Logic input 28 VBB1 Load supply for bridge 1 – PAD* Thermal pad * GND, PGND, and thermal pad must be connected together externally under the device. Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A5979 Microstepping DMOS Driver with Translator FUNCTIONAL BLOCK DIAGRAM CP1 VREG Logic Supply VDD UVLO Charge Pump Regulator SENSE1 Reference Supply REF CP2 VCP Load Supply VBB1 DAC ÷8 RC1 DMOS H-BRIDGE 4 STEP DIR PWM Timer PWM Latch Blanking Mixed Decay RESETn MS1 Translator OUT1A OUT1B SENSE1 MS2 HOMEn 4 SLEEPn Control Logic SR Gate Drive SENSE1 VBB2 ENABLEn DMOS H-BRIDGE RC2 PWM Timer PWM Latch Blanking Mixed Decay VDD OUT2A OUT2B DAC SENSE2 PFD AGND PGND Exposed Thermal Pad (Required) Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 A5979 Microstepping DMOS Driver with Translator ELECTRICAL CHARACTERISTICS1: Valid at TA = 25°C, VBB = 40 V, unless otherwise noted Characteristics Symbol Load Supply Voltage Range VBB Output Leakage Current IDSS Output On-Resistance Body Diode Forward Voltage VBB Supply Current VDD Supply Current RDS(On) VF IBB IDD Test Conditions Min. Typ.2 Max. Units Operating 8 – 40 V During sleep mode 0 – 40 V VOUT = VBB – <1 20 µA VOUT = 0 V – <1 –20 µA Source driver, IOUT = –2.5 A, TJ = 25°C – 0.22 0.30 Ω Sink driver, IOUT = 2.5 A, TJ = 25°C – 0.15 0.24 Ω Source diode, IF = –2.5 A – 1 1.4 V Source diode, IF = 2.5 A – 1 1.4 V fPWM < 50 kHz, duty cycle = 50% – – 8 mA Operating, outputs disabled – – 6 mA Sleep mode – <1 20 μA fPWM < 50 kHz, duty cycle = 50% – – 12 mA Operating, outputs disabled – – 10 mA Sleep mode – <1 20 μA V Control Logic Logic Supply Voltage Range Logic Input Voltage Logic Input Current Maximum Step Frequency3 HOMEn Output Voltage Blank Time Fixed Off-Time Reference Input Voltage Range Reference Input Current Gain (Gm) Error4 3 – 5.5 VIN(1) 0.7× VDD – – V VIN(0) – – 0.3 ×VDD V VDD Operating IIN(1) VIN = 0.7 × VDD –20 <1 20 µA IIN(0) VIN = 0.3 × VDD –20 <1 20 µA 500 – – kHz VOH IOH = –200 µA 0.7× VDD – – V VOL IOL = 200 µA fSTEP – – 0.3 ×VDD V tBLANK RT = 56 kΩ, CT = 680 pF 700 950 1200 ns tOFF RT = 56 kΩ, CT = 680 pF 30 38 46 μs Operating 0 – VDD V – – ±3 μA VREF = 2 V, phase current = 100.0% – – ±5 % VREF = 2 V, phase current = 70.7% – – ±5 % VREF = 2 V, phase current = 38.3% – – ±10 % 100 475 800 ns 20 – 120 ns VREFx IREF EG Crossover Dead Time tDT Motor Output Slew Time tSR 10% to 90% rising; 90% to 10% falling Continued on the next page... Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 A5979 Microstepping DMOS Driver with Translator ELECTRICAL CHARACTERISTICS1 (continued): Valid at TA = 25°C, VBB = 40 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ.2 Max. Units 2.45 2.7 2.95 V Protection Circuits VBB rising VDD UVLO Threshold VUV(VBB) VDD UVLO Hysteresis VUV(VBB)HYS 50 100 – mV IOCPST 3.5 – – A tLATCHOFF(OC) – 1.6 – ms tBLANK(OC) – 1.5 – µs TJSD 155 165 175 °C TJSDHYS – 15 – °C Overcurrent Protection Threshold Overcurrent Latch-Off Time Overcurrent Protection Blank Time Thermal Shutdown Temperature Thermal Shutdown Hysteresis 1 Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 2 Negative current is defined as coming out of (sourcing from) the specified device pin. 3 4 Operation at a step frequency greater than the specified minimum value is possible but not warranteed. EG = ( [ VREF / 8] – VSENSE ) / ( VREF / 8 ). Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A5979 Microstepping DMOS Driver with Translator tA tB STEP tC tD MSx, RESETn, or DIR t WU SLEEPn Time Duration Symbol Typ. Unit STEP Minimum, high pulse width tA 1 µs STEP Minimum, low pulse width tB 1 µs Setup time, input change to STEP tC 200 ns Hold time, input change to STEP tD 200 ns tWU 1 ms Maximum wakeup time Figure 1: Logic Interface Timing Diagram Table 1: Microstep Resolution Truth Table MS2 MS1 Microstep Resolution Excitation Mode L L Full Step 2 Phase L H Half Step 1-2 Phase H L Quarter Step W1-2 Phase H H Sixteenth Step 4W1-2 Phase Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 A5979 Microstepping DMOS Driver with Translator FUNCTIONAL DESCRIPTION Device Operation The A5979 is a complete microstepping motor driver with builtin translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step modes. The current in each of the two output full-bridges, all N-channel DMOS, is regulated with fixed off-time pulse-width modulated (PWM) control circuitry. The full-bridge current at each step is set by the value of an external current-sense resistor (RS), a reference voltage (VREF), and the output voltage of its DAC (which in turn is controlled by the output of the translator). At power-up, or reset, the translator sets the DACs and phase current polarity to the initial home state (see figures for homestate conditions), and sets the current regulator for both phases to mixed-decay mode. When a step command signal occurs on the STEP input, the translator automatically sequences the DACs to the next level (see Table 2 for the current level sequence and current polarity). The microstep resolution is set by inputs MS1 and MS2 as shown in Table 1. If the new DAC output level is lower than the previous level, the decay mode for that full-bridge will be set by the PFD input (fast, slow, or mixed decay). If the new DAC level is higher or equal to the previous level, then the decay mode for that full-bridge will be slow decay. This automatic current-decay selection will improve microstepping performance by reducing the distortion of the current waveform due to the motor BEMF. When stepping, if the new output levels of the DACs are higher than or equal to their previous levels, then the decay mode for that full-bridge is set to slow. If the new output levels of the DACs are lower than their previous output levels, then the decay mode for that full-bridge is set by the state of the PFD input (see PFD input description). This automatic current decay selection improves microstepping performance by reducing the distortion of the current waveform that results from the back-EMF of the motor. See Figure 6 on page 14 for decay mode detail. Internal PWM Current Control Each full-bridge is controlled by a fixed off-time PWM currentcontrol circuit that limits the load current to an appropriate level (ITRIP). Initially, a diagonal pair of source and sink DMOS outputs are enabled, and current flows through the motor wind- ing and the current-sense resistor, RS. When the voltage across RS rises to the DAC output voltage, the current-sense comparator resets the PWM latch, which turns off the source driver (in slowdecay mode) or the sink and source drivers (in fast- or mixeddecay mode). The maximum level of current limiting is set by the selection of RS and the voltage at the VREF input with a transconductance function approximated by: ITRIPmax = VREF / (8 × RS) The DAC output reduces the VREF output to the current-sense comparator in precise steps (see Table 2 for % ITRIPmax at each step). ITRIP = (% ITRIPmax / 100) × ITRIPmax It is critical to ensure that the maximum rating on the SENSE terminal is not exceeded (0.5 V). For full-step mode, VREF can be applied up to the maximum rating of VDD, because the peak sense value is 0.707 × VREF / 8. In all other modes, VREF should not exceed 4 V. Fixed Off-Time The internal PWM current-control circuitry uses a one-shot to control the time that the drivers remain off. The one-shot offtime, tOFF, is determined by the selection of an external resistor (RT) and capacitor (CT) connected between the RC timing terminal and ground. The off-time, over a range of values of CT = 470 pF to 1500 pF and RT = 12 kΩ to 100 kΩ is approximated by: tOFF = RT × CT RC Blanking In addition to the fixed off-time of the PWM control circuit, the CT component sets the comparator blanking time. This function blanks the output of the current-sense comparator when the outputs are switched by the internal current-control circuitry. The comparator output is blanked to prevent false overcurrent detection due to reverse-recovery currents of the clamp diodes, and/ or switching transients related to the capacitance of the load. The blank time, tBLANK, can be approximated by: tBLANK = 1400 × CT Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 A5979 Microstepping DMOS Driver with Translator Step Input (STEP) Home Output (HOMEn) A low-to-high transition on the STEP input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the state of inputs MS1 and MS2 (see Table 1). The HOMEn output is a logic output indicator of the initial state of the translator. At power-up, the translator is reset to the home state (see figures for home state conditions), and the HOMEn output will be low. When the translator is not in the home state, this output is high. Microstep Select (MS1 and MS2) Synchronous Rectification Input terminals MS1 and MS2 select the microstepping format per Table 1. Changes to these inputs do not take effect until the STEP command. When a PWM off-cycle is triggered by an internal current control, load current will recirculate according to the decay mode selected by the control logic. The A5979 synchronous rectification feature will turn on the appropriate MOSFETs during the current decay and effectively short out the body diodes with the low RDS(ON) driver. This will reduce power dissipation significantly and eliminate the need for external Schottky diodes for most applications. Direction Input (DIR) The state of the DIR input will determine the direction of rotation of the motor. Percent Fast-Decay Input (PFD) When a STEP input command results in a lower output current than the previous step, it switches the output current decay for that bridge to either slow-, fast-, or mixed-decay, depending on the voltage level at the PFD input. If the voltage at the PFD input is greater than 0.6 × VDD, then slow-decay is selected. If the voltage on the PFD input is less than 0.21 × VDD, then fast-decay is selected. Mixed-decay is selected when the voltage on the PFD input is between these two levels. This terminal should be decoupled with a 0.1 µF capacitor. Mixed-Decay Operation If the voltage on the PFD input is between 0.6 × VDD and 0.21 × VDD, the bridge will operate in mixed-decay mode when a STEP input command results in a lower output current that the previous step. As the trip point is reached, the bridge will go into fastdecay mode until the voltage on the RC terminal decays to the voltage applied to the PFD terminal. The time the bridge remains in fast-decay is approximated by: tFD = RT × CT × In (0.6 × VDD / VPFD) After this fast-decay portion, tFD, the bridge will switch to slowdecay mode for the remainder of the fixed off-time period. Reset Input (RESETn) The RESETn input (active low) sets the translator to a predefined home state (see figures for home state conditions) and turns off all of the DMOS outputs. The HOMEn output goes low and all STEP inputs are ignored until the RESETn input goes high. The synchronous rectification can be set in either active mode or disabled mode using the SR pin. Synchronous Rectification Mode (SR) When the SR input is logic-low, active mode is enabled and synchronous rectification will occur. Reversal of the current in the motor winding is prevented when using this mode by turning off synchronous rectification if the current in the winding decays to zero. When the SR input is logic-high, synchronous rectification is disabled. Synchronous rectification is typically disabled only when external diodes are required to transfer power dissipation from the A5979 package to the external diodes. Enable Input (ENABLEn) This active-low input enables all of the DMOS outputs. When logic-high, the outputs are disabled. Inputs to the translator (STEP, DIR, MS1, MS2) are all active independent of the ENABLEn input state. Sleep Mode (SLEEPn) This active-low input is used to minimize power consumption when the device is not in use. Sleep mode disables much of the internal circuitry, including the output DMOS, regulator, and charge pump. A logic-high allows normal operation and a rising edge on this input resets the translator to the home position. When coming out of sleep mode, 1 ms is required before issuing a STEP command, to allow the charge pump to stabilize. Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A5979 Microstepping DMOS Driver with Translator Charge Pump (CP1 and CP2) The charge pump is used to generate a gate supply greater than VBB to drive the source-side DMOS gates. A 0.22 µF ceramic capacitor is required between CP1 and CP2, and a 0.22 µF ceramic capacitor is required between VCP and VBB. VCP is internally monitored, and in the case of a fault condition, the outputs of the device are disabled. VREG This internally generated voltage is used to operate the sink-side DMOS gates. The VREG terminal should be decoupled with a 0.22 µF capacitor to ground. VREG is internally monitored, and in the case of a fault condition, the outputs of the device are disabled. Shutdown In the event of a fault (excessive junction temperature, or low voltage on VCP or VREG), the outputs of the device are disabled until the fault condition is removed. At power-up, and in the event of low VDD, the undervoltage lockout (UVLO) circuit disables the drivers and resets the translator to the home position. Overcurrent Protection (OCP) If any FET’s current exceeds IOCP for longer than the blank time, all FETs are disabled for 1.6 ms. RSENSE is not required for lowside OCP to function and the OCP threshold is independent of the RSENSE value. 10 Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A5979 Microstepping DMOS Driver with Translator PHASE CURRENT DIAGRAMS IOUT2(A→B) 2 70% 1 IOUT1(A→B) 70% 4 3 Figure 2: Full Step MS2 = L, MS1 = L, DIR = H. See Table 2 for step number detail. IOUT2(A→B) 3 4 70% 2 5 70% 1 IOUT1(A→B) 8 6 7 Figure 3: Half Step MS2 = L, MS1 = H, DIR = H. See Table 2 for step number detail. 11 Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A5979 Microstepping DMOS Driver with Translator IOUT2(A→B) 5 7 70% 3 9 1 70% IOUT1(A→B) 15 11 13 Figure 4: Quarter Step MS2 = H, MS1 = L, DIR = H. See Table 2 for step number detail. IOUT2(A→B) 17 25 70% 9 33 70% 1 IOUT1(A→B) 57 41 49 Figure 5: Sixteenth Step MS2 = H, MS1 = H, DIR = H. See Table 2 for step number detail. 12 Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A5979 Microstepping DMOS Driver with Translator Table 2: Step Sequencing Settings DIR = H; 360° = 4 full steps; home microstep position at step angle 45º Full Step # Half Step # 1 1/4 Step # 1 2 1* 2* 3* 4 3 5 6 2 4 7 8 1/16 Step # 1 Phase 1 Current [% ItripMax] (%) 100.0 Phase 2 Current Half Step # 5 1/4 Step # 9 Phase 2 Current (%) 0.0 5.6 34 -99.5 -9.8 185.6 [% ItripMax] Full Step # Phase 1 Current Step Angle (º) 0.0 1/16 Step # 33 [% ItripMax] -100.0 (%) 0.0 (%) [% ItripMax] Step Angle (º) 180.0 2 99.5 9.8 3 98.1 19.5 11.3 35 -98.1 -19.5 191.3 4 95.7 29.0 16.9 36 -95.7 -29.0 196.9 5 92.4 38.3 22.5 37 -92.4 -38.3 202.5 10 6 88.2 47.1 28.1 38 -88.2 -47.1 208.1 7 83.1 55.6 33.8 39 -83.1 -55.6 213.8 40 -77.3 -63.4 219.4 41 -70.7 -70.7 225.0 8 77.3 63.4 39.4 9* 70.7* 70.7* 45.0* 10 63.4 77.3 50.6 42 -63.4 -77.3 230.6 3 6 11 11 55.6 83.1 56.3 43 -55.6 -83.1 236.3 12 47.1 88.2 61.9 44 -47.1 -88.2 241.9 13 38.3 92.4 67.5 45 -38.3 -92.4 247.5 12 14 29.0 95.7 73.1 46 -29.0 -95.7 253.1 15 19.5 98.1 78.8 47 -19.5 -98.1 258.8 16 9.8 99.5 84.4 48 -9.8 -99.5 264.4 17 0.0 100.0 90.0 49 0.0 -100.0 270.0 18 -9.8 99.5 95.6 50 9.8 -99.5 275.6 19 -19.5 98.1 101.3 51 19.5 -98.1 281.3 20 -29.0 95.7 106.9 52 29.0 -95.7 286.9 21 -38.3 92.4 112.5 53 38.3 -92.4 292.5 7 13 14 22 -47.1 88.2 118.1 54 47.1 -88.2 298.1 23 -55.6 83.1 123.8 55 55.6 -83.1 303.8 24 -63.4 77.3 129.4 56 63.4 -77.3 309.4 25 -70.7 70.7 135.0 57 70.7 -70.7 315.0 26 -77.3 63.4 140.6 58 77.3 -63.4 320.6 27 -83.1 55.6 146.3 59 83.1 -55.6 326.3 28 -88.2 47.1 151.9 60 88.2 -47.1 331.9 29 -92.4 38.3 157.5 61 92.4 -38.3 337.5 4 8 15 16 30 -95.7 29.0 163.1 62 95.7 -29.0 343.1 31 -98.1 19.5 168.8 63 98.1 -19.5 348.8 32 -99.5 9.8 174.4 64 99.5 -9.8 354.4 * Home state; HOMEn output low. 13 Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A5979 Microstepping DMOS Driver with Translator Slow Decay Current Decay Mode Full-Step Winding Current 0A Current Decay Mode Slow Decay Set by PFD Input Slow Decay Set by PFD Input Slow Decay Set by PFD Input Slow Decay Half-Step Winding Current 0A Current Decay Mode Slow Decay Set by PFD Input Slow Decay Set by PFD Input Slow Decay Set by PFD Input Slow Decay Quarter-Step Winding Current 0A Figure 6: Automatic Decay Mode 14 Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A5979 Microstepping DMOS Driver with Translator PACKAGE OUTLINE DRAWING 0.45 9.70 ±0.10 28 +0.05 0.15 –0.06 0.65 28 4° ±4 1.65 B 3.00 4.40 ±0.10 6.40 ±0.20 A 1 6.10 (1.00) 2 5.00 0.25 28X SEATING PLANE 0.10 C +0.05 0.25 –0.06 3.00 0.60 ±0.15 0.65 C SEATING PLANE GAUGE PLANE 1 2 5.00 C PCB Layout Reference View 1.20 MAX 0.10 MAX For reference only (reference JEDEC MO-153 AET) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Figure 7: LP Package, 28-Pin TSSOP with Exposed Thermal Pad 15 Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A5979 Microstepping DMOS Driver with Translator Revision History Revision Current Revision Date – December 21, 2015 1 January 21, 2016 2 May 31, 2016 Description of Revision Initial release Corrected formula on page 8 Corrected setup and hold time units on page 7 Copyright ©2016, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com 16 Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com