Cypress CY7C4292V-15ASC 64k/128kx9 low voltage deep sync fifos w/ retransmit & depth expansion Datasheet

CY7C4282V
CY7C4292V
64K/128Kx9 Low Voltage Deep Sync FIFOs
w/ Retransmit & Depth Expansion
Features
Functional Description
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO)
memories
• 64K x 9 (CY7C4282V)
• 128K x 9 (CY7C4292V)
• 0.35 micron CMOS for optimum speed/power
• High-speed, Near Zero Latency (True Dual-Ported
Memory Cell), 100-MHz operation (10 ns read/write
cycle times)
• Low power
— ICC = 25 mA
•
•
•
•
•
•
•
•
•
•
The CY7C4282V/92V are high-speed, low-power, first-in firstout (FIFO) memories with clocked read and write interfaces.
All devices are 9 bits wide. The CY7C4282V/92V can be cascaded to increase FIFO depth. Programmable features include
Almost Full/Almost Empty flags. These FIFOs provide solutions
for a wide variety of data buffering needs, including high-speed data
acquisition, multiprocessor interfaces, video and communications
buffering.
These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a Write Enable
pin (WEN).
— ISB = 6 mA
Fully asynchronous and simultaneous read and write
operation
Empty, Full, and Programmable Almost Empty and Almost Full status flags
Retransmit function
Output Enable (OE) pin
Independent read and write enable pins
Supports free-running 50% duty cycle clock inputs
Width Expansion Capability
Depth Expansion Capability through token-passing
scheme (no external logic required)
64-pin 10x10 STQFP
Pin-compatible 3.3V solution for CY7C4282/92
D0 −
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the Cascade Input (XI), Cascade Output (XO), and First Load (FL) pins. The XO pin is connected
to the XI pin of the next device, and the XO pin of the last device
should be connected to the XI pin of the first device. The FL pin of the
first device is tied to VSS and the FL pin of all the remaining devices
should be tied to VCC
When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data
is continually written into the FIFO on each cycle. The output
port is controlled in a similar manner by a free-running Read
Clock (RCLK) and a Read Enable pin (REN). In addition, the
CY7C4282V/92V have an Output Enable pin (OE). The read
and write clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 67 MHz are
achievable.
8
Logic Block Diagram
INPUT
REGISTER
WCLK WEN
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
FF
FLAG
LOGIC
Dual Port
RAM Array
64K x 9
128K x 9
WRITE
POINTER
RS
PAE
PAF/XO
READ
POINTER
RESET
LOGIC
THREE-STATE
OUTPUT REGISTER
FL/RT
XI/LD
EF
EXPANSION
LOGIC
PAF/XO
OE
Q0 −
Cypress Semiconductor Corporation
READ
CONTROL
•
8
3901 North First Street
RCLK REN
•
San Jose
4282V–1
•
CA 95134
•
408-943-2600
October 18, 1999
CY7C4282V
CY7C4292V
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CY7C4282V
CY7C4292V
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
WEN
RS
D8
D7
D6
N/C
N/C
N/C
N/C
N/C
N/C
N/C
D5
D4
D3
D2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
WCLK
XI/LD
GND
N/C
N/C
N/C
N/C
N/C
VCC
N/C
N/C
Q8
Q7
GND
Q6
N/C
STQFP
Top View
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q5
Q4
GND
Q3
Q2
VCC
Q1
Q0
GND
N/C
FF
EF
OE
GND
FL/RT
N/C
D1
D0
N/C
N/C
N/C
VCC
PAF/XO
PAE
N/C
N/C
N/C
N/C
N/C
GND
REN
RCLK
4282V–2
Functional Description (continued)
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle
The CY7C4282V/92V provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty+7 and Full−7.
All configurations are fabricated using an advanced 0.35µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
Selection Guide
7C4282V/92V-10
7C4282V/92V-15
7C4282V/92V-25
Maximum Frequency (MHz)
100
66.7
40
Maximum Access Time (ns)
8
10
15
Minimum Cycle Time (ns)
10
15
25
Minimum Data or Enable Set-Up (ns)
3.5
4
6
Minimum Data or Enable Hold (ns)
0
0
1
Maximum Flag Delay (ns)
8
10
15
25
25
25
Active Power Supply
Current (ICC) (mA)
Commercial
Industrial
30
CY7C4282V
CY7C4292V
Density
64k x 9
128k x 9
Package
64-pin 10x10 TQFP
64-pin 10x10 TQFP
2
CY7C4282V
CY7C4292V
Pin Definitions
Signal Name
Description
I/O
Description
D0−8
Data Inputs
I
Data Inputs for 9-bit bus.
Q0−8
Data Outputs
O
Data Outputs for 9-bit bus.
WEN
Write Enable
I
The only write enable when device is configured to have programmable flags. Data is
written on a LOW-to-HIGH transition of WCLK when WEN is asserted and FF is HIGH.
REN
Read Enable
I
Enables the device for Read operation. REN must be asserted LOW to allow a Read
operation.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty.
When LD is LOW, RCLK reads data out of the programmable flag-offset register.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value programmed into the FIFO. PAE is synchronized to RCLK.
PAF/XO
Programmable
Almost Full/
Expansion
Output
O
Dual-Mode Pin:
Cascaded - Connected to XI of next device.
Not Cascaded - When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is synchronized to WCLK.
FL/RT
First Load/
Retransmit
I
Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to VSS; all other devices
will have FL tied to V CC. In standard mode or width expansion, FL is tied to V SS
on all devices.
Not Cascaded - Retransmit function is available in stand-alone mode by strobing
RT.
XI/LD
Expansion Input/Load
I
Dual-Mode Pin:
Cascaded - Connected to XO of previous device.
Not Cascaded - LD is used to write or read the programmable flag offset registers. LD
must be asserted LOW during reset to enable standalone or width expansion operation.
If programmable offset register access is not required, LD can be tied to RS directly.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current ..................................................... >200 mA
Storage Temperature ....................................... −65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied .................................................... −55°C to +125°C
Range
Ambient
Temperature
Supply Voltage to Ground Potential..........−0.5V to V CC +0.5V
VCC [2]
Commercial
0°C to +70°C
3.3V + /−300mV
−40°C to +85°C
3.3V + /−300mV
DC Voltage Applied to Outputs
in High Z State ..............................................−0.5V to VCC+0.5V
Industrial
DC Input Voltage .........................................−0.5V to V CC +0.5V
Output Current into Outputs (LOW) ............................. 20 mA
Notes:
1. TA is the “instant on” case temperature.
2. VCC Range for commercial -10 ns is 3.3V ± 150 mV.
3
[1]
CY7C4282V
CY7C4292V
Electrical Characteristics Over the Operating Range
Parameter
Description
7C4282V/92V
-10
7C4282V/92V
-15
7C4282V/92V
-25
Test Conditions
Min.
Min.
Min.
2.4
Max.
Max.
VOH
Output HIGH Voltage
VCC = Min., IOH = −1.0 mA
VCC = 3.0V, IOH = −2.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 4.0 mA
VCC = 3.0V, IOL = 8.0 mA
VIH
Input HIGH Voltage
2.0
VCC
2.0
VCC
VIL
Input LOW Voltage
−0.5
0.8
−0.5
IIX
Input Leakage Current
VCC = Max.
−10
+10
IOZL
IOZH
Output OFF, High Z
Current
OE > VIH, VSS < VO < V CC
−10
+10
ICC1[3]
Active Power Supply
Current
Com’l
Average Standby
Current
Com’l
ISB[4]
2.4
0.4
Max.
2.4
Unit
V
0.4
0.4
V
2.0
VCC
V
0.8
−0.5
0.8
V
−10
+10
−10
+10
µA
−10
+10
−10
+10
µA
25
mA
25
25
Ind
30
6
mA
6
Ind
6
mA
6
mA
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
5
pF
7
pF
AC Test Loads and Waveforms (-15 , -25) [6, 7]
R1=330Ω
ALL INPUT PULSES
3.3V
OUTPUT
3.0V
R2=510Ω
CL
GND
≤ 3 ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
90%
10%
90%
10%
≤ 3 ns
4282V–4
THÉVENIN EQUIVALENT
200 Ω
OUTPUT
4282V–5
2.0V
AC Test Loads and Waveforms (-10)
ALL INPUT PULSES
VCC/2
3.0V
90%
10%
50Ω
GND
I/O
≤ 3 ns
Z0=50Ω
90%
10%
≤ 3 ns
4282V–5
Notes:
3. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency 20 MHz, while data inputs
switch at 10 MHz. Outputs are unloaded.
4. All inputs = VCC − 0.2V, except WCLK and RCLK (which are switching at frequency = 0 MHz). All outputs are unloaded.
5. Tested initially and after any design or process changes that may affect these parameters.
6. CL = 30 pF for all AC parameters except for tOHZ.
7. CL = 5 pF for tOHZ.
4
CY7C4282V
CY7C4292V
Switching Characteristics Over the Operating Range
Parameter
Description
7C4282V/92V
-10
7C4282V/92V
-15
7C4282V/92V
-25
Min.
Min.
Min.
Max.
100
Max.
Unit
40
MHz
15
ns
tS
Clock Cycle Frequency
tA
Data Access Time
2
tCLK
Clock Cycle Time
10
15
25
ns
tCLKH
Clock HIGH Time
4.5
6
10
ns
tCLKL
Clock LOW Time
4.5
6
10
ns
tDS
Data Set-Up Time
3.5
4
6
ns
tDH
Data Hold Time
0
0
1
ns
tENS
Enable Set-Up Time
3.5
4
6
ns
tENH
Enable Hold Time
0
0
1
ns
tRS
Reset Pulse Width[8]
10
15
25
ns
tRSS
Reset Set-Up Time
8
10
15
ns
tRSR
Reset Recovery Time
8
10
15
ns
tRSF
Reset to Flag and Output Time
tPRT
Retransmit Pulse Width
tRTR
Retransmit Recovery Time
8
66.7
Max.
2
10
[9]
10
2
15
25
ns
60
60
60
ns
90
90
90
ns
0
0
0
ns
tOLZ
Output Enable to Output in Low Z
tOE
Output Enable to Output Valid
3
7
3
10
3
12
ns
tOHZ
Output Enable to Output in High Z[9]
3
7
3
8
3
12
ns
tWFF
Write Clock to Full Flag
8
10
15
ns
tREF
Read Clock to Empty Flag
8
10
15
ns
tPAF
Clock to Programmable Almost-Full Flag
8
10
15
ns
tPAE
Clock to Programmable Almost-Full Flag
8
10
15
ns
tSKEW1
Skew Time between Read Clock and Write Clock
for Empty Flag and Full Flag
5
6
10
ns
tSKEW2
Skew Time between Read Clock and Write Clock
for Almost-Empty Flag and Almost-Full Flag
10
15
18
ns
Notes:
8. Pulse widths less than minimum values are not allowed.
9. Values guaranteed by design, not currently tested.
5
CY7C4282V
CY7C4292V
Switching Waveforms
Write Cycle Timing
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
D0 –D17
tENS
tENH
WEN
NO OPERATION
tWFF
tWFF
FF
tSKEW1
[10]
RCLK
REN
4282V–6
Read Cycle Timing
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
REN
NO OPERATION
tREF
tREF
EF
tA
Q0 –Q17
VALID DATA
tOLZ
tOHZ
tOE
OE
tSKEW1
[11]
WCLK
WEN
4282V–7
Notes:
10. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
11. tSKEW1 is also the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
6
CY7C4282V
CY7C4292V
Switching Waveforms (continued)
Reset Timing
[12]
tRSS
[13]
LD
tRS
RS
tRSR
REN, WEN
tRSF
EF,PAE
tRSF
FF,PAF
[14]
tRSF
OE=1
Q0 – Q8
OE=0
4282V–8
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
tDS
D0 –D8
D0 (FIRSTVALID WRITE)
D1
tENS
D2
D3
D4
[15]
tFRL
WEN
tSKEW1
RCLK
tREF
EF
REN
[16]
tA
Q0 –Q8
tA
D0
D1
tOLZ
tOE
OE
4282V–9
Notes:
12. The clocks (RCLK, WCLK) can be free-running during reset.
13. For standalone or width expansion configuration only.
14. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
15. When t SKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
16. The first word is available the cycle after EF goes HIGH, always.
7
CY7C4282V
CY7C4292V
Switching Waveforms (continued)
Empty Flag Timing
WCLK
tDS
tDS
DATA WRITE 2
DATA WRITE 1
D0 –D8
tENH
tENS
tENH
tENS
WEN
tFRL
[15]
tFRL
[15]
RCLK
tREF
tREF
tSKEW1
tREF
tSKEW2
EF
REN
LOW
OE
tA
DATA IN OUTPUT REGISTER
Q0 –Q8
DATA READ
4282V–10
Full Flag Timing
NO WRITE
NO WRITE
WCLK
tSKEW1[10]
[10]
tDS
DATA WRITE
tSKEW1
DATA WRITE
D0 –D8
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENH
REN
OE
tENH
tENS
tENS
LOW
tA
Q0 –Q8
tA
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
4282V–11
8
CY7C4282V
CY7C4292V
Switching Waveforms (continued)
Programmable Almost Empty Flag Timing
tCLKL
tCLKH
WCLK
tENS tENH
WEN
Note 18
PAE
tSKEW2
[17]
N + 1 WORDS
IN FIFO
tPAE
Note 19 t
PAE
RCLK
tENS
tENS tENH
REN
4282V–12
Programmable Almost Full Flag Timing
tCLKH
tCLKL
Note 20
WCLK
tENS tENH
WEN
tPAF
PAF
FULL − M WORDS
IN FIFO [21]
FULL − (M+1)WORDS
IN FIFO
tSKEW2 [22]
tPAF
RCLK
tENS
tENS tENH
REN
4282V–13
Notes:
17. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the
rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.
18. PAE offset= n.
19. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW
20. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.
21. 64K − m words for CY7C4282V, 128K − m words for CY4292V.
22. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.
9
CY7C4282V
CY7C4292V
Switching Waveforms (continued)
Write Programmable Registers
tCLK
tCLKL
tCLKH
WCLK
tENS
tENH
LD
tENS
WEN
tDS
tDH
D0 –D8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
4282V–14
Read Programmable Registers
tCLK
tCLKL
tCLKH
RCLK
tENS
LD
tENH
tENS
PAF OFFSET
MSB
REN
tA
UNKNOWN
Q0 –Q15
PAE OFFSET LSB
PAE OFFSET MSB
PAF OFFSET
LSB
4282V–15
Retransmit Timing
[23, 24, 25]
FL/RT
tPRT
tRTR
REN/WEN
EF/FF
4282V–16
Notes:
23. Clocks are free-running in this case.
24. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
25. For the synchronous PAE and PAF flags an appropriate clock cycle is necessary after tRTR to update these flags.
10
CY7C4282V
CY7C4292V
register again. Figure 1 shows the registers sizes and default
values for the various device types.
Architecture
The CY7C4282V/92V consists of an array of 64K to 128K
words of 9 bits each (implemented by a dual-port array of
SRAM cells), a read pointer, a write pointer, control signals
(RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, PAF, FF).
64k x 9
128kx 9
0
7
8
8
Empty Offset (LSB) Reg.
Default Value = 007h
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs (Q0 − 8) go LOW tRSF
after the rising edge of RS. In order for the FIFO to reset to its
default state, the user must not read or write while RS is LOW.
All flags are guaranteed to be valid tRSF after RS is taken LOW.
Empty Offset (LSB) Reg.
Default Value = 007h
0
7
8
0
7
0
8
(MSB)
Default Value = 000h
0
7
8
(MSB)
Default Value = 000h
8
Full Offset (LSB) Reg
Default Value = 007h
During reset of the FIFO, the state of the XI/LD pin determines
if depth expansion operation is used. For depth expansion operation, XI/LD is tied to XO of the next device. See “Depth
Expansion Configuration” and Figure 3. For standalone or
width expansion configuration, the XI/LD pin must be asserted
LOW during reset.
Full Offset (LSB) Reg
Default Value = 007h
0
7
8
0
7
0
8
(MSB)
Default Value = 000h
There is a 0-ns hold time requirement for the XI/LD configuration at the RS deassertion edge. This allows the user to tie
XI/LD to RS directly for applications that do not require access
to the flag offset registers.
(MSB)
Default Value = 000h
4282V–16
Figure 1. Offset Register Location and Default Values
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the LD input HIGH, the FIFO is returned to normal read and
write operation. The next time LD is brought LOW, a write operation stores data in the next offset register in sequence.
FIFO Operation
When the WEN is asserted LOW and FF is HIGH, data present
on the D0 −8 pins is written into the FIFO on each rising edge
of the WCLK signal. Similarly, when the REN is asserted LOW
and EF is HIGH, data in the FIFO memory will be presented
on the Q 0−8 outputs. New data will be presented on each rising
edge of RCLK while REN is active. REN must set up tENS
before RCLK for it to be a valid read function. WEN must occur
tENS before WCLK for it to be a valid write function.
The contents of the offset registers can be read to the data
outputs when LD is LOW and REN is LOW. LOW-to-HIGH transitions of RCLK read register contents to the data outputs.
Writes and reads should not be performed simultaneously on
the offset registers.
Programmable Flag (PAE, PAF) Operation
An Output Enable (OE) pin is provided to three-state the Q 0−8
outputs when OE is asserted. When OE is enabled (LOW),
data in the output register will be available to the Q0−8 outputs
after tOE. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
Whether the flag offset registers are programmed as described in Table 1 or the default values are used, the programmable Almost Empty flag (PAE) and programmable Almost Full
flag (PAF) states are determined by their corresponding offset
registers and the difference between the read and write
pointers.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0−8 outputs
even after additional reads occur.
Table 1. Writing the Offset Registers
WCLK [26]
LD
WEN
Programming
0
0
When LD is held LOW during Reset, this pin is the Load Enable (LD) for flag offset programming. In this configuration, LD
can be used to access the four 9-bit offset registers contained
in the CY7C4282V/92V for writing or reading data to these
registers.
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
When the device is configured for programmable flags and
both LD and WEN are LOW, the first LOW-to-HIGH transition
of WCLK writes data from the data inputs to the empty offset
least significant bit (LSB) register. The second, third, and
fourth LOW-to-HIGH transitions of WCLK store data in the
empty offset most significant bit (MSB) register, full offset LSB
register, and full offset MSB register, respectively, when LD
and WEN are LOW. The fifth LOW-to-HIGH transition of WCLK
while LD and WEN are LOW writes data to the empty LSB
Selection
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Note:
26. The same selection sequence applies to reading from the registers. REN
is enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
11
CY7C4282V
CY7C4292V
The number formed by the empty offset least significant bit
register and empty offset most significant bit register is referred to as n and determines the operation of PAE. PAE is
synchronized to the LOW-to-HIGH transition of RCLK by one
flip-flop and is LOW when the FIFO contains n or fewer unread
words. PAE is set HIGH by the LOW-to-HIGH transition of
RCLK when the FIFO contains (n+1) or greater unread words.
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK.
Empty Flag
The number formed by the full offset least significant bit register and full offset most significant bit register is referred to as
m and determines the operation of PAF. PAF is synchronized
to the LOW-to-HIGH transition of WCLK by one flip-flop and is
set LOW when the number of unread words in the FIFO is
greater than or equal to CY7C4282V (64K − m) and
CY7C4292V (128K − m). PAF is set HIGH by the LOW-toHIGH transition of WCLK when the number of available memory locations is greater than m.
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW, regardless of the state of REN. EF is synchronized to RCLK, i.e., it is
exclusively updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C4282V/92V features programmable Almost Empty
and Almost Full Flags. Each flag can be programmed (described in the Programming section) a specific distance from
the corresponding boundary flags (Empty or Full). When the
FIFO contains the number of words or fewer for which the flags
have been programmed, the PAF or PAE will be asserted, signifying that the FIFO is either Almost Full or Almost Empty. See
Table 2 for a description of programmable flags.
Flag Operation
The CY7C4282V/92V devices provide four flag pins to indicate
the condition of the FIFO contents. All flags operate synchronously.
Table 2. Status Flags
Number of Words in FIFO
CY7C4282V
0
CY7C4292V
0
[27]
[27]
FF
PAF
PAE
EF
H
H
L
L
1 to n
1 to n
H
H
L
H
(n+1) to (65536 − (m+1))
(n+1) to (131072 − (m+1))
H
H
H
H
(65536 − m)
(131072 − m)
H
L
H
H
L
L
H
H
[28]
to 65535
65536
[28]
to 131071
131072
Notes:
27. n = Empty Offset (n=7 default value).
28. m = Full Offset (m=7 default value).
12
CY7C4282V
CY7C4292V
Retransmit
ten to the FIFO after activation of RT are transmitted also. The
full depth of the FIFO can be repeatedly retransmitted.
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
Width Expansion Configuration
Word width may be increased simply by connecting the corresponding input control signals of multiple devices. A composite
flag should be created for each of the end-point status flags
(EF and FF). The partial status flags (PAE and PAF) can be
detected from any one device. Figure 2 demonstrates a 18-bit
word width by using two CY7C4282V/92V. Any word width can
be attained by adding additional CY7C4282V/92V.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred and at least one word has been read since
the last RS cycle. A HIGH pulse on RT resets the internal read
pointer to the first physical location of the FIFO. WCLK and
RCLK may be free running but must be disabled during and
tRTR after the retransmit pulse. With every valid read cycle after
retransmit, previously accessed data is read and the read
pointer is incremented until it is equal to the write pointer. Flags
are governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Data writ-
When the CY7C4282V/92V is in a Width Expansion Configuration, the Read Enable (REN) control input can be grounded
(see Figure 2). In this configuration, the Load (LD) pin is set to
LOW at Reset so that the pin operates as a control to load and
read the programmable flag offsets.
RESET (RS)
DATA IN (D) 18
RESET (RS)
9
9
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
OUTPUT ENABLE (OE)
LOAD (LD)
PROGRAMMABLE(PAE)
7C4282V
7C4292V
HALF FULL FLAG (HF)
PROGRAMMABLE (PAF)
7C4282V
7C4292V
EMPTY FLAG (EF)
FF
FF
EF
EF
9
FULL FLAG (FF)
DATA OUT (Q)
18
9
FIRST LOAD (FL)
EXPANSION IN (XI)
FIRST LOAD (FL)
EXPANSION IN (XI)
4282V–17
Figure 2. Block Diagram of 64Kx9/128Kx9 Low-Voltage Deep Sync FIFO Memory Used in a Width Expansion
Configuration
13
CY7C4282V
CY7C4292V
Depth Expansion Configuration
1. The first device must be designated by grounding the First
Load (FL) control input.
The CY7C4282V/92V can easily be adapted to applications
requiring more than 64K/128K words of buffering. Figure 3
shows Depth Expansion using three CY7C4282V/92Vs. Maximum depth is limited only by signal loading. Follow these
steps:
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to
the Expansion In (XI) pin of the next device.
4. EF and FF composite flags are created by ORing together
each individual respective flag.
XO
RCLK
WCLK
REN
WEN
OE
RS
7C4282V
D 7C4292V Q
VCC
FL
FF
EF
XI
XO
RCLK
WCLK
REN
WEN
OE
RS
7C4282V
7C4292V Q
D
DATA IN (D)
DATA OUT (Q)
VCC
FL
FF
EF
XI
WRITECLOCK (WCLK)
WCLK
WRITEENABLE (WEN)
XO
RCLK
WEN
READ CLOCK (RCLK)
READ ENABLE (REN)
REN
RESET (RS)
OUTPUTENABLE (OE)
RS 7C4282V OE
D 7C4292V Q
FF
FF
FL
EF
EF
XI
FIRST LOAD (FL)
4282V–25
Figure 3. Block Diagram of 64Kx9/128Kx9 Low-Voltage Deep Sync FIFO Memory
with Programmable Flags used in Depth Expansion Configuration
14
CY7C4282V
CY7C4292V
Ordering Information
64K x 9 Low Voltage Deep Sync FIFO
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
10
CY7C4282V-10ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
15
CY7C4282V-15ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
CY7C4282V-15ASI
A64
64-Lead 10x10 Thin Quad Flatpack
Industrial
CY7C4282V-25ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
25
128K x 9 Low Voltage Deep Sync FIFO
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
10
CY7C4292V-10ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
15
CY7C4292V-15ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
CY7C4292V-15ASI
A64
64-Lead 10x10 Thin Quad Flatpack
Industrial
CY7C4292V-25ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
25
Document #: 38-00657-B
Package Diagram
64-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A64
51-85051-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
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