® DAC4814 Quad 12-Bit Digital-to-Analog Converter (Serial Interface) FEATURES ● COMPLETE QUAD DAC — INCLUDES INTERNAL REFERENCES AND OUTPUT AMPLIFIERS ● GUARANTEED SPECIFICATIONS OVER TEMPERATURE DAC4814 +VS 15 –VS ● GUARANTEED MONOTONIC OVER TEMPERATURE 10V Ref 7 AGND 12 ● HIGH-SPEED SERIAL INTERFACE (10MHz CLOCK) 4 +VREF Out 3 Inv In 10kΩ +VL 28 10kΩ A5 11 Inv Out DGND 17 ● LOW POWER: 600mW (150mW/DAC) 10 VREF In ● LOW GAIN DRIFT: 5ppm/°C ● LOW NONLINEARITY: ±1/2 LSB max 20kΩ ● UNIPOLAR OR BIPOLAR OUTPUT ● CLEAR/RESET TO UNIPOLAR OR BIPOLAR ZERO 6 BPO A 2 VOUT A 5 BPO B 1 VOUT B 9 BPO C 20kΩ DAC A A1 DESCRIPTION 20kΩ The DAC4814 is one in a family of dual and quad 12bit digital-to-analog converters. Serial, 8-bit, 12-bit interfaces are available. 20kΩ The DAC4814 is complete. It contains CMOS logic, switches, a high-performance buried-zener reference, and low-noise bipolar output amplifiers. No external components are required for either unipolar 0 to 10V, 0 to –10V, or bipolar ±10V output ranges. DAC B A2 Serial Data and Control In 20kΩ The DAC4814 has a high-speed serial interface capable of being clocked at 10MHz. Serial data are clocked DAC D MSB first into a 48-bit shift register, then strobed into each DAC separately or simultaneously as required. The DAC has an asynchronous clear control for reset to unipolar or bipolar zero depending on the mode selected. This feature is useful for power-on reset or system calibration. The DAC4814 is packaged in a 28-pin plastic DIP rated for the –40°C to +85°C extended industrial temperature range. High-stability laser-trimmed thin film resistors assure high reliability and true 12-bit integral and differential linearity over the full specified temperature range. 20kΩ Logic DAC C A3 14 VOUT C 20kΩ 8 BPO D 20kΩ DAC D A4 13 VOUT D Serial Data 18 Out International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1991 Burr-Brown Corporation PDS-1111B Printed in U.S.A. April, 1995 SPECIFICATIONS, Guaranteed over TA = –40°C to +85°C unless otherwise specified. ELECTRICAL Specifications as shown for VS = ±12V or ±15V, VL = +5V, and RL = 2kΩ unless otherwise noted. DAC4814AP PARAMETER CONDITIONS DIGITAL INPUTS Resolution VIH (Input High Voltage) VIL (Input Low Voltage) IIN ( Input Current) MIN 12 +2 0 ACCURACY Integral, Relative Linearity (1) Differential Nonlinearity (2) Unipolar Offset Error Bipolar Zero Error Gain Error Unipolar, Bipolar Power Supply Sensitivity (3) ISINK = 1.6mA ISOURCE = 500µA 0 +2.4 DYNAMIC PERFORMANCE(5) Unipolar Mode Settling Time Bipolar Mode Settling Time Slew Rate Small-Signal Bandwidth ±5 ±0.1 ±5 ±30 ±5 ±15 +10 ±2 +10.020 ±30 Bits V V µA µA pF * * V V ±1/2 * ±1 ±0.5 * ±10 ±0.15 * LSB LSB LSB mV mV mV % ppmFSR/V * * * ±20 * ±8 ppm/°C ppmFSR/°C ppmFSR/°C * * +10.015 ±20 * * 40 * V ppm/°C mA mA pF mA ppm/mA ±5 * ppm/V –9.985 ±20 V ppm/°C Ω mA pF mA +10/–5 +6.5/–5 +9.985 * * 500 ±20 –10.020 –10 * * –9.980 ±30 –10.015 0.1 * 200 ±30 1.75 7 14 * * ±7 * * 2.5 10 20 * * * * * * ±10 –VS + 1.4 +VS – 1.4 * * 0.1 CL = 100pF To 1/2 LSB of Full Scale To 1/2 LSB of Full Scale 2.5 3.5 10 3 Full Scale Transition CL= 100pF ® 2 V Ω mA pF mA * * µs µs V/µs MHz * 500 ±30 * * 10 10 * * * * kΩ kΩ kΩ V * * ±5 VOUT D/A GLITCH IMPULSE DAC4814 * * * * * * * ±1 ±3 ±20 ±0.2 30 ANALOG GROUND CURRENT (Code Dependent) DIGITAL CROSSTALK UNITS +1.5/–1 +9.980 REFERENCE INPUT Reference Input Resistance Inverter Input Resistance BPO Input Resistance Reference Input Range MAX * +0.4 +5 With Internal or External 10.0V Ref VS = ±11.4V to ±18V VL = +4.5V to +5.5V TA = 25°C TA = –40°C to +85°C TYP ±1 ±1 TA = 25°C TA = –40°C to +85°C TA = +25°C TA = –40°C to +85°C Max Load Capacitance (For Stability) Short Circuit Current Load Regulation (∆ VOUT vs ∆ ILOAD) Supply Regulation (∆ VOUT vs ∆ VS) INVERTER –10V Reference(4), Inverter Output –10V Reference Drift DC Output Impedance Output Current Max Load Capacitance (For Stability) Short Circuit Current ANALOG SIGNAL OUTPUTS Voltage Range DC Output Impedance Output Current Max Load Capacitance (For Stability) Short Circuit Current MIN 0.8 TEMPERATURE DRIFT Gain Drift Unipolar, Bipolar Unipolar Offset Drift Bipolar Zero Drift REFERENCE OUTPUT Output Voltage Reference Drift Output Current DAC4814BP MAX +5 +0.8 ±1 ±10 TA = 25°C TA = –40°C to +85°C CIN (Input Capacitance) DIGITAL OUTPUT Data Out VOL VOH TYP ±4 * mA 3 * nV-s 30 * nV-s SPECIFICATIONS (CONT), Guaranteed over TA = –40°C to +85°C unless otherwise specified. ELECTRICAL Specifications as shown for VS = ±12V or ±15V, VL = +5V, and RL = 2kΩ unless otherwise noted. DAC4814AP PARAMETER POWER SUPPLY +VS and –VS +VL +IS –IS +IL +IL Total Power, All DACs CONDITIONS TYP MAX MIN TYP MAX UNITS ±11.4 4.5 ±15 5 +20 –20 0.4 ±18 5.5 +24 –25.5 2 10 753 * * * * * * * * * * * * * * V V mA mA mA mA mW +85 +85 * * * * °C °C °C/W Digital Inputs = 0V or +VL Digital Inputs = VIL or VIH TEMPERATURE RANGE Specified Operating Thermal Resistance, θJA DAC4814BP MIN 600 –40 –40 * 75 * NOTES: (1) End point linearity. (2) Guaranteed monotonic. (3) Change in bipolar full scale output. Includes voltage output DAC, voltage reference, and reference inverter. (4) Inverter output with inverter input connected to +VREF. (5) Guaranteed to but not tested. ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS +VL to AGND ................................................................................. 0V, +7V +VL to DGND ................................................................................ 0V, +7V +VS to AGND .............................................................................. 0V, +18V –VS to AGND ............................................................................... 0V,–18V AGND to DGND ................................................................................ ±0.3V Any digital input to DGND .............................................. –0.3V, +VL +0.3V Ref In to AGND .................................................................................. ±25V Ref In to DGND .................................................................................. ±25V Storage Temperature Range .......................................... –55°C to +125°C Operating Temperature Range ......................................... –40°C to +85°C Lead Temperature (soldering, 10s) ................................................ +300°C Junction Temperature .................................................................... +155°C Output Short Circuit ................................... Continuous to common or ±VS Reference Short Circuit .............................. Continuous to common or +VS Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. PACKAGE INFORMATION MODEL DAC4814AP DAC4814BP PACKAGE PACKAGE DRAWING NUMBER(1) 28-Pin Plastic DBL Wide DIP 28-Pin Plastic DBL Wide DIP 215 215 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 DAC4814 PIN DESIGNATIONS PIN DESCRIPTOR FUNCTION PIN DESCRIPTOR FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VOUT B VOUT A Inv In +VREF Out BPO B BPO A –VS BPO D BPO C VREF In Inv Out AGND VOUT D VOUT C Analog output voltage, DAC B Analog output voltage, DAC A Inverter (A5) input Positive reference voltage output (+10V output) Biplolar offset input, DAC B Bipolar offset input, DAC A Negative analog power supply , –15V input Bipolar offset input, DAC D Bipolar offset input, DAC C ± Reference voltage input Inverter (A5) output Analog common Analog output voltage, DAC D Analog output voltage, DAC C 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +VL LATCH A LATCH B MODE CLR CS Data In LATCH C LATCH D CLK Data Out DGND NC +VS Positive logic power supply, +5V input Latch data update, logic input, DAC A Latch data update, logic input, DAC B Selection input for unipolar or bipolar reset to zero Asynchronous input reset to zero Chip select enable, DAC A, B, C, and D Serial data input Latch data update, logic input, DAC C Latch data update, logic input, DAC D Clock input Serial data output Digital common No internal connection Positive analog power supply, +15V input PIN CONFIGURATION TOP VIEW VOUT B 1 28 +VL VOUT A 2 27 LATCH A Inv In 3 26 LATCH B +VREF Out 4 25 MODE BPO B 5 24 CLR BPO A 6 23 CS –VS 7 BPO D 8 21 LATCH C BPO C 9 20 LATCH D DAC4814 22 Data In VREF In 10 19 CLK Inv Out 11 18 Data Out AGND 12 17 DGND VOUT D 13 16 NC VOUT C 14 15 +VS NC = No Internal Connection TYPICAL PERFORMANCE CURVES TA = +25°C, VS = ±12V or ±15V, VL = +5V unless otherwise noted. NOISE vs BANDWIDTH (Bipolar Mode) PSRR vs FREQUENCY (Bipolar Mode) 250 80 Voltage Noise (µVrms) 70 PSRR (dB) 60 50 40 VOUT = 0V 30 20 200 150 VOUT = +10V FFFHEX 100 50 VOUT = +10V 10 VOUT = 0V 800HEX 0 0 1k 10k 100k 100 1M Frequency (Hz) 10k Frequency (Hz) ® DAC4814 1k 4 100k 1M TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VS = ±12V or ±15V, VL = +5V unless otherwise noted. CHANGE OF GAIN, BIPOLAR OFFSET AND ZERO ERROR vs TEMPERATURE 0.0E+00 0.0E+00 Bipolar Offset –5.0E–01 –5.0E–03 –1.0E–02 –1.0E+00 –40 –20 0 20 40 60 +80 2 21.2 20.9 1.6 IS 1.2 20.6 0.8 20.3 +IL (All Logic Inputs = 0V or VL) 20 –1.5E–02 –1.5E+00 2.4 0.4 0 19.4 100 +IL (mA) Logic Supply 5.0E–03 ±IS (mA) Analog Supply Gain Error Bipolar Zero ∆ Gain Error (%) 5.0E+00 2.8 +IL (All Logic Inputs = 2V) 21.5 1.0E–02 1.0E+00 –40 Temperature (°C) –20 0 20 40 60 80 Temperature (°C) CROSSTALK (Bipolar Mode) OUTPUT VOLTAGE SWING vs RESISTOR LOAD 25 VS = ±15V 10V REF 0V VL = 5V VOUT B VOUT 15 VOUT A 10 LATCH A +5V 5 0V 0 Time (500ns/div) 10 100 1K 10K NOTE: Crosstalk is dominated by digital crosstalk/ feedthrough of the LATCH signal. Load Resistance (Ω ) FULL-SCALE OUTPUT SWING BIPOLAR (20V Step) FULL-SCALE OUTPUT SWING UNIPOLAR (10V Step) 0V VOUT (5V/div) VOUT (Vp-p) 20 VOUT (5V/div) ∆ Bipolar Offset and Zero Error (mV) POWER SUPPLY CURRENT vs TEMPERATURE 21.8 1.5E–02 1.5E+00 VOUT 0V VOUT LATCH +5V 0V Time (2µs/div) Time (2µs/div) ® 5 DAC4814 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VS = ±12V or ±15V, VL = +5V unless otherwise noted. ∆V Around –10V (2mV/div) +10V SETTLING TIME BIPOLAR (+10V to –10V Step) VOUT LATCH +5V 0V VOUT LATCH +5V 0V Time (2µs/div) SETTLING TIME UNIPOLAR (+10V to 0V STEP) SETTLING TIME UNIPOLAR (0V to +10V Step) 0V VOUT LATCH +5V 0V VOUT +10V LATCH +5V 0V Time (1µs/div) Time (1µs/div) MAJOR CARRY GLITCH DIGITAL FEEDTHROUGH 0V VOUT (5mV/div) VOUT (20mV/div) –10V Time (1µs/div) ∆V Around +10V (1mV/div) ∆V Around 0V (1mV/div) ∆V Around +10V (2mV/div) SETTLING TIME BIPOLAR (–10V to +10V) VOUT VOUT 0V LATCH +5V 0V Time (1µs/div) Time (500ns/div) NOTE: Data transition 800HEX to 7FFHEX. DAC output noise due to activity on digital inputs with latch disabled. ® DAC4814 6 TIMING CHARACTERISTICS VS = ±15V, VL = +5V, TA = –40°C to +85°C. PARAMETER t5 MINIMUM t1—Data Setup Time t2—Data Hold Time t3—Chip Select to CLK, Latch, Data Setup Time t4—Chip Select to CLK, Latch, Data Hold Time t5—CLK Pulse Width t6—Clear Pulse Width t7—Latch Pulse Width t8—CLK Edge to LATCH A, LATCH B, LATCH C, or LATCH D CLK 15ns 15ns 15ns 0V t1 5V 0V Data t3 t2 5V CS 40ns t8 LATCH A LATCH B LATCH C LATCH D 40ns 40ns 40ns 15ns t7 t4 5V t6 CLR 5V NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V • t R = tF = 5ns. (2) Timing measurement reference level is VIH + VIL . 2 INTERFACE LOGIC TRUTH TABLE MODE CLR CLK CS LATCH A LATCH B LATCH C LATCH D X X X X X X X 0 1 1 1 1 1 1 1 1 0 0 ↓ X X X X X X X X 0 1 0 0 0 0 0 X X X X 0 1 1 1 0 X X X X 1 0 1 1 0 X X X X 1 1 0 1 0 X X X X 1 1 1 0 0 X X Note: X = Don’t Care. FUNCTION Data clocked in No data transfer DAC A register updated DAC B register updated DAC C register updated DAC D register updated All DAC registers updated simultaneously All registers cleared Shift registers cleared = 000HEX, DAC registers = 800HEX ↓ = Falling edge triggered. ® 7 DAC4814 FUNCTIONAL BLOCK DIAGRAM, DAC4814 — Quad 12-bit DAC, Serial Port Data In VREF In 22 10 20kΩ 12-Bit Shift Register CLK 19 LATCH A 27 Bits 0-11 12-Bit Latch Register 12-Bit Shift Register BPO A 2 VOUT A 5 BPO B 1 VOUT B 9 BPO C 20kΩ Bits 0-11 DAC A A1 Bit 11 LATCH B 26 6 20kΩ Bits 0-11 12-Bit Latch Register 20kΩ Bits 0-11 DAC B A2 LATCH C 21 Bit 11 20kΩ LATCH D 20 Control Logic 12-Bit Shift Register CS 23 Bits 0-11 12-Bit Latch Register 20kΩ Bits 0-11 DAC C A3 14 VOUT C CLR 24 Bit 11 20kΩ 8 MODE 25 12-Bit Shift Register Bits 0-11 12-Bit Latch Register 20kΩ Bits 0-11 DAC D A4 10kΩ +10V Voltage Reference Bit 11 18 28 15 7 Data Out +VL +VS –VS 12 17 AGND DGND ® DAC4814 8 BPO D 10kΩ A5 4 3 +VREF Out Inv In 13 VOUT D 11 Inv Out DISCUSSION OF SPECIFICATIONS DIGITAL CROSSTALK Digital crosstalk is the glitch impulse measured at the output of one DAC due to a full scale transition on the other DAC—see Typical Performance Curves. It is dominated by digital coupling. Also, the integrated area of the glitch pulse is specified in nV–s. See table of electrical specifications. INPUT CODES All digital inputs of the DAC4814 are TTL and 5V CMOS compatible. Input codes for the DAC4814 are either USB (Unipolar Straight Binary) or BOB (Bipolar Offset Binary) depending on the mode of operation. See Figure 3 for ±10V bipolar connection. See Figures 4 and 5 for 0 to 10V and 0 to –10V unipolar connections. DIGITAL FEEDTHROUGH Digital feedthrough is the noise at a DAC output due to activity on the digital inputs—see Typical Performance Curves. UNIPOLAR AND BIPOLAR OUTPUTS FOR SELECTED INPUT DIGITAL INPUT FFFHEX 800HEX 7FFHEX 000HEX UNIPOLAR (USB) BIPOLAR (BOB) +Full scale +1/2 Full scale +1/2 Full scale – 1 LSB Zero +Full scale Zero Zero – 1 LSB –Full scale OPERATION DACs can be updated simultaneously or independently as required. Data are transferred on falling clock edges into a 48-bit shift register. DAC D MSB is loaded first. Data are transferred to the DAC registers when the LATCH signals are brought low. The data are latched when the LATCH signals are brought high. All LATCH signals may be tied together to allow simultaneous update of the DACs if required. The output of the DAC shift register is provided to allow cascading of several DACS on the same bit stream. By using separate signals for LATCH A , LATCH B, LATCH C, and LATCH D it is possible to update one of the four DACs every 12 clock cycles. When CLR is brought low, the input shift registers are cleared to 000HEX while the DAC registers = 800HEX. If LATCH is brought low after CLR, the DACs are updated with 000HEX resulting in –10V (bipolar) or 0V (unipolar) on the output. INTEGRAL OR RELATIVE LINEARITY This term, also known as end point linearity, describes the transfer function of analog output to digital input code. Integral linearity error is the deviation of the analog output versus code transfer function from a straight line drawn through the end points. DIFFERENTIAL NONLINEARITY Differential nonlinearity is the deviation from an ideal 1 LSB change in the output voltage when the input code changes by 1 LSB. A differential nonlinearity specification of ±1 LSB maximum guarantees monotonicity. CIRCUIT DESCRIPTION UNIPOLAR OFFSET ERROR The output voltage for code 000HEX when the DAC is in unipolar mode of operation. Each of the four DACs in the DAC4814 consists of a CMOS logic section, a CMOS DAC cell, and an output amplifier. One buried-zener +10.0V reference and a reference inverter (for a –10.0V reference) are shared by all DACs. BIPOLAR ZERO ERROR The output voltage for code 800HEX when the DAC is in the bipolar mode of operation. Figure 1 is a simplified circuit for a DAC cell. An R, 2R ladder network is driven by a voltage reference at VREF. Current from the ladder is switched either to IOUT or AGND by 12 single-pole double-throw CMOS switches. This maintains constant current in each leg of the ladder regardless of digital input code. This makes the resistance at VREF constant (it can be driven by either a voltage or current reference). The reference can be either positive or negative polarity with a range of up to ±10V. GAIN ERROR The deviation of the output voltage span (VMAX – VMIN) from the ideal span of 10V – 1 LSB (unipolar mode) or 20V – 1 LSB (bipolar mode). The gain error is specified with and without the internal +10V reference error included. R OUTPUT SETTLING TIME The time required for the output voltage to settle within a percentage-of-full-scale error band for a full scale transition. Settling to ±0.012% (1/2 LSB) is specified for the DAC4814. R R VREF 2R 2R 2R 2R 2R R R FB IOUT DIGITAL-TO-ANALOG GLITCH D11 (MSB) Ideally, the DAC output would make a clean step change in response to an input code change. In reality, glitches occur during the transition. See Typical Performance Curves. D10 D9 D0 (LSB) AGND FIGURE 1. Simplified Circuit Diagram of DAC Cell. ® 9 DAC4814 CMOS switches included in series with the ladder terminating resistor and the feedback resistor, RFB, compensate for the temperature drift of the ladder switch ON resistance. reference ground must be kept to a minimum. Connect DACs as shown in Figure 2 or use a ground plane to keep ground impedance less than 0.1Ω for less than 0.1LSB error. The output op amps are connected as transimpedance amplifiers to convert the DAC-cell output current into an output voltage. They have been specially designed and compensated for precision and fast settling in this application. –10V REFERENCE An internal inverting amplifier (Gain = –1.0V/V) is provided to invert the +10V reference. Connect +VREF Out to Inv In for a –10V reference at Inv Out. POWER SUPPLY CONNECTIONS The DAC4814 is specified for operation with power supplies of VL = +5V and VS = either ±12V or ±15V. Even with the VS supplies at ±11.4V the DACs can swing a full ±10V. Power supply decoupling capacitors (1µF tantalum) should be located close to the DAC power supply connections. OUTPUT RANGE CONNECTIONS ±10V Output Range For a ±10V bipolar output connect the DAC4814 as shown in Figure 3. Connect the MODE to logic high (+5V) for reset to bipolar zero. With MODE connected low (GND) reset will be to –Full-Scale. Separate digital and analog ground pins are provided to permit separate current returns. They should be connected together at one point. Proper layout of the two current returns will prevent digital logic switching currents from degrading the analog output signal. The analog ground current is code dependent so the impedance to the system 0 To +10V Output Range For 0 to +10V unipolar outputs connect the DAC4814 as shown in Figure 4. Connect the MODE to logic low (GND) for reset to unipolar zero. DAC4814 DAC4814 DAC A DAC A VOUT A VOUT A DAC B DAC B VOUT B VOUT B DAC C DAC C VOUT C VOUT C DAC D DAC D VOUT D VOUT D AGND AGND R GND R GND NOTE: Ideally RGND = 0Ω FIGURE 2. Recommended Ground Connections for Multiple DAC Packages. ® DAC4814 10 DAC4814 10kΩ +5V + +5V 20kΩ +15V 6 1µF 10 15 20kΩ + 1µF 2 A1 DAC A VOUT A 1µF 20kΩ 5 + 20kΩ 1 A2 20kΩ DAC B VOUT B 20kΩ Serial Data and Control In 9 14 A3 20kΩ 9 DAC C VOUT C 14 A3 20kΩ 8 VOUT C 8 20kΩ 20kΩ DAC D 13 A4 DGND VOUT B 20kΩ DAC C 17 1 A2 20kΩ +5V 5 20kΩ DAC B MODE 25 VOUT A 7 20kΩ Serial Data and Control In 2 A1 –15V 7 + 6 20kΩ 20kΩ DAC A –15V 11 A5 10 15 + 10kΩ 11 A5 +15V 10V Ref 1µF 10kΩ 3 28 + 10V Ref 4 10kΩ 3 28 1µF 1µF DAC4814 4 DAC D VOUT D 13 A4 MODE 25 12 17 DGND AGND VOUT D 12 AGND FIGURE 3. Analog Connections for ±10V DAC Output. FIGURE 4. Analog Connections for 0 to +10V DAC Output. 0 To –10V Output Range For 0 to –10V unipolar outputs connect the DAC4814 as shown in Figure 5. Connect the MODE to logic low (GND) for reset to unipolar zero. cascaded on the same input bit stream as shown in Figure 6. This arrangement allows all DACs in the system to be updated simultaneously and requires a minimum number of control signal inputs. However, up to 48N CLK cycles may be required to update any given DAC, where N = number of DAC4814s. CONNECTION TO DIGITAL BUS Parallel Bus Connection Cascaded Bus Connection Several DAC4814s can also have their DATA inputs connected in parallel as shown in Figure 7. This allows any DAC in the system to be updated in a maximum of 48 CLK cycles. Multiple DAC4814s can be connected to the same CLK and DATA input lines in two ways. Since the output of the DAC shift register is available, any number of DAC4814s can be ® 11 DAC4814 DAC4814 DAC4814 22 Data +5V 28 27 LATCH + 10V Ref 1µF 4 26 21 20 +15V 1µF CLK 10 15 20kΩ + 19 2 A1 VOUT A 27 7 26 + 20kΩ 21 5 20 20kΩ 19 DAC B 1 A2 LATCH B LATCH C LATCH D Data Out CLK 18 CS Data In 23 LATCH A LATCH B LATCH C LATCH D CLK Data Out 18 To Other DACs VOUT B FIGURE 6. Cascaded Serial Bus Connection for Multiple DAC Packages. 20kΩ Serial Data and Control In LATCH A DAC4814 22 DAC A 1µF 23 6 20kΩ –15V CS Data In 9 20kΩ DAC4814 DAC C 14 A3 Data VOUT C LATCH 1 22 27 26 20kΩ 21 8 20 20kΩ DAC D 13 A4 CLK VOUT D 19 CS Data In 23 LATCH A LATCH B LATCH C LATCH D Data Out CLK 18 DAC4814 MODE 25 17 DGND 22 12 AGND LATCH 2 27 26 FIGURE 5. Analog Connections for 0 to –10V DAC Output. 21 20 19 Data In CS 23 LATCH A LATCH B LATCH C LATCH D CLK Data Out 18 FIGURE 7. Parallel Bus Connection for Multiple DAC Packages. ® DAC4814 12