PRELIMINARY Integrated Circuit Systems, Inc. ICS8316 LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS GENERAL DESCRIPTION FEATURES The ICS8316 is a low skew, 1-to-16 LVCMOS/ LVTTL Fanout Buffer with 1.2V LVCMOS Outputs HiPerClockS™ and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8316 single ended clock input accepts LVCMOS or LVTTL input levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. • Sixteen 1.2V LVCMOS / LVTTL outputs ICS • LVCMOS / LVTTL clock input • Maximum output frequency: 150MHz • Output skew: TBD • Propagation delay: 3.5ns (typical) • 3.3V core/1.2V output operating supply mode Guaranteed output and part-to-part skew characteristics along with the 1.2V output makes the ICS8316 ideal for high performance, single ended applications that also require a limited output voltage. • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request • Available in both standard and lead-free RoHS-compliant packages VDDO QD0 QD1 QD2 QD3 GND OED PIN ASSIGNMENT GND BLOCK DIAGRAM 32 31 30 29 28 27 26 25 CLK 4 QA0:QA3 OEA 4 QB0:QB3 OEB 4 QC0:QC3 OEC VDDO 1 24 VDDO QA0 2 23 QC0 QA1 3 22 QC1 QA2 4 21 QC2 QA3 5 20 QC3 GND 6 19 GND OEA 7 18 OEC CLK 8 17 GND ICS8316 9 10 11 12 13 14 15 16 VDDO QB0 QB1 QB2 QB3 OED GND VDD QD0:QD3 OEB 4 32-Lead VFQFN 5mm x 5mm x 0.95 package body K Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8316AK http://www.icst.com/products/hiperclocks.html 1 REV. A DECEMBER 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8316 LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 16, 24, 25 VDDO Power Output supply pins. 2, 3, 4, 5 6, 11, 17, 19, 30, 32 QA0, QA1, QA2, QA3 Output Bank A clock outputs. LVCMOS / LVTTL interface levels. GND Power Power supply ground. 7 OEA Input 8 CLK Input 9 VDD Power 10 OEB Input 12, 13, 14, 15 QB3, QB2, QB1, QB0 Output 18 OEC Input 20, 21, 22, 23 QC3, QC2, QC1, QC0 Output 26, 27, 28, 29 QD0, QD1, QD2, QD3 Output Bank A output enable pin. Controls enabling and disabling of QA0:QA3 outputs. LVCMOS / LVTTL interface levels. Pulldown Clock input. LVCMOS / LVTTL interface levels. Pullup Core supply pin. Bank B output enable pin. Controls enabling and disabling of QB0:QB3 outputs. LVCMOS / LVTTL interface levels. Bank B clock outputs. LVCMOS / LVTTL interface levels. Bank C output enable pin. Controls enabling and disabling of QC0:QC3 outputs. LVCMOS / LVTTL interface levels. Bank C clock outputs. LVCMOS / LVTTL interface levels. Pullup Pullup Bank D clock outputs. LVCMOS / LVTTL interface levels. Bank D output enable pin. Controls enabling and disabling 31 OED Input Pullup of QD0:QD3 outputs. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN RPULLUP Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor RPULLDOWN Input Pulldown Resistor ROUT Output Impedance CPD Test Conditions TABLE 3A. OUTPUT ENABLE AND Outputs Qx0:Qx3 Hi-Z Active Typical Maximum Units 4 pF TBD pF 51 kΩ 51 kΩ 15 Ω CLOCK ENABLE FUNCTION TABLE OE[A:D] 1 VDDO = 1.26V VDDO = 1.2 ± 5% Control Inputs 0 Minimum TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs 8316AK Outputs OE[A:D] CLK Qx0:Qx3 1 0 LOW 1 1 HIGH http://www.icst.com/products/hiperclocks.html 2 REV. A DECEMBER 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8316 LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 34.8°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V, VDDO = 1.2V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 1.2 1.26 VDDO Output Supply Voltage IDD Power Supply Current 1.14 TBD µA V IDDO Output Supply Current TBD µA TABLE 4B. LVCMOS DC CHARACTERISTICS, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical 2 -0.3 Maximum Units VDD + 0.3 V 0.8 V CLK VDD = VIN = 3.465V 150 µA OEA:OED VDD = VIN = 3.465V 5 µA CLK VDD = 3.465V, VIN = 0V -5 µA OEA:OED VDD = 3.465V, VIN = 0V -150 µA VDD*0.7 VOH Output High Voltage VDDO = 1.2V ± 5%; NOTE 1 VOL Output Low Voltage VDDO = 1.2V ± 5%; NOTE 1 V VDD*0.3 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagram. TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.2V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions fMAX Output Frequency tpLH Propagation Delay Low to High; NOTE 1 t sk(o) Minimum Typical Maximum Units 150 MHz 3.5 ns Output Skew; NOTE 2, 5 TBD ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 5 TBD ps tR/tF Output Rise Time; NOTE 4 650 ps odc Output Duty Cycle 50 % 20% to 80% All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 8316AK http://www.icst.com/products/hiperclocks.html 3 REV. A DECEMBER 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8316 LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS PARAMETER MEASUREMENT INFORMATION 2.7V±5% 0.6V±5% V SCOPE V DD VDDO DDO Qx 2 Qx LVCMOS V GND DDO Qy 2 tsk(o) -0.6V±5% 3.3V CORE/1.2V OUTPUT LOAD AC TEST CIRCUIT Part 1 Qx OUTPUT SKEW V DDO Qx0:Qx3 2 Part 2 VDDO 2 VDDO 2 V DDO Qy Qx0:Qx3 2 tsk(pp) tsk(b) PART-TO-PART SKEW BANK SKEW (where x denotes outputs in the same bank) QA0:QA3, QB0:QB3, QC0:QC3, QD0:QD3 VDD 2 CLK V DDO 2 t PW QA0:QA3, QB0:QB3, QC0:QC3, QD0:QD3 t VDDO 2 t PD odc = t PW x 100% t PERIOD PROPAGATION DELAY OUTPUT DUTY CYCLE/PLUSE WIDTH/PERIOD 80% Clock Outputs PERIOD 80% 20% 20% tR tF OUTPUT RISE/FALL TIME 8316AK http://www.icst.com/products/hiperclocks.html 4 REV. A DECEMBER 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8316 LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN θJA vs. 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 34.8°C/W TRANSISTOR COUNT The transistor count for ICS8316 is: 416 8316AK http://www.icst.com/products/hiperclocks.html 5 REV. A DECEMBER 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE AND ICS8316 LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS VHHD-2 SYMBOL MINIMUM NOMINAL 32 N A 0.80 A1 0 -- 1.00 -- 0.05 0.25 Ref. A3 b MAXIMUM 0.18 0.25 8 NE 5.00 BASIC D D2 1.25 2.25 1.25 2.25 3.25 0.50 BASIC e L 3.25 5.00 BASIC E E2 0.30 8 ND 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 8316AK http://www.icst.com/products/hiperclocks.html 6 REV. A DECEMBER 22, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8316 LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8316AK ICS8316AK 32 Lead VFQFN tray 0°C to 70°C ICS8316AKT ICS8316AK 32 Lead VFQFN 2500 tape & reel 0°C to 70°C ICS8316AKLF TBD 32 Lead "Lead-Free" VFQFN tray 0°C to 70°C ICS8316AKLFT TBD 32 Lead "Lead-Free" VFQFN 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8316AK http://www.icst.com/products/hiperclocks.html 7 REV. A DECEMBER 22, 2005