MAS MCP795B11 Spi real-time clock calendar Datasheet

MCP795WXX/MCP795BXX
SPI Real-Time Clock Calendar with
Enhanced Features and Battery Switchover
Part Number
MCP795W20
User Memory:
32 kHz
Boot-up
SRAM
(Bytes)
EEPROM
(Kbits)
No
64
2
Unique
ID
Blank
MCP795W10
No
64
1
Blank
MCP795W21
No
64
2
EUI-48™
MCP795W11
No
64
1
EUI-48™
MCP795W22
No
64
2
EUI-64™
MCP795W12
No
64
1
EUI-64™
MCP795B20
Yes
64
2
Blank
MCP795B10
Yes
64
1
Blank
MCP795B21
Yes
64
2
EUI-48™
™
MCP795B11
Yes
64
1
EUI-48
MCP795B22
Yes
64
2
EUI-64™
MCP795B12
Yes
64
1
EUI-64™
Note:
Watchdog Timer and Event Detects in all devices.
Timekeeping Features:
• Real-Time Clock/Calendar:
- Hours, Minutes, Seconds, Hundredth of
Seconds, Day of Week, Month, Year, Leap
Year
• Crystal Oscillator requires External 32,768 kHz
Tuning Fork Crystal and Load Capacitors.
• Clock Out Function:
- 1Hz, 4.096 kHz, 8.192 kHz, 32.768 kHz
• 32 kHz Boot-up Clock at Power-up (MCP795BXX)
• 2 Programmable Alarms – Supports IRQ or WDO
• Programmable open drain output – Alarm or
Interrupt
• On-Chip Digital Trimming/Calibration:
- +/- 255 PPM range in 1 PPM steps
• Power-Fail Time-Stamp @ Battery Switchover:
- Logs time when VCC fails and VCC is restored
• 64-Byte Battery-Backed SRAM
• 2 Kbit and 1 Kbit EEPROM Memory:
- Software block write-protect (¼, ½, or entire
array)
- Write Page mode (up to 8 bytes)
- Endurance: 1M erase/write cycles
• 128-Bit Unique ID in Protected Area of EEPROM:
- Available blank or preprogrammed
- EUI-48™ or EUI-64™ MAC address
- Unlock sequence for user programming
Enhanced Features:
• SPI Clock Speed up to 10 MHz
• Programmable Watchdog Timer:
- Dedicated watchdog output pin
- Dual retrigger using SPI bus or EVHS digital
input
• Dual Configurable Event Detect Inputs:
- High-Speed Digital Event Detect (EVHS) with
pulse count for 1st, 4th,16th or 32nd event
- Low-Speed Event Detect (EVLS) with
programmable debounce delays of 31 msec
and 500 msec
- Edge triggered (rising or falling)
- Operates from VCC or VBAT
• Operating Temperature Ranges:
- Industrial (I Temp): -40°C to +85°C.
• Packages include 14-Lead SOIC and TSSOP
SOIC/TSSOP
Low-Power Features:
• Wide Operating Voltage:
- VCC: 1.8V to 5.5V
- VBAT: 1.3V to 5.5V
• Low Operating Current:
- VCC Standby Current < 1uA @ 3V
- VBAT Timekeeping Current: <700nA @ 1.8V
• Automatic Battery Switchover from VCC to VBAT:
- Backup power for timekeeping and SRAM
retention
 2011 Microchip Technology Inc.
Note:
Preliminary
X1
1
14
Vcc
13
CLKOUT/BOOT
12
EVHS
11
EVLS
10
SCK
X2
2
VBAT
3
WDO
4
IRQ
5
CS
6
VSS
7
MCP795XXX
Device Selection Table
9
SI
8
SO
MCP795XXX is used in this document as a
generic part number for the MCP795WXX,
MCP795BXX devices.
DS22280A-page 1
MCP795WXX/MCP795BXX
FIGURE 1-1:
The MCP795XXX is a low-power Real-Time Clock/
Calendar (RTCC) that uses digital trimming compensation for an accurate clock/calendar, an interrupt output to support alarms and events, a power sense
circuit that automatically switches to the backup supply, non-volatile memory for safe data storage and
several enhanced features that support system
requirements.
X1
Vcc
OSC
CLKOUT Divider
VBAT
VBAT
SWITCHOVER
X2
CLKOUT/
BOOT
EVHS
EEPROM
/WDO
The device is fully accessible through the serial interface, while VCC is between 1.8V and 5.5V, but can
operate down to 1.3V through the backup supply connected to the VBAT input for timekeeping and SRAM
retention only.
As part of the power sense circuit, a time saver
function is implemented to store the time when main
power is lost and again, when power is restored to log
the duration of a power failure.
EVLS
ID
/IRQ
WDT
SCK
SRAM
/CS
Vss
TIME-STAMP
ALARMS
Along with a low-cost 32,768 kHz crystal, this RTCC
tracks time using several internal registers and then
communicates the data over a 10 MHz SPI bus that is
fast enough to support a programmable millisecond
alarm.
BLOCK DIAGRAM
EVENT
DETECT
Description:
SPI
SI
SO
Along with the onboard serial EEPROM and batterybacked SRAM, a 128-bit protected space is available
for a unique ID. This space can be ordered
preprogrammed with a MAC address, or blank for the
user to program.
This clock/calendar automatically adjusts for months
with fewer than 31 days including corrections for leap
years. The clock operates in either 24-hour or 12-hour
format with AM/PM indicator and settable alarm(s).
Using the external crystal, the CLKOUT pin can be set
to generate a number of output frequencies. In
addition, the MCP795BXX devices support a 32 kHz
clock output at power-up on the CLKOUT/BOOT pin
by using the same crystal driving the RTCC device.
For versatility, a digital event detect with a
programmable pulse count can identify the 1st, 4th,
16th or 32nd pulse before sending an interrupt. A
second event detect with built-in debounce input filter
was also implemented to support noisy mechanical
switches.
Since many microcontrollers do not have an integrated
Watchdog Timer, this peripheral has been implemented in the RTCC. For many applications, this
function must be performed outside the microcontroller
for increased robustness.
DS22280A-page 2
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ................................................................................................................. -0.6V to +6.5V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature under bias............................................................................................................... -40°C to +85°C
ESD protection on all pins.......................................................................................................................................... 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Industrial (I):
TAMB = -40°C to +85°C
VCC = 1.8V to 5.5V
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
D001
VIH1
High-level input
voltage
.7 VCC
VCC+1
V
D002
VIL1
-0.3
0.3VCC
V
D003
VIL2
Low-level input
voltage
-0.3
0.2VCC
V
VCC < 2.5V
D004
VOL
Low-level output
voltage
—
0.4
V
IOL = 2.1 mA
—
0.2
V
IOL = 1.0 mA, VCC < 2.5V
VCC -0.5
—
V
IOH = -400 A
Test Conditions
VCC2.5V
D005
VOL
D006
VOH
High-level output
voltage
D007
ILI
Input leakage current
±1
A
CS = VCC, VIN = VSS TO VCC
D008
ILO
Output leakage
current
±1
A
CS = VCC, VOUT = VSS TO VCC
D009
CINT
Internal Capacitance
(all inputs and
outputs)
—
7
pF
TAMB = 25°C, CLK = 1.0 MHz
VCC = 5.0V (Note 1)
D010
ICC Read
Operating Current
—
3
mA
VCC = 5.5V; FCLK = 10.0 MHz
SO = Open
D011
IDD write
Write Current
—
5
mA
VCC = 5.5V
D012
IBAT
VBAT Current
—
700
nA
VBAT = 1.8V @ 25°C (Note 2)
D013
VTRIP
VBAT Change Over
1.3
1.7
V
1.5V typical at TAMB = 25°C
D014
VCCFT
VCC Fall Time
300
s
From VTRIP (max) to VTRIP (min)
D015
VCCRT
VCC Rise Time
0
s
From VTRIP (min) to VTRIP (max)
D016
VBAT
VBAT Voltage Range
1.3
5.5
V
—
D017
ICCS
Standby Current
—
1
A
—
Note 1: This parameter is periodically sampled and not 100% tested.
2: With oscillator running.
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 3
MCP795WXX/MCP795BXX
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
TAMB = -40°C to +85°C VCC = 1.8V to 5.5V
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
1
FCLK
Clock Frequency
—
—
—
10
5
3
MHz
MHz
MHz
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
2
TCSS
CS Setup Time
50
100
150
—
—
—
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
3
TCSH
CS Hold Time
50
100
150
—
—
—
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
Test Conditions
4
TCSD
CS Disable Time
50
—
ns
—
5
Tsu
Data Setup Time
10
20
30
—
—
—
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
6
THD
Data Hold Time
20
40
50
—
—
—
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
7
TR
CLK Rise Time
—
100
ns
(Note 1)
8
TF
CLK Fall Time
—
100
ns
(Note 1)
9
THI
Clock High Time
50
100
150
—
—
—
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
10
TLO
Clock Low Time
50
100
150
—
—
—
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
11
TCLD
Clock Delay Time
50
—
ns
—
12
TCLE
Clock Enable Time
50
—
ns
—
13
TV
Output Valid from Clock
Low
—
—
—
50
100
160
ns
ns
ns
4.5V Vcc  5.5V
2.5V Vcc  4.5V
1.8V Vcc  2.5V
14
THO
Output Hold Time
0
—
ns
(Note 1)
15
TDIS
Output Disable Time
—
—
—
40
80
160
ns
ns
ns
4.5V Vcc  5.5V (Note 1)
2.5V Vcc  4.5V (Note 1)
1.8V Vcc  2.5V (Note 1)
16
TWC
Internal Write Cycle Time
—
5
ms
(Note 3)
17
—
Endurance
1,000,000
—
E/W (Note 2)
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site:
www.microchip.com.
3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
DS22280A-page 4
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
FIGURE 1-1:
SERIAL INPUT TIMING
4
CS
12
2
7
SCK
6
MSB In
LSB In
High-Impedance
SO
FIGURE 1-2:
3
9
5
SI
8
10
11
SERIAL OUTPUT TIMING
CS
9
3
10
SCK
13
SO
SI
 2011 Microchip Technology Inc.
14
MSB Out
15
LSB Out
Don’t Care
Preliminary
DS22280A-page 5
MCP795WXX/MCP795BXX
2.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 2-1.
2.5
FIGURE 2-1:
The SCK is used to synchronize the communication
between a master and the MCP795XXX. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
DEVICE PINOUTS
SOIC/TSSOP
2.1
1
14
Vcc
X2
2
13
CLKOUT/BOOT
VBAT
3
12
EVHS
WDO
4
11
EVLS
IRQ
5
10
SCK
CS
6
VSS
7
MCP795XXX
X1
9
SI
8
SO
2.6
2.7
Chip Select (CS)
Serial Output (SO)
Watchdog Output (WDO)
X1, X2
The X1 and X2 pins connect to the onboard oscillator
block. X1 is the input to the module and X2 is the output of the module. The device can be run from an
external CMOS signal by feeding into the X1 pin. If
driving X1 the X2 pin should be a No Connect.
2.8
VBAT
The VBAT pin is a secondary supply input to maintain
the Clock and SRAM contents when VCC is removed.
2.9
CLKOUT/BOOT
The CLKOUT is a push-pull output that can be used to
generate a squarewave or is used for the boot-up clock
output at power-up. Please refer to Section 9.1.2,
Clockout Function for more details.
2.10
The SO pin is used to transfer data out of the
MCP795XXX. During a read cycle, data is shifted out
on this pin after the falling edge of the serial clock.
2.3
Interrupt Output (IRQ)
The IRQ pin is shared with the onboard event detect
and the Alarms. This pin requires an external pull-up to
VCC or VBAT. The onboard N-Channel will pull the pin
low during an event detection or an alarm. The pin
remains low until such time that the interrupt flag in the
register is cleared by software. This pin has a maximum sink current of 10mA.
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already initiated or in progress will be completed, regardless of the
CS input signal. If CS is brought high during a program
cycle, the device will go in Standby mode as soon as
the programming cycle is complete. When the device is
deselected, SO goes into the high-impedance state,
allowing multiple parts to share the same SPI bus. A
low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence
being initiated.
2.2
Serial Clock (SCK)
EVHS and EVLS
The EVHS and EVLS are inputs for the High and Low
Speed Event Detection circuit.
TABLE 2-1:
Pin Name
PIN DESCRIPTIONS
Pin Function
This pin is a hardware open drain from the internal
watchdog circuit. This pin requires an external pull-up
to VCC. When a watchdog overflow occurs the onboard
N-Channel will pulse this pin low. The pulse duration is
user selectable (Address 0x0A:4). This pin has a maximum sink current of 10mA.
VSS
X1
X2
VBAT
VCC
SI
Ground
Xtal Input, External Oscillator Input
Xtal Output
Battery Backup Input (3V Typ)
+1.8V to +5.5V Power Supply
Serial Input
2.4
WDO
SCK
CLKOUT/
BOOT
Watchdog Output
Serial Clock
Clock Out (Boot Clock on
MCP795BXX)
CS
Chip Select
IRQ
EVHS
EVLS
SO
Interrupt Ouput
High-Speed Event Detect Input
Low-Speed Event Detect Input
Serial Output
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
DS22280A-page 6
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
2.11
RTCC Memory Map
The RTCC registers are contained in addresses 0x00h0x1fh. 64 bytes of user-accessable SRAM are located
in the address range 0x20-0x5f. The SRAM memory is
a separate block from the RTCC control and Configuration registers. All SRAM locations are battery-backedup during a VCC power fail. Unused locations are not
accessible.
• Addresses 0x00h-0x07h are the RTCC Time and
Date registers. These are read/write registers.
Care must be taken when writing to these registers with the oscillator running.
• Incorrect data can appear in the Time and Date
registers if a write is attempted during the time
frame where these internal registers are being
incremented. The user can minimize the
likelihood of data corruption by ensuring that any
writes to the Time and Date registers occur before
the contents of the second register reach a value
of 0x59H.
FIGURE 2-2:
• Addresses 0x08h-0x0Bh are the device Configuration, Calibration, Watchdog Configuration and
Event Detect Configuration registers.
• Addresses 0x0ch-0x11h are the Alarm 0 registers.
These are used to set up the Alarm 0, the interrupt pin and the Alarm 0 compare.
• Addresses 0x12h-0x17h are the Alarm 1 registers. These are used to set up the Alarm 1, the
interrupt pin and the Alarm 1 compare, Alarm 1
offers a enhanced resolution of tenth and
hundredths of seconds.
• Addresses 0x18h-0x1Fh are used for the PowerDown and Power-Up time-stamp feature. The
detailed memory map is shown in Table 4-1. No
error checking is provided when loading Time and
Date registers.
MEMORY MAP
RTCC Register/SRAM
0x00
EEPROM
0x00
Time and Date
0x07
0x09
0x0B
0x0C
Configuration and Calibration
Alarm 0
EEPROM
Memory
0x11
0x12
Alarm 1
0x17
0x18
0x1F
0x20
Time-Stamp
0xFF
Note: 1K EEPROM Max address is 0x7F.
Unique ID
SRAM (64 Bytes)
0x00
0x07
0x08
Unique ID Location 1
EUI-48/64
Unique ID Location 2
0x5F
 2011 Microchip Technology Inc.
0x0F
Preliminary
DS22280A-page 7
MCP795WXX/MCP795BXX
3.0
SPI BUS OPERATION
The MCP795XXX contains an 8-bit instruction register.
The MCP795XXX is designed to interface directly with
the Serial Peripheral Interface (SPI) port of many of
today’s popular microcontroller families, including
Microchip’s PIC® microcontrollers. It may also interface
with microcontrollers that do not have a built-in SPI port
by using discrete I/O lines programmed properly in software to match the SPI protocol.
TABLE 3-1:
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low for the entire operation.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSb first, LSb last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low.
INSTRUCTION SET SUMMARY
Instruction Name
Instruction Format
Description
EEREAD
0000 0011
Read data from EE memory array beginning at selected address
EEWRITE
0000 0010
Write data to EE memory array beginning at selected address
EEWRDI
0000 0100
Reset the write enable latch (disable write operations)
EEWREN
0000 0110
Set the write enable latch (enable write operations)
SRREAD
0000 0101
Read STATUS register
SRWRITE
0000 0001
Write STATUS register
READ
0001 0011
Read RTCC/SRAM array beginning at selected address
WRITE
0001 0010
Write RTCC/SRAM data to memory array beginning at selected
address
UNLOCK
0001 0100
Unlock ID Locations
IDWRITE
0011 0010
Write to the ID Locations
IDREAD
0011 0011
Read the ID Locations
CLRWDT
0100 0100
Clear Watchdog TImer
CLRRAM
0101 0100
Clear RAM Location to ‘0’
3.1
Read Sequence
The device is selected by pulling CS low. The various
8-bit read instructions are transmitted to the
MCP795XXX followed by an 8-bit address. See
Figure 3-1 for more details.
After the correct instruction and address are sent, the
data stored in the memory at the selected address is
shifted out on the SO pin. Data stored in the memory at
FIGURE 3-1:
the next address can be read sequentially by continuing to provide clock pulses to the slave. The internal
Address Pointer automatically increments to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to the first valid address allowing the
read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 1-1).
EEREAD SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
0
0
0
0
0
Address Byte
0
1
1 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
High-Impedance
7
SO
DS22280A-page 8
Preliminary
6
5
4
3
2
1
0
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
3.2
Nonvolatile Memory Write
Sequence
tionally, a page address begins with XXXX 0000 and
ends with XXXX X111. If the internal address counter
reaches XXXX X111 and clock signals continue to be
applied to the chip, the address counter will roll back to
the first address of the page and overwrite any data that
previously existed in those locations.
Prior to any attempt to write data to the nonvolatile
memory (EEPROM, Unique ID and STATUS register)
in the MCP795XXX, the write enable latch must be set
by issuing the EEWREN instruction (Figure 3-4). This is
done by setting CS low and then clocking out the
proper instruction into the MCP795XXX. After all eight
bits of the instruction are transmitted, CS must be
driven high to set the write enable latch. If the write
operation is initiated immediately after the EEWREN
instruction without CS driven high, data will not be written to the array since the write enable latch was not
properly set.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to Figure 3-2 and Figure 3-3 for more
detailed illustrations on the byte write sequence and
the page write sequence, respectively. While the nonvolatile memory write is in progress, the STATUS register may be read to check the status of the WIP, WEL,
BP1 and BP0 bits. Attempting to read a memory array
location will not be possible during a write cycle. Polling
the WIP bit in the STATUS register is recommended in
order to determine if a write cycle is in progress. When
the nonvolatile memory write cycle is completed, the
write enable latch is reset.
After setting the write enable latch, the user may proceed by driving CS low, issuing either an EEWRITE,
IDWRITE or a SWRITE instruction, followed by the
remainder of the address, and then the data to be written. Up to 8 bytes of data can be sent to the device
before a write cycle is necessary. The only restriction is
that all of the bytes must reside in the same page. Addi-
FIGURE 3-2:
BYTE EEWRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
0
0
0
0
0
Address Byte
0
Data Byte
0 A7 A6 A5 A4 A3 A2 A1 A0
1
Twc
7
6
5
4
3
2
1
0
High-Impedance
SO
FIGURE 3-3:
PAGE EEWRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Address Byte
Instruction
SI
0
0
0
0
0
0 1
Data Byte 1
0 A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Data Byte 2
SI
7
6
5
4
 2011 Microchip Technology Inc.
3
2
Data Byte n (8 max)
Data Byte 3
1
0
7
6
5
4
3
2
Preliminary
1
0
7
6
5
4
3
2
1
0
DS22280A-page 9
MCP795WXX/MCP795BXX
3.3
Write Enable (EEWREN) and Write
Disable (EEWRDI)
The following is a list of conditions under which the
write enable latch will be reset:
•
•
•
•
•
The MCP795XXX contains a write enable latch.
This latch must be set before any EEWRITE,
SRWRITE and IDWRITE operation will be completed
internally. The EEWREN instruction will set the latch, and
the EEWRDI will reset the latch.
FIGURE 3-4:
Power-up
EEWRDI instruction successfully executed
SRWRITE instruction successfully executed
EEWRITE instruction successfully executed
IDWRITE instruction successfully executed
WRITE ENABLE SEQUENCE (EEWREN)
CS
0
1
2
3
4
5
6
7
SCK
0
SI
0
0
0
1
1
0
High-Impedance
SO
FIGURE 3-5:
0
WRITE DISABLE SEQUENCE (EEWRDI)
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
0
High-Impedance
SO
DS22280A-page 10
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
4.0
RTCC FUNCTIONALITY
4.0.1
RTCC REGISTER MAP
All of the RTCC registers are backed up from the VBAT
supply when VCC is not available, provided that the
VBATEN bit is set. Any unused bits or non implemented addresses read back as ‘0’. No error checking
is provided for any of the RTCC, the user may load
any value.
The RTCC register space runs from 0x00 through to
0x1F. Any read or write that is started within the RTCC
register address space will wrap to the beginning of
the RTCC registers.
TABLE 4-1:
Address
The RTCC register map is shown in Table 4-1.
RTCC REGISTER MAP
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION
RANGE
Time and Configuration Registers
00h
01h
Tenth Seconds
ST (CT)
02h
03h
CALSGN
Seconds
Seconds
00-59
Minutes
Minutes
00-59
Hours
1-12 + AM/PM
00 - 23
Day
1-7
Date
01-31
05h
10 Hour
Hour
VBAT
VBATEN
Day
10 Date
06h
LP
07h
10 Year
OUT
SQWE
00-99
10 Minutes
OSCON
04h
Hundredths of
seconds
10 Seconds
10 Hour
AM/PM
12/24
08h
Hundredths of Seconds
Date
10 Month
Month
Year
ALM1
ALM0
09h
EXTOSC
WDTEN
WDTIF
WDDEL
WDTPLS
0Bh
EVHIF
EVLIF
EVEN1
EVEN0
01-12
Year
00-99
RS2
RS1
RS0
Control Reg.
WD3
WD2
WD1
WD0
Watchdog
EVWDT
EVLDB
EVHS1
EVHS0
Event Detect
CALIBRATION
0Ah
Month
Calibration
Alarm 0 Registers
0Ch
10 Seconds
Seconds
Seconds
0Dh
10 Minutes
Minutes
Minutes
00-59
Hours
1-12 + AM/PM
00-23
Day
1-7
Date
01-31
Month
01-12
Hundredths
of Seconds
00-99
00-59
0Eh
0Fh
ALM0PIN
12/24
10 Hour
AM/PM
ALM0C2
ALM0C1
10h
10 Hours
ALM0C0
Hour
ALM0IF
Day
10 Date
Date
10 Month
11h
Month
00-59
Alarm 1 Registers
12h
Tenth Seconds
Hundredths of seconds
13h
10 Seconds
Seconds
Seconds
14h
10 Minutes
Minutes
Minutes
00-59
Hours
1-12 + AM/PM
00-23
Day
1-7
Date
01-31
12/24
10 Hour
AM/PM
ALM1C2
ALM1C1
15h
16h
ALM1PIN
10 Hours
ALM1C0
Hour
ALM1IF
10 Date
17h
Day
Date
Power-down Time-stamp Registers
18h
10 Minutes
19h
12/24
10 Hour
AM/PM
Minutes
10 Hours
10 Date
1Ah
1Bh
Day
1Ch
10 Minutes
Hour
Date
10 Month
Month
Power-Up Time-stamp Registers
1Dh
12/24
10 Hours
10 Date
1Eh
1Fh
Minutes
10 Hour
AM/PM
Day
 2011 Microchip Technology Inc.
Hour
Date
10 Month
Preliminary
Month
DS22280A-page 11
MCP795WXX/MCP795BXX
5.0
TIME AND CONFIGURATION REGISTERS
REGISTER 5-1:
HUNDREDTHS OF SECONDS 0X00
RW
RW
Tenth Seconds
bit 7
Hundredths of Seconds
bit 4 bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-4
Tenth Seconds
bit 3-0
Hundredths of Seconds
Note:
Contains the BCD Tens and Hundredths of seconds
REGISTER 5-2:
SECONDS 0X01
RW
RW
RW
ST (CT)
10 Seconds
Seconds
bit 7
bit 6
bit 4 bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
bit 6-4
ST (CT)
Setting this bit ‘1’ starts the oscillator and clearing this bit ‘0’ stops the on-board oscillator. For the
MCP795BXX devices the ST bit is replaced by the CT bit. Setting this bit starts the timekeeping registers
counting.
10 Seconds
bit 3-0
Seconds
Note:
Contains the BCD seconds and 10 seconds. The range is 00 to 59.
REGISTER 5-3:
MINUTES 0X02
U
bit 7
bit 6
RW
RW
10 Minutes
Minutes
bit 4 bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
bit 6-4
Unimplemented
10 Minutes
bit 3-0
Minutes
Note:
Contains the BCD minutes and 10 minutes. The range is 00 to 59.
DS22280A-page 12
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
REGISTER 5-4:
RW
HOUR 0X03
RW
RW
RW
CALSGN
12/24
RW
10 Hour
AM/PM
10 Hour
Hour
bit 7
bit 6
bit 5
bit 4
bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
CALSGN
Bit 7 is the sign bit (CALSGN) for the calibration. Clearing this bit produces a positive calibration, setting
this bit produces a negative calibration.
bit 6
12/24
Clearing this bit to ‘0’ enables 24-hour format, setting this bit ‘1’ enables 12-hour format.
bit 5
10 Hour (AM/PM bit for 12-hour time)
bit 4
10 Hour
bit 3-0
Hour
Note:
Contains the BCD hour in bits <3:0>. Bits <5:4> contain either the 10-hour in BCD for 24-hour format or
the AM/PM indicator and the 10-hour bit for 12-hour format. Bit 5 determines the hour format.
REGISTER 5-5:
U
bit 7
DAY 0X04
U
bit 6
R
RW
OSCON
VBAT
bit 5
bit 4
RW
RW
VBATEN
bit 3
Day
bit 2
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-6
Unimplemented bit, read as ‘0’
bit 5
Bit 5 is the OSCON bit. This is set and cleared by hardware. If this bit is set the oscillator is running, if
clear, the oscillator is not running. This bit does not indicate that the oscillator is running at the correct frequency. The bit will wait 32 oscillator cycles before the bit is set.
bit 4
Bit 4 is the VBAT bit. This bit is set by hardware when the VCC fails and the VBAT is used to power the
oscillator and the RTCC registers. This bit is cleared by software.
bit 3
Bit 3 is the VBATEN bit. If this bit is set the internal circuitry is connected to the VBAT pin. If this bit is ‘0’
then the VBAT pin is disconnected and the only current drain on the external battery is the VBAT pin
leakage.
bit 2-0
Day
Note:
Contains the BCD day. The range is 1-7. Also, additional bits are used for configuration and Status.
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 13
MCP795WXX/MCP795BXX
REGISTER 5-6:
U
bit 7
DATE 0X05
U
bit 6
RW
RW
10 Date
Date
bit 5
bit 4
bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-6
Unimplemented bit, read as ‘0’
bit 5-4
10 Date
bit 3-0
Date
Note:
Contains the BCD Date and 10 Date. The range is 01-31.
REGISTER 5-7:
U
bit 7
MONTH 0X06
U
bit 6
R
RW
RW
LP
10 Month
bit 5
bit 4
Month
bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-6
bit 5
bit 4
Unimplemented bit, read as ‘0’
Bit 5 is the Leap Year bit, this is set during a leap year and is read-only.
10 Month
bit 3-0
Month
Note:
Contains the BCD month. Bit 4 contains the 10 month.
REGISTER 5-8:
bit 7
YEAR 0X07
RW
RW
10 Year
Year
bit 4 bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-4
10 Year
bit 3-0
Year
Note:
Contains the BCD Year and 10 Year. The Range is 00-99.
DS22280A-page 14
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
REGISTER 5-9:
CONTROL REG 0X08
RW
RW
RW
RW
RW
RW
RW
RW
OUT
SQWE
ALM1
ALM0
EXTOSC
RS2
RS1
RS0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
Bit 7 is the OUT bit, this sets the logic level on the CLKOUT when not using this as a square wave output.
bit 6
Bit 6 is the SQWE bit, setting this bit enables the divided output from the crystal oscillator.
bit 5:4
ALM1 Bits <5:4> determine which alarms are active.
- 00 – No Alarms are active
- 01 – Alarm 0 is active
- 10 – Alarm 1 is active
- 11 – Both Alarms are active
bit 3
Bit 3 is the EXTOSC enable bit. Setting this bit will allow an external 32.768 kHz signal to drive the RTCC
registers, eliminating the need for an external crystal.
bit 2:0
RS2 Bits <2:0> set the internal divider for the 32.768 kHz oscillator to be driven to the CLKOUT. The following frequencies are available. The output is responsive to the Calibration register.
- 000 – 1 Hz
- 001 – 4.096 kHz
- 010 – 8.192 kHz
- 011 – 32.768 kHz
- 1XX enables the Cal Output function. Cal output appears on CLKOUT if SQWE is set (1 Hz nominal).
Note:
When RS2 is set to enable the Cal Output function, the RTCC counters will continue to increment.
REGISTER 5-10:
CALIBRATION 0X09
RW
CALIBRATION
bit 7
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-0
Calibration Value
Note:
This is an 8-bit register that is used to add or subtract clocks from the RTCC counter every minute. The
CALSGN (0x03:7) is the sign bit and indicates if the count should be added or subtracted. The 8 bits in
the Calibration register, with each bit adding or subtracting two clocks, gives the user the ability to add or
subtract up to 510 clocks per minute.
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 15
MCP795WXX/MCP795BXX
REGISTER 5-11:
WATCHDOG 0X0A
RW
RW
RW
RW
RW
RW
RW
RW
WDTEN
WDTIF
WDDEL
WDTPLS
WD3
WD2
WD1
WD0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
Bit 7 is a read/write bit that is set by the user and can be cleared by the user of the hardware. This bit is
set to enable the WDT function and cleared to disable the function. This bit is cleared by the hardware
when the VCC supply is not present, it is not set again when VCC is present.
bit 6
Bit 6 is a read/write bit that is set in hardware when the WDT times out and the WD pin is asserted. This
bit must be cleared in software to restart the WDT.
bit 5
Bit 5 is a read/write bit and is set to enable a 64-second delay before the WDT starts to count. If this bit is
set and the WDTIF bit is cleared then there will be a 64 second delay before the WDT starts to count. This
bit should be set before the WDTEN bit is set.
bit 4
Bit 4 is a read/write bit that is used to select the pulse width on the WD pin when the WDT times out.
- 0 – 122 us Pulse
- 1 – 125 ms Pulse
bit 3:0
Bits <3:0> are read/write bits that are used to set the WDT time-out period as below (all times are based
off the uncalibrated crystal reference). Bit 3 should be cleared and is reserved for future use:
- 000 – 977 us
- 001 – 15.6 ms
- 010 – 62.5 ms
- 011 – 125 ms
- 100 – 1s
- 101 – 16s
- 110 – 32s
- 111 – 64s
Note:
Please see Section 9.1.3, Watchdog Timer for more information.
DS22280A-page 16
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
REGISTER 5-12:
EVENT DETECT 0X0B
RW
RW
RW
RW
RW
RW
RW
RW
EVHIF
EVLIF
EVEN1
EVEN0
EVWDT
EVLDB
EVHS1
EVHS0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
When the configured number of high speed events has occurred the IRQ pin is asserted and the EVHIF
bit is set in hardware. The clear the IRQ pin and reset the EVHIF bit must be cleared in software.
bit 6
When an event occurs on the low-speed pin this IRQ pin is asserted and the EVLIF bit is set. This bit must
be cleared by software to reset the module and clear the IRQ pin.
bit 5:4
<1:0> These two bits determine what combination of the high and low-speed modules are enabled.
- 00 – Both modules are Off
- 01 – Low-speed module enabled, high speed disabled
- 10 – Low-speed module disabled, high speed enabled
- 11 – Both modules are enabled
bit 3
Setting this bit overrides any setting for the High-Speed Event Detection and allows the EVHS pin to clear
the Watchdog Timer. This is edge triggered. Either and H-L or L-H transition will clear the WDT.
bit 2
This is the Low-Speed Event Debounce setting. Depending on the state of this bit the low-speed pin will
have to remain at the same state for the following periods to be considered valid.
- 0 – 31.25 ms
- 1 – 500 ms
bit 1:0
EVHS <1:0> These bits determine how many high-speed events must occur before the EVHIF bit is set.
All of these events must occur within 250 ms (based on the uncalibrated 32.768 kHz clock).
- 00 – 1st Event
- 01 – 4th Event
- 10 – 16th Event
- 11 – 32nd Event
Note:
Please see Section 9.1.4, Event Detection for more information.
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 17
MCP795WXX/MCP795BXX
6.0
ALARM 0 REGISTERS
REGISTER 6-1:
SECONDS 0X0C
RW
RW
RW
10 Seconds
bit 7
Seconds
bit 6
bit 4 bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
Unimplemented
bit 6-4
10 Seconds
bit 3-0
Seconds
Note:
This contains the seconds match for the Alarm 0.
REGISTER 6-2:
MINUTES 0X0D
RW
RW
RW
10 Minutes
bit 7
Minutes
bit 6
bit 4 bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
Unimplemented
bit 6-4
10 Minutes
bit 3-0
Minutes
Note:
This contains the minutes match for the Alarm 0.
REGISTER 6-3:
HOURS 0X0E
RW
bit 7
RW
RW
12/24
10 Hour
AM/PM
10 Hour
bit 6
bit 5
bit 4
Hour
bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
Unimplemented
bit 6
12/24 (this is a copy of bit 6 in the Hours register (0x03)
bit 5
10 Hour AM/PM
bit 4
10 Hour
bit 3-0
Hour
DS22280A-page 18
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
REGISTER 6-4:
DAY 0X0F
RW
RW
ALM0PIN
ALM0C2
bit 7
bit6
ALM0C1
RW
RW
ALM0C0
ALM0IF
Day
bit 4
bit 3
bit 2
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
BIT 6:4
bit 3
bit 2-0
Bit 7 configures the pin that is used for the Alarm 0 output. If this bit is clear the IRQ pin is used. If set, the
WDO pin is used. If the WDT is enabled then a valid Alarm will assert the WDO pin for 122 us.
Bits <6:4> sets the condition on what the Alarm will trigger. The following options are available:
000 – Seconds match
001 – Minutes match
010 – Hours match (logic takes into account 12/24 operation)
011 – Day match. Generates interrupt at 12:00:00 AM
100 – Date match
101 – Unimplemented, do not use
110 – Unimplemented, do not use
111 – Seconds, Minutes, Hour, Day, Date and Month
Bit 3 is the ALM0IF bit. This is set by hardware when an alarm condition has be generated. The bit must
be cleared in software.
Day
REGISTER 6-5:
U
DATE 0X10
U
RW
RW
RW
10 Date
bit 7
bit 6
bit 5
bit 4
Date
bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-6
Unimplemented
bit 5-4
10 Date
bit 3-0
Date
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 19
MCP795WXX/MCP795BXX
REGISTER 6-6:
U
MONTH 0X11
U
U
RW
RW
10 Month
bit 7
bit 6
bit 5
bit 4
Month
bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-5
bit 4
Unimplemented
10 Month
bit 3-0
Month
Note:
Month match is only available on Alarm 0.
DS22280A-page 20
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
7.0
ALARM 1 REGISTERS
REGISTER 7-1:
HUNDREDTHS OF SECONDS 0X12
RW
RW
Tenth Seconds
bit 7
Hundredths of Seconds
bit 4 bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-4
Tenth Seconds
bit 3-0
Hundredths of Seconds
Note:
Hundredths and Tenth seconds only available on Alarm 1.
REGISTER 7-2:
SECONDS 0X13
U
bit 7
RW
RW
10 Seconds
Seconds
bit 6
bit 4 bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
Unimplemented
bit 6-4
10 Seconds
bit 3-0
Seconds
REGISTER 7-3:
MINUTES 0X14
U
RW
RW
10 Minutes
bit 7
bit 6
Minutes
bit 4 bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
Unimplemented
bit 6-4
10 Minutes
bit 3-0
Minutes
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 21
MCP795WXX/MCP795BXX
REGISTER 7-4:
U
bit 7
HOURS 0X15
RW
RW
RW
12/24
RW
10 Hour
AM/PM
10 Hour
Hour
bit 6
bit 5
bit 4
bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
Unimplemented
bit 6
12/24
bit 5
10 Hour AM/PM
bit 4
10 Hour
bit 3-0
Hour
REGISTER 7-5:
RW
DAY 0X16
RW
RW
RW
RW
RW
ALM1PIN
ALM1C2
ALM1C1
ALM1C0
ALM1IF
Day
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
BIT 6:4
bit 3
bit 2-0
Bit 7 configures the pin that is used for the Alarm 0 output. If this bit is clear the IRQ pin is used. If set, the
WDO pin is used. If the WDT is enabled then a valid Alarm will assert the WDO pin for 122 us.
Bits <6:4> sets the condition on what the Alarm will trigger. The following options are available:
000 – Seconds match
001 – Minutes match
010 – Hours match (logic takes into account 12/24 operation)
011 – Day match, generates interrupt at 12:00:00 am
100 – Date match
101 – Hundredths/Tenth of Seconds
110 – Unimplemented do not use
111 – Seconds, Minutes, Hour, Day and Date
Bit 3 is the ALM1IF bit. This is set by hardware when an alarm condition has be generated. The bit must
be cleared in software.
Day
DS22280A-page 22
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
REGISTER 7-6:
U
bit 7
DATE 0X17
U
bit 6
bit 5
RW
RW
10 Date
Date
bit 4
bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-6
Unimplemented
bit 5-4
10 Date
bit 3-0
Date
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 23
MCP795WXX/MCP795BXX
8.0
POWER-DOWN TIME-STAMP REGISTERS
Note:
It is strongly recommended that the timesaver function only be used when the oscillator is running. This
will ensure accurate functionality.
REGISTER 8-1:
MINUTES 0X18
U
RW
RW
10 Minutes
bit 7
Minutes
bit 6
bit 4 bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
Unimplemented
bit 6-4
10 Minutes
bit 3-0
Minutes
HOUR 0X19
REGISTER 8-2:
U
bit 7
RW
RW
RW
12/24
10 Hour
AM/PM
10 Hours
bit 6
bit 5
bit 4
RW
Hour
bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
Unimplemented
bit 6
12/24 (this is a copy of the status of the bit in register 0x03:6 at the time of the event)
bit 5
10 Hour AM/PM
bit 4
bit 3-0
10 Hour
Hour
REGISTER 8-3:
U
DATE 0X1A
U
RW
RW
RW
10 Date
bit 7
bit 6
bit 5
bit 4
Date
bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-6
Unimplemented
bit 5-4
10 Date
bit 3-0
Date
DS22280A-page 24
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
REGISTER 8-4:
RW
MONTH 0X1B
RW
RW
Day
bit 7
bit 6
RW
RW
10 Month
bit 5
bit 4
Month
bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-5
bit 4
bit 3-0
Day
10 Month
Month
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 25
MCP795WXX/MCP795BXX
9.0
POWER-UP TIME REGISTERS
Note:
It is strongly recommended that the timesaver function only be used when the oscillator is running. This
will ensure accurate functionality.
REGISTER 9-1:
MINUTES 0X1C
U
RW
RW
10 Minutes
bit 7
Minutes
bit 6
bit 4 bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
Unimplemented
bit 6-4
10 Minutes
bit 3-0
Minutes
HOUR 0X1D
REGISTER 9-2:
U
bit 7
RW
RW
RW
12/24
10 Hour
AM/PM
10 Hours
bit 6
bit 5
bit 4
RW
Hour
bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7
Unimplemented
bit 6
12/24 (this is a copy of the status of the bit in register 0x03:6 at the time of the event)
bit 5
10 Hour AM/PM
bit 4
bit 3-0
10 Hour
Hour
DS22280A-page 26
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
REGISTER 9-3:
U
DATE 0X1E
U
RW
RW
RW
10 Date
bit 7
bit 6
bit 5
Date
bit 4
bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-6
Unimplemented
bit 5-4
10 Date
bit 3-0
Date
MONTH 0X1F
REGISTER 9-4:
RW
RW
RW
Day
bit 7
bit 6
RW
RW
10 Month
bit 5
bit 4
Month
bit 3
bit 0
Legend: R = Readable Bit W = Writable Bit U = Unimplemented bit, Read as ‘0’
bit 7-5
bit 4
bit 3-0
Day
10 Month
Month
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 27
MCP795WXX/MCP795BXX
9.1
Features
9.1.1
CALIBRATION
The Calibration register (0x09h) allows a number of
RTCC counts to be added or subtracted (Cal Sign bit
located at 0x03:7) each minute. This allows for
calibration to reduce the PPM error due to oscillator
shift. This register is volatile.
The frequencies listed in the table presume an input
clock source of exactly 32.768 kHz. In terms of the
equivalent number of input clock cycles, the table
becomes:
RS2
RS1
RS0
Output Signal
0
0
0
0
0
0
1
1
0
1
0
1
32768
8
4
1
The CALSIGN determines if calibration is positive or
negative.
A value of 0x00 in the Calibration register will result in
no calibration.
The calibration is linear, with one bit representing two
RTC clocks.
The MCP795XXX utilizes digital calibration to correct
for the inaccuracies of the input clock source (either
external or crystal). Calibration is enabled by setting
the value of the Calibration register at address 08H.
Calibration is achieved by adding or subtracting a
number of input clock cycles per minute in order to
achieve ppm level adjustments in the internal timing
function of the MCP795XXX.
The CALSGN bit is the sign bit, with a ‘1’ indicating
subtraction and a ‘0’ indicating addition. The eight bits
in the calibration register indicate the number of input
clock cycles (multiplied by two) that are subtracted or
added per minute to the internal timing function.
The internal timing function can be monitored using
the CLKOUT output pin by setting bit 6 (SQWE) and
bits <2:0> (RS2, RS1, RS0) of the Control register at
address 07H. Note that the CLKOUT output waveform
is disabled when the MCP795XXX is running in VBAT
mode. With the SQWE bit set to ‘1’, there are two
methods that can be used to observe the internal
timing function of the MCP795XXX:
A. RS2 bit set to ‘0’
With the RS2 bit set to ‘0’, the RS1 and RS0 bits
enable the following internal timing signals to be
output on the CLKOUT pin:
RS2
RS1
RS0
Output Signal
0
0
0
0
0
0
1
1
0
1
0
1
1 Hz
4.096 kHz
8.192 kHz
32.768 kHz
DS22280A-page 28
With regards to the calibration function, the Calibration
register setting has no impact upon the CLKOUT
output clock signal when bits RS1 and RS0 are set to
‘11’. The setting of the calibration register to a nonzero value enables the calibration function which can
be observed on the CLKOUT output pin. The
calibration function can be expressed in terms of the
number of input clock cycles added/subtracted from
the internal timing function.
With bits RS1 and RS0 set to ‘00’, the calibration
function can be expressed as:
=
(32768 +/- (2 * CALREG)) Tinput
Toutput
=
clock period of CLKOUT output
signal
Tinput
=
clock period of input signal
CALREG
=
decimal value of calibration
register setting and the sign is
determined by the CALSGN bit.
Toutput
where:
Since the calibration is done once per minute (i.e.
when the internal minute counter is incremented), only
one cycle in sixty of the CLKOUT output waveform is
affected by the calibration setting. Also note that the
duty cycle of the CLKOUT output waveform will not
necessarily be at 50% when the calibration setting is
applied.
With bits RS1 and RS0 set to ‘01’ or ‘10’, the
calibration function can not be expressed in terms of
the input clock period. In the case where the MSB of
the Calibration register is set to ‘0’, the waveform
appearing at the CLKOUT output pin will be “delayed”,
once per minute, by twice the number of input clock
cycles defined in the Calibration register. The CLKOUT
waveform will appear as shown in Figure 9-1.
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
In the case where the MSB of the Calibration register
is set to ‘1’, the CLKOUT output waveforms that
appear when bits RS1 and RS0 are set to ‘01’ or ‘10’
are not as responsive to the setting of the Calibration
register. For example, when outputting the 4.096 kHz
waveform (RS1, RS0 set to ‘01’), the output waveform
is generated using only eight input clock cycles.
Consequently, attempting to subtract more than eight
input clock cycles from this output does not have a
meaningful affect on the resulting waveform. Any
affect on the output will appear as a modification in
both the frequency and duty cycle of the waveform
appearing on the CLKOUT output pin.
B.RS2 bit set to ‘1’
With the RS2 bit set to ‘1’, the following internal timing
signal is output on the CLKOUT pin:
RS2
RS1
RS0
Output Signal
1
x
x
1.0 Hz
The frequency listed in the table presumes an input
clock source of exactly 32.768 kHz. In terms of the
equivalent number of input clock cycles, the table
becomes:
RS2
RS1
RS0
Output Signal
1
x
x
32768
Unlike the method previously described, the
calibration setting is continuously applied and affects
every cycle of the output waveform. This results in the
modulation of the frequency of the output waveform
based upon the setting of the Calibration register.
Using this setting, the calibration function can be
expressed as:
=
(32768 +/- (2 * CALREG)) Tinput
Toutput
=
clock period of CLKOUT output
signal
Tinput
=
clock period of input signal
CALREG
=
decimal value of calibration
register setting and the sign is
determined by the CALSGN bit.
Toutput
where:
Since the calibration is done every cycle, the frequency
of the output CLKOUT waveform is constant.
FIGURE 9-1:
CLKOUT WAVEFORM
Delay
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 29
MCP795WXX/MCP795BXX
9.1.2
CLOCKOUT FUNCTION
The MCP795W20 features a push-pull pin CLKOUT
that can supply a digital signal based on a division of
the main 32.768 kHz clock. If this function is not used
the pin may be directly controlled using the OUT bit in
the Control register (0x08). In VBAT mode, CLKOUT is
logic low. In VDD POR condition, the CLKOUT is tristated. For the MCP795BXX devices, this pin functions
as a Power-up Boot clock. A 32.768 kHz clock is
enabled upon application of VCC.
9.1.3
WATCHDOG TIMER
The on-board Watchdog Timer is configured by loading
the register at address 0x0A. The WDT is not available
when the MCP795XXX is operating from the VBAT supply. When in this condition, the WDT is disabled by the
hardware and must be re-enabled when VCC is
restored. The output of the WDT is based on the uncalibrated 32.768 kHz oscillator.
Description of WDT Bits:
• Bit 7 is a read/write bit that is set and cleared by
software. This bit is set to enable the WDT function and cleared to disable the function. A VCC
power fail will cause this bit to be cleared and not
re-enabled when VCC is restored.
• Bit 6 is a read/write bit that is set in hardware
when the WDT times out and the WDO pin is
asserted. This bit must be cleared in software to
restart the WDT.
• Bit 5 is a read/write bit and is set to enable a 64second delay before the WDT starts to count. If
this bit is set and the WDTIF bit is cleared then
there will be a 64-second delay before the WDT
starts to count. This bit should be set before the
WDTEN bit is set.
• Bit 4 is a read/write bit that is used to select the
pulse width on the WDO pin when the WDT times
out.
- 0 – 122 us Pulse
- 1 – 125 ms Pulse
• Bits <3:0> are read/write bits that are used to set
the WDT time-out period as below (all times are
based off the uncalibrated crystal reference). Bit 3
should be cleared and is reserved for future use:
- 000 – 977 us
- 001– 15.6 ms
- 010 – 62.5 ms
- 011 – 125 ms
- 100 – 1s
- 101 – 16s
- 110 – 32s
- 111 – 64s
DS22280A-page 30
To reset the WDT the CLRWDT instruction must be
issued over the SPI interface, as shown in Figure 9-7.
If the WDT is not cleared with the CLRWDT command
before time-out then the WDO pin will assert and the
WDTIF bit will be set. The WDTIF bit must be cleared
by software to restart the WDT.
9.1.4
EVENT DETECTION
The on-chip event detection consists of two separate
detection circuits.
The high-speed circuit is designed to operate with a
digital signal from the output of an external signal conditioning circuit. The input is edge triggered, and will
generate an interrupt when the correct number of
events has occurred.
The low-speed circuit is designed to operate directly
with mechanical switches and support built-in switch
debounce.
Registers associated with the event detection module:
• EVHIF – When the configured number of high
speed events has occurred the IRQ pin is
asserted and the EVHIF bit is set. This bit must be
cleared by software to reset the module and clear
the IRQ pin.
• EVLIF – When an event occurs on the low-speed
pin this IRQ pin is asserted and the EVLIF bit is
set. This bit must be cleared by software to reset
the module and clear the IRQ pin.
• EVEN<1:0> – These two bits determine what
combination of the high and low-speed modules
are enabled.
- 00 – Both modules are off
- 01 – Only low-speed module enabled
- 10 – Only high-speed module disabled
- 11 – Both modules are enabled
• EVWDT – setting this bit overrides any setting for
the High-Speed Event Detection and allows the
EVHS pin to clear the Watchdog Timer. This is
edge triggered. Either H-L or L-H transition will
clear the WDT.
• EVLDB – This is the low-speed event debounce
setting. Depending on the state of this bit the lowspeed pin will have to remain at the same state for
the following periods to be considered valid.
- 0 – 31.25 ms
- 1 – 500 ms
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
The debounce will only operate if the clock is running
and these timings are based on the uncalibrated
32.768 kHz clock.
TABLE 9-1:
• EVHS<1:0> – These bits determine how many
high-speed events must occur before the EVHIF
bit is set. All of these events must occur within
250 ms.
- 00 – 1st Event
- 01 – 4th Event
- 10 – 16th Event
- 11 – 32nd Event
9.1.5
Supply
Condition
Read/Write
Access
Powered
By
VCC < VTRIP, VCC < VBAT
VCC > VTRIP, VCC < VBAT
VCC > VTRIP, VCC > VBAT
No
Yes
Yes
VBAT
VCC
VCC
For more information on VBAT conditions see the RTCC
Best Practices Application Note, AN1365 (DS01365).
9.1.6
VBAT SWITCHOVER
UNIQUE ID LOCATIONS
When the unique ID locations are preprogrammed from
the factory with either an EUI-48 or EUI-64, the EUI
code is programmed into location 0x00-0x07. Locations 0x08-0x0F are blank (0x0F).
If the VBAT feature is not used, the VBAT pin should be
connected to GND. A low value series resistor and
Schottky diode are recommended between the
external battery and the VBAT pin to reduce inrush
current and also to prevent any leakage current
reaching the external VBAT source.
Note:
For EUI-64, the data is located in address
0x00-0x07. For EUI-48 locations, 0x020x07 contain the data. 0x00/01 contain
0xFF.
To read the unique ID location the IDREAD command
is given with the starting address. Valid addresses are
0x00 through 0x0F. All 16 bytes can be read out in a
single command by clocking the device. Trying to
access locations past 0x0F will result in the address
wrapping within these 16 bytes.
The VTRIP point is defined as 1.5V typical. When VDD
falls below 1.5V the system will continue to operate
the RTCC and SRAM using the VBAT supply. There is
~50mV hyst in the trip point changeover. The following
conditions apply:
FIGURE 9-2:
VBAT CHANGOVER
CONDITIONS
IDREAD COMMAND SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
0
0
1
1
0
Address Byte
0
1
1
0
0
0
0
3
2
1
Don’t Care
0
Data Out
High-Impedance
7
SO
6
5
4
3
2
1
0
Address range is 0x00-0x0F, address counter will wrap within this range.
To write to the unique ID locations, the IDWRITE command is used. The device must be write enabled and
the correct unlock sequence must have been performed. See Section 10.1.4, Write to the Unlock
Register for more details.
 2011 Microchip Technology Inc.
The ID locations can be written to using the IDWRITE
command. The valid address is between 0x00 and
0x0F. The entire 16 bytes must be written in two
groups of 8 bytes. A maximum of 8 bytes can be
written at once.
Preliminary
DS22280A-page 31
MCP795WXX/MCP795BXX
FIGURE 9-3:
IDWRITE COMMAND SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 13 14 15 16 17 18 19 20 21 22 23 24
SCK
Instruction
SI
0
0
1
1
0
Address Byte
0
1
0
0
0
0
3
0
2
Data Byte 1
1
0
7
6
5
4
3
2
1
0
CS
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SCK
Data Byte 2
SI
7
DS22280A-page 32
6
5
4
3
Data Byte 3
2
1
0
7
6
5
4
3
Data Byte n (8 max)
2
Preliminary
1
0
7
6
5
4
3
2
1
0
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
9.1.7
POWER-FAIL TIME-STAMP
The MCP795XXX family of RTCC devices feature a
power-fail time-stamp feature. This feature will save the
time at which VCC crosses the VTRIP voltage and is
shown in Figure 9-4. To use this feature, a VBAT supply
must be present and the oscillator must also be running. There are two separate sets of registers that are
used to record this information:
• The second set of registers, located at 0x1Ch
through 0x1Fh, are loaded at the time when VCC
is restored and the RTCC switches to VCC.
The power-fail time-stamp registers are cleared when
the VBAT bit is cleared in software.
Note:
• The first set located at 0x18h through 0x1Bh are
loaded at the time when VCC falls below VTRIP
and the RTCC operates on the VBAT. The VBAT
(register 0x03h bit 4) bit is also set at this time.
FIGURE 9-4:
It is strongly recommended that the timesaver function only be used when the
oscillator is running. This will ensure accurate functionality
POWER-FAIL GRAPH
VCC
VTRIP(max)
VTRIP(min)
Power-Down
Time-Stamp
Power-Up
Time-Stamp
VCCRT
VCCFT
9.1.8
READ STATUS REGISTER
(SRREAD)
The Read Status Register (SRREAD) instruction provides access to the STATUS register. The STATUS
register may be read at any time, even during a write
cycle. The STATUS register is formatted as follows:
7
—
X
6
—
X
5
—
X
4
—
X
3
R/W
BP1
2
R/W
BP0
1
R
WEL
0
R
WIP
via the WREN or WRDI commands, regardless of the
state of write protection on the STATUS register. This
bit is read-only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile.
See Figure 9-5 for the RDSR timing sequence.
*
Note:
Once a Write Status Register is initiated
and a Read Status Register is attempted
the new values for the nonvolatile bits will
be read regardless of whether the values
have been actually programmed into the
device. (i.e., The values are moved to the
latches prior to the write operation).
The Write-In-Process (WIP) bit indicates whether the
MCP795XXX is busy with a nonvolatile memory write
operation. When set to a ‘1’, a write is in progress,
when set to a ‘0’, no write is in progress. This bit is
read-only.
The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a ‘1’, the
latch allows writes to the nonvolatile memory, when
set to a ‘0’, the latch prohibits writes to the nonvolatile
memory. The state of this bit can always be updated
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 33
MCP795WXX/MCP795BXX
FIGURE 9-5:
READ STATUS REGISTER TIMING SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction
SI
0
0
0
0
0
High-Impedance
SO
1
0
1
Data from STATUS Register
7
6
5
4
3
2
1
0
* Data should be able to continuously be read from the STATUS register without toggling CS, for updating of
the WIP and WEL bits.
DS22280A-page 34
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
9.1.9
WRITE STATUS REGISTER
(SRWRITE)
The Write Status Register (SRWRITE) instruction
allows the user to select one of four levels of protection for the array by writing to the appropriate bits in
the status register. The array is divided up into four
segments. The user has the ability to write protect
none, one, two, or all four of the segments of the array.
The partitioning is controlled as shown in Table 9-2.
See Figure 9-6 for the SRWRITE timing sequence.
TABLE 9-2:
ARRAY PROTECTION
Array Addresses
Write-Protected
(2 kbit shown)
BP1
BP0
0
0
none
0
1
upper 1/4
(C0h-FFh)
1
0
upper 1/2
(80h-FFh)
1
1
all
(00h-FFh)
FIGURE 9-6:
WRITE STATUS REGISTER TIMING SEQUENCE
CS
TWC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
0
Data to STATUS Register
0
0
1
7
6
5
4
3
2
High-Impedance
SO
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 35
MCP795WXX/MCP795BXX
9.1.10
DATA PROTECTION
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal EEPROM
write cycle is ignored and programming is continued
• Block protect bits are ignored for UID writes
The following protection has been implemented to prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A Write Enable instruction must be issued to set
the write enable latch
• After a byte write, page write, unique ID write, or
STATUS register write, the write enable latch is
reset
FIGURE 9-7:
9.1.11
CLEAR WATCHDOG INSTRUCTION
The Clear Watchdog command resets the internal
Watchdog Timer.
CLRWDT
CS
0
1
2
3
4
5
6
7
SCK
0
SI
1
0
0
0
1
0
0
High-Impedance
SO
9.1.12
CLEAR RAM INSTRUCTION
The Clear Ram instruction is a 2-byte command that
will reset the internal SRAM to the known value. Using
this command, all locations in the SRAM are set to 00h
and the data value contained in the second byte of the
command is ignored.
FIGURE 9-8:
CLRRAM
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
Instruction
SI
0
1
0
1
0
Data
1
0
0 A7 6
5
4
3
2
1
A0
High-Impedance
SO
DS22280A-page 36
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
9.2
Crystal Specification and
Selection
The MCP795XXX has been designed to operate with a
standard 32.768 kHz tuning fork crystal. The on-board
oscillator has been characterized to operate with a
crystal of maximum ESR of 70K Ohms.
Crystals with a comparable specification are also suitable for use with the MCP795XXX.
The table below is given as design guidance and a
starting point for crystal and capacitor selection.
Manufacturer
Crystal
Capacitance
Part Number
CX1 Value
CX2 Value
Micro Crystal
CM7V-T1A
7pF
10pF
12pF
Citizen
CM200S-32.768KDZB-UT
6pF
10pF
8 pF
Please work with your crystal vendor.
EQUATION 9-1:
Gerber files are available on request. Please contact
your Microchip Sales representative.
CX2  CX1
C load = ----------------------------- + C stray
CX2 + CX1
The following must also be taken into consideration:
• Pin capacitance (to be included in Cx2 and Cx1)
• Stray Board Capacitance
The recommended board layout for the oscillator area
is shown in Figure 9-9. This actual board shows the
crystal and the load capacitors. In this example, C2 is
CX1, C1 is CX2 and the crystal is designated as Y1.
It is required that the final application should be tested
with the chosen crystal and capacitor combinations
across all operating and environmental conditions.
Please also consult with the crystal specification to
observe correct handling and reflow conditions and for
information on ideal capacitor values.
For more information please see the RTCC Best
Practices AN1365 (DS01365).
When calculating the effective load capacitance,
Equation 9-1 can be used.
FIGURE 9-9:
BOARD LAYOUT
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 37
MCP795WXX/MCP795BXX
10.0
ON-BOARD MEMORY
10.1.2
The part is selected by pulling CS low. The 8-bit READ
instruction is transmitted to the MCP795W20 followed
by the 8-bit address (A7 through A0). After the correct
READ instruction and address are sent, the data stored
in the memory at the selected address is shifted out on
the SO pin. The data stored in the memory at the next
address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after
each byte of data is shifted out.
The MCP795XXX has both on-board EEPROM memory and battery-backed SRAM. The SRAM is arranged
as 64 x 8 bytes and is retained when VCC supply is
removed. The EEPROM is organized as 256/128 x 8
bytes. The EEPROM is nonvolatile and does not
require VBAT supply for retention.
10.1
SRAM
The SRAM array is a battery-backed-up array of 64
bytes. The SRAM is accessed using the Read and
Write commands, starting at address 0x20h.
As the RTCC registers are separate from the SRAM
array, when reading the RTCC registers set the
address will wrap back to the start of the RTCC registers. Also when an address within the SRAM array is
loaded the internal Address Pointer will wrap back to
the start of the SRAM array. The READ instruction can
be used to read the registers and array indefinitely by
continuing to clock the device. The read operation is
terminated by raising the CS pin (Figure 10-1).
Upon power-up the SRAM locations are in an undefined state but can be set to a known value using the
CLRRAM instruction (Figure 9-8).
10.1.1
READ SEQUENCE
SRAM/RTCC OPERATION
The MCP795XXX contains a Real-Time Clock and Calendar. The RTCC registers and SRAM array are
accessed using the same commands. The RTCC registers and SRAM array are powered internally from the
switched supply that is either connected to VCC or VBAT
supply. No external read/write operations are permitted
when the device is running from the VBAT supply.
10.1.3
WRITE SEQUENCE
As the RTCC registers and SRAM array do not require
the WREN sequence like the nonvolatile memory, the
user may proceed by setting the CS low, issuing the
WRITE instruction, followed by the address, and then
the data to be written. As no write cycle is required for
the RTCC registers and SRAM array the entire contents can be written in a single command.
Table 1-2 contains a list of the possible instruction
bytes and format for device operation.
For the last data byte to be written to the RTCC registers and SRAM array, the CS must be brought high
after the last byte has been clocked in. If CS is brought
high at any other time, the last byte will not be written.
Refer to Figure 10-2 for more detailed illustrations on
the write sequence.
FIGURE 10-1:
READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Address Byte
Instruction
SI
0
0
0
1
0
0
1
1 A7 6
5
4
3
2
1
A0
Don’t Care
Data Out
High-Impedance
7
SO
6
5
4
3
2
1
0
The address will rollover to the start of either the RTCC registers or SRAM array.
DS22280A-page 38
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
FIGURE 10-2:
WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
0
0
0
1
0
Data Byte
Address Byte
0 1
0 A7 6
5
4
3
2
1
A0
7
6
5
4
3
2
1
0
High-Impedance
SO
10.1.4
WRITE TO THE UNLOCK REGISTER
The following is a list of strict conditions which have to
be followed before the unique locations can be written
to:
The MCP795XXX contains a protected area of 64 bits
that can be used to hold a unique ID, such as a serial
number or MAC address code. To gain write access to
these locations, a specific sequence is required. Any
deviation from this sequence will reset the lock on
these locations. Once these locations have been
unlocked they have to be written to in the next command by issuing the correct command. A write to a different location will lock the ID locations and clear the
WEL bit.
• EEWREN instruction successfully executed
• UNLOCK 0x55 instruction successfully executed
• UNLOCK 0xAA instruction successfully executed
To issue each Unlock instruction the UNLOCK command is sent followed by 0x55. Then in a separate
command the UNLOCK command is issued followed
by 0xAA. It is a requirement that each command be
separate, that is CS must toggle between each command.
Information on how to read and write the ID locations
is detailed in Section 9.1.6, Unique ID Locations.
FIGURE 10-3:
UNLOCK SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
Instruction
SI
0
0
0
1
0
Data
1
0
0
7
6
5
4
3
2
1
0
High-Impedance
SO
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 39
MCP795WXX/MCP795BXX
11.0
PACKAGING INFORMATION
11.1
Package Marking Information
14-Lead SOIC (.150”)
Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
MCP795W20
-I/SL
1144017
14-Lead TSSOP
Example
XXXXXXXX
YYWW
NNN
795W20T
1144
017
Part Number
SOIC
TSSOP
MCP795W20
MCP795W20
795W20T
MCP795W10
MCP795W10
795W10T
MCP795W21
MCP795W21
795W21T
MCP795W11
MCP795W11
795W11T
MCP795W22
MCP795W22
795W22T
MCP795W12
MCP795W12
795W12T
MCP795B20
MCP795B20
795B20T
MCP795B10
MCP795B10
795B10T
MCP795B21
MCP795B21
795B21T
MCP795B11
MCP795B11
795B11T
MCP795B22
MCP795B22
795B22T
MCP795B12
MCP795B12
795B12T
Note:
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS22280A-page 40
1st Line Marking Codes
T = Temperature grade
NN = Alphanumeric traceability code
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 41
MCP795WXX/MCP795BXX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22280A-page 42
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
! "# $ % &" ' #
())$$$ ) "
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 43
MCP795WXX/MCP795BXX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22280A-page 44
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 45
MCP795WXX/MCP795BXX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22280A-page 46
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
APPENDIX A:
REVISION HISTORY
Revision A (11/2011)
Initial Release.
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 47
MCP795WXX/MCP795BXX
NOTES:
DS22280A-page 48
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 49
MCP795WXX/MCP795BXX
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
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RE:
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Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: MCP795WXX/MCP795BXX
Literature Number: DS22280A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS22280A-page 50
Preliminary
 2011 Microchip Technology Inc.
MCP795WXX/MCP795BXX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not every possible ordering
combination is listed below.
MCP795
1
W
Base Part Additional Memory
Features
0
T
Unique
ID
T/R
I
/SN
Temp Package
Range
MCP794 = I2C™ RTCC
MCP795 = SPI RTCC
Additional
Features:
Blank = None
W
= Watchdog Timer, 2 Event Detects
B
= 32 kHz Boot-up Clock, Watchdog Timer, 2 Event
Detects
Memory:
0
1
2
= 64 Bytes SRAM
= 1 Kbit EE, 64 Bytes SRAM
= 2 Kbits EE, 64 Bytes SRAM
ID/MAC Address:
0
1
2
= Blank
= EUI-48™ MAC Address
= EUI-64™ MAC Address
Blank = Tube
T
= Tape and Reel
Temperature
Range:
I
Package:
SL = 14-Pin SOIC
ST = 14-Pin TSSOP
=
a)
b)
c)
Base Part No.:
T/R:
Examples:
d)
e)
f)
MCP795W20-I/SL: 2K EEPROM, Blank ID,
Industrial Temperature, SOIC Package
MCP795W10-I/ST: 1K EEPROM, Blank ID,
Industrial Temperature, TSSOP Package
MCP795W21-I/SL: 2K EEPROM, EUI-48™,
Industrial Temperature, SOIC Package
MCP795W22-I/ST: 2K EEPROM, EUI-64™,
Industrial Temperature, TSSOP Package
MCP795B20-I/SL: Boot Clock, 2K EEPROM,
Blank ID, Industrial Temperature, SOIC
Package
MCP795B10-I/ST: Boot Clock, 1K EEPROM,
Blank ID, Industrial Temperature, TSSOP
Package
Note
1:
All devices include a Watchdog Timer
and two Event Detects.
-40C to +85C
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 51
MCP795WXX/MCP795BXX
NOTES:
DS22280A-page 52
Preliminary
 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-780-5
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2011 Microchip Technology Inc.
Preliminary
DS22280A-page 53
Worldwide Sales and Service
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DS22280A-page 54
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
08/02/11
Preliminary
 2011 Microchip Technology Inc.