Cypress B9948L 2.5v/3.3v, 160-mhz, 1:12 clock distribution buffer Datasheet

B9948L
2.5V/3.3V, 160-MHz, 1:12 Clock Distribution Buffer
Product Features
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Description
160-MHz clock support
2.5V or 3.3V output capability
200-ps maximum output-to-output skew
LVPECL or LVCMOS/LVTTL clock input
LVCMOS/LVTTL compatible inputs
12 clock outputs: drive up to 24 clock lines
Synchronous Output Enable
Output Three-state control
Pin compatible with MPC948L
Industrial temp. range: –40°C to +85°C
32-pin TQFP package
The B9948L is a low-voltage clock distribution buffer with the
capability to select either a differential LVPECL or a LVCMOS/
LVTTL compatible input clock. The two clock sources can be
used to provide for a test clock as well as the primary system
clock. All other control inputs are LVCMOS/LVTTL compatible.
The twelve outputs are 2.5V or 3.3V LVCMOS or LVTTL compatible and can drive two series-terminated 50Ω transmission
lines. With this capability the B9948L has an effective fanout
of 1:24. The outputs can also be three-stated via the threestate input TS#. Low output-to-output skews make the B9948L
an ideal clock distribution buffer for nested clock trees in the
most demanding of synchronous systems.
The B9948L also provides a synchronous output enable input
for enabling or disabling the output clocks. Since this input is
internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
Pin Configuration
PECL_CLK
PECL_CLK#
0
TCLK
1
VDDC
32
31
30
29
28
27
26
25
VDD
VSS
Q0
VDDC
Q1
VSS
Q2
VDDC
Q3
Block Diagram
12
TCLK_SEL
TCLK
PECL_CLK
PECL_CLK#
SYNC_OE
TS#
VDD
VSS
Q0-Q11
TCLK_SEL
SYNC_OE
B9948L
24
23
22
21
20
19
18
17
VSS
Q4
VDDC
Q5
VSS
Q6
VDDC
Q7
Q11
VDDC
Q10
VSS
Q9
VDDC
Q8
VSS
9
10
11
12
13
14
15
16
TS#
1
2
3
4
5
6
7
8
Cypress Semiconductor Corporation
Document #: 38-07080 Rev. *C
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3901 North First Street
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San Jose
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CA 95134 • 408-943-2600
Revised December 21, 2002
B9948L
Pin Description[1]
Pin
Name
PWR
3
PECL_CLK
I, PU
PECL Input Clock.
4
PECL_CLK#
I, PD
PECL Input Clock.
2
TCLK
I, PU
External Reference/Test Clock Input.
9, 11, 13, 15, 17,
19, 21, 23, 25, 27,
29, 31
Q(11:0)
1
TCLK_SEL
I, PU
Clock Select Input. When LOW, PECL clock is selected and
when HIGH TCLK is selected.
5
SYNC_OE
I, PU
Output Enable Input. When asserted HIGH, the outputs are
enabled and when set low the outputs are disabled in a LOW
state.
6
TS#
I, PU
Three-state Control Input. When asserted LOW, the output
buffers are three-stated. When set HIGH, the output buffers
are enabled.
10, 14, 18, 22, 26,
30
VDDC
7
VDD
3.3V Power Supply.
8, 12, 16, 20, 24,
28, 32
VSS
Common Ground.
VDDC
I/O
O
Description
Clock Outputs.
2.5V or 3.3V Power Supply for Output Clock Buffers.
Note:
1. PD = Internal Pull-Down, PU = Internal Pull-Up.
Output Enable/Disable
The B9948L features a control input to enable or disable the
outputs. This data is latched on the falling edge of the input
clock. When SYNC_OE is asserted LOW, the outputs are disabled in a LOW state. When SYNC_OE is set HIGH, the outputs are enabled as shown in Figure 1.
TCLK
SYNC_OE
Q
Figure 1. SYNC_OE Timing Diagram
Document #: 38-07080 Rev. *C
Page 2 of 6
B9948L
Maximum Ratings[2]
Storage Temperature: ................................–65°C to + 150°C
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For
proper operation, Vin and Vout should be constrained to the
range:
Operating Temperature: ................................ –40°C to +85°C
VSS < (Vin or Vout) < VDD
Maximum ESD protection ............................................... 2 kV
Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V
Maximum Input Voltage Relative to VDD:............. VDD + 0.3V
Maximum Power Supply: ................................................5.5V
Maximum Input Current:..................................................±20 mA
DC Parameters: VDDC = 2.5V±5% or 3.3V ±5%, VDD = 3.3V ±5%, TA = –40°C to +85°C
Parameter
VIL
VIH
Description
Input Low Voltage
Input High Voltage
Conditions
Min.
Input Low Current (@VIL = VSS)
IIH
Input High Current (@VIL =VDD)
VPP
Peak-to-Peak Input Voltage
PECL_CLK
VCMR
Common Mode Range PECL_CLK
VOL
VOH
Output Low Voltage
Output High Voltage
Quiescent Supply Current
Cin
Input Capacitance
V
1.825
All other inputs
VSS
0.8
PECL_CLK, Single ended
2.135
2.42
2.0
VDD
Note 3
Note 4
µA
100
µA
300
1000
mV
VDD – 2.0
VDD – 0.6
V
0.4
V
IOL = 20 mA
[5]
2.5
[5]
2.0
IOH = –20 mA, VDDC = 3.3V
All VDDC and VDD
4.
5.
V
–100
[5]
Notes:
2. The voltage on any input or I/O pin cannot exceed the power pin during
power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up resistors that effect input current, PECL_CLK# has a
pull-down resistor.
Document #: 38-07080 Rev. *C
Unit
1.49
IOH = –20 mA, VDDC = 2.5V
IDD
Max.
PECL_CLK, Single ended
All other inputs
IIL
Typ.
V
1
2
mA
4
pF
The VCMR is the difference from the most positive side of the differential
input signal. Normal operation is obtained when the “High” input is within
the VCMR range and the input lies within the VPP specification.
Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission
lines.
Page 3 of 6
B9948L
AC Parameters[6]: VDDC = 2.5V±5% or 3.3V ±5%, VDD = 3.3V ±5%, TA = –40°C to +85°C
Parameter
Description
Conditions
Min.
Typ.
Max.
Fmax
Maximum Input Frequency[7]
160
Tpd
PECL_CLK to Q Delay[7]
4.0
-
9.0
TCLK to Q Delay[7]
4.4
-
8.9
FoutDC
Output Duty Cycle[7,8]
tpZL, tpZH
tpLZ, tpHZ
TCYCLE/2 +
1000
ps
Output enable time (all outputs)
2
10
ns
Output disable time (all outputs)
2
10
ns
200
ps
Part to Part
Skew[10]
Set-up Time
Hold
Tr/Tf
ns
TCYCLE/2 –
1000
Output-to-Output Skew
Tskew (pp)
Th
MHz
[7,9]
Tskew
Ts
Measured at VDDC/2
Unit
[7,11]
Time[7,11]
Output Clocks Rise/Fall Time
[9]
PECL_CLK to Q
1.5
TCLK to Q
2.0
SYNC_OE to PECL_CLK
1.0
SYNC_OE to TCLK
0.0
PECL_CLK to SYNC_OE
0.0
TCLK to SYNC_OE
1.0
10% to 90%
0.3
ns
ns
ns
1.6
ns
Notes:
6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7. Outputs driving 50Ω transmission lines.
8. 50% input duty cycle.
9. Outputs loaded with 30 pF each
10. Part-to-Part Skew at a given temperature and voltage.
11. Set-up and Hold times are relative to the falling edge of the input clock
Ordering Information
Part Number[12]
B9948LAA
Package Type
32-Pin TQFP
Production Flow
Industrial, –40°C to +85°C
Note:
12. The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below.
Marking: Example:
Cypress
B9948LAA
Date Code, Lot #
B9948LAA
Package
A = TQFP
Revision
Device Number
Document #: 38-07080 Rev. *C
Page 4 of 6
B9948L
Package Drawing and Dimensions
32-Pin TQFP Outline Dimensions
Inches
D
D1
12°
L
Document #: 38-07080 Rev. *C
Symbol
Min.
Nom.
Max.
Min.
Nom.
Max.
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
-
0.041
0.95
-
1.05
D
-
0.354
-
-
9.00
-
D1
-
0.276
-
-
7.00
-
b
0.012
-
0.018
0.30
-
0.45
e
A1
e
Ml
L
0.031 BSC
0.018
-
0.80 BSC
0.030
0.45
-
0.75
b
Page 5 of 6
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
B9948L
Document Title: B9948L 2.5V/3.3V, 160 MHz, 1:12 Clock Distribution Buffer
Document Number: 38-07080
Rev.
ECN No.
Issue
Date
Orig. of
Change
Description of Change
**
107116
06/06/01
IKA
Convert from IMI to Cypress
*A
108061
07/03/01
NDP
Changed Commercial to Industrial (See page 6)
*B
109806
02/01/02
DSG
Convert from Word to Frame
*C
122765
12/21/02
RBI
Add power up requirements to maximum ratings information.
Document #: 38-07080 Rev. *C
Page 6 of 6
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