AD AD797 Ultralow distortion, ultralow noise op amp Datasheet

a
Ultralow Distortion,
Ultralow Noise Op Amp
AD797*
FEATURES
Low Noise
0.9 nV/√Hz typ (1.2 nV/√Hz max) Input Voltage
Noise at 1 kHz
50 nV p-p Input Voltage Noise, 0.1 Hz to 10 Hz
Low Distortion
–120 dB Total Harmonic Distortion at 20 kHz
Excellent AC Characteristics
800 ns Settling Time to 16 Bits (10 V Step)
110 MHz Gain Bandwidth (G = 1000)
8 MHz Bandwidth (G = 10)
280 kHz Full Power Bandwidth at 20 V p-p
20 V/ms Slew Rate
Excellent DC Precision
80 mV max Input Offset Voltage
1.0 mV/8C VOS Drift
Specified for 65 V and 615 V Power Supplies
High Output Drive Current of 50 mA
CONNECTION DIAGRAM
8-Pin Plastic Mini-DIP (N),
Cerdip (Q) and SOIC (R) Packages
PRODUCT DESCRIPTION
The AD797 is a very low noise, low distortion operational
amplifier ideal for use as a preamplifier. The low noise of
0.9 nV/√Hz and low total harmonic distortion of –120 dB at
audio bandwidths give the AD797 the wide dynamic range
2
7
+VS
+IN
3
6
OUTPUT
–VS
4
5
OFFSET NULL
TOP VIEW
The AD797 is also useful in IR and Sonar Imaging applications
where the widest dynamic range is necessary. The low distortion and 16-bit settling time of the AD797 make it ideal for
buffering the inputs to Σ∆ ADCs or the outputs of high resolution DACs especially when they are used in critical applications
such as seismic detection and spectrum analyzers. Key features
such as a 50 mA output current drive and the specified power
supply voltage range of ± 5 to ± 15 volts make the AD797 an
excellent general purpose amplifier.
5
–90
3
2
1
–100
0.001
–110
0.0003
–120
0.0001
THD – %
4
THD – dB
Hz
–IN
necessary for preamps in microphones and mixing consoles.
Furthermore, the AD797’s excellent slew rate of 20 V/µs and
110 MHz gain bandwidth make it highly suitable for low frequency ultrasound applications.
APPLICATIONS
Professional Audio Preamplifiers
IR, CCD, and Sonar Imaging Systems
Spectrum Analyzers
Ultrasound Preamplifiers
Seismic Detectors
SD ADC/DAC Buffers
INPUT VOLTAGE NOISE – nV/
1
AD797
8
DECOMPENSATION &
DISTORTION
NEUTRALIZATION
OFFSET NULL
MEASUREMENT
LIMIT
0
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
AD797 Voltage Noise Spectral Density
–130
100
300
1k
3k
10k
FREQUENCY – Hz
30k
100k
300k
THD vs. Frequency
*Patent pending.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD797–SPECIFICATIONS (@ T = +258C and V = 615 V dc, unless otherwise noted)
A
Model
Conditions
S
VS
Min
± 5 V, ± 15 V
INPUT OFFSET VOLTAGE
TMIN to TMAX
Offset Voltage Drift
INPUT BIAS CURRENT
0.25
0.5
1.5
3.0
0.25 0.9
0.25 2.0
µA
µA
± 5 V, ± 15 V
100
120
400
600/700
80
120
nA
nA
± 15 V
G = 1000
G = 10002
G = 10
VO = 20 V p-p,
RLOAD = 1 kΩ
RLOAD = 1 kΩ
10 V Step
± 15 V
± 15 V
± 15 V
COMMON-MODE REJECTION
VCM = CMVR
TMIN to TMAX
± 5 V, ± 15 V
POWER SUPPLY REJECTION
VS = ± 5 V to ± 18 V
TMIN to TMAX
INPUT VOLTAGE NOISE
f = 0. 1 Hz to 10 Hz
f = 10 Hz
f = 1 kHz
f = 10 Hz–1 MHz
± 15 V
± 15 V
± 15 V
± 15 V
50
1.7
0.9
1.0
f = 1 kHz
± 15 V
2.0
–3 dB Bandwidth
Full Power Bandwidth3
Slew Rate
Settling Time to 0.0015%
INPUT CURRENT NOISE
INPUT COMMON-MODE
VOLTAGE RANGE
OUTPUT VOLTAGE SWING
RLOAD = 2 kΩ
RLOAD = 600 Ω
RLOAD = 600 Ω
Short-Circuit Current
Output Current4
TOTAL HARMONIC DISTORTION
RLOAD = 1 kΩ, CN = 50 pF
f = 250 kHz, 3 V rms
RLOAD = 1 kΩ
f = 20 kHz, 3 V rms
1
1
1
1
14000
± 15 V
± 15 V
± 15 V
POWER SUPPLY
Operating Range
Quiescent Current
20
6
15
5
20000
2
2
2
2
14000
110
450
8
12.5
280
20
800
12.5
1200
200
300
20
10
15
7
20000
V/µV
V/µV
V/µV
V/µV
V/V
110
450
8
MHz
MHz
MHz
280
20
800
kHz
V/µs
ns
1200
114
110
130
120
120
114
130
120
dB
dB
114
110
130
120
120
114
130
120
dB
dB
50
1.7
0.9
1.0
1.2
1.3
2.5
1.2
1.2
nV p-p
nV/√Hz
nV/√Hz
µV rms
2.0
pA/√Hz
± 15 V
±5 V
± 11
± 2.5
± 12
±3
± 11
± 2.5
± 12
±3
V
V
± 15 V
± 15 V
±5 V
± 5 V, ± 15 V
± 5 V, ± 15 V
± 12
± 11
± 2.5
± 13
± 13
±3
80
50
± 12
± 11
± 2.5
± 13
± 13
±3
80
50
V
V
V
mA
mA
30
30
± 15 V
–98
–90
–98
± 15 V
–120
–110
–120 –110
dB
7.5
100
20
5
7.5
100
20
5
kΩ
MΩ
pF
pF
3
3
mΩ
INPUT CHARACTERISTICS
Input Resistance (Differential)
Input Resistance (Common Mode)
Input Capacitance (Differential)5
Input Capacitance (Common Mode)
OUTPUT RESISTANCE
µV
µV
µV/°C
± 5 V, ± 15 V
± 5 V, ± 15 V
40
60
0.6
Units
10
30
0.2
VOUT = ± 10 V
RLOAD = 2 kΩ
TMIN to TMAX
RLOAD = 600 Ω
TMIN to TMAX
@ 20 kHz2
DYNAMIC PERFORMANCE
Gain Bandwidth Product
AD797B
Typ Max
80
125/180
1.0
TMIN to TMAX
OPEN-LOOP GAIN
Min
25
50
0.2
TMIN to TMAX
INPUT OFFSET CURRENT
AD797A/S1
Typ Max
AV = +1, f = 1 kHz
± 5 V, ± 15 V
±5
8.2
± 18
10.5
±5
8.2
–90
± 18
10.5
dB
V
mA
NOTES
1
See standard military drawing for 883B specifications.
2
Specified using external decompensation capacitor, see Applications section.
3
Full Power Bandwidth = Slew Rate/2 π VPEAK.
4
Output Current for |V S – VOUT| >4 V, A OL > 200 kΩ.
5
Differential input capacitance consists of 1.5 pF package capacitance and 18.5 pF from the input differential pair.
Specifications subject to change without notice.
–2–
REV. C
AD797
ABSOLUTE MAXIMUM RATINGS 1
3
The AD797’s inputs are protected by back-to-back diodes. To achieve low noise,
internal current limiting resistors are not incorporated into the design of this
amplifier. If the differential input voltage exceeds ± 0.7 V, the input current should
be limited to less than 25 mA by series protection resistors. Note, however, that this
will degrade the low noise performance of the device.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation @ +25°C2
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . ± 0.7 V
Output Short Circuit Duration . . . . . . . Indefinite Within max
Internal Power Dissipation
Storage Temperature Range (Cerdip) . . . . . . –65°C to +150°C
Storage Temperature Range (N, R Suffix) . . –65°C to +125°C
Operating Temperature Range
AD797A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD797S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . +300°C
ESD SUSCEPTIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without
detection. Although the AD797 features proprietary ESD protection circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Internal Power Dissipation:
8-Pin SOIC = 0.9 Watts (T A–25°C)/θJA
8-Pin Plastic DIP and Cerdip = 1.3 Watts – (T A–25°C)/θJA
Thermal Characteristics
8-Pin Plastic DIP Package: θJA = 95°C/W
8-Pin Cerdip Package: θJA = 110°C/W
8-Pin Small Outline Package: θJA = 155°C/W
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD797AN
AD797BN
AD797BR
AD797BR-REEL
AD797BR-REEL7
AD797AR
AD797AR-REEL
AD797AR-REEL7
5962-9313301MPA
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
8-Pin Plastic DIP
8-Pin Plastic DIP
8-Pin Plastic SOIC
8-Pin Plastic SOIC
8-Pin Plastic SOIC
8-Pin Plastic SOIC
8-Pin Plastic SOIC
8-Pin Plastic SOIC
8-Pin Cerdip
N-8
N-8
SO-8
SO-8
SO-8
SO-8
SO-8
SO-8
Q-8
METALIZATION PHOTO
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
NOTE
The AD797 has double layer metal. Only one layer is shown here for clarity.
REV. C
–3–
AD797–Typical Characteristics
VERTICAL SCALE – 0.01µV/DIV
INPUT COMMON-MODE RANGE – ±Volts
20
15
10
5
0
0
5
15
10
20
HORIZONTAL SCALE – 5 sec/DIV
SUPPLY VOLTAGE – ±Volts
Figure 4. 0.1 Hz to 10 Hz Noise
Figure 1. Common-Mode Voltage Range vs. Supply
0.0
INPUT BIAS CURRENT – µA
OUTPUT VOLTAGE SWING – ±Volts
20
15
10
+VOUT
–V OUT
5
5
10
15
–1.0
–1.5
–2.0
–60
0
0
–0.5
20
–40
–20
0
SUPPLY VOLTAGE – ±Volts
100
120
140
Figure 5. Input Bias Current vs. Temperature
Figure 2. Output Voltage Swing vs. Supply
140
SHORT CIRCUIT CURRENT – mA
30
OUTPUT VOLTAGE SWING – Volts p-p
20
40
60
80
TEMPERATURE – °C
VS = ±15V
20
10
V S = ±5V
100
1k
LOAD RESISTANCE – Ω
100
SOURCE CURRENT
SINK CURRENT
80
60
40
–60
0
10
120
10k
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE – °C
Figure 6. Short Circuit Current vs. Temperature
Figure 3. Output Voltage Swing vs. Load Resistance
–4–
REV. C
AD797
140
+125°C
9
+25°C
8
7
–55°C
6
0
5
15
10
120
100
150
125
80
CMR
60
100
40
75
50
1M
20
20
1
SUPPLY VOLTAGE – ±Volts
10
100
1k
10k
100k
FREQUENCY – Hz
Figure 10. Power Supply and Common-Mode Rejection
vs. Frequency
Figure 7. Quiescent Supply Current vs. Supply Voltage
–60
12
RL = 600 Ω
G = +10
FREQ = 10kHz
NOISE BW = 100kHz
FREQ = 1kHz
RL = 600Ω
G = +10
9
THD + NOISE – dB
OUTPUT VOLTAGE – Volts rms
PSR
+SUPPLY
PSR
–SUPPLY
6
–80
VS = ±5V
–100
3
VS = ±15V
–120
0.01
0
0
±5
±15
±10
±20
0.1
1.0
10
OUTPUT LEVEL – Volts
SUPPLY VOLTAGE – Volts
Figure 11. Total Harmonic Distortion (THD) + Noise vs.
Output Level
Figure 8. Output Voltage vs. Supply for 0.01% Distortion
30
1.0
±15V SUPPLIES
RL = 600 Ω
SETTLING TIME – µs
0.8
0.0015%
20
0.6
0.01%
0.4
10
±5V SUPPLIES
0.2
0.0
0
2
4
6
8
0
10k
10
100k
1M
10M
STEP SIZE – Volts
Figure 12. Large Signal Frequency Response
Figure 9. Settling Time vs. Step Size (± )
REV. C
COMMON MODE REJECTION – dB
10
POWER SUPPLY REJECTION – dB
QUIESCENT SUPPLY CURRENT – mA
11
–5–
120
35
GAIN/BANDWIDTH PRODUCT
4
110
30
SLEW RATE – V/µs
INPUT VOLTAGE NOISE – nV/
Hz
5
3
2
SLEW RATE
RISING EDGE
25
100
SLEW RATE
FALLING EDGE
20
90
1
15
–60
0
10
100
1k
10k
100k
1M
10M
–40
–20
0
20
40
60
80
100
120
GAIN/BANDWIDTH PRODUCT – MHz (G = 1000)
AD797–Typical Characteristics
80
140
TEMPERATURE – °C
FREQUENCY – Hz
Figure 13. Input Voltage Noise Spectral Density
120
Figure 16. Slew Rate & Gain/Bandwidth Product vs.
Temperature
+100
160
+80
WITHOUT
RS*
WITH RS*
+60
80
+40
60
GAIN
+20
40
WITHOUT
RS*
*RS = 100Ω
SEE FIGURE 22
20
OPEN-LOOP GAIN – dB
OPEN-LOOP GAIN – dB
100
PHASE MARGIN – DEGREES
PHASE MARGIN
140
120
0
WITH RS*
0
100
1k
10k
100k
1M
10M
100
100M
100
LOAD RESISTANCE – Ohms
Figure 17. Open-Loop Gain vs. Resistive Load
Figure 14. Open-Loop Gain & Phase vs. Frequency
MAGNITUDE OF OUTPUT IMPEDANCE – Ohms
INPUT OFFSET CURRENT – nA
300
OVER COMPENSATED
150
0
–150
UNDER COMPENSATED
–300
–60
10k
1k
FREQUENCY – Hz
100
10
* SEE FIGURE 29
1
WITHOUT CN*
0.1
WITH CN*
0.01
–40
–20
0
20
40
60
80
100
120
10
140
TEMPERATURE – °C
100
1k
10k
100k
1M
FREQUENCY – Hz
Figure 15. Input Offset Current vs. Temperature
Figure 18. Magnitude of Output Impedance vs. Frequency
–6–
REV. C
AD797
20pF
50mV
1µs
1kΩ
+V S
100
100
90
90
10
10
100ns
**
1kΩ
2
VIN
7
AD797
3
VOUT
6
4
**
5V
–VS
** SEE FIGURE 32
0%
0%
Figure 19. Inverter
Connection
Figure 21. Inverter Small Signal
Pulse Response
Figure 20. Inverter Large Signal
Pulse Response
100Ω
5V
+V S
2
**
1µs
50mV
100
100
90
90
10
10
0%
0%
100ns
7
VOUT
AD797
RS*
V IN
3
4
6
**
600Ω
–VS
* VALUE OF SOURCE RESISTANCE –
SEE TEXT
** SEE FIGURE 32
Figure 23. Follower Large Signal
Pulse Response
Figure 22. Follower
Connection
5mV
Figure 24. Follower Small Signal
Pulse Response
500ns
5mV
100
100
90
90
10
10
0%
0%
500ns
See Figure 40 for settling time
test circuit.
Figure 25. 16-Bit Settling Time
Positive Input Pulse
REV. C
–7–
Figure 26. 16-Bit Settling Time
Negative Input Pulse
AD797
This matching benefits not just dc precision but since it holds
up dynamically, both distortion and settling time are also
reduced. This single stage has a voltage gain of >5 × 106 and
VOS <80 µV, while at the same time providing THD + noise of
less than –120 dB and true 16 bit settling in less than 800 ns.
The elimination of second stage noise effects has the additional
benefit of making the low noise of the AD797 (<0.9 nV/√Hz)
extend to beyond 1 MHz. This means new levels of performance for sampled data and imaging systems. All of this performance as well as load drive in excess of 30 mA are made
possible by Analog Devices’ advanced Complementary Bipolar
(CB) process.
THEORY OF OPERATION
The new architecture of the AD797 was developed to overcome
inherent limitations in previous amplifier designs. Previous precision amplifiers used three stages to ensure high open-loop
gain, Figure 27b, at the expense of additional frequency compensation components. Slew rate and settling performance are
usually compromised, and dynamic performance is not adequate beyond audio frequencies. As can be seen in Figure 27b,
the first stage gain is rolled off at high frequencies by the compensation network. Second stage noise and distortion will then
appear at the input and degrade performance. The AD797 on
the other hand, uses a single ultrahigh gain stage to achieve dc
as well as dynamic precision. As shown in the simplified schematic (Figure 28), nodes A, B, and C all track in voltage forcing
the operating points of all pairs of devices in the signal path to
match. By exploiting the inherent matching of devices fabricated
on the same IC chip, high open-loop gain, CMRR, PSRR, and
low VOS are all guaranteed by pairwise device matching (i.e.,
NPN to NPN & PNP to PNP), and not absolute parameters
such as beta and early voltage.
gm
A single equation yields the open-loop transfer function of this
amplifier, solving it (at Node B) yields:
VO
gm
=
V IN CN
C
jω – CN jω – C jω
A
A
VOUT
BUFFER
R1
Another unique feature of this circuit is that the addition of a
single capacitor, CN (Figure 28), enables cancellation of distortion due to the output stage. This can best be explained by
referring to a simplified representation of the AD797 using idealized blocks for the different circuit elements (Figure 29).
RL
C1
gm = the transconductance of Q1 and Q2
A = the gain of the output stage, (~1)
VO = voltage at the output
VIN = differential input voltage
GAIN = gmR1 ≈ 5 x 10 6
a.
When CN is equal to CC this gives the ideal single pole op amp
response:
VO
gm
=
VIN
jωC
The terms in A, which include the properties of the output
stage such as output impedance and distortion, cancel by
simple subtraction, and therefore the distortion cancellation
does not affect the stability or frequency response of the amplifier. With only 500 µA of output stage bias the AD797 delivers
a 1 kHz sine wave into 600 Ω at 7 V rms with only 1 ppm of
distortion.
C2
gm
A3
A2
R1
VOUT
BUFFER
RL
C1
R2
GAIN = gmR1 *A2 *A3
b.
Figure 27. Model of AD797 vs. That of a Typical
Three-Stage Amplifier
VCC
R2
R3
I1
I2
CN
CN
R1
I5
Q4
B
–IN
Q1
Q2
I1
Q5
C
Q6
CC
Q12
A
OUT
Q9
+IN
OUT
Q10
Q7
A
–IN
+IN
Q1
Q8
CURRENT
MIRROR
Q2
Q11
CC
1
I3
I6
I7
B
A
Q3
C
I4
I4
VSS
Figure 29. AD797 Block Diagram
Figure 28. AD797 Simplified Schematic
–8–
REV. C
AD797
NOISE AND SOURCE IMPEDANCE CONSIDERATIONS
LOW FREQUENCY NOISE
The AD797’s ultralow voltage noise of 0.9 nV/√Hz is achieved
with special input transistors running at nearly 1 mA of collector
current. It is important then to consider the total input referred
noise (eNtotal), which includes contributions from voltage noise
(eN), current noise (iN), and resistor noise (√4 kTrS).
where rS = total input source resistance.
Analog Devices specifies low frequency noise as a peak to peak
(p-p) quantity in a 0.1 Hz to 10 Hz bandwidth. Several techniques can be used to make this measurement. The usual technique involves amplifying, filtering, and measuring the amplifiers
noise for a predetermined test time. The noise bandwidth of the
filter is corrected for and the test time is carefully controlled
since the measurement time acts as an additional low frequency
roll-off.
This equation is plotted for the AD797 in Figure 30. Since optimum dc performance is obtained with matched source resistances, this case is considered even though it is clear from
Equation 1 that eliminating the balancing source resistance will
lower the total noise by reducing the total rS by a factor of two.
The plot in Figure 4 was made using a slightly different technique. Here an FFT based instrument (Figure 31) is used to
generate a 10 Hz “brickwall” filter. A low frequency pole at
0.1 Hz is generated with an external ac coupling capacitor, the
instrument being dc coupled.
eNtotal = [eN2 + 4 kTrS + 4 (iNrS)2]l/2
Equation 1
At very low source resistance (rS <50 Ω), the amplifiers’ voltage
noise dominates. As source resistance increases the Johnson
noise of rS dominates until at higher resistances (rS >2 kΩ) the
current noise component is larger than the resistor noise.
Several precautions are necessary to get optimum low frequency
noise performance:
1. Care must be used to account for the effects of rS, even a
10 Ω resistor has 0.4 nV/√Hz of noise (an error of 9% when
root sum squared with 0.9 nV/√Hz).
100
NOISE – nV/
Hz
2. The test set up must be fully warmed up to prevent eOS drift
from erroneously contributing to input noise.
3. Circuitry must be shielded from air currents. Heat flow out
of the package through its leads creates the opportunity for a
thermoelectric potential at every junction of different metals.
Selective heating and cooling of these by random air currents
will appear as 1/f noise and obscure the true device noise.
TOTAL NOISE
10
RESISTOR
NOISE
ONLY
1
4. The results must be interpreted using valid statistical
techniques.
100kΩ
0.1
10
100
1000
+VS
10000
**
SOURCE RESISTANCE – Ω
1Ω
Figure 30. Noise vs. Source Resistance
2
The AD797 is the optimum choice for low noise performance
provided the source resistance is kept <1 kΩ. At higher values of
source resistance, optimum performance with respect to noise
alone is obtained with other amplifiers from Analog Devices (see
Table I).
7
AD797
3
4
1.5µF
6
VOUT
HP 3465
DYNAMIC SIGNAL
ANALYZER
(10Hz)
**
–V S
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 31. Test Setup for Measuring 0.1 Hz to 10 Hz Noise
Table I. Recommended Amplifiers for Different Source
Impedances
WIDEBAND NOISE
rS, ohms
Recommended Amplifier
0 to <1 k
1 k to <10 k
10 k to <100 k
>100 k
AD797
AD707, AD743/AD745, OP27/OP37, OP07
AD705, AD743/AD745, OP07
AD548, AD549, AD645, AD711, AD743/
AD745
REV. C
The AD797, due to its single stage design, has the property that
its noise is flat over frequencies from less than 10 Hz to beyond
1 MHz. This is not true of most dc precision amplifiers where
second stage noise contributes to input referred noise beyond
the audio frequency range. The AD797 offers new levels of performance in wideband imaging applications. In sampled data
systems, where aliasing of out of band noise into the signal band
is a problem, the AD797 will out perform all previously available IC op amps.
–9–
AD797
BYPASSING CONSIDERATIONS
To take full advantage of the very wide bandwidth and dynamic
range capabilities of the AD797 requires some precautions.
First, multiple bypassing is recommended in any precision
application. A 1.0 µF–4.7 µF tantalum in parallel with 0.1 µF
ceramic bypass capacitors are sufficient in most applications.
When driving heavy loads a larger demand is placed on the supply bypassing. In this case selective use of larger values of tantalum capacitors and damping of their lead inductance with small
value (1.1 Ω to 4.7 Ω) carbon resistors can be an improvement.
Figure 32 summarizes bypassing recommendations. The symbol
(**) is used throughout this data sheet to represent the parallel
combination of a 0.1 µF and a 4.7 µF capacitor.
follower. Operation on 5 volt supplies allows the use of a 100 Ω
or less feedback network (R1 + R2). Since the AD797 shows
no unusual behavior when operating near its maximum rated
current, it is suitable for driving the AD600/AD602 (Figure 47)
while preserving their low noise performance.
Optimum flatness and stability at noise gains >1 sometimes
requires a small capacitor (CL) connected across the feedback
resistor (R1, Figure 35). Table II includes recommended values
of CL for several gains. In general, when R2 is greater than
100 Ω and CL is greater than 33 pF, a 100 Ω resistor should
be placed in series with CL. Source resistance matching is
assumed, and the AD797 should never be operated with unbalanced source resistance >200 kΩ/G.
VS
VS
OR
0.1µF
CL
4.7 – 22.0µF
100 Ω
4.7µF
0.1µF
1.1 – 4.7Ω
USE SHORT
LEAD LENGTHS
(<5mm)
+VS
KELVIN RETURN
KELVIN RETURN
USE SHORT
LEAD RETURNS
(<5mm)
LOAD
CURRENT
2
LOAD
CURRENT
7
AD797
RS*
VIN
Figure 32. Recommended Power Supply Bypassing
**
3
6
4
VOUT
600 Ω
**
CS*
–VS
THE NONINVERTING CONFIGURATION
Ultralow noise requires very low values of rBB’ (the internal
parasitic resistance) for the input transistors (≈6 Ω). This implies very little damping of input and output reactive interactions. With the AD797, additional input series damping is
required for stability with direct input to output feedback. A
100 Ω resistor in the inverting input (Figure 33) is sufficient;
the 100 Ω balancing resistor (R2) is recommended, but is not
required for stability. The noise penalty is minimal (eNtotal
≈2.1 nV/√Hz), which is usually insignificant. Best response
flatness is obtained with the addition of a small capacitor
(CL < 33 pF) in parallel with the 100 Ω resistor (Figure 34).
The input source resistance and capacitance will also affect the
response slightly and experimentation may be necessary for best
results.
* SEE TEXT
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 34. Alternative Voltage Follower Connection
CL
R2
+VS
**
R1
7
2
AD797
3
VIN
R1
100Ω
4
VOUT
6
RL
**
–VS
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
+V S
**
2
VIN
7
AD797
R2
100Ω
3
Figure 35. Low Noise Preamplifier
4
Table II. Values for Follower With Gain Circuit
6
**
VOUT
RL
600Ω
–VS
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 33. Voltage Follower Connection
Low noise preamplification is usually done in the noninverting
mode (Figure 35). For lowest noise the equivalent resistance of
the feedback network should be as low as possible. The 30 mA
minimum drive current of the AD797 makes it easier to achieve
this. The feedback resistors can be made as low as possible with
due consideration to load drive and power consumption. Table
II gives some representative values for the AD797 as a low noise
Gain
R1
R2
CL
2
2
10
20
>35
1 kΩ
300 Ω
33.2 Ω
16.5 Ω
10 Ω
1 kΩ
≈20 pF
300 Ω
≈10 pF
300 Ω
≈5 pF
316 Ω
(G–1) • 10 Ω
Noise
(Excluding rS)
3.0 nV/√Hz
1.8 nV/√Hz
1.2 nV/√Hz
1.0 nV/√Hz
0.98 nV/√Hz
The I-to-V converter is a special case of the follower configuration. When the AD797 is used in an I-to-V converter, for instance as a DAC buffer, the circuit of Figure 36 should be used.
The value of CL depends on the DAC and again, if CL is
–10–
REV. C
AD797
20–120pF
DRIVING CAPACITIVE LOADS
100 Ω
The capacitive load driving capabilities of the AD797 are displayed in Figure 38. At gains over 10 usually no special precautions are necessary. If more drive is desirable the circuit in
Figure 39 should be used. Here a 5000 pF load can be driven
cleanly at any noise gain ≥ 2.
R1
+VS
**
IIN
2
7
CS*
4
VOUT
6
**
100nF
600 Ω
CAPACITIVE LOAD DRIVE CAPABILITY
AD797
3
RS*
–VS
* SEE TEXT
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 36. I-to-V Converter Connection
greater than 33 pF a 100 Ω series resistor is required. A bypassed balancing resistor (RS and CS) can be included to minimize dc errors.
10nF
1nF
100pF
THE INVERTING CONFIGURATION
10pF
1pF
1
The inverting configuration (Figure 37) presents a low input
impedance, R1, to the source. For this reason, the goals of both
low noise and input buffering are at odds with one another.
Nonetheless, the excellent dynamics of the AD797 will make it
the preferred choice in many inverting applications, and with careful selection of feedback resistors the noise penalties will be minimal. Some examples are presented in Table II and Figure 37.
10
100
1k
CLOSED-LOOP GAIN
Figure 38. Capacitive Load Drive Capability vs. Closed
Loop Gain
20pF
1k Ω
100 Ω
200pF
CL
+VS
R2
**
1k Ω
2
+VS
VIN
**
AD797
R1
2
VIN
7
AD797
3
4
3
6
**
4
33 Ω
VOUT
6
**
C1
VOUT
–VS
RL
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
RS*
–VS
* SEE TEXT
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 37. Inverting Amplifier Connection
Table III. Values for Inverting Circuit
Gain
R1
R2
CL
Noise
(Excluding rS)
–1
–1
–10
1 kΩ
300 Ω
150 Ω
1 kΩ
300 Ω
1500 Ω
≈20 pF
≈10 pF
≈5 pF
3.0 nV/√Hz
1.8 nV/√Hz
1.8 nV/√Hz
REV. C
7
Figure 39. Recommended Circuit for Driving a High
Capacitance Load
SETTLING TIME
The AD797 is unique among ultralow noise amplifiers in that it
settles to 16 bits (<150 µV) in less than 800 ns. Measuring this
performance presents a challenge. A special test setup (Figure
40) was developed for this purpose. The input signal was obtained from a resonant reed switch pulse generator, available
from Tektronix as calibration Fixture No. 067-0608-00. When
open, the switch is simply 50 Ω to ground and settling is purely
a passive pulse decay and inherently flat. The low repetition rate
signal was captured on a digital oscilloscope after being amplified and clamped twice. The selection of plug-in for the oscilloscope was made for minimum overload recovery.
–11–
AD797
TO TEKTRONIX
7A26
OSCILLOSCOPE
PREAMP INPUT
SECTION
4.26k Ω
226 Ω
R1
1M Ω
20pF
50pF
R2
2
(VIA LESS THAN 1FT
50Ω COAXIAL CABLE)
2
250ΩΩ
A2
AD829
AD797
VERROR X 5
VIN
2x
HP2835
4
2x
HP2835
a.
0.47µF
0.47µF
R1
+VS
–VS
C2
1kΩ Ω
TEKTRONIX
CALIBRATION
FIXTURE
1kΩ Ω
100Ω Ω 1kΩΩ
VIN
6
3
6
7
3
8
1kΩΩ
20pF
C1
R2
NOTE:
USE CIRCUIT
BOARD
WITH GROUND
PLANE
2
8
AD797
VIN
6
3
2
A1
AD797
C1, SEE TABLE
C2 = 50pF – C1
6
51pF
7
3
b.
Figure 41. Recommended Connections for Distortion
Cancellation and Bandwidth Enhancement
4
1µF
0.1µF
+VS
–VS
Table IV. Recommended External Compensation
Figure 40. Settling Time Test Circuit
A/B
R1 R2
Ω
Ω
DISTORTION REDUCTION
At higher gains and higher frequencies THD will increase due
to reduction in loop gain. However in contrast to most conventional voltage feedback amplifiers the AD797 provides two effective means of reducing distortion, as gain and frequency are
increased; cancellation of the output stage’s distortion and gain
bandwidth enhancement by decompensation. By applying these
techniques gain bandwidth can be increased to 450 MHz at
G = 1000 and distortion can be held to –100 dB at 20 kHz for
G = 100.
G = 10
909 100 0
G = 100 1 k 10 0
G = 1000 10 k 10 0
6 MHz 0
1 MHz 15
110 kHz 33
50 6 MHz
33 1.5 MHz
15 450 kHz
0.01
G=1000
RL=600Ω
–90
The unique design of the AD797 provides for cancellation of the
output stage’s distortion (patent pending). To achieve this a capacitance equal to the effective compensation capacitance, usually 50 pF, is connected between Pin 8 and the output (C2 in
Figure 41). Use of this feature will improve distortion performance when the closed loop gain is more than 10 or when frequencies of interest are greater than 30 kHz.
Bandwidth enhancement via decompensation is achieved by
connecting a capacitor from Pin 8 to ground (C1 in Figure 41)
effectively subtracting from the value of the internal compensation capacitance (50 pF), yielding a smaller effective compensation capacitance and, therefore, a larger bandwidth. The
benefits of this begin at closed loop gains of 100 and up. A
maximum value of ≈33 pF at gains of 1000 and up is recommended. At a gain of 1000 the bandwidth is 450 kHz.
50
50
50
B
C1 C2 3 dB
(pF) BW
–80
THD – dB
The AD797 has distortion performance (THD < –120 dB, @
20 kHz, 3 V rms, RL = 600 Ω) unequaled by most voltage
feedback amplifiers.
A
C1 C2 3 dB
(pF)
BW
0.003
NOISE LIMIT, G=1000
G=1000
RL =10kΩ
–100
0.001
G=100
RL =600Ω
THD – %
1µF
0.1µF
NOISE LIMIT, G=100
0.0003
–110
G=10
RL =600Ω
–120
100
300
1k
3k
10k
30k
100k
0.0001
300k
FREQUENCY – Hz
Figure 42. Total Harmonic Distortion (THD) vs. Frequency
@ 3 V rms for Figure 41b
Table IV and Figure 42 summarize the performance of the
AD797 with distortion cancellation and decompensation.
–12–
REV. C
AD797
Differential Line Receiver
The differential receiver circuit of Figure 43 is useful for many
applications from audio to MRI imaging. It allows extraction of
a low level signal in the presence of common-mode noise. As
shown in Figure 44, the AD797 provides this function with only
9 nV/√Hz noise at the output. Figure 45 shows the AD797’s
20-bit THD performance over the audio band and 16-bit accuracy to 250 kHz.
A General Purpose ATE/Instrumentation Input/Output
Driver
The ultralow noise and distortion of the AD797 may be combined with the wide bandwidth, slew rate, and load drive of a
current feedback amplifier to yield a very wide dynamic range
general purpose driver. The circuit of Figure 46 combines the
AD797 with the AD811 in just such an application. Using the
–90
0.003
20pF
WITHOUT
OPTIONAL
50pF CN
1kΩ
–100
+VS
50pF*
THD – dB
**
DIFFERENTIAL
INPUT
7
2
8
AD797
**
1kΩ
OUTPUT
WITH
OPTIONAL
50C N
*OPTIONAL
** USE POWER SUPPLY
BYPASSING SHOWN IN
FIGURE 32.
–130
100
300
1k
3k
10k
FREQUENCY – Hz
30k
100k
300k
Figure 45. Total Harmonic Distortion (THD) vs. Frequency
for Differential Line Receiver
20pF
Figure 43. Differential Line Receiver
component values shown, this circuit is capable of better than
–90 dB THD with a ± 5 V, 500 kHz output signal. The circuit is
therefore suitable for driving high resolution A/D converters and
as an output driver in automatic test equipment (ATE) systems.
Using a 100 kHz sine wave, the circuit will drive a 600 Ω load to
a level of 7 V rms with less than –109 dB THD, and a 10 kΩ
load at less than –117 dB THD.
16
OUTPUT VOLTAGE NOISE — nV/ Hz
0.0001
–120
–VS
1kΩ
0.0003
MEASUREMENT
LIMIT
6
4
3
–110
0.001
THD – %
1kΩ
14
12
22pF
10
R2
+VS
2kΩ
**
8
+VS
2
6
10
100
1k
10k
100k
FREQUENCY — Hz
1M
AD797
1kΩ
10M
3
INPUT
**
7
4
6
3
7
AD811
**
2
Figure 44. Output Voltage Noise Spectral Density for
Differential Line Receiver
6
OUTPUT
4
**
–V S
** USE POWER SUPPLY
BYPASSING SHOWN IN
FIGURE 32.
649Ω
649Ω
–VS
Figure 46. A General Purpose ATE/lnstrumentation Input/
Output Driver
REV. C
–13–
AD797
–30
The AD600 variable gain amplifier provides the time controlled
gain (TCG) function necessary for very wide dynamic range sonar and low frequency ultrasound applications. Under some circumstances, it is necessary to buffer the input of the AD600 to
preserve its low noise performance. To optimize dynamic range
this buffer should have at most 6 dB of gain. The combination
of low noise and low gain is difficult to achieve. The input
buffer circuit shown in Figure 47 provides 1 nV/√Hz noise performance at a gain of two (dc to 1 MHz) by using 26.1 Ω resistors
in its feedback path. Distortion is only –50 dBc @ 1 MHz at a
2 volt p-p output level and drops rapidly to better than
–70 dBc at an output level of 200 mV p-p.
–40
VOUT – dB Re 1V/µA
–50
60
–60
40
–70
20
100
7
4
10k
100k
1M
FREQUENCY – Hz
10M
0
100M
Figure 49. Total Integrated Voltage Noise & VOUT of
Amorphous Detector Preamp
26.1ΩΩ
AD797
1k
**
**
3
NOISE
–80
+VS
INPUT
80
VOUT
26.1ΩΩ
2
100
VOLTAGE NOISE – µVrms (0.1Hz – Freq)
Ultrasound/Sonar Imaging Preamp
Professional Audio Signal Processing—DAC Buffers
AD600
6
VOUT
**
**
–VS
VS = ±6Vdc
* USE POWER SUPPLY
** BYPASSING SHOWN IN FIGURE 32.
Figure 47. An Ultrasound Preamplifier Circuit
Amorphous (Photodiode) Detector
Large area photodiodes CS ≥ 500 pF and certain image detectors (amorphous Si), have optimum performance when used in
conjunction with amplifiers with very low voltage rather than
very low current noise. Figure 48 shows the AD797 used with
an amorphous Si (CS = 1000 pF) detector. The response is adjusted for flatness using capacitor CL, while the noise is dominated by voltage noise amplified by the ac noise gain. The 797’s
excellent input noise performance gives 27 µV rms total noise in
a 1 MHz bandwidth, as shown by Figure 49.
The low noise and low distortion of the AD797 make it an ideal
choice for professional audio signal processing. An ideal I-to-V
converter for a current output DAC would simply be a resistor
to ground, were it not for the fact that most DACs do not operate linearly with voltage on their output. Standard practice is to
operate an op amp as an I-to-V converter creating a virtual
ground at its inverting input. Normally, clock energy and current steps must be absorbed by the op amp’s output stage.
However, in the configuration of Figure 50, Capacitor CF
shunts high frequency energy to ground, while correctly reproducing the desired output with extremely low THD and IMD.
CF
82pF
100Ω
3kΩ
+VS
100Ω
**
CL
50pF
AD1862
DAC
10kΩ
2
C1
2000pF
7
AD797
3
4
6
**
+VS
**
–V S
2
IS
CS
1000pF
AD797
3
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
7
4
Figure 50. A Professional Audio DAC Buffer
6
**
–VS
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 48. Amorphous Detector Preamp
Figure 51. Offset Null Configuration
–14–
REV. C
AD797
OPERATIONAL AMPLIFIERS
LOW NOISE
LOW CURRENT NOISE – IN
LOW VOLTAGE NOISE – V N
(V N ≤ 10 nV/ √Hz @ 1 kHz)
AUDIO
AMPLIFIERS
PRECISION
AD797
OP275
SSM2015
SSM2016
SSM2017
SSM2134
SSM2139
FAST
(Slew Rate ≥ 45 V/µs)
LOW INPUT BIAS CURRENT – IBIAS
(IN ≤ 10 fA/ √ Hz @ 1 kHz, IBIAS ≤ 100 pA)
FET INPUT
AD797
AD OP27
AD OP37
OP27
OP37
OP227 (Dual)
OP270 (Dual)
OP271 (Dual)
OP275 (Dual)
OP467 (Quad)
OP470 (Quad)
OP471 (Quad)
AD645
AD743
AD795
AD796 (Dual)
Fast
AD745
High Output
Current
OP61
OP467 (Quad)
ULTRALOW VN
0.9 nV/ √ Hz
AD797
REV. C
LOW VN
Lower VN
AD743
Faster
AD745
OP282 (Dual)
OP482 (Quad)
PRECISION
AD797
OP50
AD548
AD795
AD820
AD648 (Dual)
AD796 (Dual)
AD822 (Dual)
Ultrafast
(Slew Rate ≥ 1000 V/µs)
ELECTROMETER
AD645
AD795
AD796 (Dual)
AD548
AD795
OP80
AD648 (Dual)
AD796 (Dual)
Faster
(Slew Rate ≥ 8 V/µs)
Faster
(Slew Rate ≥ 230 V/µs)
AD829
AD840
AD844
AD846
AD848
AD849
AD5539
LOW
POWER
Low
Power
OP80
FAST
AD711
AD712 (Dual)
OP249 (Dual)
AD713 (Quad)
Faster
General
Purpose
AD515A
AD545A
AD546
Lowest I BIAS
AD744
60 fA Max
OP42
OP44
AD549
AD746 (Dual)
AD810
AD811
AD844
AD9610
AD9617
AD9618
–15–
AD797
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Cerdip (Q) Package*
0.055 (1.4) MAX
8
C1677–24–6/92
0.005 (0.13) MIN
5
0.310 (7.87)
0.220 (5.59)
1
4
0.070 (1.78)
0.030 (0.76)
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.200
(5.08)
MAX
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100 (2.54)
BSC
0.015 (0.38)
0.008 (0.20)
0 - 15
SEATING PLANE
Plastic Mini-DIP
(N) Package
5
8
0.25
(6.35)
0.31
(7.87)
4
1
0.30 (7.62)
REF
0.39 (9.91)
MAX
0.035 ± 0.01
(0.89 ± 0.25)
0.165 ± 0.01
(4.19 ± 0.25)
SEATING PLANE
0.011 ± 0.003
(4.57 ± 0.76)
0.125 (3.18)
MIN
0.10
(2.54)
TYP
0.018 ± 0.003
(0.46 ± 0.08)
0.18 ± 0.03
(4.57 ± 0.76)
0 - 15
0.033
(0.84)
NOM
8-Pin SOIC (R) Package
0.198 (5.03)
8
PRINTED IN U.S.A.
0.188 (4.77)
5
0.158 (4.00)
0.150 (3.80)
1
0.050 (1.27)
TYP
0.010 (0.25)
0.004 (0.10)
0.244 (6.200)
0.228 (5.80)
4
0.018 (0.46)
0.014 (0.36)
0.069 (1.75)
0.053 (1.35)
0.205 (5.20)
0.181 (4.60)
0.015 (0.38)
0.045 (1.15)
0.007 (0.18)
0.020 (0.50)
*See military data sheet for 883B specifications.
–16–
REV. C