Cypress CY7C1917BV18-278BZI 18-mbit ddr-ii sram 4-word burst architecture Datasheet

CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
18-Mbit DDR-II SRAM 4-Word
Burst Architecture
Features
Functional Description
• 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
The CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and
CY7C1321BV18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II (Double Data Rate) architecture. The
DDR-II consists of an SRAM core with advanced synchronous
peripheral circuitry and a two-bit burst counter. Addresses for
Read and Write are latched on alternate rising edges of the
input (K) clock. Write data is registered on the rising edges of
both K and K. Read data is driven on the rising edges of C and
C if provided, or on the rising edge of K and K if C/C are not
provided. Each address location is associated with four 8-bit
words in the case of CY7C1317BV18 and four 9-bit words in
the case of CY7C1917BV18 that burst sequentially into or out
of the device. The burst counter always starts with “00” internally in the case of CY7C1317BV18 and CY7C1917BV18. On
CY7C1319BV18 and CY7C1321BV18, the burst counter
takes in the last two significant bits of the external address and
bursts four 18-bit words in the case of CY7C1319BV18, and
four 36-bit words in the case of CY7C1321BV18, sequentially
into or out of the device.
• 300-MHz clock for high bandwidth
• 4-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces
(data transferred at 600MHz) @ 300 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–VDD)
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Offered in both lead-free and non-lead free packages
Asynchronous inputs include output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need for
separately capturing data from each individual DDR-II SRAM
in the system design. Output data clocks (C/C) enable
maximum system clocking and data synchronization flexibility.
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
CY7C1317BV18 – 2M x 8
CY7C1917BV18 – 2M x 9
CY7C1319BV18 – 1M x 18
CY7C1321BV18 – 512K x 36
Selection Guide
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
300
278
250
200
167
MHz
Maximum Operating Current
550
530
500
450
400
mA
Cypress Semiconductor Corporation
Document Number: 38-05622 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 27, 2006
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
CLK
Gen.
Write Add. Decode
K
K
DOFF
Write
Reg
Write
Reg
512K x 8 Array
LD
Write
Reg
512K x 8 Array
Address
Register
512K x 8 Array
19
Write
Reg
512K x 8 Array
A(18:0)
Read Add. Decode
Logic Block Diagram (CY7C1317BV18)
8
Output
Logic
Control
R/W
C
C
Read Data Reg.
CQ
32
VREF
R/W
Reg.
Control
Logic
NWS[1:0]
16
16
CQ
Reg.
Reg.
8
DQ[7:0]
8
Logic Block Diagram (CY7C1917BV18)
DOFF
Read Add. Decode
Write
Reg
512K x 9 Array
CLK
Gen.
Write
Reg
512K x 9 Array
K
K
Write
Reg
512K x 9 Array
LD
Write
Reg
512K x 9 Array
19
Address
Register
Write Add. Decode
A(18:0)
9
Output
Logic
Control
R/W
C
C
Read Data Reg.
CQ
VREF
R/W
BWS[0]
36
Control
Logic
18
Reg.
18
CQ
Reg.
Reg.
9
9
Document Number: 38-05622 Rev. *C
DQ[8:0]
Page 2 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Logic Block Diagram (CY7C1319BV18)
Burst
Logic
A(1:0)
2
A(19:0)
Write
Reg
Write Add. Decode
Address
A(19:2) Register
LD
K
K
CLK
Gen.
Write
Reg
Write
Reg
Write
Reg
Read Add. Decode
18
20
1M x 18 Array
DOFF
18
Output
Logic
Control
R/W
C
C
Read Data Reg.
72
VREF
R/W
BWS[1:0]
36
CQ
Reg.
Control
Logic
CQ
36
Reg.
18
Reg.
DQ[17:0]
18
Logic Block Diagram (CY7C1321BV18)
Burst
Logic
A(1:0)
2
LD
K
K
CLK
Gen.
DOFF
Write Add. Decode
Address
A(18:2) Register
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Read Add. Decode
17
19
A(18:0)
512K x 36 Array
36
R/W
Output
Logic
Control
C
C
Read Data Reg.
CQ
VREF
R/W
BWS[3:0]
144
Control
Logic
72
Reg.
72
CQ
Reg.
36
Reg.
36
Document Number: 38-05622 Rev. *C
DQ[35:0]
Page 3 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Pin Configurations
165-ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1317BV18 (2M x 8)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
7
8
9
10
11
CQ
NC/72M
A
R/W
NWS1
K
NC/144M
LD
A
NC/36M
CQ
NC
NC
NC
A
NC/288M
K
NWS0
A
NC
NC
DQ3
NC
NC
NC
NC
NC
A
VSS
NC
VSS
A
VSS
VSS
VSS
NC
NC
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
NC
VREF
NC
DQ5
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
VDDQ
NC
NC
VREF
DQ1
NC
ZQ
NC
DOFF
NC
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
DQ6
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ0
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
DQ7
A
A
C
A
A
NC
NC
NC
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
CY7C1917BV18 (2M x 9)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
7
8
9
10
11
CQ
NC/72M
A
R/W
NC
K
NC/144M
LD
A
NC/36M
CQ
NC
NC
NC
A
NC/288M
K
BWS0
A
NC
NC
DQ3
NC
NC
NC
NC
NC
NC
VSS
VSS
A
VSS
NC
VSS
A
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
DOFF
NC
NC
VREF
NC
DQ5
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
VDDQ
NC
NC
VREF
DQ1
NC
NC
ZQ
NC
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
DQ6
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ0
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
DQ7
A
A
C
A
A
NC
NC
DQ8
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
NC
NC
Document Number: 38-05622 Rev. *C
Page 4 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Pin Configurations (continued)
165-ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1319BV18 (1M x 18)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
7
8
9
10
CQ
NC
11
NC/72M
A
BWS1
NC/288M
K
K
LD
A
A
NC/36M
CQ
NC
R/W
A
NC/144M
DQ9
NC
NC
DQ8
NC
NC
NC
NC
NC
DQ10
VSS
VSS
A
VSS
NC
NC
DQ11
VDDQ
NC
NC
DQ12
NC
DOFF
NC
NC
VREF
NC
DQ13
VDDQ
NC
NC
NC
DQ14
NC
DQ15
NC
NC
A0
VSS
BWS0
A1
VSS
VSS
VSS
NC
NC
DQ7
NC
NC
NC
VSS
VSS
VSS
VDDQ
NC
NC
DQ6
VDDQ
VDD
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
NC
NC
VDDQ
NC
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
NC
VREF
DQ4
DQ5
NC
ZQ
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ3
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
NC
NC
NC
DQ16
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
DQ1
NC
NC
NC
NC
NC
DQ17
A
A
C
A
A
NC
NC
DQ0
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
CY7C1321BV18 (512K x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
2
3
NC/144M NC/36M
4
5
6
7
8
9
10
11
R/W
BWS2
K
BWS1
LD
A
NC/72M
CQ
NC
DQ27
DQ18
A
BWS3
K
BWS0
A
NC
NC
DQ8
NC
NC
NC
DQ29
DQ28
DQ19
VSS
VSS
A
VSS
A0
VSS
A1
VSS
VSS
VSS
NC
NC
DQ17
NC
DQ7
DQ16
NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
NC
DOFF
NC
DQ31
VREF
NC
DQ22
VDDQ
DQ32
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
VDDQ
NC
NC
VREF
DQ13
DQ14
ZQ
DQ4
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
NC
NC
NC
DQ35
DQ34
DQ25
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
DQ11
NC
DQ1
DQ10
NC
NC
DQ26
A
A
C
A
A
NC
DQ9
DQ0
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Document Number: 38-05622 Rev. *C
Page 5 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input/Output- Data Input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid
Synchronous Write operations. These pins drive out the requested data during a Read operation. Valid data is
driven out on the rising edge of both the C and C clocks during Read operations or K and K when
in single clock mode. When Read access is deselected, Q[x:0] are automatically tri-stated.
CY7C1317BV18 - DQ[7:0]
CY7C1917BV18 - DQ[8:0]
CY7C1319BV18 - DQ[17:0]
CY7C1321BV18 - DQ[35:0]
LD
InputSynchronous Load. This input is brought LOW when a bus cycle sequence is to be defined.
Synchronous This definition includes address and read/write direction. All transactions operate on a burst of 4
data (two clock periods of bus activity).
NWS0, NWS1
InputNibble Write Select 0, 1 − active LOW (CY7C1317BV18 only). Sampled on the rising edge of
Synchronous the K and K clocks during Write operations. Used to select which nibble is written into the device
during the current portion of the Write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select will cause the corresponding nibble of data to be ignored and not written into the
device.
InputByte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocks
BWS0, BWS1,
BWS2, BWS3 Synchronous during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1917BV18 − BWS0 controls D[8:0]
CY7C1319BV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1321BV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A, A0, A1
InputAddress Inputs. These address inputs are multiplexed for both Read and Write operations.
Synchronous Internally, the device is organized as 2M x 8 (four arrays each of 512K x 8) for CY7C1317BV18,
2M x 9 (four arrays each of 512K x 9) for CY7C1917BV18, a single 1M x 18 array for
CY7C1319BV18, and a single 512K x 36 array for CY7C1321BV18.
CY7C1317BV18 – Since the least two significant bits of the address internally are “00,” only 19
address inputs are needed to access the entire memory array.
CY7C1917BV18 – Since the least two significant bits of the address internally are “00,” only 19
address inputs are needed to access the entire memory array.
CY7C1319BV18 – A0 and A1 are the inputs to the burst counter. These are incremented in a
linear fashion internally. 20 address inputs are needed to access the entire memory array.
All the address inputs are ignored when write access is deselected.
CY7C1321BV18 – A0 and A1 are the inputs to the burst counter. These are incremented in a
linear fashion internally. 19 address inputs are needed to access the entire memory array.
R/W
InputSynchronous Read/Write Input. When LD is LOW, this input designates the access type (Read
Synchronous when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and
hold times around edge of K.
C
InputClock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
C
InputClock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
K
InputClock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
InputClock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[x:0] when in single clock mode.
CQ
Clock Output CQ is referenced with respect to C. This is a free-running clock and is synchronized to the input
clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC Timing table.
Document Number: 38-05622 Rev. *C
Page 6 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Pin Definitions (continued)
Pin Name
CQ
I/O
Pin Description
Clock Output CQ is referenced with respect to C. This is a free-running clock and is synchronized to the input
clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC Timing table.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DOFF
Input
DLL Turn Off - active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
TDO
Output
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/36M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/72M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/144M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/288M
N/A
Not connected to the die. Can be tied to any voltage level.
VREF
VDD
InputReference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.
Power Supply Power supply inputs to the core of the device.
VSS
VDDQ
TDO for JTAG.
Ground
Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
Functional Overview
The CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and
CY7C1321BV18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the rising edge of the output clocks (C/C or
K/K when in single-clock mode).
All synchronous data inputs (D[x:0]) pass through input
registers controlled by the rising edge of the input clocks (K
and K). All synchronous data outputs (Q[x:0]) pass through
output registers controlled by the rising edge of the output
clocks (C/C or K/K when in single clock mode).
All synchronous control (R/W, LD, BWS[0:X]) inputs pass
through input registers controlled by the rising edge of the
input clock (K).
CY7C1319BV18 is described in the following sections. The
same basic descriptions apply to CY7C1317BV18,
CY7C1917BV18, and CY7C1321BV18.
Read Operations
The CY7C1319BV18 is organized internally as a 1M x 18
SRAM. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to the Address inputs is
Document Number: 38-05622 Rev. *C
stored in the Read address register and the least two significant bits of the address are presented to the burst counter.
The burst counter increments the address in a linear fashion.
Following the next K clock rise the corresponding 18-bit word
of data from this address location is driven onto the Q[17:0]
using C as the output timing reference. On the subsequent
rising edge of C the next 18-bit data word from the address
location generated by the burst counter is driven onto the
Q[17:0]. This process continues until all four 18-bit data words
have been driven out onto Q[17:0]. The requested data will be
valid 0.45 ns from the rising edge of the output clock (C or C,
or K or K when in single clock mode, 250-MHz and 200-MHz
device). In order to maintain the internal logic, each Read
access must be allowed to complete. Each Read access
consists of four 18-bit data words and takes two clock cycles
to complete. Therefore, Read accesses to the device can not
be initiated on two consecutive K clock rises. The internal logic
of the device will ignore the second Read request. Read
accesses can be initiated on every other K clock rise. Doing
so will pipeline the data flow such that data is transferred out
of the device on every rising edge of the output clocks (C/C or
K/K when in single-clock mode).
When Read access is deselected, the CY7C1319BV18 will
first complete the pending Read transactions. Synchronous
internal circuitry will automatically tri-state the outputs
following the next rising edge of the positive output clock (C).
This will allow for a seamless transition between devices
without the insertion of wait states in a depth expanded
memory.
Page 7 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to Address inputs are stored in the Write
address register and the least two significant bits of the
address are presented to the burst counter. The burst counter
increments the address in a linear fashion. On the following K
clock rise the data presented to D[17:0] is latched and stored
into the 18-bit Write Data register provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K) the information presented to D[17:0] is also
stored into the Write Data register provided BWS[1:0] are both
asserted active. This process continues for one more cycle
until four 18-bit words (a total of 72 bits) of data are stored in
the SRAM. The 72 bits of data are then written into the memory
array at the specified location. Therefore, Write accesses to
the device can not be initiated on two consecutive K clock
rises. The internal logic of the device will ignore the second
Write request. Write accesses can be initiated on every other
rising edge of the positive input clock (K). Doing so will pipeline
the data flow such that 18 bits of data can be transferred into
the device on every rising edge of the input clocks (K and K).
When Write access is deselected, the device will ignore all
inputs after the pending Write operations have been
completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1319BV18.
A Write operation is initiated as described in the Write Operations section above. The bytes that are written are determined
by BWS0 and BWS1, which are sampled with each set of 18-bit
data words. Asserting the appropriate Byte Write Select input
during the data portion of a write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a Write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
and double data rate mode of operation. The CY7C1319BV18
requires a No Operation (NOP) cycle when transitioning from
a Read to a Write cycle. At higher frequencies, some applications may require a second NOP cycle to prevent contention.
If a Read occurs after a Write cycle, address and data for the
Write are stored in registers. The write information must be
stored because the SRAM can not perform the last word Write
to the array without conflicting with the Read. The data stays
in this register until the next Write cycle occurs. On the first
Write cycle after the Read(s), the stored data from the earlier
Write will be written into the SRAM array. This is called a
Posted Write.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5x the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the DDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are free running
clocks and are synchronized to the output clock of the DDR-II.
In the single clock mode, CQ is generated with respect to K
and CQ is generated with respect to K. The timings for the
echo clocks are shown in the AC Timing table.
Single Clock Mode
DLL
The CY7C1917BV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-on. This function is
a strap option and not alterable during device operation.
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented, the DLL may be
disabled by applying ground to the DOFF pin. For information
refer to the application note “DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+”.
DDR Operation
The CY7C1319BV18 enables high-performance operation
through high clock frequencies (achieved through pipelining)
Document Number: 38-05622 Rev. *C
Page 8 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Application Example[1]
ZQ
CQ/CQ#
LD# R/W# C C# K K#
SRAM#1
DQ
A
DQ
Addresses
Cycle Start#
R/W#
Return CLK
Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
BUS
MASTER
(CPU
or
ASIC)
DQ
A
R = 250ohms
ZQ
CQ/CQ#
LD# R/W# C C# K K#
SRAM#2
R = 250ohms
Vterm = 0.75V
R = 50ohms
Vterm = 0.75V
Truth Table[2, 3, 4, 5, 6, 7]
Operation
K
LD
R/W
DQ
DQ
DQ
DQ
L-H
Write Cycle:
Load address; wait one
cycle; input write data on
four consecutive K and K
rising edges.
L
L
D(A1) at K(t + 1) ↑ D(A2) at K(t + 1) ↑ D(A3) at K(t + 2) ↑ D(A4) at K(t + 2) ↑
Read Cycle:
L-H
Load address; wait one
and a half cycle; read
data on four consecutive
C and C rising edges.
L
H
Q(A1) at C(t + 1) ↑ Q(A2) at C(t + 2) ↑ Q(A3) at C(t + 2) ↑ Q(A4) at C(t + 3) ↑
NOP: No Operation
H
X
High-Z
High-Z
High-Z
High-Z
Standby: Clock Stopped Stopped X
X
Previous State
Previous State
Previous State
Previous State
L-H
Linear Burst Address Table (CY7C1319BV18 and CY7C1321BV18)
First Address (External)
Second Address (Internal)
Third Address (Internal)
Fourth Address (Internal)
X..X00
X..X01
X..X10
X..X11
X..X01
X..X10
X..X11
X..X00
X..X10
X..X11
X..X00
X..X01
X..X11
X..X00
X..X01
X..X10
Notes:
1. The above application shows 2 DDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. On CY7C1319BV18 and CY7C1321BV18, “A1” represents address location latched by the devices when transaction was initiated and A2, A3, A4 represents
the addresses sequence in the burst. On CY7C1317BV18, “A1” represents A + ‘00’, A2 represents A + ‘01’, “A3” represents A + ‘10’ and “A4” represents A + ‘11’.
5. “t” represents the cycle at which a Read/Write operation is started. t+1, t + 2 and t +3 are the first, second and third clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Document Number: 38-05622 Rev. *C
Page 9 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Write Cycle Descriptions(CY7C1317BV18 and CY7C1319BV18)[2, 8]
BWS0,NWS0 BWS1,NWS1
K
K
-
L
L
L-H
L
L
-
L
H
L-H
L
H
-
H
L
L-H
H
L
-
H
H
L-H
H
H
-
Comments
During the Data portion of a Write sequence:
CY7C1317BV18 − both nibbles (D[7:0]) are written into the device,
CY7C1319BV18 − both bytes (D[17:0]) are written into the device.
L-H During the Data portion of a Write sequence:
CY7C1317BV18 − both nibbles (D[7:0]) are written into the device,
CY7C1319BV18 − both bytes (D[17:0]) are written into the device.
-
During the Data portion of a Write sequence:
CY7C1317BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain
unaltered,
CY7C1319BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain
unaltered.
L-H During the Data portion of a Write sequence:
CY7C1317BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain
unaltered,
CY7C1319BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain
unaltered.
-
During the Data portion of a Write sequence:
CY7C1317BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will
remain unaltered,
CY7C1319BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain
unaltered.
L-H During the Data portion of a Write sequence:
CY7C1317BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will
remain unaltered,
CY7C1319BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain
unaltered.
-
No data is written into the devices during this portion of a Write operation.
L-H No data is written into the devices during this portion of a Write operation.
Note:
8. Assumes a Write cycle was initiated per the Write Cycle Description Truth Table. NWS0, NWS1,BWS0, BWS1,BWS2, BWS3 can be altered on different portions
of a Write cycle, as long as the set-up and hold requirements are achieved.
Document Number: 38-05622 Rev. *C
Page 10 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Write Cycle Descriptions (CY7C1321BV18)[2, 8]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L-H
-
During the Data portion of a Write sequence, all four bytes (D[35:0]) are written
into the device.
L
L
L
L
-
L-H
During the Data portion of a Write sequence, all four bytes (D[35:0]) are written
into the device.
L
H
H
H
L-H
-
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
L
H
H
H
-
L-H
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
H
L
H
H
L-H
-
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
H
L
H
H
-
L-H
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
H
H
L
H
L-H
-
During the Data portion of a Write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] will remain unaltered.
H
H
L
H
-
L-H
During the Data portion of a Write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] will remain unaltered.
H
H
H
L
L-H
H
H
H
L
-
L-H
H
H
H
H
L-H
-
No data is written into the device during this portion of a Write operation.
H
H
H
H
-
L-H
No data is written into the device during this portion of a Write operation.
During the Data portion of a Write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] will remain unaltered.
Write Cycle Descriptions (CY7C1917BV18)[2, 8]
BWS0
K
K
L
L-H
-
During the Data portion of a Write sequence, the single byte (D[8:0]) is written
into the device.
L
-
L-H
During the Data portion of a Write sequence, the single byte (D[8:0]) is written
into the device.
H
L-H
-
No data is written into the device during this portion of a Write operation.
H
-
L-H
No data is written into the device during this portion of a Write operation.
Document Number: 38-05622 Rev. *C
Comments
Page 11 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 1.8V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port—Test Clock
Boundary Scan Register
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document Number: 38-05622 Rev. *C
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
Page 12 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
Document Number: 38-05622 Rev. *C
Page 13 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
TAP Controller State Diagram[9]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
SHIFT-IR
0
1
0
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Note:
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 38-05622 Rev. *C
Page 14 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30 29
.
.
2
Identification Register
106 .
.
.
.
2
1
0
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics Over the Operating Range[10, 13, 14]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.4
V
VOH2
Output HIGH Voltage
IOH = −100 µA
1.6
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
0.2
V
VIH
Input HIGH Voltage
0.65VDD
VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
0.35VDD
V
IX
Input and OutputLoad Current
–5
5
µA
GND ≤ VI ≤ VDD
TAP AC Switching Characteristics Over the Operating Range[11, 12]
Parameter
Description
Min.
Max.
Unit
20
MHz
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
20
ns
tTL
TCK Clock LOW
20
ns
tTMSS
TMS Set-up to TCK Clock Rise
5
ns
tTDIS
TDI Set-up to TCK Clock Rise
5
ns
50
ns
Set-up Times
Notes:
10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
11. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
12. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
13. Overshoot: VIH(AC) < VDD+0.85V (Pulse width less than tTCYC/2); Undershoot VIL(AC) > −1.5V (Pulse width less than tTCYC/2).
14. All voltage referenced to ground.
Document Number: 38-05622 Rev. *C
Page 15 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
TAP AC Switching Characteristics Over the Operating Range[11, 12] (continued)
Parameter
Description
tCS
Min.
Max.
Unit
Capture Set-up to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
0
ns
ns
TAP Timing and Test Conditions[12]
0.9V
50Ω
ALL INPUT PULSES
TDO
1.8V
Z0 = 50Ω
0.9V
CL = 20 pF
0V
tTH
(a)
tTL
GND
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
Document Number: 38-05622 Rev. *C
tTDOX
Page 16 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Identification Register Definitions
Value
Instruction Field
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Description
Revision Number
(31:29)
000
000
000
000
Version number.
Cypress Device ID 11010100011000101 11010100011001101
(28:12)
Cypress JEDEC
ID (11:1)
11010100011010101
11010100011100101 Defines the type
of SRAM.
00000110100
00000110100
00000110100
00000110100
Allows unique
identification of
SRAM vendor.
1
1
1
1
Indicate the
presence of an
ID register.
ID Register
Presence (0)
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
107
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 38-05622 Rev. *C
Page 17 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
27
11H
54
7B
81
3G
1
6P
28
10G
55
6B
82
2G
2
6N
29
9G
56
6A
83
1J
3
7P
30
11F
57
5B
84
2J
4
7N
31
11G
58
5A
85
3K
5
7R
32
9F
59
4A
86
3J
6
8R
33
10F
60
5C
87
2K
7
8P
34
11E
61
4B
88
1K
8
9R
35
10E
62
3A
89
2L
9
11P
36
10D
63
1H
90
3L
10
10P
37
9E
64
1A
91
1M
11
10N
38
10C
65
2B
92
1L
12
9P
39
11D
66
3B
93
3N
13
10M
40
9C
67
1C
94
3M
14
11N
41
9D
68
1B
95
1N
15
9M
42
11B
69
3D
96
2M
16
9N
43
11C
70
3C
97
3P
17
11L
44
9B
71
1D
98
2N
18
11M
45
10B
72
2C
99
2P
19
9L
46
11A
73
3E
100
1P
20
10L
47
Internal
74
2D
101
3R
21
11K
48
9A
75
2E
102
4R
22
10K
49
8B
76
1E
103
4P
23
9J
50
7C
77
2F
104
5P
24
9K
51
6C
78
3F
105
5N
25
10J
52
8A
79
1G
106
5R
26
11J
53
7A
80
1F
Document Number: 38-05622 Rev. *C
Page 18 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Power-Up Sequence in DDR-II SRAM[15, 16]
DDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power-Up Sequence
• Apply power and drive DOFF LOW (All other inputs can be
HIGH or LOW)
— Apply VDD before VDDQ
— Apply VDDQ before VREF or at the same time as VREF
DLL Constraints
• DLL uses either K or C clock as its synchronizing input.The
input should have low phase jitter, which is specified as
tKC Var
• The DLL will function at frequencies down to 80 MHz
• If the input clock is unstable and the DLL is enabled, then
the DLL may lock to an incorrect frequency, causing
unstable SRAM behavior
• After the power and clock (K, K, C, C) are stable take DOFF
HIGH
• The additional 1024 cycles of clocks are required for the
DLL to lock
~
~
Power-up Waveforms
K
K
~
~
Unstable Clock
> 1024 Stable clock
Start Normal
Operation
Clock Start (Clock Starts after V DD / V DDQ Stable)
VDD / VDDQ
DOFF
V DD / V DDQ Stable (< +/- 0.1V DC per 50ns )
Fix High (or tied to VDDQ)
Notes:
15. It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1 Kohm.
16. During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
Document Number: 38-05622 Rev. *C
Page 19 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015)... > 2001V
(Above which the useful life may be impaired.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied .. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V
Supply Voltage on VDQD Relative to GND ...... –0.5V to +VDD
DC Applied to Outputs in High-Z......... –0.5V to VDDQ + 0.3V
DC Input Voltage[13] ...............................–0.5V to VDD + 0.3V
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Com’l
Ind’l
Ambient
Temperature
VDD[17]
VDDQ[17]
0°C to +70°C
1.8 ± 0.1V
1.4V to VDD
–40°C to +85°C
Electrical Characteristics Over the Operating Range[14]
DC Electrical Characteristics Over the Operating Range
Parameter
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
VOH(LOW)
Test Conditions
Typ.
Max.
Unit
1.7
1.8
1.9
V
1.4
1.5
VDD
V
Note 18
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
Output LOW Voltage
Note 19
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
Output HIGH Voltage
IOH = −0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
IOL = 0.1 mA, Nominal Impedance
VOL(LOW)
Output LOW Voltage
VIH
Input HIGH Voltage[13]
Voltage[13]
VIL
Input LOW
IX
Input Leakage Current
GND ≤ VI ≤ VDDQ
IOZ
Output Leakage Current
GND ≤ VI ≤ VDDQ, Output Disabled
VREF
Input Reference Voltage[20] Typical Value = 0.75V
IDD
VDD Operating Supply
ISB1
Min.
Automatic
Power-down
Current
VSS
0.2
V
VREF + 0.1
VDDQ + 0.3
V
–0.3
VREF – 0.1
V
–5
5
µA
5
µA
0.95
V
VDD = Max.,IOUT = 0 mA, 167 MHz
f = fMAX = 1/tCYC
200 MHz
400
mA
450
mA
250 MHz
500
mA
278 MHz
530
mA
–5
0.68
0.75
300 MHz
550
mA
Max. VDD, both ports
167 MHz
Deselected, VIN ≥ VIH or 200 MHz
VIN ≤ VIL,f = fMAX =
250 MHz
1/tCYC, Inputs Static
278 MHz
200
mA
220
mA
240
mA
250
mA
300 MHz
260
mA
Max.
Unit
AC Input Requirements Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
VIH
Input High (Logic 1) Voltage
VREF + 0.2
–
–
V
VIL
Input Low (Logic 0) Voltage
–
–
VREF – 0.2
V
Capacitance[21]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CO
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 1.8V
VDDQ = 1.5V
Max.
Unit
5
pF
6
pF
7
pF
Notes:
17. Power-up: Assumes a linear ramp from 0V to VDD(Min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
18. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
19. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
20. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.
21. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05622 Rev. *C
Page 20 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Thermal Resistance[21]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
165 FBGA
Package
Unit
28.51
°C/W
5.91
°C/W
AC Test Loads and Waveforms
VREF = 0.75V
VREF
0.75V
VREF
OUTPUT
Z0 = 50Ω
Device
Under
Test
RL = 50Ω
VREF = 0.75V
ZQ
RQ =
250Ω
0.75V
R = 50Ω
ALL INPUT PULSES
1.25V
0.75V
OUTPUT
Device
Under
Test ZQ
5 pF
[22]
0.25V
Slew Rate = 2 V/ns
RQ =
250Ω
(a)
(b)
Note:
22. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
Document Number: 38-05622 Rev. *C
Page 21 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Switching Characteristics Over the Operating Range [22, 23]
Cypress Consortium
Parameter Parameter
300 MHz
Description
VDD(Typical) to the first
Access[24]
tPOWER
278 MHz
Min. Max. Min. Max.
1
1
250 MHz
200 MHz
167 MHz
Min. Max. Min. Max. Min. Max.
1
1
1
Unit
ms
tCYC
tKHKH
K Clock and C Clock
Cycle Time
3.30
5.25
3.4
5.25
4.0
6.3
5.0
7.9
6.0
8.4
ns
tKH
tKHKL
Input Clock (K/K and
C/C) HIGH
1.32
–
1.4
–
1.6
–
2.0
–
2.4
–
ns
tKL
tKLKH
Input Clock (K/K and
C/C) LOW
1.32
1.6
–
2.0
–
2.4
–
ns
tKHKH
tKHKH
K Clock Rise to K
Clock Rise and C to C
Rise (rising edge to
rising edge)
1.49
–
1.6
–
1.8
–
2.2
–
2.7
–
ns
tKHCH
tKHCH
K/K Clock Rise to C/C
Clock Rise (rising
edge to rising edge)
0.0
1.45
0.0
1.55
0.0
1.8
0.0
2.2
0.0
2.7
ns
1.4
Set-up Times
tSA
tAVKH
Address Set-up to K
Clock Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tSC
tIVKH
Control Set-up to K
Clock Rise (LD, R/W)
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tSCDDR
tIVKH
Double Data Rate
Control Set-up to
Clock (K, K) Rise
(BWS0, BWS1, BWS2,
BWS3)
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
tSD[25]
tDVKH
D[X:0] Set-up to Clock
(K/K) Rise
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
tHA
tKHAX
Address Hold after K
Clock Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tHC
tKHIX
Control Hold after K
Clock Rise (LD, R/W)
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tHCDDR
tKHIX
0.30
Double Data Rate
Control Hold after
Clock (K, K) Rise
(BWS0, BWS1, BWS2,
BWS3)
–
0.30
–
0.35
–
0.4
–
0.5
–
ns
tHD
tKHDX
D[X:0] Hold after Clock
(K/K) Rise
–
0.30
–
0.35
–
0.4
–
0.5
–
ns
Hold Times
0.30
Notes:
23. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
24. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
25. For DQ2 data signal on CY7C1917BV18 device, tSD is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies.
Document Number: 38-05622 Rev. *C
Page 22 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Switching Characteristics Over the Operating Range (continued)[22, 23]
Cypress Consortium
Parameter Parameter
300 MHz
Description
278 MHz
Min. Max. Min. Max.
250 MHz
200 MHz
167 MHz
Min. Max. Min. Max. Min. Max.
Unit
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K
in single clock mode)
to Data Valid
tDOH
tCHQX
Data Output Hold after –0.45
Output C/C Clock Rise
(Active to Active)
tCCQO
tCHCQV
C/C Clock Rise to
Echo Clock Valid
tCQOH
tCHCQX
Echo Clock Hold after –0.45
C/C Clock Rise
tCQD
tCQHQV
Echo Clock High to
Data Valid
tCQDOH
tCQHQX
Echo Clock High to
Data Invalid
tCHZ
tCHQZ
Clock (C/C) Rise to
High-Z
(Active to High-Z)[26, 27]
tCLZ
tCHQX1
Clock (C/C) Rise to
Low-Z[26, 27]
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
–
0.27
–
0.27
–
0.30
–
0.35
–
0.40
ns
–0.27
–
–0.27
–
–0.30
–
–0.35
–
–0.40
–
ns
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
–
DLL Timing
tKC Var
tKC Var
Clock Phase Jitter
–
0.20
–
0.20
–
0.20
–
0.20
–
0.20
ns
tKC lock
tKC lock
DLL Lock Time (K, C)
1024
–
1024
–
1024
–
1024
–
1024
–
Cycles
tKC Reset
tKC Reset
K Static to DLL Reset
30
30
30
30
30
ns
Notes:
26. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
27. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Document Number: 38-05622 Rev. *C
Page 23 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Switching Waveforms[28, 29, 30]
NOP
READ
(burst of 4)
2
3
1
READ
(burst of 4)
5
4
NOP
NOP
6
7
WRITE
(burst of 4)
9
8
WRITE
(burst of 4)
11
10
READ
(burst of 4)
13
12
K
t KH t KL
t CYC
t KHKH
K
LD
t SC t HC
tCO
R/W
A
A0
A1
A3
A2
t SA t HA
t HD
t HD
t SD
t SD
DQ
Q00
Q01
Q02
tDOH
tKHCH
Q03
Q11
Q12
D20 D21 D22 D23 D30 D31 D32 D33
Q13
tCQD
tCO
t CLZ
Q10
A4
tCQDOH
t CHZ
C
tKH
tKHCH
tKL
t CYC
t KHKH
C
tCCQO
tCQOH
CQ
tCQOH
tCCQO
CQ
DON’T CARE
UNDEFINED
Notes:
28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.
29. Output are disabled (High-Z) one clock cycle after a NOP.
30. In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 38-05622 Rev. *C
Page 24 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
167
Ordering Code
CY7C1317BV18-167BZC
Package
Diagram
Operating
Range
Package Type
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Commercial
CY7C1917BV18-167BZC
CY7C1319BV18-167BZC
CY7C1321BV18-167BZC
CY7C1317BV18-167BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1917BV18-167BZXC
CY7C1319BV18-167BZXC
CY7C1321BV18-167BZXC
CY7C1317BV18-167BZI
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
CY7C1917BV18-167BZI
CY7C1319BV18-167BZI
CY7C1321BV18-167BZI
CY7C1317BV18-167BZXI
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1917BV18-167BZXI
CY7C1319BV18-167BZXI
CY7C1321BV18-167BZXI
200
CY7C1317BV18-200BZC
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Commercial
CY7C1917BV18-200BZC
CY7C1319BV18-200BZC
CY7C1321BV18-200BZC
CY7C1317BV18-200BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1917BV18-200BZXC
CY7C1319BV18-200BZXC
CY7C1321BV18-200BZXC
CY7C1317BV18-200BZI
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
CY7C1917BV18-200BZI
CY7C1319BV18-200BZI
CY7C1321BV18-200BZI
CY7C1317BV18-200BZXI
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1917BV18-200BZXI
CY7C1319BV18-200BZXI
CY7C1321BV18-200BZXI
250
CY7C1317BV18-250BZC
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Commercial
CY7C1917BV18-250BZC
CY7C1319BV18-250BZC
CY7C1321BV18-250BZC
CY7C1317BV18-250BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1917BV18-250BZXC
CY7C1319BV18-250BZXC
CY7C1321BV18-250BZXC
Document Number: 38-05622 Rev. *C
Page 25 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
250
Ordering Code
CY7C1317BV18-250BZI
Package
Diagram
Operating
Range
Package Type
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
CY7C1917BV18-250BZI
CY7C1319BV18-250BZI
CY7C1321BV18-250BZI
CY7C1317BV18-250BZXI
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1917BV18-250BZXI
CY7C1319BV18-250BZXI
CY7C1321BV18-250BZXI
278
CY7C1317BV18-278BZC
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Commercial
CY7C1917BV18-278BZC
CY7C1319BV18-278BZC
CY7C1321BV18-278BZC
CY7C1317BV18-278BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1917BV18-278BZXC
CY7C1319BV18-278BZXC
CY7C1321BV18-278BZXC
CY7C1317BV18-278BZI
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
CY7C1917BV18-278BZI
CY7C1319BV18-278BZI
CY7C1321BV18-278BZI
CY7C1317BV18-278BZXI
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1917BV18-278BZXI
CY7C1319BV18-278BZXI
CY7C1321BV18-278BZXI
300
CY7C1317BV18-300BZC
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Commercial
CY7C1917BV18-300BZC
CY7C1319BV18-300BZC
CY7C1321BV18-300BZC
CY7C1317BV18-300BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1917BV18-300BZXC
CY7C1319BV18-300BZXC
CY7C1321BV18-300BZXC
CY7C1317BV18-300BZI
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
CY7C1917BV18-300BZI
CY7C1319BV18-300BZI
CY7C1321BV18-300BZI
CY7C1317BV18-300BZXI
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1917BV18-300BZXI
CY7C1319BV18-300BZXI
CY7C1321BV18-300BZXI
Document Number: 38-05622 Rev. *C
Page 26 of 28
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Package Diagram
165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D
165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)
BOTTOM VIEW
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 MØ0.05
CAB MC
PIN 1 CORNER
Ø0.25 M C A B
Ø0.50 -0.06
(165X)
PIN 1 CORNER
1
2
1
+0.14
4
2
5
3
6
4
7
5
8
6
9
7
10
11
8
9
11
10
11
10
9
11
8
10
7
9
6
8
5
7
Ø0.50 -0.06 (165X)
4
6
1
3 +0.14
2
5
4
3
2
1A
B
A
C
B
C
B
D
C
D
C
E
D
F
1.00
A
1.00
B
F
E
G
F
G
F
H
G
H
G
J
H
K
J
L
K
M
L
N
M
P
N
P
N
R
P
R
P
7.00
7.00
14.00
D
E
14.00
15.00±0.10
E
15.00±0.10
15.00±0.10
A
15.00±0.10
3
J
H
K
J
L
K
M
L
N
M
R
R
A
A
A
1.00
5.00
A
1.00
5.00
10.00
10.00
B
B
13.00±0.10
B
13.00±0.10
B
13.00±0.10
13.00±0.10
SEATING PLANE
NOTES :
NOTES
:
SOLDER
PAD TYPE
: NON-SOLDER MASK DEFINED (NSMD)
PACKAGE
WEIGHT
SOLDER
PAD: 0.475g
TYPE : NON-SOLDER MASK DEFINED (NSMD)
JEDEC REFERENCE
: MO-216
/ DESIGN 4.6C
PACKAGE WEIGHT
: 0.475g
PACKAGE
CODE
: BB0AC : MO-216 / DESIGN 4.6C
JEDEC
REFERENCE
PACKAGE CODE : BB0AC
51-85180-*A
0.35±0.06
C
0.35±0.06
0.36
0.36
SEATING PLANE
C
0.15 C
1.40 MAX.
1.40 MAX.
0.15(4X)
0.15 C
0.53±0.05
0.53±0.05
0.25
C
0.25 C
0.15(4X)
51-85180-*A
QDR™ SRAMs and Quad Data Rate™ SRAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron,
NEC and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective
holders.
Document Number: 38-05622 Rev. *C
Page 27 of 28
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
Document History Page
Document Title: CY7C1317BV18/CY7C1917BV18/CY7C1319BV18/CY7C1321BV18 18-Mbit DDR-II SRAM 4-Word Burst
Architecture
Document Number: 38-05622
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
252474
See ECN
SYT
New Data Sheet
*A
325581
See ECN
SYT
Removed CY7C1917BV18 from the title
Included 300-MHz Speed Bin
Added Industrial Temperature Grade
Replaced TBDs for IDD and ISB1 specs
Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 28.51°C/W
and ΘJC = 5.91°C/W
Replaced TBDs in the Capacitance Table for the 165 FBGA Package
Changed the package diagram from BB165E (15 x 17 x 1.4 mm) to BB165D
(13 x 15 x 1.4 mm)
Added Lead-Free Product Information
Updated the Ordering Information by Shading and Unshading MPNs as per
availability
*B
413999
See ECN
NXR
Added CY7C1917BV18 part number to the title
Added 278-MHz speed Bin
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed C/C Pin Description in the features section and Pin Description
Added power-up sequence details and waveforms
Added foot notes #15, 16, 17 on page# 19
Replaced Three-state with Tri-state
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 20
Modified the IDD and ISB values
Modified test condition in Footnote #18 on page# 20 from VDDQ < VDD to
VDDQ < VDD
Replaced Package Name column with Package Diagram in the Ordering
Information table
*C
472384
See ECN
NXR
Converted from Preliminary to Final
Modified the ZQ Definition from Alternately, this pin can be connected directly
to VDD to Alternately, this pin can be connected directly to VDDQ
Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND
Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH,
tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC
Switching Characteristics table
Modified Power-Up waveform
Changed the Maximum rating of Ambient Temperature with Power Applied
from –10°C to +85°C to –55°C to +125°C
Added additional notes in the AC parameter section
Modified AC Switching Waveform
Corrected the typo In the AC Switching Characteristics Table
Updated the Ordering Information Table
Document Number: 38-05622 Rev. *C
Page 28 of 28