STMicroelectronics M48Z129Y 5.0 v or 3.3 v, 1 mbit (128 kb x 8) zeropowerâ® sram Datasheet

M48Z129Y
M48Z129V
5.0 V or 3.3 V, 1 Mbit (128 Kb x 8) ZEROPOWER® SRAM
Features
■
Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■
Conventional SRAM operation; unlimited
WRITE cycles
■
10 years of data retention in the absence of
power
■
Microprocessor power-on reset (reset valid
even during battery backup mode)
■
Battery low pin - provides warning of battery
end-of-life
■
Automatic power-fail chip deselect and WRITE
protection
■
WRITE protect voltages
(VPFD = power-fail deselect voltage):
– M48Z129Y: VCC = 4.5 to 5.5 V
4.2 V ≤ VPFD ≤ 4.5 V
(contact the ST sales office for availability)
– M48Z129V: VCC = 3.0 to 3.6 V
2.7 V ≤ VPFD ≤ 3.0 V
■
Self-contained battery in the CAPHAT™ DIP
package
■
Pin and function compatible with JEDEC
standard 128 K x 8 SRAMs
■
RoHS compliant
– Lead-free second level interconnect
June 2010
Doc ID 5716 Rev 7
32
1
PMDIP32 module (PM)
1/20
www.st.com
1
Contents
M48Z129Y, M48Z129V
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
Doc ID 5716 Rev 7
M48Z129Y, M48Z129V
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PMDIP32 – 32-pin plastic DIP, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Doc ID 5716 Rev 7
3/20
List of figures
M48Z129Y, M48Z129V
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
4/20
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8
WRITE enable controlled, WRITE mode AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PMDIP32 – 32-pin plastic module DIP, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Doc ID 5716 Rev 7
M48Z129Y, M48Z129V
1
Description
Description
The M48Z129Y/V ZEROPOWER® SRAM is a 1,048,576 bit non-volatile static RAM
organized as 131,072 words by 8 bits. The device combines an internal lithium battery, a
CMOS SRAM and a control circuit in a plastic 32-pin DIP module. The M48Z129Y/V directly
replaces industry standard 128 K x 8 SRAM. It also provides the non-volatility of FLASH
without any requirement for special WRITE timing or limitations on the number of WRITEs
that can be performed.
Figure 1.
Logic diagram
VCC
17
8
A0-A16
W
DQ0-DQ7
M48Z129Y
M48Z129V
E
RST
BL
G
VSS
AI02309
Table 1.
Signal names
A0-A16
DQ0-DQ7
Address inputs
Data inputs / outputs
E
Chip enable
G
Output enable
W
WRITE enable
RST
BL
Reset output (open drain)
Battery low output (open drain)
VCC
Supply voltage
VSS
Ground
Doc ID 5716 Rev 7
5/20
Description
M48Z129Y, M48Z129V
Figure 2.
DIP connections
RST
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Figure 3.
1
32
2
31
30
3
29
4
28
5
27
6
26
7
8 M48Z129Y 25
9 M48Z129V 24
23
10
22
11
21
12
20
13
19
14
18
15
17
16
VCC
A15
BL
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI02310
Block diagram
VCC
A0-A16
POWER
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
131,072 x 8
SRAM ARRAY
E
DQ0-DQ7
W
G
INTERNAL
BATTERY
RST
6/20
BL
Doc ID 5716 Rev 7
VSS
AI03608
M48Z129Y, M48Z129V
2
Operation modes
Operation modes
The M48Z129Y/V also has its own power-fail detect circuit. This control circuitry constantly
monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance,
the circuit write protects the SRAM, providing data security in the midst of unpredictable
system operation. As VCC falls, the control circuitry automatically switches to the battery,
maintaining data until valid power is restored.
Table 2.
Operating modes
Mode
VCC
Deselect
WRITE
READ
4.5 to 5.5 V
or
3.0 to 3.6 V
READ
Deselect
VSO to VPFD
≤
Deselect
1.
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
X
X
X
High Z
CMOS standby
X
X
X
High Z
Battery backup mode
(min)(1)
VSO(1)
See Table 10 for details.
Note:
X = VIH or VIL; VSO = battery backup switchover voltage
2.1
READ mode
The M48Z129Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the 17 address inputs defines which one of
the 131,072 bytes of data is to be accessed. Valid data will be available at the data I/O pins
within tAVQV (address access time) after the last address input signal is stable, providing the
E and G access times are also satisfied. If the E and G access times are not met, valid data
will be available after the latter of the chip enable access times (tELQV) or output enable
access time (tGLQV).
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If
the address inputs are changed while E and G remain active, output data will remain valid
for tAXQX (output data hold time) but will go indeterminate until the next address access.
Figure 4.
Address controlled, READ mode AC waveforms
tAVAV
VALID
A0-A16
tAVQV
tAXQX
DQ0-DQ7
DATA VALID
DATA VALID
AI02324
Note:
Chip enable (E) and output enable (G) = low, WRITE enable (W) = high
Doc ID 5716 Rev 7
7/20
Operation modes
M48Z129Y, M48Z129V
Figure 5.
Chip enable or output enable controlled, READ mode AC waveforms
tAVAV
VALID
A0-A16
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI01197
Table 3.
READ mode AC characteristics
M48Z129Y
M48Z129V
–70
–85
Parameter(1)
Symbol
Min
Max
READ cycle time
tAVQV
Address valid to output valid
70
85
ns
tELQV
Chip enable low to output valid
70
85
ns
tGLQV
Output enable low to output valid
35
45
ns
(2)
70
Min
tAVAV
85
ns
Chip enable low to output transition
5
5
ns
tGLQX(2)
tEHQZ(2)
tGHQZ(2)
Output enable low to output transition
3
5
ns
tAXQX
Address transition to output transition
tELQX
8/20
Max
Unit
Chip enable high to output Hi-Z
30
40
ns
Output enable high to output Hi-Z
20
25
ns
5
5
1.
Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
2.
CL = 5pF (see Figure 9).
Doc ID 5716 Rev 7
ns
M48Z129Y, M48Z129V
2.2
Operation modes
WRITE mode
The M48Z129Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable)
are active. The start of a WRITE is referenced from the latter occurring falling edge of W or
E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held
valid throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable
or tWHAX from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in
must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G
should be kept high during WRITE cycles to avoid bus contention; although, if the output
bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after
W falls.
Figure 6.
WRITE enable controlled, WRITE mode AC waveform
tAVAV
VALID
A0-A16
tAVWH
tAVEL
tWHAX
E
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI02382
Figure 7.
Chip enable controlled, WRITE mode AC waveforms
tAVAV
VALID
A0-A16
tAVEH
tAVEL
tELEH
tEHAX
E
tWLWH
tAVWL
W
tDVEH
tEHDX
DATA INPUT
DQ0-DQ7
AI03611
Doc ID 5716 Rev 7
9/20
Operation modes
Table 4.
M48Z129Y, M48Z129V
WRITE mode AC characteristics
M48Z129Y
M48Z129V
–70
–85
Parameter(1)
Symbol
Min
Min
Max
tAVAV
WRITE cycle time
70
85
ns
tAVWL
Address valid to WRITE enable low
0
0
ns
tAVEL
Address valid to chip enable low
0
0
ns
tWLWH
WRITE enable pulse width
55
65
ns
tELEH
Chip enable low to chip enable high
55
75
ns
tWHAX
WRITE enable high to address transition
5
5
ns
tEHAX
Chip enable high to address transition
15
15
ns
tDVWH
Input valid to WRITE enable high
30
35
ns
tDVEH
Input valid to chip enable high
30
35
ns
tWHDX
WRITE enable high to input transition
0
0
ns
tEHDX
Chip enable high to input transition
10
15
ns
tWLQZ(2)(3)
WRITE enable low to output Hi-Z
25
30
ns
tAVWH
Address valid to WRITE enable high
65
75
ns
tAVEH
Address valid to chip enable high
65
75
ns
WRITE enable high to output transition
5
5
ns
tWHQX(2)(3)
2.3
Max
Unit
1.
Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
2.
CL = 5 pF (see Figure 9).
3.
If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Data retention mode
With valid VCC applied, the M48Z129Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting
itself when VCC falls between VPFD (max), VPFD (min) window. All outputs become high
impedance and all inputs are treated as “Don’t care”.
Note:
A power failure during a WRITE cycle may corrupt data at the current addressed location,
but does not jeopardize the rest of the RAM’s content. At voltages below VPFD(min), the
memory will be in a write protected state, provided the VCC fall time is not less than tF. The
M48Z129Y/V may respond to transient noise spikes on VCC that cross into the deselect
window during the time the device is sampling VCC. Therefore, decoupling of the power
supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery,
preserving data. The internal energy source will maintain data in the M48Z129Y/V for an
accumulated period of at least 10 years at room temperature. As system power rises above
VSO, the battery is disconnected, and the power supply is switched to external VCC.
Deselect continues for tREC after VCC reaches VPFD(max).
For more information on battery storage life refer to the application note AN1012.
10/20
Doc ID 5716 Rev 7
M48Z129Y, M48Z129V
2.4
Operation modes
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 8) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.
Figure 8.
Supply voltage protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
Doc ID 5716 Rev 7
11/20
Maximum ratings
3
M48Z129Y, M48Z129V
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5.
Absolute maximum ratings
Symbol
TA
TSTG
TSLD(1)
Parameter
Ambient operating temperature
Storage temperature (VCC off, oscillator off)
Lead solder temperature for 10 seconds
Value
Unit
0 to 70
°C
–40 to 85
°C
260
°C
VIO
Input or output voltages
–0.3 to 7
V
VCC
Supply voltage
–0.3 to 7
V
IO
Output current
20
mA
PD
Power dissipation
1
W
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. In order to protect the lithium
battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 °C.
Furthermore, the devices shall not be exposed to IR reflow.
Caution:
12/20
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Doc ID 5716 Rev 7
M48Z129Y, M48Z129V
4
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 6.
Operating and AC measurement conditions
Parameter
M48Z129Y
M48Z129V
Unit
4.5 to 5.5
3.0 to 3.6
V
Supply voltage (VCC)
0 to 70
0 to 70
°C
Load capacitance (CL)
Ambient operating temperature (TA)
100
50
pF
Input rise and fall times
≤5
≤5
ns
0 to 3
0 to 3
V
1.5
1.5
V
Input pulse voltages
Input and output timing ref. voltages
Note:
Output Hi-Z is defined as the point where data is no longer driven.
Figure 9.
AC testing load circuit
650Ω
DEVICE
UNDER
TEST
CL = 100pF
or 50pF(1)
1.75V
CL includes JIG capacitance
AI03630
1. 50 pF for M48Z129V (3.3 V).
Table 7.
Capacitance
Parameter(1)(2)
Symbol
CIN
CIO
(3)
Min
Max
Unit
Input capacitance
-
10
pF
Input / output capacitance
-
10
pF
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. At 25 °C, f = 1 MHz.
3. Outputs deselected.
Doc ID 5716 Rev 7
13/20
DC and AC parameters
Table 8.
M48Z129Y, M48Z129V
DC characteristics
Sym
Parameter
M48Z129Y
M48Z129V
–70
–85
Test condition(1)
Min
ILI
ILO(2)
Input leakage current
Output leakage current
Max
Min
Unit
Max
0 V ≤ VIN ≤ VCC
±1
±1
µA
0 V ≤ VOUT ≤ VCC
±1
±1
µA
Outputs open
95
50
mA
E = VIH
7
4
mA
E = VCC – 0.2 V
4
3
mA
ICC
Supply current
ICC1
Supply current (standby) TTL
ICC2
Supply current (standby) CMOS
VIL
Input low voltage
–0.3
0.8
–0.3
0.6
V
VIH
Input high voltage
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VOL
Output low voltage
IOL = 2.1 mA
VOH
Output high voltage
IOH = –1 mA
0.4
2.4
0.4
2.2
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
2. Outputs deselected.
14/20
Doc ID 5716 Rev 7
V
V
M48Z129Y, M48Z129V
DC and AC parameters
Figure 10. Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tDR
tFB
tRB
tREC
tWPT
E
DON'T CARE
RECOGNIZED
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
RST
AI03610
Table 9.
Power down/up AC characteristics
Parameter(1)
Symbol
tF(2)
VPFD (max) to VPFD (min) VCC fall time
tFB(3)
VPFD (min) to VSS VCC fall time
Min
Max
300
M48Z129Y
10
M48Z129V
150
Unit
µs
µs
tR
VPFD (min) to VPFD (max) VCC rise time
10
µs
tRB
VSS to VPFD (min) VCC rise time
1
µs
tWPT
Write protect time
tREC
VPFD (max) to RST high
M48Z129Y
40
150
M48Z129V
40
250
40
200
µs
ms
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10.
Power down/up trip points DC characteristics
Parameter(1)(2)
Symbol
VPFD
Power-fail deselect voltage
VSO
Battery backup switchover voltage
tDR(3)
Expected data retention time
Min
Typ
Max
Unit
M48Z129Y
4.2
4.35
4.5
V
M48Z129V
2.7
2.9
3.0
V
M48Z129Y
3.0
V
M48Z129V
2.45
V
10
Years
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
3. At 25 °C, VCC = 0 V.
Doc ID 5716 Rev 7
15/20
Package mechanical data
5
M48Z129Y, M48Z129V
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 11. PMDIP32 – 32-pin plastic module DIP, package outline
A
A1
B
S
L
C
eA
e1
e3
D
N
E
1
PMDIP
Note:
Drawing is not to scale.
Table 11.
PMDIP32 – 32-pin plastic DIP, package mechanical data
mm
inches
Symb
Typ
Min
Max
A
9.27
A1
Min
Max
9.52
0.365
0.375
0.38
–
0.015
–
B
0.43
0.59
0.017
0.023
C
0.20
0.33
0.008
0.013
D
42.42
43.18
1.670
1.700
E
18.03
18.80
0.710
0.740
e1
2.29
2.79
0.090
0.110
e3
16/20
38.1
Typ
1.5
eA
14.99
16.00
0.590
0.630
L
3.05
3.81
0.120
0.150
S
1.91
2.79
0.075
0.110
N
32
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M48Z129Y, M48Z129V
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Part numbering
Part numbering
Table 12.
Ordering information scheme
Example:
M48Z
129Y
–70
PM
1
Device Type
M48Z
Supply voltage and write protect voltage
129Y(1) = VCC = 4.5 to 5.5 V; 4.2 V ≤ VPFD ≤ 4.5 V
129V = VCC = 3.0 to 3.6 V; 2.7 V ≤ VPFD ≤ 3.0 V
Speed
–70 = 70 ns (M48Z129Y)
–85 = 85 ns (M48Z129V)
Package
PM = PMDIP32
Temperature range
1 = 0 to 70 °C
Shipping method
blank = ECOPACK® package, tubes
1. Contact local ST sales office.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
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Environmental information
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M48Z129Y, M48Z129V
Environmental information
Figure 12. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
Please refer to the following web site address for additional information regarding
compliance statements and waste recycling.
Go to www.st.com/nvram, then select "Lithium Battery Recycling" from "Related Topics".
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Revision history
Revision history
Table 13.
Document revision history
Date
Revision
Dec-1999
1.0
Changes
First issue
30-Mar-2000
2
20-Jun-2000
2.1
From preliminary data to datasheet
14-Sep-2001
3
29-May-2002
3.1
02-Apr-2003
4
v2.2 template applied; test condition updated (Table 10)
18-Feb-2005
5
Reformatted; IR reflow update (Table 5)
22-Apr-2010
6
Updated Table 11, 12, footnote 1 of Table 5; added Ecopack® text to
Section 5; reformatted document.
23-Jun-2010
7
Updated Features, Table 11; added Section 7: Environmental information;
minor textual changes.
tGLQX changed for M48Z129Y (Table 3)
Reformatted; temperature information added to tables (Table 7, 8, 3, 4, 9,
10)
Add countries to disclaimer
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M48Z129Y, M48Z129V
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