IK Semicon IN74ACT651 Octal 3-state bus transceivers and d flip-flops high-speed silicon-gate cmo Datasheet

TECHNICAL DATA
IN74ACT651
Octal 3-State Bus Transceivers
and D Flip-Flops
High-Speed Silicon-Gate CMOS
The IN74ACT651 is identical in pinout to the LS/ALS651,
HC/HCT651. The IN74ACT651 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
These devices consists of bus transceiver circuits, D-type flip-flop,
and control circuitry arranged for multiplex transmission of data directly
from the data bus or from the internal storage registers. Direction and
Output Enable are provided to select the read-time or stored data function.
Data on the A or B Data bus, or both, can be stored in the internal D flipflops by low-to-high transitions at the appropriate clock pins (A-to-B
Clock or B-to-A Clock) regardless of the select or enable or enable
control pins. When A-to-B Source and B-to-A Source are in the real-time
transfer mode, it is also possible to store data without using the internal
D-type flip-flops by simultaneously enabling Direction and Output
Enable. In this configuration each output reinforces its input. Thus, when
all other data sources to the two sets of bus lines are at high impedance,
each set of bus lines will remain at its last state.
The IN74ACT651 has inverted outputs.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74ACT651N Plastic
IN74ACT651DW SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 24=VCC
PIN 12 = GND
Rev. 00
IN74ACT651
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TJ
Junction Temperature (PDIP)
TA
Operating Temperature, All Package Types
IOH
Output Current - High
IOL
Output Current - Low
tr, tf
*
Parameter
Input Rise and Fall Time
(except Schmitt Inputs)
*
Min
Max
Unit
4.5
5.5
V
0
VCC
V
140
°C
+85
°C
-24
mA
24
mA
10
8.0
ns/V
-40
VCC =4.5 V
VCC =5.5 V
0
0
VIN from 0.8 V to 2.0 V
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
Rev. 00
IN74ACT651
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Test Conditions
Guaranteed Limits
V
25 °C
-40°C to
85°C
Unit
VIH
Minimum HighLevel Input Voltage
VOUT=0.1 V or VCC-0.1 V
4.5
5.5
2.0
2.0
2.0
2.0
V
VIL
Maximum Low Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
V
VOH
Minimum HighLevel Output Voltage
IOUT ≤ -50 µA
4.5
5.5
4.4
5.4
4.4
5.4
V
4.5
5.5
3.86
4.86
3.76
4.76
4.5
5.5
0.1
0.1
0.1
0.1
VIN=VIH or VIL
IOL=24 mA
IOL=24 mA
4.5
5.5
0.36
0.36
0.44
0.44
±0.1
±1.0
µA
1.5
mA
±6.0
µA
*
VIN=VIH or VIL
IOH=-24 mA
IOH=-24 mA
VOL
Maximum LowLevel Output Voltage
IOUT ≤ 50 µA
V
*
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
5.5
∆ICCT
Additional Max.
ICC/Input
VIN=VCC - 2.1 V
5.5
IOZ
Maximum ThreeState Leakage
Current
VI (OE)= VIH or VIL
VI =VCC or GND
VO =VCC or GND
5.5
IOHD
+Minimum Dynamic
Output Current
VOLD=1.65 V Max
5.5
75
mA
IOHD
+Minimum Dynamic
Output Current
VOHD=3.85 V Min
5.5
-75
mA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
5.5
80
µA
±0.6
8.0
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Rev. 00
IN74ACT651
AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits
Symbol
Parameter
25 °C
-40°C to 85°C
Min
Max
Min
Max
Unit
tPLH
Propagation Delay, A-to-B Clock or B-to-A Clock
to A or B Data Port (Figure 1)
4.0
14.5
3.5
16.5
ns
tPHL
Propagation Delay, A-to-B Clock or B-to-A Clock
to A or B Data Port (Figure 1)
3.5
14.5
3.0
16.5
ns
tPLH
Propagation Delay, Input A to Output B or Input B
to Output A (Figures 2,3)
2.5
11.5
2.0
13.0
ns
tPHL
Propagation Delay, Input A to Output B or Input B
to Output A (Figures 2,3)
2.5
11.5
2.0
13.0
ns
tPLH
Propagation Delay, A-to-B Source or B-to-A
Source to A or B Data Port (Figure 4)
2.5
12.0
2.0
13.5
ns
tPHL
Propagation Delay, A-to-B Source or B-to-A
Source to A or B Data Port (Figure 4)
3.0
12.0
2.5
13.5
ns
tPZH
Propagation Delay, Output Enable to A Data Port
(Figure 5)
2.0
11.5
1.5
13.0
ns
tPZL
Propagation Delay, Output Enable to A Data Port
(Figure 5)
2.5
11.5
2.0
13.0
ns
tPHZ
Propagation Delay, Output Enable to A Data Port
(Figure 5)
3.0
13.0
2.5
14.0
ns
tPLZ
Propagation Delay, Output Enable to A Data Port
(Figure 5)
2.5
12.5
2.0
14.0
ns
tPZH
Propagation Delay, Direction to B Data Port
(Figure 6)
2.5
12.0
2.0
13.5
ns
tPZL
Propagation Delay, Direction to B Data Port
(Figure 6)
2.5
12.0
2.0
13.5
ns
tPHZ
Propagation Delay, Direction to B Data Port
(Figure 6)
3.5
13.5
3.0
14.5
ns
tPLZ
Propagation Delay, Direction to B Data Port
(Figure 6)
3.0
13.5
2.5
15.0
ns
CIN
Maximum Input Capacitance
4.5
4.5
pF
Input/Output Capacitance
15
15
pF
COUT
Typical @25°C,VCC=5.0 V
CPD
Power Dissipation Capacitance
60
pF
Rev. 00
IN74ACT651
TIMING REQUIREMENTS (VCC=5.0 V ± 10 %, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits
Symbol
Parameter
25 °C
-40°C to
85°C
Unit
tsu
Minimum Setup Time, A or B Data Port to A-to-B
Clock or B-to-A Clock (Figure 7)
7.0
8.0
ns
th
Minimum Hold Time, A-to-B Clock or B-to-A Clock
to A or B Data Port (Figure 7)
2.5
2.5
ns
tw
Minimum Pulse Width, A-to-B Clock or B-to-A Clock
(Figure 7)
6.0
7.0
ns
TIMING DIAGRAM
Rev. 00
IN74ACT651
FUNCTION TABLE
Dir.
OE
L
H
CAB CBA SAB SBA
X
X*
L
L
X
X
X*
X*
X
X*
A
B
INPUTS
INPUTS
Both the A bus and the B bus are inputs.
X
X
Z
Z
The output functions of the A and B bus
are disabled.
X
X
INPUTS
INPUTS
Both the A and B bus are used for inputs
to the internal flip-flops. Data at the bus
will be stored on low to high transition of
the clock inputs.
OUTPUTS
INPUTS
The A bus are outputs and the B bus are
inputs.
X
L
H
L
L
H
The data at the B bus are displayed at the
A bus.
X
L
H
L
L
H
The data at the B bus are displayed at the
A bus. The data of the B bus are stored to
the internal flip-flops on low to high
transition of the clock pulse.
X
H
Qn
X
The data stored to the internal flip-flops,
are displayed at the A bus.
X
H
L
H
H
L
The data at the B bus are stored to the
internal flip-flops on low to high
transition of the clock pulse. The states of
the internal flip-flops output directly to
the A bus.
INPUTS
X
H
H
X
L
X
OUTPUTS The A bus are inputs and the B bus are
outputs.
X*
L
X
H
L
L
H
The data at the A bus are displayed at the
B bus.
X*
L
X
H
L
L
H
The data at the B bus are displayed at the
A bus. The data of the B bus are stored to
the internal flip-flops on low to high
transition of the clock pulse.
X*
H
X
X
Qn
The data stored to the internal flip-flops
are displayed at the B bus.
X*
H
X
H
L
L
H
The data at the A bus are stored to the
internal flip-flops on low to high
transition of the clock pulse. The states of
the internal flip-flops output directly to
the B bus.
OUTPUTS
H
FUNCTION
X
OUTPUTS Both the A bus and the B bus are outputs
H
H
Qn
Qn
The data stored to the internal flip-flops
are displayed at the A and B bus
respectively.
H
H
Qn
Qn
The output at the A bus are displayed at
the B bus, the output at the B bus are
displayed at the A bus respec.
X : DON’T CARE
Z : HIGH IMPEDANCE
Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION
OF THE CLOCK INPUTS
*
: THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW
TO TRANSITION OF THE CLOCK INPUTS
Rev. 00
IN74ACT651
SWITCHING DIAGRAMS
Figure 1. Switching Waveforms
Figure 2. A Data Port = Input, B Data Port =
Output
Figure 3. A Data Port = Output, B Data Port =
Input
Figure 4. Switching Waveforms
Figure 5. Switching Waveforms
Figure 6. Switching Waveforms
Figure 7. Switching Waveforms
Rev. 00
IN74ACT651
EXPANDED LOGIC DIAGRAM
Rev. 00
IN74ACT651
N SUFFIX PLASTIC DIP
(MS - 001AF)
A
Dimension, mm
13
24
Symbol
MIN
MAX
A
31.24
32.51
B
6.1
7.11
B
12
1
C
F
L
5 .33
D
0.36
0.56
F
1.14
1.78
C
-T- SEATING
G
2.54
H
7.62
PLANE
N
G
M
K
H
D
J
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 013AD)
Dimension, mm
A
24
13
H
B
1
P
12
G
R x 45
C
-TK
D
SEATING
PLANE
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
J
F
Symbol
MIN
MAX
A
15.2
15.6
B
7.4
7.6
C
2.35
2.65
D
0.33
0.51
F
0.4
1.27
G
1.27
H
9.53
M
J
0°
8°
K
0.1
0.3
M
0.23
0.32
P
10
10.65
R
0.25
0.75
Rev. 00
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