APA3163 20W Stereo Digital Class-D Audio Power Amplifier with EQ and DRC Features General Description • Operating Voltage: 8.0V~24V for PVDD The APA3163 is a digital input, stereo, high efficiency, • – 3.0V~3.6V for DVDD and AVDD High Efficiency Class-D Operation Eliminate the Class-D audio amplifier available in a TQFP7x7-48P package. Need of Heatsinks Digital Serial Audio Input (Stereo Output) The APA3163 accepts the digital serial audio data and using the digital audio processor to convert the audio I2C Control Interface Sampling Rate can Support from 32kHz to 192kHz data becomes the stereo Class-D output speaker amplifier. This provides the seamless integration between Separated Volume Control from 24dB to Mute Soft Mute (50% Duty Cycle) the codec and the speaker amplifier. The APA3163 is a slave device receiving clocks from ex- Programmable Dynamic Range Compression – Power Limiter ternal source, and the Class-D’s PWM switching frequency is 352.8kHz for the sampling rate 44.1kHz or 384 – Speaker Protection – Night-Mode Listening kHz for sampling 48kHz, depend on the input signal’s sampling rate. Programmable Biquads for Speaker EQ Shutdown and Mute Function Pin Configuration • • • • • Thermal and Over-Current Protections with AutoRecovery 48 PGND_AB 47 PGND_AB 46 OUT_B 45 PVDD_B 44 PVDD_B 43 BBS 42 CBS 41 PVDD_C 40 PVDD_C 39 OUT_C 38 PGND_CD 37 PGND_CD • • • • • • Space Saving Package TQFP7x7-48P Lead Free and Green Devices Available (RoHS Compliant) Applications • LCD TV Simplified Application Circuit OUT_A 1 PVDD_A 2 PVDD_A 3 ABS 4 GDREG 5 NC 6 NC 7 TM 8 AVSS 9 PLL_LF 10 36 OUT_D 35 PVDD_D 34 PVDD_D 33 DBS 32 GDREG 31 DVREG 30 AGND 29 GND 28 DVSS 27 DVDD 26 TP3 TOP VIEW (APA3163) NC 11 NC 12 MCLK LRCLK SCLK SDIN OUT_A OUT_B Left Channel Speaker AVDD 13 ERROR 14 MCLK 15 TP1 16 TP2 17 1V8_DV 18 SD 19 LRCK 20 SCLK 21 SDIN 22 SDA 23 SCL 24 Digital Audio Source APA3163 OUT_C I2C Control SDA SCL OUT_D 25 RST Right Channel Speaker ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 1 www.anpec.com.tw APA3163 Ordering and Marking Information Package Code QCA : TQFP7x7-48P Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA3163 Assembly Material Handling Code Temperature Range Package Code APA3163 QCA : APA3163 XXXXX XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol TJ (Note 1) Parameter Unit Supply Voltage (PVDD_X to PGND_XX) -0.3 to 26 Supply Voltage (DVDD to DVSS) -0.3 to 3.6 Supply Voltage (AVDD to AVSS) -0.3 to 3.6 Input Voltage (MCLK to AVSS) -0.5 to AVDD+2.5 Input Voltage (SD, RST, LRCLK, SCLK, SDIN, SDA, SCL to DVSS) -0.5 to DVDD+2.5 Input Voltage (OUT_X to PGND_XX) -0.3 to +26 Input Voltage (XBS to PGND_XX) -0.3 to +31 Input Voltage (AVSS, DVSS, AGND to PGND_XX) -0.3 to +0.3 Maximum Junction Temperature TSTG Storage Temperature Range TSDR Soldering Temperature Range, 10 seconds PD Rating Power Dissipation V 150 ο -65 to +150 ο 260 ο C C C Internally Limited W Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Junction-to-Ambient Resistance in Free Air (Note 2) TQFP7x7-48P Typical Value Unit 25 °C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of TQFP7X7-48P is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TQFP7X7-48P package. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 2 www.anpec.com.tw APA3163 Recommended Operating Conditions Symbol VDD PVDD Range Parameter Min. Max. 3 3.6 8 24 2 5 0 1 Supply Voltage Full Bridge Stage Supply Voltage (PVDD_X) SD, MCLK, LRCLK, SCLK, SDIN, SDA, SCL, RST SD, MCLK, LRCLK, SCLK, SDIN, SDA, SCL, RST Unit V VIH High Level Threshold Voltage VIL Low Level Threshold Voltage TA Ambient Temperature Range -40 85 TJ Junction Temperature Range -40 125 RL Speaker Resistance 6 - Ω LO Output Low Pass Filter Inductance 10 - µH ο C PWM Operating Conditions Symbol Parameter Test Conditions Value 32 kHz Data Rate ±2% fS Output Sample Rate Unit 256 44.1k/88.2k/176.4 kHz Data Rate ±2% 352.8 48k/96k/192 kHz Data Rate ±2% kHz 384 PLL Input Parameters and External Filter Components Symbol fMCLK tr/tf (MCLK) Parameter Test Conditions APA3163 Min. Typ. Max. MCLK Frequency 2.8224 - 24.576 MCLK Duty Cycle Unit MHz 40 50 60 % Rise/Fall Time for MCLK - - 5 ns LRCLK Allowable Drift before LRCLK Reset - - 4 MCLKs External PLL Filter Capacitor C1 SMD 0603 Y5V - 47 - External PLL Filter Capacitor C2 SMD 0603 Y5V - 4.7 - - 470 - External PLL Filter Resistor R nF Ω Electrical Characteristics ο TA=25 C, PVDD=18V, VDD=3.3V (AVDD and DVDD), RL=8Ω, BD Mode, fS=48kHz (unless otherwise noted) Symbol Parameter APA3163 Test Conditions Min. Typ. Unit Max. DC CHARACTERISTICS IDD 3.3V Supply Current (AVDD, DVDD) Normal Mode (No load) - 10 20 Reset (No load) - 7.2 14.5 IPVDD Full Bridge Stage Supply Current (PVDD_X) Normal Mode (No load) - 18 36 Reset (No load) - 0.5 1 VI<VIL, VDD=3.6V (AVDD and DVDD) - 150 - IIL Low Level Input Current Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 3 mA µA www.anpec.com.tw APA3163 Electrical Characteristics (Cont.) ο TA=25 C, PVDD=18V, VDD=3.3V (AVDD and DVDD), RL=8Ω, BD Mode, fS=48kHz (unless otherwise noted) Symbol Parameter APA3163 Test Conditions Unit Min. Typ. Max. - 150 - µA - 180 - mΩ - 180 - mΩ Thermal Protection Threshold - 160 170 Thermal Protection Threshold Hysteresis - 25 - - 88 - % - 3 - kΩ 14.5 16 - DC CHARACTERISTICS (CONT.) IIH rDS(ON) High Level Input Current Drain to source resistance,LS Drain to source resistance,HS TTP η ROUT Efficiency VI>VIH, VDD=3.6V (AVDD and DVDD) TJ=25oC, includes metallization resistance TJ=25oC, includes metallization resistance ο Stereo, RL=8Ω, PO=18W Internal Pull-Down Resistance at Each OUT_X C AC CHARACTERISTICS PVDD=18V THD+N=1% fin=1kHz, RL=8Ω PO Output Power THD+N=1% fin=1kHz, RL=6Ω THD+N=10% fin=1kHz, RL=6Ω Crosstalk Total Harmonic Distortion Plus Noise 7.2 - 3.2 - PVDD=12V 8.1 9 - PVDD=18V - 20 - PVDD=12V - 9 - PVDD=8V - 4 - PVDD=12V - 11 - PVDD=18V, PO=1W - 0.06 - fin=1kHz, RL=8Ω PVDD=12V, PO=1W - 0.13 - PVDD=8V, PO=1W - 0.2 - PO=0.25W, RL=8Ω, fin=1kHz - -82 - Mute Attenuation fin=1kHz, RL=8Ω, VO=1Vrms - -70 - Attshutdown Shutdown Attenuation fin=1kHz, RL=8Ω, VO=1Vrms - -110 - S/N Signal to Noise Ratio RL=8Ω, PO=16W, With A-Weighting Filter (AV=0dB) - 97 - Vn Noise Output Voltage With A-Weighting Filter (AV=0dB) - 150 - AttMute Channel Separation 6.5 2.9 W THD+N=10% fin=1kHz, RL=8Ω THD+N PVDD=12V PVDD=8V Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 4 % dB µVrms www.anpec.com.tw APA3163 Serial Audio Ports Slave Mode Over recommended operating conditions (unless otherwise noted) Symbol Parameter Test Conditions APA3163 Min. Typ. Max. 1.024 - 12.288 fSCLK Frequency, SCLK 32xfS, 48xfS, 64xfS tSetup1 Setup Time, LRCLK to SCLK Rising Edge 10 - - tHold1 Hold Time, LRCLK to SCLK Rising Edge 10 - - CL=30pF Unit MHz ns Serial Audio Ports Slave Mode Over recommended operating conditions (unless otherwise noted) Symbol tSetup2 tHold t(edge) tr/tf Parameter Test Conditions APA3163 Unit Min. Typ. Max. Setup Time, SDIN to SCLK Rising Edge 10 - - Hold Time, SDIN to SCLK Rising Edge 10 - - LRCLK Frequency 8K 48K 48K LRCLK Duty Cycle 40 50 60 SCLK Duty Cycle 40 50 60 SCLK Rising Edges Between LRCLK Riding Edges 32 - 64 SCLK edges LRCLK Clock Edge With Respect To The Falling Edge of SCLK -1/4 - 1/4 SCLK period - - 8 ns ns Rise/Fall Time for SCLK/LRCLK kHz % (SCLK/LRCLK) Reset Timing Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to “Recommended Use Model” section on usage of all terminals. Symbol tp(RST) td(12C_Ready) Parameter Pulse Duration, RST Active. Test Conditions No Load 2 Time to Enable I C Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 5 APA3163 Unit Min. Typ. Max. 100 - - µs - - 13.5 ms www.anpec.com.tw APA3163 I2C Serial Control Port Operation Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted) Symbol Parameter Test Conditions No Wait States APA3163 Min. Typ. Max. fSCL Frequency, SCL - - 400 tW(H) Pulse Duration, SCL High 0.6 - - tW(L) Pulse Duration, SCL Low 1.3 - - tr Rise Time, SCL and SDA - - 300 tf Fall Time, SCL and SDA - - 300 tsetup1 Setup Time, SCL to SDA 100 - - thold1 Hold Time, SCL to SDA 0 - - t(buf) Bus Free Time Between Stop and Start Condition 1.3 - - tsetup2 Setup Time, SCL to Start Condition 0.6 - - thold2 Hold Time, Start condition to SCL 0.6 - - tsetup3 Setup Time, SCL to Stop Condition 0.6 - - - - 400 CL Load Capacitance for Each Bus Line Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 6 Unit kHz µs ns µs pF www.anpec.com.tw APA3163 Typical Operating Characteristics THD+N vs. Frequency 10 1 1 THD+N (%) THD+N (%) THD+N vs. Frequency 10 0.1 Po=5W Po=1W PVDD=18V RL=8Ω AUX-0025 AES-17(20kHz) 0.01 50 100 Po=2.5 500 1 k 2k 5k 0.001 20 k 20 50 100 Frequency (Hz) 1 1 0.1 0.01 0.001 Po=0.5W PVDD=8V RL=8Ω AUX-0025 AES-17(20kHz) 20 50 100 Fin=20Hz 5k 20k 0.01 500 1 k 2k 5k Fin=10kHz VDD=18V RL=8Ω AUX-0025 AES-17(20kHz) 0.001 10 m 20k Fin=1kHz 0.1 Frequency (Hz) 100 m 1 2 5 10 20 50 Output Power (W) THD+N vs. Output Power THD+N vs. Output Power 10 10 1 1 Fin=1kHz Fin=10kHz THD+N (%) Fin=20Hz THD+N (%) 2k THD+N vs. Output Power 10 THD+N (%) THD+N (%) THD+N vs. Frequency Po=1W 500 1 k Frequency (Hz) 10 Po=2.5 Po=0.5W PVDD=12V RL=8Ω AUX-0025 AES-17(20kHz) 0.01 0.001 20 . 0.1 0.1 Fin=20Hz Fin=1kHz 0.01 VDD=8V RL=8Ω AUX-0025 AES-17(20kHz) 0.001 10 m 100 m 0.01 VDD=12V RL=8Ω AUX-0025 AES-17(20kHz) 0.001 10 m 100 m 1 2 5 10 50 Fin=10kHz 1 2 5 10 20 50 Output Power (W) Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 0.1 7 www.anpec.com.tw APA3163 Typical Operating Characteristics (Cont.) Output Power vs. Supply Voltage 20 RL=8Ω Duty=97.7% 90 16 80 14 70 Efficiency(%) Output Power / Per Channel(W) 18 12 THD+N=10% 10 8 PVDD=24V PVDD=18V PVDD=12V 60 PVDD=8V 50 40 30 6 20 THD+N=1% 4 2 Efficiency vs. Output Power 100 RL=8Ω Duty=97.7% 10 8 9 10 11 12 13 14 15 16 17 0 18 0 2 Supply Voltage(V) 8 10 12 14 16 18 20 22 24 -0 PVDD=18V Po=0.25W RL=8Ω AUX-0025 10~22kHz PVDD=12V Po=0.25W RL=8Ω AUX-0025 10~22kHz -20 Crosstalk (dB) -20 Crosstalk (dB) 6 Crosstalk vs. Frequency Crosstalk vs. Frequency 0 -40 -60 Left to Right -40 -60 Right to Left Left to Right Right to Left -80 -80 -100 4 Output Power / Per Channel(W) -100 20 50 100 500 1 k 2k 5k 20k 20 50 100 500 1 k 2k 5k 20k Frequency (Hz) Frequency (Hz) Crosstalk vs. Frequency 0 Crosstalk (dB) -20 PVDD=8V Po=0.25W RL=8Ω AUX-0025 10~22kHz -40 -60 Left to Right Right to Left -80 -100 20 50 100 500 1 k 2k 5k 20 k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 8 www.anpec.com.tw APA3163 Pin Description PIN FUNCTION I/O/P NO. NAME 1 OUT_A 2, 3 4 O Output of half bridge A. PVDD_A P Power supply for half bridge A. ABS I/O High side bootstrap supply for half bridge A. 5, 32 GDREG O/P Internal regulator output of gate driver. 6 NC - No connection. 7 NC - No connection. 8 TM I Test mode digital input pin. 9, 11 AVSS P Analog power supply’s ground. 10 PLL_LF O PLL negative loop filter pin. 12 2V5_AV O/P 13 AVDD P Analog powers supply and connects to 3.3V. 14 ERROR O When over temperature, over current over voltage and under voltage occur, this pin will be pull low; and it will be reset to high when the fault condition has be remove. 15 MCLK I Master clock input. 16 TP1 I/O Test mode digital input/output pin. 17 TP2 I/O Test mode digital input/output pin. 18 1V8_DV O/P Internal regulated 1.8V for digital block’s supply, Not for power external device. 19 SD I Active LOW, Shutting down the noise shaper and initiating PWM stop sequence. 20 LRCLK I Input serial audio data left/right clock. (Sample rate clock), it’s weak pull down terminal. 21 SCLK I Serial audio data clock (shift clock). SCLK is the serial audio port input data bit clock. 22 SDIN I Serial audio data input. 23 SDA IO 24 SCL I I2C serial control clock input. 25 RST I Reset control, place a logic low to this pin, will reset the APA3163 to its default condition. It’s weak pull-up terminal. 26 TP3 I/O 27 DVDD P 28 DVSS P Digital power supply’s ground. 29 GND P Power stage’s analog ground. 30 AGND P Power stage’s analog ground. 31 DVREG O/P Digital voltage regulator’s output, only for internal used. 33 DBS I/O High side bootstrap supply for half bridge D. 34, 35 PVDD_D P Power supply for half bridge D. 36 OUT_D O Output of half bridge D. 37, 38 PGND_CD P Power Ground connection for half bridge C and D. 39 OUT_C O Output of half bridge C. 40, 41 PVDD_C P Power supply for half bridge C. 42 CBS I/O High side bootstrap supply for half bridge C. 43 BBS I/O High side bootstrap supply for half bridge B. Internal regulated 2.5V for analog block’s supply, Not for power external device. I2C serial control data interface input/output. Test mode digital input/output pin. Digital powers supply and connects to 3.3V. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 9 www.anpec.com.tw APA3163 Pin Description (Cont.) PIN FUNCTION I/O/P NO. NAME 44, 45 PVDD_B P Power supply for half bridge B. 46 OUT_B O Output of half bridge B. 47, 48 PGND_AB P Power Ground connection for half bridge A and B. Block Diagram AVDD 1V8_DV SDIN Regulator 3.3V to 1.8V Serial Audio Port Volume De-emphasis & DC Blocking Inter Polarization PWM Full Bridge FET Output SDA SCL Noise Shaper Sampling Rate Serial Control Register Bank AGND PWM AVSS PLL_LF OUT_B BBS PVDD_B DGND MCLK SCLK LRCLK PVDD_A ABS OUT_A PGND_AB PLL Full Bridge FET Output Gate Driver Regulator Control Logic Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 OUT_D DBS PVDD_D Central Control DVDD PVDD_C CBS OUT_C PGND_CD RST 10 SD ERROR GDREG www.anpec.com.tw APA3163 Typical Application Circuit 470 O 0.047 µF 4700pF 0.047µF 470 O 2200 pF 1µF 4700 pF NC NC PLL_LF AVSS TM NC NC 22.1kO GDREG ABS PVDD_A PVDD_A OUT_A AVDD 10µ F 0.1µF 0. 1µ F AVDD /PDN LRCK SCLK SDIN SDA SCL 0.1µ F 22µH 0. 68µF 220µ F AVDD /ERROR 10kO MCLK 18. 2kO TP1 TP2 10kO 1V8_DV /SD LRCLK SCLK SDIN SDA SCL 13 14 15 16 17 18 19 20 21 22 23 24 0. 68µF 48 47 46 45 44 43 42 41 40 39 38 37 APA3163 PGND_AB PGND_AB OUT_B PVDD_B PVDD_B BBS DBS PVDD_C PVDD_C OUT_C PGND_CD PGND_CD 8O 22µH 0.033µ F 0.033µ F 0.1µ F PVDD 0.1µ F 22µH 0. 68µF /RST TP3 DVDD DVSS GND AGND DVREG GDREG DBS PVDD_D PVDD_D OUT_D 25 26 27 28 29 30 31 32 33 34 35 36 4.7µ F PVDD 12 11 10 9 8 7 6 5 4 3 2 1 0O A_SEL MCLK 0.033µ F PVDD 0. 68µF 0.1µ F 220µ F 8O 22µH /RESET DVDD 10µ F Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 0.1µF 0.1µ F 1µF 11 0.033 µF www.anpec.com.tw APA3163 Function Description Clock And PLL The APA3163 is a slave device and receives signals from MCLK, SCLK, and LRCLK. The digital audio processor (DAP) provides all sample rates and MCLK rates which defined in the clock control register. The APA3163 checks to verify that SCLK is a particular value of 32fS, 48fS, or 64fS. The DAP only provides a 1×fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. Serial Data Interface Serial data is an input transmitted to SDIN. The PWM outputs are derived from SDIN. Besides, the APA3163 DAP receives left-justified, right-justified, and I2S serial data formats with 16, 20, or 24 bit. PWM Section The APA3163 DAP device is a high power efficiency and high-performance digital audio reproduction. A noise shaper is used to increase dynamic range and SNR in the audio band. The PWM section receives 24bit PCM data from the DAP and outputs two BTL PWM audio output channels. The PWM section has individual channel dc blocking filters that can be enabled and disabled. The low pass filter cutoff frequency is less than 1Hz. Besides, the PWM section includes individual channel de-emphasis filters for 44.1 and 48 kHz and can be enabled and disabled. The adjustable maximum modulation limit of PWM section is from 93.8% to 98.4%. I2C Compatible Serial Control Interface The APA3163 DAP receives commands from a system controller through an I2C serial control slave interface. The serial control interface supports both normal-speed 100kHz and high-speed 400kHz operations without waiting states. As an added feature, even though the MCLK is absent, the interface operates. For status registers, the serial control interface provides both single-byte and multi-byte read and write operations; and for the general control registers, they associated with the PWM. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 12 www.anpec.com.tw APA3163 Function Description (Cont.) Serial Interface Control And Timing I2S Timing I2S timing uses LRCLK to define the data for the left channel and the right channel when the data being transmitted. For the left channel, the LRCLK is low; for the right channel, the LRCLK is high. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. When the LRCLK signal changes state, there is a delay of one bit clock from the time which the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks unused trailing data bit positions. 32 Clks 32 Clks LRCLK (Note Reversed Phase) Left Channel Right Channel SCLK SCLK MSB 24-Bit Mode 23 22 LSB 9 8 5 4 1 MSB 24-Bit Mode 0 23 22 20-Bit Mode 19 18 9 8 5 4 5 4 1 0 1 0 1 0 20-Bit Mode 5 4 1 0 19 18 16-Bit Mode 16-Bit Mode 15 14 LSB 1 0 15 14 Figure 1. I2S 64 fS Format 24 Clks 24 Clks LRCLK (Note Reversed Phase) Left Channel Right Channel SCLK SCLK MSB 24-Bit Mode 23 22 LSB 17 16 9 8 5 4 3 2 1 0 20-Bit Mode 19 18 23 22 17 16 9 8 5 4 13 12 5 4 1 0 1 0 3 2 1 20-Bit Mode 13 12 5 4 1 0 19 18 16-Bit Mode 15 14 LSB MSB 24-Bit Mode 16-Bit Mode 9 8 1 0 15 14 9 8 Figure 2. I2S 48 fS Format 16 Clks LRCLK (Note Reversed Phase) 16Clks Right Channel Left Channel SCLK SCLK MSB 16-Bit Mode 15 14 13 12 11 10 LSB 9 8 5 4 3 2 LSB MSB 16-Bit Mode 1 0 15 14 13 12 11 10 9 8 5 4 3 2 1 Figure 3. I2S 32 fS Format Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 13 www.anpec.com.tw APA3163 Function Description (Cont.) Left-Justified Left-justified (LJ) timing uses LRCLK to define the data for the left channel and the right channel when the data being transmitted. For the left channel, the LRCLK is high; for the right channel, the LRCLK is low. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines when LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions. 32Clks LRCLK 32Clks Right Channel Left Channel SCLK SCLK MSB 24-Bit Mode 23 22 LSB 9 8 5 4 1 MSB 24-Bit Mode 0 23 22 20-Bit Mode 19 18 9 8 5 4 5 4 1 0 1 0 1 0 20-Bit Mode 5 4 1 0 19 18 16-Bit Mode 16-Bit Mode 15 14 LSB 1 0 15 14 Figure 4. Left-Justified 64 fS Format 24Clks LRCLK 24 Clks Left Channel Right Channel SCLK SCLK MSB 24-Bit Mode 23 22 LSB 17 16 9 8 5 4 3 2 1 0 23 22 20-Bit Mode 19 18 17 16 9 8 5 4 13 12 5 4 1 0 9 1 0 3 2 1 20-Bit Mode 13 12 5 4 1 0 19 18 16-Bit Mode 15 14 LSB MSB 24-Bit Mode 16-Bit Mode 9 8 1 0 15 14 8 Figure 5. Left-Justified 48 fS Format 16 Clks LRCLK 16Clks Left Channel Right Channel SCLK SCLK MSB 16-Bit Mode 15 14 13 12 11 10 LSB MSB 16-Bit Mode 9 8 5 4 3 2 1 0 15 14 13 12 11 10 LSB 9 8 5 4 3 2 1 0 Figure 6. Left-Justified 32 fS Format Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 14 www.anpec.com.tw APA3163 Function Description (Cont.) Right-Justified Right-justified (RJ) timing uses LRCLK to define the data for the left channel and the right channel when the data being transmitted. For the left channel, the LRCLK is high; for the right channel, the LRCLK low. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. After LRCLK toggles, for 24bit data, the first bit of data appears on the data 8 bit-clock. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks unused leading data bit positions. 32 Clks LRCLK 32 Clks Right Channel Left Channel SCLK SCLK MSB 24-Bit Mode LSB 23 22 19 18 15 14 1 MSB 24-Bit Mode 0 LSB 23 22 20-Bit Mode 19 18 15 14 1 0 19 18 15 14 1 0 15 14 1 0 20-Bit Mode 19 18 15 14 1 0 16-Bit Mode 16-Bit Mode 15 14 1 0 Figure 7. Right-Justified 64 fS Format 24 Clks LRCLK 24 Clks Right Channel Left Channel SCLK SCLK LS B MSB 24-Bit Mode 23 22 20-Bit Mode 19 18 15 14 19 18 15 14 16-Bit Mode 15 14 6 6 6 5 2 5 2 5 2 1 1 1 LS B MSB 24-Bit Mode 0 23 22 20-Bit Mode 0 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 16-Bit Mode 0 Figure 8. Right-Justified 48 fS Format 16 Clks LRCLK 16Clks Left Channel Right Channel SCLK SCLK MSB 16-Bit Mode 15 14 13 12 11 10 LSB MSB 16-Bit Mode 9 8 5 4 3 2 1 0 15 14 13 12 11 10 LSB 9 8 5 4 3 2 1 0 Figure 9. Right-Justified 32 fS Format Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 15 www.anpec.com.tw APA3163 Function Description (Cont.) I2C Serial Control Interface The APA3163 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol. Besides, it provides both 100kHz and 400kHz data transfer rates to single and multiple bytes write and read operations. This is a slave only device, and it doesn’t support a multi-master bus environment or wait state insertion. The function of the control interface is to read device status and to program the registers of the device. The DAP supports the standard-mode I2C bus operation (100kHz maximum) and the fast I2C bus operation (400kHz maximum). Without I2C wait cycles, the DAP performs I2C operations. General I2C Operation The I2C bus uses SDA (data) and SCL (clock) to communicate between integrated circuits in a system. Data is transferred on the bus serially one bit at a time. With the most significant bit (MSB) transferred first, the address and data can be transferred in byte (8bit) format. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the SDA when the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the clock. These conditions are shown in Figure 10. The master generates the 7bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The APA3163 holds SDA low during the acknowledge clock to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and SCL signals to set the high level for the bus. SDA 7-Bit Slave Address R/ W A 7 6 5 4 3 2 1 0 8-Bit Register Address (N) A 7 6 5 4 3 2 1 0 8-Bit Register Data for Address (N) 7 6 5 4 3 2 1 0 A 8-Bit Register Data for Address (N) A 7 6 5 4 3 2 1 0 SCL Start Stop Figure 10. Typical I2C Sequence There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 10. The 7bit address for APA3163 is 0011 010 (0x34). APA3163 address can be changed from 0x34 to 0x38 by writing 0x38 to device address register 0xF9. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 16 www.anpec.com.tw APA3163 Function Description (Cont.) Single- and Multiple-Byte Transfers The serial control interface supports single-byte and multiple-byte (R/W) operations for sub-addresses 0x00 to 0x1F. However, for the sub-addresses 0x20 to 0xFF, the serial control interface supports only multiple-byte read/write operations (in multiples of 4 bytes). During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the sub-address assigned, as long as the master device continues to respond with acknowledges. If a particular sub-address does not contain 32 bits, the unused bits are read as logic 0. During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes that are required for each specific sub-address. Supplying a sub-address for each sub-address transaction is referred to as random I2C addressing. The APA3163 also supports sequential I2C addressing. For write transactions, if a sub-address is issued and followed by data for that sub-address and the 15 sub-addresses that follow, a sequential I2C write transaction has taken place, and the data for all 16 sub-addresses is successfully received by the APA3163. For I2C sequential write transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many sub-addresses are written. As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last sub-address is discarded. However, if all other data written is accepted, only the incomplete data is discarded. Single-Byte Write As shown in Figure 11, a single-byte data write transfer begins with the master device transmitting a start condition followed by the I2C device address and the R/W bit. The R/W bit determines the direction of the data transfer. For a write data transfer, the R/W bit will be a 0. After receiving the correct I2C device address and the R/W bit, the DAP responds with an acknowledge bit. And then, the master transmits the address byte or bytes corresponding to the APA3163 internal memory address being accessed. After receiving the address byte, the APA3163 responds with an acknowledge bit again. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the APA3163 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer. Start Condition Acknowledge Acknowledge Acknowledge A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK I2C Device Address and Read/ Write Bit Sub-address Data Byte Stop Condition Figure 11. Single-Byte Write Transfer Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 17 www.anpec.com.tw APA3163 Function Description (Cont.) Multiple-Byte Write A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the DAP as shown in Figure 12. After receiving each data byte, the APA3163 responds with an acknowledge bit. Start Condition Acknowledge A6 A5 A1 A0 R/W ACK A7 A6 I2C Device Address and Read/ Write Bit A2 A1 Acknowledge Acknowledge A0 ACK D7 D0 ACK D7 Sub-address First Data Byte Acknowledge Acknowledge D0 ACK D7 Other Data Bytes D0 ACK Last Data Byte Stop Condition Figure 12. Multiple-Byte Write Transfer Single-Byte Read As shown in Figure 13, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the R/W bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the R/W bit becomes a 0. After receiving the APA3163 address and the read/write bit, APA3163 responds with an acknowledge bit. Besides, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the APA3163 address and the read/write bit again. This time the read/ write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the APA3163 again responds with an acknowledge bit. And then, the APA3163 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer. Start Condition Acknowledge A6 A5 Acknowledge A1 A0 R/W ACK A7 A6 I2C Device Address and Read/ Write Bit Acknowledge A1 A0 ACK Sub-address A6 A5 Repeat Start Condition Not Acknowledge A1 A0 R/W ACK D7 D6 I2C Device Address and Read/ Write Bit D1 D0 ACK Stop Condition Data Byte Figure 13. Single-Byte Read Transfer Multiple-Byte Read A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the APA3163 to the master device as shown in Figure 14. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. Start Condition Repeat Start Condition Acknowledge Acknowledge A6 A0 R/WACK A7 A6 I2C Device Address and Read/ Write Bit A1 A0 ACK A6 Acknowledge A0 R/WACK D7 I2C Device Address and Read/ Write Bit Subaddress Acknowledge Acknowledge Not Acknowledge D0 ACK D7 First Data Byte D0 ACK D7 Other Data Bytes D0 ACK Last Data Byte Stop Condition Figure 14. Multiple-Byte Read Transfer Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 18 www.anpec.com.tw APA3163 Function Description (Cont.) Dynamic Range Control (DRC) The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the left/ right channels. The DRC input/output diagram is shown in Figure 15. Vin Limit Level Time Limit Level Figure 15. Dynamic Range Control Attack Time Gain Release Time VOUT Limit Level Time A E B C D Limit Level F Figure 16. DRC Structure Biquad Structure All biquads use a 2nd order IIR filter structure as shown below. Each biquad has 3 coefficients on the direct path (b0, b1, b2) and 2 coefficients on feedback path (a1 and a2) which is shown in the diagram. b0 x(n) Magnitude Trunction Σ y(n) Z-1 b1 a1 Z-1 Z-1 b2 a2 Z-1 Figure 17. Biquad Filter Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 19 www.anpec.com.tw APA3163 Function Description (Cont.) 26Bit 3.23 Number Format All mixer gain coefficients are 26 bit coefficients and use a 3.23 number format. Numbers formatted as 3.23 numbers means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point. This is shown in Figure 18. 2-23 Bit 2-5 Bit 2-1 Bit 20 Bit 21 Bit Sign Bit S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx Figure 18. 3.23 Format The decimal value of a 3.23 format number can be found by following the weighting and is shown in Figure 18. If the MSB is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the MSB is a logic 1, and then the number is a negative number. In this case, every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 19 applied to obtain the magnitude of the negative number. 21 Bit 20 Bit 2-1 Bit 2-4 Bit 2-23 Bit (1 or 0) x21+ (1 or 0) x20+ (1 or 0) x2 -1+ (1 or 0) x2-4+ (1 or 0) x2-23 Figure 19. Conversion Weighting Facroes 3.23 Format to Floating Point Gain coefficients, entered via the I2C bus, must be entered as 32 bit binary numbers. The format of the 32 bit number (4 byte or 8 digit hexadecimal number) is shown in Figure 20. Sign Bit Integer Digit 1 u u u u Coefficient digit 8 u u S x Coefficient digit 7 Fraction Digit 1 x x x x Coefficient digit 6 Fraction Digit 2 x x x x Coefficient digit 5 Fraction Digit 3 x x x x Coefficient digit 4 Fraction Digit 4 x x x x Coefficient digit 3 Fraction Digit 5 x x x x Coefficient digit 2 Fraction Digit 6 x x x x 0 Coefficient digit 1 Figure 20. Alignment of 3.23 Coefficient in 32Bit I2C Word Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 20 www.anpec.com.tw APA3163 Function Description (Cont.) Sample Calculation for 3.23 Format dB Linear Decimal Hex (3.23 Format) 0 1 8388608 00800000 5 1.7782794 14917288 00E39EA8 -5 0.5623413 4717260 0047FACC X L = 10(X/20) D = 8388608 × L H = dec2hex (D, 8) dB Linear Decimal Hex (9.17 Format) 0 1 131072 00020000 5 1.7782794 233082.6 00038E7A -5 0.5623413 X L = 10 Sample Calculation for 9.17 Format (X/20) 73707.2 00011FEB D = 131072 × L H = dec2hex (D, 8) Recommended Use Model Normal Operation Intialization Power Down Shutdown AVDD/DVDD 3V 3V tDL-VDDH tVDDH-DL SD tPOR I2S MCLK LRCLK SCLK SDIN I2C SCL SDA tPOR Clock Errors and Rate Changes OK Stable and Valid Clocks texitSD Trim tautodetect DAP Config Other Config Stable and Valid Clocks tautodetect Volume and Mute Commands Reconfigure DAP After Shutdown Reconfigure DAP After Shutdown Exit SD tenterSD Enter SD tRL-DV tDV-RH tRH-I2C RST tVDD-PVCCL PVDD/AVCC tRL-PVCCH tPVCCH-I2C tPVCCL-VDDH 10V 7.5V 10V 7.5V Figure 21. Recommended Command Sequence Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 21 www.anpec.com.tw APA3163 Function Description (Cont.) Recommended Use Model (Cont.) Parameter APA3163 Description tVDDH-DL Time digital inputs must remain low after AVDD/DVDD goes above 3V tDL-VDDH Time digital inputs must be low before AVDD/DVDD goes below 3V tVDDH-PVDDL Time PVDD/AVCC remains below 7.5V after AVDD/DVDD goes above 3V tPVDDL-VDDH Time PVDD/AVCC must be below 7.5V before AVDD/DVDD goes below 3V tPVDDH-I2C Time PVDD/AVCC must be above 10V before I2C commands may address device tRL-PVDDH Time PVDD/AVCC must remain above 10V after RST goes low Unit Min. Typ. Max. 0 - - 0 - - 100 - - 0 - - 10 - - 2 - - tRH-I2C Time RESET must be high before I2C commands may address device 13.5 - - tDV-RH Time digital inputs must be valid (driven as recommended) before RST goes high 100 - - tRL-DV Time digital inputs must remain valid (driven as recommended) after RST goes low 2 - - tautodetect Auto-detect completion wait time (given stable and valid clocks) before issuing further commands 50 - - texitSD Exit shutdown wait time before issuing further commands to device (t start given by 1+1.3 x register 0x1A) tstart - - tenterSD Enter shutdown wait time before issuing further commands to device (t stop given 1+1.3 x by register 0x1A) tstop - - tPOR Power-on-reset wait time after 1st trim following AVDD/DVDD power-up (tstart given 240 + by register 0x1A) (does not apply to trim commands following subsequent resets) 1.3 x tstart - - µs ms µs ms Sudden Power Loss (BD) AVDD/DVDD 3V tDL-VDDH SD IS MCLK LRCLK SCLK SDIN I 2C SCL SDA 2 tPL-HL RST tRL-PVCCH tPVCCL-VDDH PVDD/AVCC 10V 7.5V Figure 22. Power Loss Sequence Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 22 www.anpec.com.tw APA3163 Function Description (Cont.) Recommended Use Model (Cont.) Parameter APA3163 Description Unit Min. Typ. Max. Time digital inputs must remain valid (driven as recommended) after RST goes low 2 - - tDL-VDDH Time digital inputs must be low before AVDD/DVDD goes below 3V 0 - - tRL-PVDDH Time PVDD/AVCC must remain above 10V after RST goes low 2 - - tPVDDL-VDDH Time PVDD/AVCC must be below 7.5V before AVDD/DVDD goes below 3V 0 - - tRL-DV µs Recommended Command Sequences The DAP has two groups of commands. One set is for configuration and is intended for use only during initialization. The other set has built-in click and pop protection and may be used during normal operation while audio is streaming. The following supported command sequences illustrate how to initialize, operate, and shutdown the device. Initialization Sequence Use the following sequence to power-up and initialize the device: 1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3V. 2. Initialize digital inputs and PVDD supply as follows: • Drive RST=0, SD=1, and other digital inputs to their desired state while ensuring that all are never more than 2.5V above AVDD/DVDD. Provide stable and valid I2S clocks (MCLK, LRCLK, and SCLK). Wait at least 100µs, drive RST=1, and wait at least another 13.5ms. • Ramp up PVDD to at least 8V while ensuring that it remains below 6V for at least 100µs after AVDD/DVDD reaches 3V. Then wait at least another 10µs. 3. Configure the DAP via I2C (see Users’s Guide for typical values): biquads (0x29-36)DRC parameters (0x3A-3C, 0x40-42, and 0x46) Bank select (0x50). 4. Configure remaining registers. 5. Exit shutdown (sequence defined below). Normal Operation The following are the only events supported during normal operation: (a) Writes to master/channel volume registers (b) Writes to soft mute register (c) Enter and exit shutdown (sequence defined below) (d) Clock errors and rate changes Note: Events (c) and (d) are not supported for 240ms+1.3xt0 0after trim following AVDD/DVDD power up ramp (where Tstart is specified by register 0x1A). Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 23 www.anpec.com.tw APA3163 Function Description (Cont.) Shutdown Sequence Enter: 1. Ensure I2S clocks have been stable and valid for at least 50ms. 2. Write 0x40 to register 0x05. 3. Wait at least 1ms+1.3xtstop (where tstop is specified by register 0x1A). 4. Once in shutdown, stable clocks are not required while device remains idle. 5. If desired, reconfigure by ensuring that clocks have been stable and valid for at least 50ms before returning to step 4 of initialization sequence. Exit: 1. Ensure I2S clocks have been stable and valid for at least 50ms. 2. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240ms after trim following AVDD/DVDD powerup ramp). 3. Wait at least 1ms+1.3xtstart (where tstart is specified by register 0x1A). 4. Proceed with normal operation. Power-down Sequence Use the following sequence to power-down the device and its supplies: 1. If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss, assert SD=0 and wait at least 2ms. 2. Assert RST=0. 3. Drive digital inputs low and ramp down PVDD supply as follows: • Drive all digital inputs low after RST has been low for at least 2µs. • Ramp down PVDD while ensuring that it remains above 8V until RST has been low for at least 2µs. 4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVDD is below 6V and that it is never more than 2.5V below the digital inputs. Table 1. Serial Control Interface Register Summary Sub Address Register Name No. of Bytes Contents Initialization Values A u indicates unused bits. 0x00 Clock control register 1 Description shown in subsequent section 0x6C 0x01 Device ID register 1 Description shown in subsequent section 0x00 0x02 Error status register 1 Description shown in subsequent section 0x00 0x03 System control register 1 1 Description shown in subsequent section 0x80 0x04 Serial data interface 1 Description shown in subsequent section 0x05 1 Description shown in subsequent section 0x40 0x05 0x06 Soft mute register 1 Description shown in subsequent section 0x00 0x07 Master volume 1 Description shown in subsequent section 0xFF (mute) 0x08 Channel 1 vol 1 Description shown in subsequent section 0x30 (0dB) 0x09 Channel 2 vol 1 Description shown in subsequent section 0x30 (0dB) 0x0A Fine master volume 1 Description shown in subsequent section 0x00 (0dB) Reserved (1) 0x0B - 0X0D 0x0E Volume configuration register Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 1 Description shown in subsequent section 24 0x91 www.anpec.com.tw APA3163 Function Description (Cont.) Table 1. Serial Control Interface Register Summary (Cont.) Sub Address Register Name 0x0F 0x10 Modulation limit register 0x15-0x19 0x1A Contents 1 Reserved 1 Description shown in subsequent section 1 Reserved Description shown in subsequent section 1 Reserved (1) 0x1C 1 Reserved (1) 0x1D–0x1F 1 Reserved (1) 4 Description shown in subsequent section 0x21-0x24 0x25 4 PWM MUX register 0x26-0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E ch1_bq [0] ch1_bq [1] ch1_bq [2] ch1_bq [3] ch1_bq [4] ch1_bq [5] Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 Reserved 4 Description shown in subsequent section Reserved (1) 20 20 20 20 20 0x0A 0x 0089 777A (1) 4 20 0x02 (1) 1 Input MUX register Initialization Values (1) 0x1B 0x20 Start/stop period register No. of Bytes 0x0102 1345 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 25 www.anpec.com.tw APA3163 Function Description (Cont.) Table 1. Serial Control Interface Register Summary (Cont.) Sub Address Register Name No. of Bytes 0x2E ch1_bq [5] 20 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 ch1_bq [6] ch2_bq [0] ch2_bq [1] ch2_bq [2] ch2_bq [3] ch2_bq [4] ch2_bq [5] Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 20 20 20 20 20 20 20 Contents Initialization Values u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 26 www.anpec.com.tw APA3163 Function Description (Cont.) Table 1. Serial Control Interface Register Summary (Cont.) Sub Address Register Name No. of Bytes 0x35 ch2_bq [5] 20 0x36 ch2_bq [6] 20 0x37~ 0x45 0x46 4 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 u [31:26], a2 [25:0] 0x0000 0000 (2) Description shown in subsequent section Reserved 0x0000 0000 (2) Reserved (2) EQ Control Initialization Values u [31:26], a2 [25:0] Reserved DRC Control 0x47-0x4F 0x50 Contents 0x0F70 8000 Reserved (2) 0x51-0x5F 0x60 DRC attack threshold 4 u [31:24], attackTh [23:0] 0x0003 2D64 0x61 DRC release threshold 4 u [31:24], attackTh [23:0] 0x0002 FFE4 0x62 DRC WinIdx 1 Description shown in subsequent section 0x63-0xF8 0xF9 Reserved Update Device Address 0xFA-0xFF 4 0x01 (2) u [31:8], New Dev Id[7:0] (New Dev Id=0x38) 0x00000034 Reserved (2) Note (1): Reserved register should not be accessed. Note (2): Reserved register should not be accessed. Note (3): “ae” stands for α of energy filter, “aa” stands for α of attack filter and “ad” stands for α of decay filter and 1-α = ω. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 27 www.anpec.com.tw APA3163 Function Description (Cont.) Clock Control Register (0x00) The clocks and data rates are automatically determined by the APA3163. The clock control register contains the autodetected clock status. Bits D7-D5 reflect the sample rate. Bits D4-D2 reflect the MCLK frequency. Table 2. Clock Control Register (0x00) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 0 0 - - - - - fS=32kHz sample rate 0 0 1 - - - - - fS=88.2kHz/96kHz sample rate 0 1 0 - - - - - fS=176.4kHz/192kHz sample rate 0 1 1 - - - - - fS=44.1/48kHz sample rate (5) - - - 0 0 0 - - MCLK frequency=64xfS (6) - - - 0 0 1 - - MCLK frequency=128xfS (6) - - - 0 1 0 - - MCLK frequency=192xfS (7) - - - 0 1 1 - - MCLK frequency=256xfS (5) (8) - - - 1 0 0 - - MCLK frequency=384xfS - - - 1 0 1 - - MCLK frequency=512xfS - - - 1 1 0 - - Reserved (4) - - - 1 1 1 - - Reserved (4) - - - - - - 0 - Reserved (4) - - - - - - - 0 Reserved (4) Note (4): Reserved registers should not be accessed. Note (5): Italic is default. Note (6): Only available for 44.1kHz and 48kHz rates. Note (7): Rate only available for 32/44.1/48kHz sample rates. Note (8): Not available at 8kHz. Device Id Register (0x01) The device ID register contains the ID code for the firmware revision. Table 3. General Status Register (0x01) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION X - - - - - - - Reserved - 0 0 0 0 0 0 0 Identification code Note: Italic is default. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 28 www.anpec.com.tw APA3163 Function Description (Cont.) Error Status Register (0x02) The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors. Error Definitions: MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing. SCLK Error: The number of SCLKs per LRCLK is changing. LRCLK Error: LRCLK frequency is changing. Table 4. Error Status Register (0x02) D7 D6 D5 D4 D3 D2 D1 D0 1 - - - - - - - MCLK error - 1 - - - - - - PLL auto clock error - - 1 - - - - - SCLK error - - - 1 - - - - LRCLK error - - - - 1 - - - Reserved - - - - - 1 - - Reserved - - - - - - 1 - Over temperature warning (sets around 145OC) POR error, OCP, thermal shutdown error 0 0 0 0 0 0 0 0 No errors FUNCTION Note: Italic is default. System Control Register 1 (0x03) The system control register 1 has several functions: Bit D7: If 0, the dc-blocking filter for each channel is disabled. If 1, the dc-blocking filter ( -3dB cutoff < 1Hz ) for each channel is enabled (default). Bit D5: If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes same time as volume ramp defined in reg 0x0E. If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single step volume ramp Bits D1-D0: Select de-emphasis. Table 5. System Control Register 1 (0x03) D7 D6 D5 D4 D3 D2 D1 D0 0 - - - - - - - PWM high-pass (dc blocking) disenabled FUNCTION 1 - - - - - - - PWM high-pass (dc blocking) enabled - 0 - - - - - - Reserved - - 0 - - - - - Reserved - - 0 - - - - - Reserved - - - 0 - - - - Reserved - - - - 0 - - - Reserved - - - - - 0 - - Reserved - - - - - - 0 0 No de-emphasis - - - - - - 0 1 Reserved - - - - - - 1 0 De-emphasis for fS=44.1kHz - - - - - - 1 1 De-emphasis for fS=48kHz Note: Italic is default. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 29 www.anpec.com.tw APA3163 Function Description (Cont.) Serial Data Interface Register (0x04) As shown in Table 6, the APA3163 supports 9 serial data modes. The default is 24bit, I2S mode. Table 6. Serial Data Interface Control Register (0x04) Format D7 D6 D5 D4 D3 D2 D1 D0 Word Length Receive Serial Data Interface Format 0 0 0 0 0 0 0 0 16 Right-justified 0 0 0 0 0 0 0 1 20 Right-justified 0 0 0 0 0 0 1 0 24 Right-justified 0 0 0 0 0 0 1 1 16 I2S 0 0 0 0 0 1 0 0 20 I2S 0 0 0 0 0 1 0 1 24 I2S 0 0 0 0 0 1 1 0 16 Left-justified 0 0 0 0 0 1 1 1 20 Left-justified 0 0 0 0 1 0 0 0 24 Left-justified 0 0 0 0 1 - 1 0 - Reserved 0 0 0 0 1 - - 1 - Reserved 0 0 0 0 1 1 1 1 - Reserved Note: Italic is default. System Control Register 2 (0x05) When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs are shut down (hard mute). Table 7. System Control Register 2 (0x05) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 - - - - - - - Reserved - 1 - - - - - - Enter all channel shut down (hard mute) - 0 - - - - - - Exit all channel shut down (Normal operation) - - 0 0 0 0 0 0 Reserved Note: Italic is default. Soft Mute Register (0x06) Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute). Table 8. Soft Mute Register (0x06) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION - - - - - - - 1 Soft mute channel 1 - - - - - - - 0 Soft un-mute channel 1 - - - - - - 1 - Soft mute channel 2 - - - - - - 0 - Soft un-mute channel 2 0 0 0 0 0 0 - - Reserved Note: Italic is default. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 30 www.anpec.com.tw APA3163 Function Description (Cont.) Volume Registers (0x07, 0x08, 0x09) Step size is 0.5 dB. Master volume - 0x07 (default is mute) Channel-1 volume - 0x08 (default is 0 dB) Channel-2 volume - 0x09 (default is 0 dB) Table 9. Volume Registers (0x07, 0x08, 0x09) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 0 0 0 0 0 0 0 24dB 0 0 1 1 0 0 0 0 0dB 1 1 0 0 1 1 0 1 -78.5dB 1 1 0 0 1 1 1 0 -79.0dB 1 1 0 0 1 1 1 1 Values between 0xCF and 0xFE are Reserved 1 1 1 1 1 1 1 1 MUTE (default for master volume) Note: Italic is default. Master Fine Volume Register (0x0A) This register can be used to provide precision tuning of master volume. Table 10. Master Fine Volume Register (0x0A) D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - 0 0 0dB - - - - - - 0 1 0.125dB - - - - - - 1 0 0.25dB - - - - - - 1 1 0.345dB 1 - - - - - - - Write enable bit - - - - - - - - Ignore write to register 0x0A FUNCTION Note: Italic is default. Volume Configuration Register (0x0E) Bits Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the D2-D0: number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of the I2S data as follows. Sample Rate (kHz) Approximate Ramp Rate 8/16/32 125µs/step 11.025/22.05/44.1 90.7µs/step 12/24/48 83.3µs/step Table 11. Volume Control Register (0x0E) D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 - - - Reserved - - - - - 0 0 0 Volume slew 512 steps (43ms volume ramp time at 48kHz) Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 FUNCTION 31 www.anpec.com.tw APA3163 Function Description (Cont.) Volume Configuration Register (0x0E) (Cont.) Table 11. Volume Control Register (0x0E) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION - - - - - 0 0 1 Volume slew 1024 steps (85ms volume ramp time at 48kHz) - - - - - 0 1 0 Volume slew 2048 steps (171ms volume ramp time at 48kHz) - - - - - 0 1 1 Volume slew 256 steps (21ms volume ramp time at 48kHz) - - - - - 1 x x Reserved Note: Italic is default. Modulation Limit Register (0x10) Table 12. Modulation Limit Register (0x10) D7 D6 D5 D4 D3 D2 D1 D0 MODULATION LIMIT - - - - - 0 0 0 Reserved - - - - - 0 0 1 98.4% - - - - - 0 1 0 97.7% - - - - - 0 1 1 96.9% - - - - - 1 0 0 96.1% - - - - - 1 0 1 95.3% - - - - - 1 1 0 94.5% - - - - - 1 1 1 93.8% 0 0 0 0 0 - - - Reserved Note: Italic is default. Start/Stop Period Register (0x1A) This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down command or change in the SD state. This helps reduce pops and clicks at start-up and shutdown. The times are only approximate and vary depending on device activity level and I2S clock stability. Table 13. Start/Stop Period Register (0x1A) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 - - - - - Reserved - - - 0 0 - - - No 50% duty cycle start/stop period - - - 0 1 0 0 0 16.5ms 50% duty cycle start/stop period - - - 0 1 0 0 1 23.9ms 50% duty cycle start/stop period - - - 0 1 0 1 0 31.4ms 50% duty cycle start/stop period - - - 0 1 0 1 1 40.4ms 50% duty cycle start/stop period - - - 0 1 1 0 0 53.9ms 50% duty cycle start/stop period - - - 0 1 1 0 1 70.3ms 50% duty cycle start/stop period - - - 0 1 1 1 0 94.2ms 50% duty cycle start/stop period - - - 0 1 1 1 1 125.7ms 50% duty cycle start/stop period Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 FUNCTION 32 www.anpec.com.tw APA3163 Function Description (Cont.) Start/Stop Period Register (0x1A) (Cont.) Table 13. Start/Stop Period Register (0x1A) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION - - - 1 0 0 0 0 164.6ms 50% duty cycle start/stop period - - - 1 0 0 0 1 239.4ms 50% duty cycle start/stop period - - - 1 0 0 1 0 314.2ms 50% duty cycle start/stop period - - - 1 0 0 1 1 403.9ms 50% duty cycle start/stop period - - - 1 0 1 0 0 538.6ms 50% duty cycle start/stop period - - - 1 0 1 0 1 703.4ms 50% duty cycle start/stop period - - - 1 0 1 1 0 942.5ms 50% duty cycle start/stop period - - - 1 0 1 1 1 1256.6ms 50% duty cycle start/stop period - - - 1 1 0 0 0 1728.1ms 50% duty cycle start/stop period - - - 1 1 0 0 1 2513.6ms 50% duty cycle start/stop period - - - 1 1 0 1 0 3299.1ms 50% duty cycle start/stop period - - - 1 1 0 1 1 4241.7ms 50% duty cycle start/stop period - - - 1 1 1 0 0 5655.6ms 50% duty cycle start/stop period - - - 1 1 1 0 1 7383.7ms 50% duty cycle start/stop period - - - 1 1 1 1 0 9897.3ms 50% duty cycle start/stop period - - - 1 1 1 1 0 13196.4ms 50% duty cycle start/stop period Note: Italic is default. Input Multiplexer Register (0x20) This register controls the modulation scheme (BD mode) as well as the routing of I2S audio to the internal channels. Table 14. Input Multiplexer Register (0x20) D31 D30 D29 D28 D27 D26 D25 D24 0 0 0 0 0 0 0 0 D23 D22 D21 D20 D19 D18 D17 D16 0 - - - - - - - Reserved 1 - - - - - - - Channel 1 BD mode - 0 0 0 - - - - SDIN-L to Channel 1 - 0 0 1 - - - - SDIN-R to Channel 1 - 0 1 0 - - - - Reserved - 0 1 1 - - - - Reserved - 1 0 0 - - - - Reserved - 1 0 1 - - - - Reserved - 1 1 0 - - - - Ground (0) to channel 1 - 1 1 1 - - - - Reserved - - - - 0 - - - Reserved - - - - 1 - - - Channel-2 BD mode Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 FUNCTION Reserved FUNCTION 33 www.anpec.com.tw APA3163 Function Description (Cont.) Input Multiplexer Register (0x20) (Cont.) Table 14. Input Multiplexer Register (0x20) D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION - - - - - 0 0 0 SDIN-L to Channel 2 - - - - - 0 0 1 SDIN-R to Channel 2 - - - - - 0 1 0 Reserved - - - - - 0 1 1 Reserved - - - - - 1 0 0 Reserved - - - - - 1 0 1 Reserved - - - - - 1 1 0 Ground (0) to channel 2 - - - - - 1 1 1 Reserved D15 D14 D13 D12 D11 D10 D9 D8 0 1 1 1 0 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 0 0 1 0 FUNCTION Reserved FUNCTION Reserved Note: Italic is default. Pwm Output Mux Register (0x25) This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be output to any external output pin. Bits D21-D20: Selects which PWM channel is output to OUT_A Bits D17-D16: Selects which PWM channel is output to OUT_B Bits D13-D12: Selects which PWM channel is output to OUT_C Bits D09-D08: Selects which PWM channel is output to OUT_D Note that channels are enclosed so that channel 1=0x00, channel 2=0x01, channel 1=0x02, and channel 2=0x03. Table 15. PWM Output Mux Register (0x25) D31 D30 D29 D28 D27 D26 D25 D24 0 0 0 0 0 0 0 0 D23 D22 D21 D20 D19 D18 D17 D16 0 0 - - - - - - Reserved - - 0 0 - - - - Multiplex channel 1 to OUT_A - - 0 1 - - - - Multiplex channel 2 to OUT_A - - 1 0 - - - - Multiplex channel 1 to OUT_A - - 1 1 - - - - Multiplex channel 2 to OUT_A - - - - 0 0 - - Reserved - - - - - - 0 0 Multiplex channel 1 to OUT_B - - - - - - 0 1 Multiplex channel 2 to OUT_B - - - - - - 1 0 Multiplex channel 1 to OUT_B Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 FUNCTION Reserved FUNCTION 34 www.anpec.com.tw APA3163 Function Description (Cont.) Pwm Output Mux Register (0x25) (Cont.) Table 15. PWM Output Mux Register (0x25) D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION - - - - - - 1 1 D15 D14 D13 D12 D11 D10 D9 D8 0 0 - - - - - - Reserved - - 0 0 - - - - Multiplex channel 1 to OUT_C - - 0 1 - - - - Multiplex channel 2 to OUT_C - - 1 0 - - - - Multiplex channel 1 to OUT_C - - 1 1 - - - - Multiplex channel 2 to OUT_C - - - - 0 0 - - Reserved - - - - - - 0 0 Multiplex channel 1 to OUT_D - - - - - - 0 1 Multiplex channel 2 to OUT_D - - - - - - 1 0 Multiplex channel 1 to OUT_D - - - - - - 1 1 Multiplex channel 2 to OUT_D D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 1 Multiplex channel 2 to OUT_B FUNCTION FUNCTION Reserved Note: Italic is default. DRC Control (0x46) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION 0 0 0 0 0 0 0 0 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - 0 DRC turned OFF - - - - - - - 1 DRC turned ON 0 0 0 0 0 0 0 - Reserved Reserved FUNCTION Reserved FUNCTION Reserved FUNCTION Note: Italic is default. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 35 www.anpec.com.tw APA3163 Function Description (Cont.) Error Reporting Any fault resulting in device shutdown is signaled by the ERROR pin going low (see Table 18). A sticky version of this pin is available on D1 of register 0X02. Table 16. ERROR Output States Fault Description Error 0 Over-Current (OC) or Under-Voltage (UVP) or Over-Temperature (OTP) 1 No faults (normal operation) Over-Current (OC) Protection With Current-Limiting The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The detector outputs are closely monitored by two protection systems. The first protection system controls the power stage in order to prevent the output current further increasing, i.e., it performs a cycle-by-cycle current-limiting function, rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load impedance drops. If the high-current condition situation persists, i.e., the power stage is being overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. The device returns to normal operation once the fault condition (i.e., a short circuit on the output) is removed. Current limiting and overcurrent protection are not independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are shut down. Over-Temperature Protection The APA3163 has over-temperatureprotection system. If the device junction temperature exceeds 150°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The APA3163 recovers automatically once the temperature drops approximately 30°. Under-Voltage Protection (UVP) and Power-On-Reset (POR) The UVP and POR circuits of the APA3163 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the PVDD and AVDD supply voltages reach 7.6V and 2.7V, respectively. Although PVDD and AVDD are independently monitored, a supply voltage drop below the UVP threshold on AVDD or either PVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and ERROR being asserted low. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 36 www.anpec.com.tw APA3163 Application Information Layout Recommendation AVDD Power stage block, please use high voltage -bearing component . 10kO 470O 0.047µ F 4700 pF 0.047µ F 470O Output & VDD traces width =40mil, should be as short as they can, and symmetric. JP1 2200 pF 1µ F 4700 pF 0.033 µF NC NC PLL_LF AVSS TM NC NC 22.1kO GDRE G ABS PVDD_A PVDD_A OUT_A PVDD AVDD 10µ F 0.1µ F A_SEL MCLK 0.1µF AV DD /PDN LRCK SCLK SDIN SDA SCL AVDD /ERROR 10kO MCLK 18.2kO TP1 TP2 10kO 1V8_DV /SD LRCLK SCLK SDIN SDA SCL 13 14 15 16 17 18 19 20 21 22 23 24 0.68µ F 48 47 46 45 44 43 42 41 40 39 38 37 PGND_AB PGND_AB OUT_B PVDD_B PVDD_B BBS CBS PVDD_C PVDD_C OUT_C PGND_CD PGND_CD 8O 22µ H 0. 033µF 0. 033µF 0.1µF PVDD 0.1µF 22µ H 0.68µ F /RST TP3 DVDD DVSS GND AGND DVREG GDREG DBS PVDD_D PVDD_D OUT_D 25 26 27 28 29 30 31 32 33 34 35 36 4.7µ F 0.68µ F 220µF 12 11 10 9 8 7 6 5 4 3 2 1 0O 0.1µF 22µ H 0.68µ F 0.1µF 8O 220 µF 22µ H /RESET DVDD 10µF AVDD cap. & DVDD cap. should be close to the chip . PVDD 0.1µF 1µ F 0.1µ F Thermal pad should be soldered on ground plane of the PCB . Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 37 0.033µ F PVDD cap. and bootstrap cap . should be close to the chip . www.anpec.com.tw APA3163 Application Information(Cont.) Layout Recommendation 5.5mm Via diameter =0.3mm X16 1.7mm 0.28mm 5.0mm 0.5mm Exposed for thermal PAD connected Ground plane for ThermalPAD TQFP7X7-48 Land Pattern Recommendation Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 38 www.anpec.com.tw APA3163 Application Information(Cont.) Layout Recommendation PCB Referance (Top Layer) Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 39 www.anpec.com.tw APA3163 Application Information(Cont.) Layout Recommendation PCB Referance (Bottom Layer) Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 40 www.anpec.com.tw APA3163 Package Information TQFP7x7-48P D 0.25 E E2 EXPOSED PAD E1 c A1 D2 A A2 D1 L b S Y M B O L 0 GAUGE PLANE SEATING PLANE e TQFP7x7-48P MILLIMETERS MIN. INCHES MIN. MAX. A MAX. 0.047 1.20 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 0.011 b 0.17 0.27 0.007 c 0.09 0.20 0.004 0.008 D 8.80 9.20 0.346 0.362 D1 6.90 7.10 0.272 0.280 D2 3.00 5.50 0.118 0.177 E 8.80 9.20 0.346 0.362 E1 6.90 7.10 0.272 0.280 E2 3.00 5.50 0.118 0.177 e L 0.50 BSC 0.020 BSC 0.45 0.75 0.018 0.030 0o 7o 0o 7o Note : 1. Followed from JEDEC MS-026 ABC. 2. Dimension "D1" and "E1" do not include mold protrusions. Allowable protrusions is 0.25 mm per side. "D1" and "E1" are maximun plasticbody size dimensions including mold mismatch. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 41 www.anpec.com.tw APA3163 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TQFP7x7-48P A H T1 C d D W E1 F 330.0±2.00 50 MIN. 16.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.5±0.10 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 9.4±0.20 9.4±0.20 1.8±0.20 4.0±0.10 12.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity TQFP7x7-48P Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 42 www.anpec.com.tw APA3163 Taping Direction Information TQFP7x7-48P USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 43 www.anpec.com.tw APA3163 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 44 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APA3163 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2013 45 www.anpec.com.tw