Low Voltage Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SOT-23 ADM6821/ADM6822/ADM6823/ADM6824/ADM6825 FEATURES FUNCTIONAL BLOCK DIAGRAM Precision low voltage monitoring 9 reset threshold options: 1.58 V to 4.63 V 140 ms (min) reset timeout Watchdog timer with 1.6 sec timeout Manual reset input Reset output stages Push-pull active-low Open-drain active-low Push-pull active-high Low power consumption (7 μA) Guaranteed reset output valid to VCC = 1 V Power supply glitch immunity Specified from −40°C to +125°C 5-lead SOT-23 package ADM6823 VCC VCC RESET GENERATOR VREF MR RESET DEBOUNCE GND 04535-001 WATCHDOG DETECTOR WDI Figure 1. APPLICATIONS Microprocessor systems Computers Controllers Intelligent instruments Portable equipment GENERAL DESCRIPTION The ADM682x are supervisory circuits that monitor power supply voltage levels and code execution integrity in microprocessor-based systems. As well as providing power-on reset signals, an on-chip watchdog timer can reset the microprocessor if it fails to strobe within a preset timeout period. A reset signal can also be asserted by means of an external push-button through a manual reset input. The parts feature different combinations of watchdog input and manual reset input and output stage configurations, as shown in Table 1. Each part is available in nine reset threshold options, ranging from 1.58 V to 4.63 V. The reset and watchdog timeout periods are fixed at 140 ms (min) and 1.6 sec (typ), respectively. The ADM682x are available in 5-lead SOT-23 packages and typically consume only 7 μA, making them suitable for use in low power, portable applications. Table 1. Selection Table Output Stage Part No. ADM6821 ADM6822 ADM6823 ADM6824 ADM6825 Watchdog Timer Yes Yes Yes Yes - Manual Reset Yes Yes Yes Yes RESET Open-Drain Push-Pull Push-Pull Push-Pull RESET Push-Pull Push-Pull Push-Pull Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADM6821/ADM6822/ADM6823/ADM6824/ADM6825 TABLE OF CONTENTS Specifications..................................................................................... 3 Watchdog Input .............................................................................9 Absolute Maximum Ratings............................................................ 5 Application Information................................................................ 10 ESD Caution.................................................................................. 5 Watchdog Input Current ........................................................... 10 Pin Configurations and Function Descriptions ........................... 6 Negative-Going VCC Transients ................................................ 10 Typical Performance Characteristics ............................................. 7 Ensuring Reset Valid to VCC = 0 V ........................................... 10 Circuit Description........................................................................... 9 Watchdog Software Considerations......................................... 10 Reset Output ................................................................................. 9 Outline Dimensions ....................................................................... 11 Manual Reset Input ...................................................................... 9 Ordering Guide .......................................................................... 11 REVISION HISTORY 6/05—Revision 0: Initial Version Rev. 0 | Page 2 of 12 ADM6821/ADM6822/ADM6823/ADM6824/ADM6825 SPECIFICATIONS VCC = 4.5 V to 5.5 V for ADM682_L/M; VCC = 2.7 V to 3.6 V for ADM682_T/S/R; VCC = 2.1 V to 2.75 V for ADM682_Z/Y; VCC = 1.53 V to 2.0 V for ADM682_W/V; TA = –40°C to +125°C, unless otherwise noted. Table 2. Parameter SUPPLY VCC Operating Voltage Range Supply Current RESET THRESHOLD VOLTAGE ADM682xL ADM682xM ADM682xT ADM682xS ADM682xR ADM682xZ ADM682xY ADM682xW ADM682xV RESET THRESHOLD TEMPERATURE COEFFICIENT RESET THRESHOLD HYSTERESIS VCC TO RESET DELAY RESET TIMEOUT PERIOD RESET Output Voltage VOL (Push-Pull or Open-Drain) VOH (Push-Pull Only) RESET OUTPUT LEAKAGE CURRENT (Open-Drain Only) RESET OUTPUT VOLTAGE (Push-Pull Only) VOH Min Typ Max Unit Test Conditions/Comments 10 7 5.5 20 16 V μA μA WDI and MR unconnected, VCC = 5.5 V WDI and MR unconnected, VCC = 3.6 V VTH − VCC = 100 mV 1 4.50 4.25 3.00 2.85 2.55 2.25 2.12 1.62 1.52 4.63 4.38 3.08 2.93 2.63 2.32 2.19 1.67 1.58 60 2 x VTH 20 4.75 4.50 3.15 3.00 2.70 2.38 2.25 1.71 1.62 V V V V V V V V V ppm/°C mV μs 140 200 280 ms 0.3 0.3 0.3 0.4 1 V V V V V V V μA VCC > = 1 V, ISINK = 50 μA VCC > = 1.2 V, ISINK = 100 μA VCC > = 2.55 V, ISINK = 1.2 mA VCC > = 4.25 V, ISINK = 3.2 mA VCC > = 1.8 V, ISOURCE = 200 μA VCC > = 3.15 V, ISOURCE = 500 μA VCC > = 4.75 V, ISOURCE = 800 μA RESET not asserted 0.3 0.3 0.4 V V V V V V V VCC > = 1 V, ISOURCE = 1 μA VCC > = 1.5 V, ISOURCE = 100 μA VCC > = 2.55 V, ISOURCE = 500 μA VCC > = 4.25 V, ISOURCE = 800 μA VCC > = 1.8 V, ISINK = 500 μA VCC > = 3.15 V, ISINK = 1.2 mA VCC > = 4.75 V, ISINK = 3.2 mA 0.8 × VCC 0.8 × VCC 0.8 × VCC 0.8 × VCC 0.8 × VCC 0.8 × VCC 0.8 × VCC VOL MANUAL RESET INPUT (ADM6821/ADM6822/ADM6823/ADM6825) MR Input Threshold VIL VIH MR Input Pulse Width MR Glitch Rejection MR to Reset Delay MR Pull-Up Resistance 0.3 × VCC 0.7 × VCC 1 25 100 200 50 75 Rev. 0 | Page 3 of 12 V V μs ns ns kΩ ADM6821/ADM6822/ADM6823/ADM6824/ADM6825 Parameter WATCHDOG INPUT (ADM6821/ADM6822/ADM6823/ADM6824) Watchdog Timeout Period WDI Pulse Width WDI Input Threshold VIL VIH WDI Input Current Min Typ Max Unit 1.12 50 1.6 2.40 sec ns 0.3 × VCC V V μA μA 0.7 × VCC −20 120 −15 160 Rev. 0 | Page 4 of 12 Test Conditions/Comments VWDI = VCC VWDI = 0 ADM6821/ADM6822/ADM6823/ADM6824/ADM6825 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VCC Output Current (RESET, RESET) Operating Temperature Range Storage Temperature Range θJA Thermal Impedance Soldering Temperature Sn/Pb Pb-Free Rating −0.3 V to +6 V 20 mA −40°C to +125°C −65°C to +150°C 170°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 240°C, 30 sec 260°C, 40 sec ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 12 ADM6821/ADM6822/ADM6823/ADM6824/ADM6825 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 5 RESET 1 VCC GND 2 TOP VIEW (Not to Scale) MR 3 4 WDI 04535-002 GND 2 MR 3 5 RESET 1 VCC ADM6822/ ADM6823 TOP VIEW (Not to Scale) 4 WDI Figure 4. ADM6824 Pin Configuration 5 VCC 4 MR ADM6825 GND 2 4 WDI 04535-003 GND 2 VCC TOP VIEW (Not to Scale) RESET 3 Figure 2. ADM6821 Pin Configuration RESET 1 5 ADM6824 04535-004 ADM6821 RESET 3 Figure 3. ADM6822/ADM6823 Pin Configuration TOP VIEW (Not to Scale) 04535-005 RESET 1 Figure 5. ADM6825 Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 Name RESET (ADM6822/ADM6823/ADM6824/ADM6825) RESET (ADM6821) GND MR (ADM6821/ADM6822/ADM6823) RESET (ADM6824/ADM6825) WDI (ADM6821/ADM6822/ADM6823/ADM6824) MR (ADM6825) VCC Description Active-Low Reset Output. Asserted whenever VCC is below the reset threshold, VTH. Open-Drain Output Stage for the ADM6822. Push-Pull Output Stage for the ADM6823/ADM6824/ADM6825. Active-High Push-Pull Reset Output. Ground. Manual Reset Input. This is an active-low input, which, when forced low for at least 1 μs, generates a reset. It features a 50 kΩ internal pull-up. Active-High Push-Pull Reset Output. Watchdog Input. Generates a reset if the voltage on the pin remains low or high for the duration of the watchdog timeout. The timer is cleared if a logic transition occurs on this pin or if a reset is generated. Manual Reset Input. Power Supply Voltage Being Monitored. Rev. 0 | Page 6 of 12 ADM6821/ADM6822/ADM6823/ADM6824/ADM6825 TYPICAL PERFORMANCE CHARACTERISTICS 10.0 1.20 9.5 8.5 NORMALIZED WATCHDOG TIMEOUT 9.0 VCC = 5V 8.0 ICC (μA) 7.5 7.0 6.5 VCC = 3.3V 6.0 5.5 5.0 4.5 VCC = 1.5V 1.15 1.10 1.05 1.00 0.95 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 0.90 –40 04535-006 Figure 6. Supply Current vs. Temperature 20 40 60 TEMPERATURE (°C) 80 100 120 1.05 1.04 NORMALIZED RESET THRESHOLD 1.15 NORMALIZED RESET TIMEOUT 0 Figure 9. Normalized Watchdog Timeout Period vs. Temperature 1.20 1.10 1.05 1.00 0.95 0.90 0.85 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 0.95 –40 04535-007 0.80 –40 –20 Figure 7. Normalized RESET Timeout Period vs. Temperature –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 04535-010 3.5 –40 04535-009 4.0 Figure 10. Normalized RESET Threshold vs. Temperature 100 160 90 140 60 50 40 30 20 100 80 60 40 20 10 0 –40 120 –20 0 20 40 60 TEMPERATURE (°C) 80 100 Figure 8. VCC to RESET Output Delay vs. Temperature 120 0 10 VCC = 2.93V VCC = 4.63V 100 RESET THRESHOLD OVERDRIVE (mV) 1000 04535-011 MINIMUM PULSE WIDTH (μs) 70 04535-008 VCC TO RESET DELAY (μs) 80 Figure 11. Maximum VCC Transient Duration vs. RESET Threshold Overdrive Rev. 0 | Page 7 of 12 ADM6821/ADM6822/ADM6823/ADM6824/ADM6825 0.20 2.92 VCC = 2.9V VCC = 2.9V 2.90 0.15 VOUT (V) 2.86 0.05 0 0 1 2 3 4 ISINK (mA) 5 6 7 Figure 12. Voltage Output Low vs. ISINK 2.82 0 0.2 0.4 0.6 ISOURCE (mA) 0.8 Figure 13. Voltage Output High vs. ISOURCE Rev. 0 | Page 8 of 12 1.0 04535-018 2.84 04535-017 VOUT (V) 2.88 0.10 ADM6821/ADM6822/ADM6823/ADM6824/ADM6825 CIRCUIT DESCRIPTION Problems with microprocessor code execution can be monitored and corrected with a watchdog timer (ADM6821/ ADM6822/ADM6823/ADM6824). When watchdog strobe instructions are included in microprocessor code, a watchdog timer detects if the microprocessor code breaks down or becomes stuck in an infinite loop. If this happens, the watchdog timer asserts a reset pulse, which restarts the microprocessor in a known state. If the user detects a problem with the system’s operation, a manual reset input is available (ADM6821/ADM6822/ ADM6823/ADM6825) to reset the microprocessor by means of an external push-button, for example. RESET OUTPUT The ADM6821 features an active-high push-pull reset output. The ADM6822 features an active-low open-drain reset output, while the ADM6823 features an active-low push-pull output. The ADM6824/ADM6825 feature dual active-low and activehigh push-pull reset outputs. For active-low and active-high outputs, the reset signal is guaranteed to be logic low and logic high, respectively, for VCC down to 1 V. The reset output is asserted when VCC is below the reset threshold (VTH), when MR is driven low, or when WDI is not serviced within the watchdog timeout period (tWD). Reset remains asserted for the duration of the reset active timeout period (tRP) after VCC rises above the reset threshold, after MR transitions from low to high, or after the watchdog timer times out. Figure 14 shows the reset outputs. VCC VCC MANUAL RESET INPUT The ADM6821/ADM6822/ADM6823/ADM6825 feature a manual reset input (MR), which, when driven low, asserts the reset output. When MR transitions from low to high, reset remains asserted for the duration of the reset active timeout period before deasserting. The MR input has a 50 kΩ internal pull-up so that the input is always high when unconnected. An external push-button switch can be connected between MR and ground so that the user can generate a reset. Debounce circuitry is integrated on-chip for this purpose. Noise immunity is provided on the MR input, and fast, negative-going transients of up to 100 ns (typ) are ignored. A 0.1 μF capacitor between MR and ground provides additional noise immunity. WATCHDOG INPUT The ADM6821/ADM6822/ADM6823/ADM6824 feature a watchdog timer, which monitors microprocessor activity. A timer circuit is cleared with every low-to-high or high-to-low logic transition on the watchdog input pin (WDI), which detects pulses as short as 50 ns. If the timer counts through the preset watchdog timeout period (tWD), reset is asserted. The microprocessor is required to toggle the WDI pin to avoid being reset. Failure of the microprocessor to toggle WDI within the timeout period therefore indicates a code execution error, and the reset pulse generated restarts the microprocessor in a known state. In addition to logic transitions on WDI, the watchdog timer is also cleared by a reset assertion due to an undervoltage condition on VCC or MR being pulled low. When reset is asserted, the watchdog timer is cleared and does not begin counting again until reset deassserts. The watchdog timer can be disabled by leaving WDI floating or by three-stating the WDI driver. VCC RESET VCC tRD tRP tRD 04535-012 0V 1V 0V tRP tWD VCC Figure 15. Watchdog Timing Diagram tRP VCC RESET VCC 0V 1V 0V RESET VTH 1V 0V Figure 14. Reset Timing Diagram Rev. 0 | Page 9 of 12 tRD 0V WDI VTH VTH VCC 04535-013 The ADM682x provide microprocessor supply voltage supervision by controlling the microprocessor’s reset input. Code execution errors are avoided during power-up, powerdown, and brownout conditions by asserting a reset signal when the supply voltage is below a preset threshold. In addition, the ADM682x allow supply voltage stabilization with a fixed timeout before the reset deasserts after the supply voltage rises above the threshold. ADM6821/ADM6822/ADM6823/ADM6824/ADM6825 APPLICATION INFORMATION WATCHDOG INPUT CURRENT WATCHDOG SOFTWARE CONSIDERATIONS To minimize watchdog input current (and minimize overall power consumption), leave WDI low for the majority of the watchdog timeout period. When driven high, WDI can draw as much as 160 μA. Pulsing WDI low-high-low at a low duty cycle reduces the effect of the large input current. When WDI is unconnected, a window comparator disconnects the watchdog timer from the reset output circuitry so that reset is not asserted when the watchdog timer times out. In implementing the microprocessor’s watchdog strobe code, quickly switching WDI low-high and then high-low (minimizing WDI high time) is desirable for current consumption reasons. However, a more effective way of using the watchdog function can be considered. NEGATIVE-GOING VCC TRANSIENTS To avoid unnecessary resets caused by fast power supply transients, the ADM682x are equipped with glitch rejection circuitry. The typical performance characteristic in Figure 11 plots VCC transient duration versus. the transient magnitude. The curves show combinations of transient magnitude and duration for which a reset is not generated for the 4.63 V and 2.93 V reset threshold parts. For example, with the 2.93 V threshold, a transient that goes 100 mV below the threshold and lasts 8 μs typically does not cause a reset, but if the transient is any bigger in magnitude or duration, a reset is generated. An optional 0.1 μF bypass capacitor mounted close to VCC provides additional glitch rejection. A low-high-low WDI pulse within a given subroutine prevents the watchdog from timing out. However, if the subroutine becomes stuck in an infinite loop, the watchdog could not detect this because the subroutine continues to toggle WDI. A more effective coding scheme for detecting this error involves using a slightly longer watchdog timeout. In the program that calls the subroutine, WDI is set high. The subroutine sets WDI low when it is called. If the program executes without error, WDI is toggled high and low with every loop of the program. If the subroutine enters an infinite loop, WDI is kept low, the watchdog times out, and the microprocessor is reset. ENSURING RESET VALID TO VCC = 0 V START SET WDI HIGH PROGRAM CODE INFINITE LOOP: WATCHDOG TIMES OUT SUBROUTINE SET WDI LOW 04535-014 Both active-low and active-high reset outputs are guaranteed to be valid for VCC as low as 1 V. However, by using an external resistor with push-pull configured reset outputs, valid outputs for VCC as low as 0 V are possible. For an active-low reset output, a resistor connected between RESET and ground pulls the output low when it is unable to sink current. For the activehigh case, a resistor connected between RESET and VCC pulls the output high when it is unable to source current. A large resistance such as 100 kΩ should be used so that it does not overload the reset output when VCC is above 1 V. RETURN Figure 17. Watchdog Flow Diagram VCC VCC VCC RESET 100kΩ 100kΩ ADM6821/ ADM6824/ ADM6825 RESET RESET μP ADM6823 RESET GND MR WDI I/O 04535-016 GND RESET 04535-015 ADM6822/ ADM6823/ ADM6824/ ADM6825 Figure 18. Typical Application Circuit Figure 16. Ensuring Reset Valid to VCC = 0 V Rev. 0 | Page 10 of 12 ADM6821/ADM6822/ADM6823/ADM6824/ADM6825 OUTLINE DIMENSIONS 2.90 BSC 5 4 2.80 BSC 1.60 BSC 1 2 3 PIN 1 0.95 BSC 1.90 BSC 1.30 1.15 0.90 1.45 MAX 0.15 MAX 0.50 0.30 0.22 0.08 10° 5° 0° SEATING PLANE 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-AA Figure 19. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters ADM682 x x YRJZ -RL7 GENERIC NUMBER (1 TO 5) ORDERING QUANTITY RL7: 3,000 PIECE REEL RESET THRESHOLD NUMBER TEMPERATURE RANGE Y: –40°C TO +125°C L: 4.63V M: 4.38V T: 3.08V S: 2.93V R: 2.63V Z: 2.32V Y: 2.19V W: 1.67V V: 1.58V Z: LEAD-FREE 04535-019 PACKAGE CODE RJ: 5-LEAD SOT-23 Figure 20. Ordering Code Structure ORDERING GUIDE Standard Models 1 ADM6821SYRJZRL7 2 ADM6822SYRJZ-RL72 ADM6822TYRJZ-RL72 Reset Threshold (V) 2.93 Reset Timeout (ms) 140 Temperature Range −40°C to +125°C Quantity 3k Package Option RJ-5 Branding N0A 2.93 3.08 140 140 −40°C to +125°C −40°C to +125°C 3k 3k RJ-5 RJ-5 N0B N0B ADM6823SYRJ-R7 ADM6823SYRJZ-RL72 2.93 2.93 140 140 −40°C to +125°C −40°C to +125°C 3k 3k RJ-5 RJ-5 N0C N0Q ADM6823TYRJ-R7 ADM6823TYRJZ-RL72 3.08 3.08 140 140 −40°C to +125°C −40°C to +125°C 3k 3k RJ-5 RJ-5 N0C N0Q ADM6824TYRJZ-R72 3.08 140 −40°C to +125°C 3k RJ-5 N0D 2 3.08 140 −40°C to +125°C 3k RJ-5 N0E ADM6825TYRJZ-R7 1 If ordering nonstandard models, complete the ordering code shown in Figure 20 by inserting the part number and reset threshold suffixes. Contact Sales for availability of nonstandard models. 2 Z = Pb-free part. Rev. 0 | Page 11 of 12 ADM6821/ADM6822/ADM6823/ADM6824/ADM6825 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04535–0–6/05(0) Rev. 0 | Page 12 of 12