Cypress CY7C1328G-133AXI 4-mbit (256 k ã 18) pipelined dcd sync sram Datasheet

CY7C1328G
4-Mbit (256 K × 18)
Pipelined DCD Sync SRAM
4-Mbit (256 K × 18) Pipelined DCD Sync SRAM
Features
Functional Description
■
Registered inputs and outputs for pipelined operation
■
Optimal for performance (double-cycle deselect)
❐ Depth expansion without wait state
■
256 K × 18 common I/O architecture
■
3.3 V core power supply (VDD)
■
3.3 V/2.5 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 4.0 ns (for 133-MHz device)
■
Provide high-performance 3-1-1-1 access rate
■
User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed writes
■
Asynchronous output enable
■
Available in Pb-free 100-pin TQFP package
■
“ZZ” sleep mode option
The CY7C1328G SRAM integrates 256 K × 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW[A:B], and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Pin Definitions on page 5 and Truth Table on
page 8 for further details). Write cycles can be one to two bytes
wide as controlled by the byte write control inputs. GW active
LOW causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off the
output buffers an additional cycle when a deselect is executed.
This feature allows depth expansion without penalizing system
performance.
The CY7C1328G operates from a +3.3 V core power supply
while all outputs operate with a +3.3 V or a +2.5 V supply. All
inputs and outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
133 MHz
Unit
Maximum access time
Description
4.0
ns
Maximum operating current
225
mA
Maximum CMOS standby current
40
mA
Cypress Semiconductor Corporation
Document Number: 38-05523 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 25, 2012
CY7C1328G
Functional Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
MODE
ADV
CLK
A[1:0]
Q1
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
BWB
BWA
BWE
GW
CE1
CE2
CE3
DQB , DQPB
BYTE
WRITE DRIVER
DQB, DQPB
BYTE
WRITE REGISTER
DQA, DQPA
BYTE
WRITE DRIVER
DQA , DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs,
DQPA
DQPB
E
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document Number: 38-05523 Rev. *J
Page 2 of 22
CY7C1328G
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 7
Sleep Mode ................................................................. 7
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Document Number: 38-05523 Rev. *J
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagram ............................................................ 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Page 3 of 22
CY7C1328G
Pin Configurations
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
NC
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1328G
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
BYTE A
Document Number: 38-05523 Rev. *J
A
A
A
A
A
A
A
NC
NC
NC
NC
VSS
VDD
MODE
A
A
A
A
A1
A0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
BYTE B
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Page 4 of 22
CY7C1328G
Pin Definitions
Pin
A0, A1, A
BWA, BWB
TQFP
Type
Description
InputAddress inputs used to select one of the 256 K address locations. Sampled at the
37, 36, 32, 33,
34, 35, 44, 45, synchronous rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are
46, 47, 48, 49,
sampled active. A[1:0] are fed to the two-bit counter.
50, 80, 81, 82,
99, 100
93,94
InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the
synchronous SRAM. Sampled on the rising edge of CLK.
GW
88
BWE
87
InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK,
synchronous a global write is conducted (all bytes are written, regardless of the values on BW[A:B] and
BWE).
InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal
synchronous must be asserted LOW to conduct a byte write.
CLK
89
CE1
98
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is
HIGH. CE1 is sampled only when a new external address is loaded.
CE2
97
CE3
92
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
synchronous conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
synchronous conjunction with CE1 and CE2 to select/deselect the device. CE3 is sampled only when
a new external address is loaded.
OE
86
InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins are
tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
ADV
83
ADSP
84
Inputsynchronous
Inputsynchronous
ADSC
85
ZZ
64
Inputclock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Advance input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW.
synchronous When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
InputZZ “sleep” input, active HIGH. When asserted HIGH places the device in a
asynchronous non-time-critical “sleep” condition with data integrity preserved. During normal operation,
this pin has to be low or left floating. ZZ pin has an internal pull-down.
DQs,
DQP[A:B]
58, 59, 62, 63,
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
68, 69, 72, 73, synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
74, 8, 9, 12,
memory location specified by the addresses presented during the previous clock rise of
13, 18, 19, 22,
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
23, 24
the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a tristate
condition.
VDD
VSS
VDDQ
15, 41, 65, 91 Power supply Power supply inputs to the core of the device.
17, 40, 67, 90
Ground
Ground for the core of the device.
4, 11, 20, 27,
I/O power Power supply for the I/O circuitry.
54, 61, 70, 77
supply
VSSQ
5, 10, 21, 26,
55, 60, 71, 76
I/O ground
Document Number: 38-05523 Rev. *J
Ground for the I/O circuitry.
Page 5 of 22
CY7C1328G
Pin Definitions (continued)
Pin
MODE
NC
TQFP
Type
Description
31
Inputstatic
1, 2, 3, 6, 7,
14, 16, 25, 28,
29, 30, 38, 39,
42, 43, 51, 52,
53, 56, 57, 66,
75, 78, 79, 95,
96
–
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode pin has an internal pull-up.
No connects. Not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock.
The CY7C1328G supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the processor address strobe (ADSP) or the controller
address strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BW[A:B]) inputs. A global write
enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip
select is asserted active. The address presented is loaded into
the address register and the address advancement logic while
being delivered to the memory core. The write signals (GW,
BWE, and BW[A:B]) and ADV inputs are ignored during this first
cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the
corresponding address location in the memory core. If GW is
HIGH, then the write operation is controlled by BWE and BW[A:B]
signals. The CY7C1328G provides byte write capability that is
described in the Write Cycle Description table. Asserting the byte
write enable input (BWE) with the selected byte write input will
selectively write to only the desired bytes. Bytes not selected
during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided to
simplify the write operations.
Synchronous chip selects CE1, CE2, CE3 and an asynchronous
output enable (OE) provide for easy bank selection and output
tristate control. ADSP is ignored if CE1 is HIGH.
Because the CY7C1328G is a common I/O device, the output
enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tristate the output drivers. As a
safety precaution, DQ are automatically tri-stated whenever a
write cycle is detected, regardless of the state of OE.
Single Read Accesses
Single Write Accesses Initiated by ADSC
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is
HIGH. The address presented to the address inputs is stored into
the address advancement logic and the address register while
being presented to the memory core. The corresponding data is
allowed to propagate to the input of the output registers. At the
rising edge of the next clock the data is allowed to propagate
through the output register and onto the data bus within tCO if OE
is active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its outputs
are always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported.
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) chip select is asserted active, and (4) the appropriate
combination of the write inputs (GW, BWE, and BW[A:B]) are
asserted active to conduct a write to the desired byte(s). ADSC
triggered write accesses require a single clock cycle to complete.
The address presented is loaded into the address register and
the address advancement logic while being delivered to the
memory core. The ADV input is ignored during this cycle. If a
global write is conducted, the data presented to the DQX is
written into the corresponding address location in the memory
core. If a byte write is conducted, only the selected bytes are
written. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
The CY7C1328G is a double-cycle deselect part. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output will tristate immediately after
the next clock rise.
Because the CY7C1328G is a common I/O device, the output
enable (OE) must be deasserted HIGH before presenting data
to the DQX inputs. Doing so will tristate the output drivers. As a
Document Number: 38-05523 Rev. *J
Page 6 of 22
CY7C1328G
safety precaution, DQX are automatically tri-stated whenever a
write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1328G provides a two-bit wraparound counter, fed by
A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input. Both read and write burst operations
are supported.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Asserting ADV LOW at clock rise will automatically increment the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1:A0
Linear Burst Address Table
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CEs,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Snooze mode standby current
ZZ > VDD 0.2 V
tZZS
Device operation to ZZ
ZZ > VDD  0.2 V
tZZREC
ZZ recovery time
ZZ < 0.2 V
tZZI
ZZ active to snooze current
tRZZI
Min
Max
Unit
–
40
mA
–
2tCYC
ns
2tCYC
–
ns
This parameter is sampled
–
2tCYC
ns
ZZ inactive to exit snooze current This parameter is sampled
0
–
ns
Document Number: 38-05523 Rev. *J
Page 7 of 22
CY7C1328G
Truth Table
The Truth Table for part CY7C1328G is as follows. [1, 2, 3, 4, 5]
Operation
Deselected cycle, power-down
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
None
H
X
X
L
X
L
X
X
X L–H Tristate
Deselected cycle, power-down
None
L
L
X
L
L
X
Deselected cycle, power-down
None
L
X
H
Deselected cycle, power-down
None
L
L
X
X
X
X
L–H
Tristate
L
L
X
X
X
X
L–H
Tristate
L
H
L
X
X
X
L–H
Tristate
Deselected cycle, power-down
None
L
X
H
L
H
L
X
X
X
L–H
Tristate
ZZ mode, power-down
None
X
X
X
H
X
X
X
X
X
X
Tristate
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
H
L–H
Tristate
Write cycle, begin burst
External
L
H
L
L
H
L
X
L
X
L–H
D
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
H
L–H
Tristate
Next
X
X
X
L
H
H
L
H
L
L–H
Q
Read cycle, continue burst
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
H
L–H
Tristate
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
L
L–H
Q
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
H
L–H
Tristate
Write cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
Write cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L–H
Tristate
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L–H
Q
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L–H
Tristate
Write cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more byte write enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all byte write enable signals (BWA, BWB), BWE,
GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care
for the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05523 Rev. *J
Page 8 of 22
CY7C1328G
Truth Table for Read/Write
The Truth Table for read or write for part CY7C1328G is as follows. [6]
Function
GW
BWE
BWA
BWB
Read
H
H
X
X
Read
H
L
H
H
Write byte A – (DQA and DQPA)
H
L
L
H
Write byte B – (DQB and DQPB)
H
L
H
L
Write all bytes
H
L
L
L
Write all bytes
L
X
X
X
Note
6. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
Document Number: 38-05523 Rev. *J
Page 9 of 22
CY7C1328G
Maximum Ratings
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) .......................... > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
Range
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
Ambient
Temperature (TA)
Industrial
–40 °C to +85 °C
VDDQ
VDD
3.3 V5% / 2.5 V5% to
+ 10%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [7, 8]
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
Output HIGH voltage
VOL
VIH
VIL
IX
Test Conditions
VDDQ = 3.3 V, VDD = Min, IOH = –4.0 mA
VDDQ = 2.5 V, VDD = Min, IOH = –1.0 mA
Output LOW voltage
VDDQ = 3.3 V, VDD = Max, IOL = 8.0 mA
VDDQ = 2.5 V, VDD = Max, IOL = 1.0 mA
Input HIGH voltage[7]
VDDQ = 3.3 V
VDDQ = 2.5 V
Input LOW voltage[7]
VDDQ = 3.3 V
VDDQ = 2.5 V
Input leakage current except ZZ GND  VI  VDDQ
and MODE
Input current of MODE
Input = VSS
Input current of ZZ
IOZ
IDD
Output leakage current
VDD operating supply current
ISB1
Automatic CE power-down
current – TTL inputs
ISB2
Automatic CE power-down
current – CMOS inputs
ISB3
Automatic CE power-down
current – CMOS inputs
ISB4
Automatic CE power-down
current – TTL inputs
Input = VDD
Input = VSS
Input = VDD
GND  VI  VDDQ, output disabled
VDD = Max, IOUT = 0 mA,
7.5-ns cycle,
f = fMAX = 1/tCYC
133 MHz
VDD = Max, device deselected, 7.5-ns cycle,
VIN  VIH or VIN  VIL,
133 MHz
f = fMAX = 1/tCYC
VDD = Max, device deselected, 7.5-ns cycle,
VIN  0.3 V or VIN > VDDQ – 0.3 V, 133 MHz
f=0
VDD = Max, device deselected, 7.5-ns cycle,
VIN  0.3 V or VIN > VDDQ – 0.3 V, 133 MHz
f = fMAX = 1/tCYC
VDD = Max, device deselected, 7.5-ns cycle,
133 MHz
VIN  VIH or VIN  VIL, f = 0
Min
3.135
2.375
2.4
2.0
–
–
2.0
1.7
–0.3
–0.3
–5
Max
Unit
3.6
V
VDD
V
–
V
–
V
0.4
V
0.4
V
VDD + 0.3 V V
VDD + 0.3 V V
0.8
V
0.7
V
5
µA
–30
–
–5
–
–5
–
–
5
–
30
5
225
µA
µA
µA
µA
µA
mA
–
90
mA
–
40
mA
–
75
mA
–
45
mA
Notes
7. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > – 2 V (Pulse width less than tCYC/2).
8. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05523 Rev. *J
Page 10 of 22
CY7C1328G
Capacitance
Parameter [9]
100-pin TQFP
Max
Unit
5
pF
5
pF
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
30.32
°C/W
6.85
°C/W
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 3.3 V
Thermal Resistance
Parameter [9]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317 
3.3 V
OUTPUT
OUTPUT
RL = 50 
Z0 = 50 
GND
5 pF
R = 351 
VT = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
2.5 V I/O Test Load
OUTPUT
RL = 50 
Z0 = 50 
INCLUDING
JIG AND
SCOPE
 1 ns
 1 ns
(c)
ALL INPUT PULSES
VDDQ
GND
5 pF
90%
10%
90%
(b)
R =1538 
VT = 1.25 V
(a)
10%
R = 1667 
2.5 V
OUTPUT
ALL INPUT PULSES
VDDQ
(b)
10%
90%
10%
90%
 1 ns
 1 ns
(c)
Note
9. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05523 Rev. *J
Page 11 of 22
CY7C1328G
Switching Characteristics
Over the Operating Range
Parameter [10, 11]
Description
-133
Unit
Min
Max
VDD(typical) to the first access [12]
1.0
–
ms
tCYC
Clock cycle time
7.5
–
ns
tCH
Clock HIGH
3.0
–
ns
tCL
Clock LOW
3.0
–
ns
tPOWER
Clock
Output Times
tCO
Data output valid after CLK rise
–
4.0
ns
tDOH
Data output hold after CLK rise
1.5
–
ns
0
–
ns
–
4.0
ns
–
4.0
ns
0
–
ns
–
4.0
ns
tCLZ
Clock to low Z
[13, 14, 15]
[13, 14, 15]
tCHZ
Clock to high Z
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[13, 14, 15]
OE HIGH to output high Z
[13, 14, 15]
Setup Times
tAS
Address setup before CLK rise
1.5
–
ns
tADS
ADSC, ADSP setup before CLK rise
1.5
–
ns
tADVS
ADV setup before CLK rise
1.5
–
ns
tWES
GW, BWE, BWX setup before CLK rise
1.5
–
ns
tDS
Data input setup before CLK rise
1.5
–
ns
tCES
Chip enable setup before CLK rise
1.5
–
ns
tAH
Address hold after CLK rise
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.5
–
ns
tADVH
ADV hold after CLK rise
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
ns
Hold Times
Notes
10. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
11. Test conditions shown in (a) of Figure 2 on page 11 unless otherwise noted.
12. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
13. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 11. Transition is measured ±200 mV from steady-state voltage.
14. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
Document Number: 38-05523 Rev. *J
Page 12 of 22
CY7C1328G
Switching Waveforms
Figure 3. Read Timing [16]
tCYC
CLK
tCH
tCL
tADS tADH
ADSP
tADS
tADH
ADSC
tAS
ADDRESS
tAH
A1
A2
A3
Burst continued with
new base address
tWES tWEH
GW, BWE,BW
[A:B]
Deselect
cycle
tCES tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
Data Out (DQ)
CLZ
t OEHZ
Q(A1)
High-Z
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
t CO
Single READ
BURST READ
DON’T CARE
Burst wraps around
to its initial state
UNDEFINED
Note
16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 38-05523 Rev. *J
Page 13 of 22
CY7C1328G
Switching Waveforms (continued)
Figure 4. Write Timing [17, 18]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BW[A :B]
tWES tWEH
GW
tCES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
tDS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.
Document Number: 38-05523 Rev. *J
Page 14 of 22
CY7C1328G
Switching Waveforms (continued)
Figure 5. Read/Write Timing [19, 20, 21]
tCYC
CLK
tCL
tCH
tADS
tADH
ADSP
ADSC
tAS
ADDRESS
A1
tAH
A2
A3
A4
tWES
tWEH
tDS
tDH
A5
A6
D(A5)
D(A6)
BWE,
BW[A:B]
tCES
tCEH
CE
ADV
OE
tCO
tOELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A4)
Q(A2)
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
20. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
21. GW is HIGH.
Document Number: 38-05523 Rev. *J
Page 15 of 22
CY7C1328G
Switching Waveforms (continued)
Figure 6. ZZ Mode Timing [22, 23]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
22. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
23. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05523 Rev. *J
Page 16 of 22
CY7C1328G
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
133
Package
Diagram
Ordering Code
CY7C1328G-133AXI
Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Industrial
Ordering Code Definitions
CY
7
C
1328
G - 133
A
X
I
Temperature range:
I = Industrial
Pb-free
Package Type:
A = 100-pin TQFP
Speed Grade: 133 MHz
Process Technology: G  90 nm
Part Identifier: 1328 = DCD, 256 K × 18 (4 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05523 Rev. *J
Page 17 of 22
CY7C1328G
Package Diagram
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *D
Document Number: 38-05523 Rev. *J
Page 18 of 22
CY7C1328G
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
chip enable
CMOS
complementary metal oxide semiconductor
°C
degree Celsius
EIA
electronic industries alliance
MHz
megahertz
I/O
input/output
µA
microampere
JEDEC
joint electron devices engineering council
mA
milliampere
OE
output enable
mm
millimeter
SRAM
static random access memory
ms
millisecond
TQFP
thin quad flat pack
mV
millivolt
TTL
transistor-transistor logic
nm
nanometer
ns
nanosecond

ohm
%
percent
Document Number: 38-05523 Rev. *J
Symbol
Unit of Measure
pF
picofarad
V
volt
W
watt
Page 19 of 22
CY7C1328G
Document History Page
Document Title: CY7C1328G, 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM
Document Number: 38-05523
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
224371
See ECN
RKF
New data sheet.
*A
288909
See ECN
VBL
Updated Ordering Information (Changed TQFP package to Pb-free TQFP
package).
*B
333625
See ECN
SYT
Updated Pin Configurations (Modified Address Expansion balls in the pinouts
for 100-pin TQFP Package as per JEDEC standards).
Updated Pin Definitions.
Updated Electrical Characteristics (Updated test conditions for VOL and VOH
parameters).
Updated Thermal Resistance (Replaced TBD’s for JA and JC to their
respective values).
Updated Ordering Information (By shading and unshading MPNs as per
availability).
*C
419264
See ECN
RXU
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Features (Removed 133 MHz frequency related information, replaced
166 MHz with 167 MHz).
Updated Selection Guide (Removed 133 MHz frequency related information,
replaced 166 MHz with 167 MHz).
Updated Electrical Characteristics (Updated Note 8 (Changed test condition
from VIH < VDD to VIH VDD), changed the test condition for VOL parameter
from VDD = Min. to VDD = Max., changed “Input Load Current except ZZ and
MODE” to “Input Leakage Current except ZZ and MODE”, removed 133 MHz
frequency related information, replaced 166 MHz with 167 MHz).
Updated Switching Characteristics (Removed 133 MHz frequency related
information, replaced 166 MHz with 167 MHz).
Updated Ordering Information (Updated part numbers, replaced Package
Name column with Package Diagram in the Ordering Information table).
Updated Package Diagram.
*D
430373
See ECN
NXR
Updated Features (Included 133 MHz frequency related information).
Updated Selection Guide (Included 133 MHz frequency related information).
Updated Electrical Characteristics (Included 133 MHz frequency related
information).
Updated Switching Characteristics (Included 133 MHz frequency related
information).
Updated Ordering Information (Updated part numbers).
*E
480368
See ECN
VKN
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
*F
2896584
03/20/2010
NJY
Updated Ordering Information (Removed obsolete part numbers).
Updated Package Diagram.
*G
3045943
10/03/2010
NJY
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*H
3353361
08/24/2011
PRIT
Updated Functional Description (Updated Note as “For best practices
recommendations, refer to SRAM System Design Guidelines.” and referred the
note in same place in this section).
Updated Package Diagram.
Document Number: 38-05523 Rev. *J
Page 20 of 22
CY7C1328G
Document History Page (continued)
Document Title: CY7C1328G, 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM
Document Number: 38-05523
Rev.
ECN No.
Issue Date
*I
3589101
04/17/2012
*J
3754982
09/25/2012
Document Number: 38-05523 Rev. *J
Orig. of
Change
Description of Change
NJY / PRIT Updated Features (Removed 250 MHz, 200 MHz and 167 MHz frequencies
related information).
Updated Functional Description (Removed the Note “For best practices
recommendations, refer to SRAM System Design Guidelines.”).
Updated Selection Guide (Removed 250 MHz, 200 MHz and 167 MHz
frequencies related information).
Updated Operating Range (Removed Commercial Temperature Range).
Updated Electrical Characteristics (Removed 250 MHz, 200 MHz and 167 MHz
frequencies related information).
Updated Switching Characteristics (Removed 250 MHz, 200 MHz and
167 MHz frequencies related information).
PRIT
No technical updates. Completing sunset review.
Page 21 of 22
CY7C1328G
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
PSoC Solutions
cypress.com/go/automotive
psoc.cypress.com/solutions
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 5
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
Optical & Image Sensing
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2006-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05523 Rev. *J
Revised September 25, 2012
Page 22 of 22
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may be the trademarks of their respective holders.