LINER LTC1605IN 16-bit, 100ksps, sampling adc Datasheet

LTC1605
16-Bit, 100ksps,
Sampling ADC
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FEATURES
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DESCRIPTIO
The LTC ®1605 is a 100ksps, sampling 16-bit A/D converter that draws only 55mW (typical) from a single 5V
supply. This easy-to-use device includes sample-andhold, precision reference, switched capacitor successive
approximation A/D and trimmed internal clock.
Single 5V Supply
Bipolar Input Range: ±10V
Power Dissipation: 55mW Typ
Guaranteed No Missing Codes
Sample Rate: 100ksps
Integral Nonlinearity: ±2.0LSB Max
Signal-to-Noise Ratio: 86dB Typ
Operates with Internal or External Reference
Internal Synchronized Clock
Improved 2nd Source to ADS7805 and AD976
28-Pin 0.3” PDIP, SSOP and SW Packages
The LTC1605’s input range is an industry standard ±10V.
Maximum DC specs include ±2.0LSB INL and 16-bits no
missing codes over temperature. An external reference
can be used if greater accuracy over temperature is
needed.
The ADC has a microprocessor compatible, 16-bit or two
byte parallel output port. A convert start input and a data
ready signal (BUSY) ease connections to FIFOs, DSPs and
microprocessors.
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APPLICATIO S
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Industrial Process Control
Multiplexed Data Acquisition Systems
High Speed Data Acquisition for PCs
Digital Signal Processing
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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TYPICAL APPLICATIO
Typical INL Curve
Low Power, 100kHz, 16-Bit Sampling ADC on 5V Supply
2.0
5V
1.5
0.1µF
10µF
28
27
1.0
±10V 200Ω
INPUT
1 VIN
6 TO 13
15 TO 22
20k
16-BIT
SAMPLING ADC
33.2k
4k
D15 TO D0
16-BIT
OR 2 BYTE
PARALLEL
BUS
10k
0.5
0
–0.5
–1.0
4 CAP
–1.5
BUSY 26
2.2µF
BUFFER
3 REF
INL (LSBs)
VDIG VANA
CONTROL
LOGIC AND
TIMING
4k
REFERENCE
CS 25
R/C 24
–2.0
DIGITAL
CONTROL
SIGNALS
0
16384
32768
49152
65535
CODE
1605 • TA02
BYTE 23
2.2µF
AGND1
2
AGND2
5
DGND
14
1605 • TA01
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LTC1605
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ABSOLUTE
PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
TOP VIEW
VANA .......................................................................... 7V
VDIG to VANA ........................................................... 0.3V
VDIG ........................................................................... 7V
Ground Voltage Difference
DGND, AGND1 and AGND2 .............................. ±0.3V
Analog Inputs (Note 3)
VIN ..................................................................... ±25V
CAP ............................ VANA + 0.3V to AGND2 – 0.3V
REF .................................... Indefinite Short to AGND2
Momentary Short to VANA
Digital Input Voltage (Note 4) ........ DGND – 0.3V to 10V
Digital Output Voltage ........ VDGND – 0.3V to VDIG + 0.3V
Power Dissipation .............................................. 500mW
Operating Ambient Temperature Range
LTC1605C ............................................... 0°C to 70°C
LTC1605I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
VIN 1
28 VDIG
AGND1 2
27 VANA
REF 3
26 BUSY
CAP 4
25 CS
AGND2 5
24 R/C
D15 (MSB) 6
23 BYTE
D14 7
22 D0
D13 8
21 D1
D12 9
20 D2
D11 10
19 D3
D10 11
18 D4
D9 12
17 D5
D8 13
16 D6
DGND 14
15 D7
N PACKAGE
28-LEAD PDIP
SW PACKAGE
G PACKAGE
28-LEAD PLASTIC SO WIDE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/W (G)
TJMAX = 125°C, θJA = 130°C/W (N)
TJMAX = 125°C, θJA = 130°C/W (SW)
ORDER PART NUMBER
LTC1605CN
LTC1605ACG
LTC1605CSW
LTC1605ACSW
LTC1605IG
LTC1605AIG
LTC1605IN
LTC1605AISW
LTC1605ISW
LTC1605CG
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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CONVERTER CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With external reference (Notes 5, 6).
PARAMETER
CONDITIONS
MIN
Resolution
●
16
No Missing Codes
●
15
Transition Noise
LTC1605
TYP
MAX
(Note 7)
●
Bipolar Zero Error
Ext. Reference = 2.5V (Note 8)
●
LTC1605A
TYP
MAX
16
UNITS
Bits
16
1.0
Integral Linearity Error
MIN
Bits
1.0
±3
LSB
±2
±10
±10
LSB
mV
Bipolar Zero Error Drift
±2
±2
ppm/°C
Full-Scale Error Drift
±7
±5
ppm/°C
Full-Scale Error
Ext. Reference = 2.5V (Notes 12, 13)
Full-Scale Error Drift
Ext. Reference = 2.5V
Power Supply Sensitivity
VANA = VDIG = VDD
VDD = 5V ±5% (Note 9)
±0.50
●
±2
±0.25
±2
±8
%
ppm/°C
±8
LSB
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LTC1605
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ANALOG INPUT
The ● denotes specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIN
CIN
Analog Input Range (Note 9)
Analog Input Capacitance
4.75V ≤ VANA ≤ 5.25V, 4.75V ≤ VDIG ≤ 5.25V
RIN
Analog Input Impedance
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DYNAMIC ACCURACY
MIN
●
LTC1605/LTC1605A
TYP
MAX
UNITS
±10
10
V
pF
20
kΩ
(Notes 5, 14)
PARAMETER
Signal-to-(Noise + Distortion) Ratio
CONDITIONS
1kHz Input Signal (Note 14)
10kHz Input Signal
20kHz, – 60dB Input Signal
THD
Total Harmonic Distortion
1kHz Input Signal, First 5 Harmonics
10kHz Input Signal, First 5 Harmonics
– 102
– 94
dB
dB
Peak Harmonic or Spurious Noise
1kHz Input Signal
10kHz Input Signal
– 102
– 94
dB
dB
Full-Power Bandwidth
Aperture Delay
(Note 15)
275
40
kHz
ns
Aperture Jitter
Transient Response
Full-Scale Step (Note 9)
Overvoltage Recovery
(Note 16)
MIN
LTC1605/LTC1605A
TYP
MAX
87.5
87
30
SYMBOL
S/(N + D)
Sufficient to Meet AC Specs
2
150
UNITS
dB
dB
dB
µs
ns
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INTERNAL REFERENCE CHARACTERISTICS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
VREF Output Voltage
CONDITIONS
IOUT = 0
VREF Output Tempco
Internal Reference Source Current
IOUT = 0
External Reference Voltage for Specified Linearity
External Reference Current Drain
(Notes 9, 10)
Ext. Reference = 2.5V (Note 9)
CAP Output Voltage
IOUT = 0
●
LTC1605/LTC1605A
MIN
TYP
MAX
2.470
2.500
2.520
UNITS
V
±5
1
ppm/°C
µA
2.30
2.50
●
2.70
100
V
µA
2.50
V
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DIGITAL INPUTS AND DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
VIH
PARAMETER
High Level Input Voltage
CONDITIONS
VDD = 5.25V
VIL
IIN
Low Level Input Voltage
Digital Input Current
VDD = 4.75V
VIN = 0V to VDD
CIN
VOH
Digital Input Capacitance
High Level Output Voltage
VDD = 4.75V
●
MIN
2.4
LTC1605/LTC1605A
TYP
MAX
●
0.8
±10
●
5
4.5
IO = –10µA
IO = – 200µA
●
4.0
UNITS
V
V
µA
pF
V
V
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LTC1605
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DIGITAL INPUTS AND DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
MIN
LTC1605/LTC1605A
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
VOL
Low Level Output Voltage
VDD = 4.75V
IOZ
COZ
Hi-Z Output Leakage D15 to D0
Hi-Z Output Capacitance D15 to D0
VOUT = 0V to VDD, CS High
CS High (Note 9)
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
IO = 160µA
IO = 1.6mA
0.05
0.10
●
●
●
UNITS
0.4
V
V
±10
15
µA
pF
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TIMING CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
CONDITIONS
MIN
LTC1605/LTC1605A
TYP
MAX
SYMBOL
PARAMETER
fSAMPLE(MAX)
Maximum Sampling Frequency
●
tCONV
Conversion Time
●
tACQ
Acquisition Time
t1
Convert Pulse Width
(Note 11)
●
t2
Data Valid Delay After R/C↓
(Note 9)
●
8
µs
t3
BUSY Delay from R/C↓
CL = 50pF
●
65
ns
t4
BUSY Low
8
µs
t5
BUSY Delay After End of Conversion
220
t6
Aperture Delay
40
t7
Bus Relinquish Time
●
10
35
t8
BUSY Delay After Data Valid
●
50
200
ns
t9
Previous Data Valid After R/C↓
7.4
µs
t10
R/C to CS Setup Time
t11
Time Between Conversions
t12
Bus Access and Byte Delay
100
kHz
8
●
(Notes 9, 10)
(Notes 9, 10)
UNITS
2
40
µs
µs
ns
ns
ns
83
ns
10
ns
10
µs
10
83
ns
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POWER REQUIREMENTS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
LTC1605/LTC1605A
TYP
MAX
VDD
Positive Supply Voltage
(Notes 9, 10)
4.75
5.25
IDD
Positive Supply Current
PDIS
Power Dissipation
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above VANA =
VDIG = VDD, they will be clamped by internal diodes. This product can
handle input currents of greater than 100mA below ground or above VDD
without latch-up.
●
UNITS
V
11
16
mA
55
80
mW
Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents of
90mA below ground without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a VIN input
with respect to ground.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
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LTC1605
ELECTRICAL CHARACTERISTICS
Note 8: Bipolar offset is the offset voltage measured from – 0.5 LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: With CS low the falling R/C edge starts a conversion. If R/C
returns high at a critical point during the conversion it can create small
errors. For best results ensure that R/C returns high within 3µs after the
start of the conversion.
Note 12: As measured with fixed resistors shown in Figure 4. Adjustable to
zero with external potentiometer.
Note 13: Full-scale error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions, divided by the transition
voltage (not divided by the full-scale range) and includes the effect of
offset error.
Note 14: All specifications in dB are referred to a full-scale ±10V input.
Note 15: Full-power bandwidth is defined as full-scale input frequency at
which a signal-to-(noise + distortion) degrades to 60dB or 10 bits of
accuracy.
Note 16: Recovers to specified performance after (2 • FS) input
overvoltage.
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TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Supply Voltage
12.5
12.0
50
fSAMPLE = 100kHz
11.5
11.0
10.5
10.0
40
CHANGE IN CAP VOLTAGE (mV)
POSITIVE SUPPLY CURRENT (mA)
fSAMPLE = 100kHz
12.0
SUPPLY CURRENT (mA)
Change in CAP Voltage vs
Load Current
Supply Current vs Temperature
11.5
11.0
10.5
30
20
10
0
–10
–20
–30
–40
9.5
4.50
4.75
5.00
5.25
5.50
10.0
–50
SUPPLY VOLTAGE (V)
–25
0
25
50
TEMPERATURE (°C)
1605 • TPC01
1.5
1.0
1.0
0.5
0.5
–0.5
–0.5
–1.0
–1.5
–1.5
–2.0
32768
49152
65535
CODE
–2.0
0
16384
32768
–30
–40
–50
–60
–70
49152
65535
CODE
1605 • TPC04
25
–20
0
–1.0
5
15
–5
LOAD CURRENT (mA)
Power Supply Feedthrough vs
Ripple Frequency
POWER SUPPLY FEEDTHROUGH (dB)
1.5
DNL (LSBs)
INL (LSBs)
2.0
0
–15
1605 TPC03
Typical DNL Curve
2.0
16384
–50
–25
100
1605 • TPC02
Typical INL Curve
0
75
1605 • TPC05
1
10
100
1k
10k 100k
RIPPLE FREQUENCY (Hz)
1M
1605 • TPC06
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LTC1605
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TYPICAL PERFORMANCE CHARACTERISTICS
MAGNITUDE (dB)
LTC1605 Nonaveraged 4096 Point FFT Plot
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 87.5dB
THD = –101.7dB
0
5
10
15
20
25
30
FREQUENCY (kHz)
35
45
50
1605 • TPC07
Total Harmonic Distortion vs
Input Frequency
SINAD vs Input Frequency
90
–70
TOTAL HARMONIC DISTORTION (dB)
89
88
87
SINAD (dB)
40
86
85
84
83
82
–80
–90
–100
–110
81
1
10
INPUT FREQUENCY (kHz)
100
1
10
INPUT FREQUENCY (kHz)
1605 • TPC08
100
1605 • TPC09
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PIN FUNCTIONS
VIN (Pin 1): Analog Input. Connect through a 200Ω
resistor to the analog input. Full-scale input range is
±10V.
AGND1 (Pin 2): Analog Ground. Tie to analog ground
plane.
AGND2 (Pin 5): Analog Ground. Tie to analog ground
plane.
D15 to D8 (Pins 6 to 13): Three-State Data Outputs.
Hi-Z state when CS is high or when R/C is low.
DGND (Pin 14): Digital Ground.
REF (Pin 3): 2.5V Reference Output. Bypass with 2.2µF
tantalum capacitor. Can be driven with an external reference.
D7 to D0 (Pins 15 to 22): Three-State Data Outputs.
Hi-Z state when CS is high or when R/C is low.
CAP (Pin 4): Reference Buffer Output. Bypass with 2.2µF
tantalum capacitor.
BYTE (Pin 23): Byte Select. With BYTE low, data will be
output with Pin 6 (D15) being the MSB and Pin 22 (D0)
being the LSB. With BYTE high the upper eight bits and
the lower eight bits will be switched. The MSB is output
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LTC1605
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PIN FUNCTIONS
on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on
Pin 6 and the LSB is output on Pin 13.
R/C (Pin 24): Read/Convert Input. With CS low, a falling
edge on R/C puts the internal sample-and-hold into the
hold state and starts a conversion. With CS low, a rising
edge on R/C enables the output data bits.
CS (Pin 25): Chip Select. Internally OR’d with R/C. With
R/C low, a falling edge on CS will initiate a conversion.
With R/C high, a falling edge on CS will enable the output
data.
BUSY (Pin 26): Output Shows Converter Status. It is low
when a conversion is in progress. Data valid on the rising
edge of BUSY. CS or R/C must be high when BUSY rises
or another conversion will start without time for signal
acquisition.
VANA (Pin 27): 5V Analog Supply. Bypass to ground with
a 0.1µF ceramic and a 10µF tantalum capacitor.
VDIG (Pin 28): 5V Digital Supply. Connect directly to Pin
27.
TEST CIRCUITS
Load Circuit for Output Float Delay
Load Circuit for Access Timing
5V
5V
1k
DBN
1k
DBN
1k
CL
DBN
CL
DBN
1k
50pF
50pF
LTC1605 • TC02
LTC1605 • TC01
A. HI-Z TO VOH AND VOL TO VOH
B. HI-Z TO VOL AND VOH TO VOL
A. VOH TO HI-Z
B. VOL TO HI-Z
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FUNCTIONAL BLOCK DIAGRA
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VIN
CSAMPLE
20k
10k
4k
VANA
CSAMPLE
REF
VDIG
ZEROING SWITCHES
4k
2.5V REF
+
REF BUF
COMP
16-BIT CAPACITIVE DAC
–
CAP
(2.5V)
16
SUCCESSIVE APPROXIMATION
REGISTER
AGND1
•
•
•
OUTPUT LATCHES
D15
D0
AGND2
DGND
INTERNAL
CLOCK
CONTROL LOGIC
LTC1605 • BD
CS
R/C
BYTE
BUSY
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LTC1605
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APPLICATIONS INFORMATION
Conversion Details
Driving the Analog Inputs
The LTC1605 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 16-bit or two byte parallel output. The
ADC is complete with a precision reference and an internal
clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface
section for the data format.)
The nominal input range for the LTC1605 is ±10V or
(±4 • VREF) and the input is overvoltage protected to ±25V.
The input impedance is typically 20kΩ, therefore, it should
be driven with a low impedance source. Wideband noise
coupling into the input can be minimized by placing a
1000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
capacitor as close to the device input pin as possible. If an
amplifier is to be used to drive the input, care should be
taken to select an amplifier with adequate accuracy, linearity and noise for the application. The following list is a
summary of the op amps that are suitable for driving the
LTC1605. More detailed information is available in the
Linear Technology data books and LinearViewTM CD-ROM.
Conversion start is controlled by the CS and R/C inputs. At
the start of conversion the successive approximation
register (SAR) is reset. Once a conversion cycle has begun
it cannot be restarted.
During the conversion, the internal 16-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, VIN is connected through the resistor divider to
the sample-and-hold capacitor during the acquire phase
and the comparator offset is nulled by the autozero switches.
In this acquire phase, a minimum delay of 2µs will provide
enough time for the sample-and-hold capacitor to acquire
the analog signal. During the convert phase, the autozero
switches open, putting the comparator into the compare
mode. The input switch switches CSAMPLE to ground,
injecting the analog input charge onto the summing junction. This input charge is successively compared with the
binary-weighted charges supplied by the capacitive DAC.
Bit decisions are made by the high speed comparator. At
the end of a conversion, the DAC output balances the VIN
input charge. The SAR contents (a 16-bit data word) that
represents the VIN are loaded into the 16-bit output latches.
SAMPLE
RIN1
SAMPLE
SI
CSAMPLE
RIN2
200Ω
VIN
1000pF
33.2k
CAP
1605 • F02
Figure 2. Analog Input Filtering
LT1007 - Low noise precision amplifier. 2.7mA supply
current ±5V to ±15V supplies. Gain bandwidth product
8MHz. DC applications.
LT1097 - Low cost, low power precision amplifier. 300µA
supply current. ±5V to ±15V supplies. Gain bandwidth
product 0.7MHz. DC applications.
LT1227 - 140MHz video current feedback amplifier. 10mA
supply current. ±5V to ±15V supplies. Low noise and low
distortion.
LT1360 - 37MHz voltage feedback amplifier. 3.8mA supply current. ±5V to ±15V supplies. Good AC/DC specs.
–
VIN
AIN
HOLD
LT1363 - 50MHz voltage feedback amplifier. 6.3mA supply current. Good AC/DC specs.
+
CDAC
COMPARATOR
DAC
VDAC
S
A
R
LT1364/LT1365 - Dual and quad 50MHz voltage feedback
amplifiers. 6.3mA supply current per amplifier. Good AC/
DC specs.
16-BIT
LATCH
1605 • F01
Figure 1. LTC1605 Simplified Equivalent Circuit
LinearView is a trademark of Linear Technology Corporation
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LTC1605
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APPLICATIONS INFORMATION
The LTC1605 has an on-chip, temperature compensated,
curvature corrected, bandgap reference, which is factory
trimmed to 2.50V. The full-scale range of the ADC is equal
to (±4 • VREF) or nominally ±10V. The output of the
reference is connected to the input of a unity-gain buffer
through a 4k resistor (see Figure 3). The input to the buffer
or the output of the reference is available at REF (Pin 3).
The internal reference can be overdriven with an external
reference if more accuracy is needed. The buffer output
drives the internal DAC and is available at CAP (Pin 4). The
CAP pin can be used to drive a steady DC load of less than
2mA. Driving an AC load is not recommended because it
can cause the performance of the converter to degrade.
REF
(2.5V)
4k
3
BANDGAP
REFERENCE
S
2.2µF
+
applied to VIN and R4 is adjusted until the output code is
changing between 0111 1111 1111 1110 and 0111 1111
1111 1111. Figure 6 shows the bipolar transfer characteristic of the LTC1605.
±10V INPUT
1
2
200Ω
1%
33.2k
1%
4
2.2µF
5
VIN
AGND1
LTC1605
REF
CAP
AGND2
1605 • F04
Figure 4. ±10V Input Without Trim
1
±10V INPUT
2
200Ω
1%
+
VANA
VIN
AGND1
2.2µF
3
5V
REF
LTC1605
576k
–
R4
50k
4
S
2.2µF
2.2µF
3
+
33.2k
1%
CAP
(2.5V)
+
Internal Voltage Reference
R3
50k
INTERNAL
CAPACITOR
DAC
4
+
CAP
2.2µF
5
AGND2
1605 • F05
1605 • F03
Figure 5. ±10V Input with Offset and Gain Trim
Figure 3. Internal or External Reference Source
Offset and Gain Adjustments
The LTC1605 offset and full-scale errors have been trimmed
at the factory with the external resistors shown in Figure 4.
This allows for external adjustment of offset and full scale
in applications where absolute accuracy is important. See
Figure 5 for the offset and gain trim circuit. First adjust the
offset to zero by adjusting resistor R3. Apply an input
voltage of –152.6mV (– 0.5LSB) and adjust R3 so the code
is changing between 1111 1111 1111 1111 and 0000 0000
0000 0000. The gain error is trimmed by adjusting resistor
R4. An input voltage of 9.999542V (+FS – 1.5LSB) is
011...111
BIPOLAR
ZERO
011...110
OUTPUT CODE
For minimum code transition noise the REF pin and the
CAP pin should each be decoupled with a capacitor to
filter wideband noise from the reference and the buffer
(2.2µF tantalum).
000...001
000...000
111...111
111...110
100...001
FS = 20V
1LSB = FS/65536
100...000
–FS/2
–1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
FS/2 – 1LSB
1605 • F06
Figure 6. LTC1605 Bipolar Transfer Characteristics
DC Performance
One way of measuring the transition noise associated with
a high resolution ADC is to use a technique where a DC
1605fc
9
LTC1605
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APPLICATIONS INFORMATION
signal is applied to the input of the ADC and the resulting
output codes are collected over a large number of conversions. For example in Figure 7 the distribution of output
code is shown for a DC input that has been digitized 10000
times. The distribution is Gaussian and the RMS code
transition is about 1LSB.
4500
4000
3500
COUNT
3000
2500
2000
1500
1000
500
0
–5 –4 –3 –2 –1 0 1
CODE
2
3
4
5
1605 • F07
Figure 7. Histogram for 10000 Conversions
DIGITAL INTERFACE
Internal Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 7µs. No external adjustments
are required and, with the typical acquisition time of 1µs,
throughput performance of 100ksps is assured.
Timing and Control
Conversion start and data read are controlled by two
digital inputs: CS and R/C. To start a conversion and put
the sample-and-hold into the hold mode bring CS and
R/C low for no less than 40ns. Once initiated it cannot be
restarted until the conversion is complete. Converter
status is indicated by the BUSY output and this is low while
the conversion is in progress.
There are two modes of operation. The first mode is shown
in Figure 8. The digital input R/C is used to control the start
of conversion. CS is tied low. When R/C goes low the
sample-and-hold goes into the hold mode and a conversion is started. BUSY goes low and stays low during the
conversion and will go back high after the conversion has
been completed and the internal output shift registers
have been updated. R/C should remain low for no less than
40ns. During the time R/C is low the digital outputs are in
a Hi-Z state. R/C should be brought back high within 3µs
after the start of the conversion to ensure that no errors
occur in the digitized result. The second mode, shown in
Figure 9, uses the CS signal to control the start of a
conversion and the reading of the digital output. In this
mode the R/C input signal should be brought low no less
than 10ns before the falling edge of CS. The minimum
pulse width for CS is 40ns. When CS falls, BUSY goes low
and will stay low until the end of the conversion. BUSY will
go high after the conversion has been completed. The new
data is valid when CS is brought back low again to initiate
t1
R/C
t 11
t2
t4
t3
BUSY
t6
MODE
t5
ACQUIRE
CONVERT
ACQUIRE
t CONV
t ACQ
CONVERT
t9
DATA MODE
PREVIOUS
DATA VALID
HI-Z
t7
PREVIOUS
DATA VALID
DATA
VALID
NOT VALID
HI-Z
t8
DATA
VALID
1605 • F08
Figure 8. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low)
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APPLICATIONS INFORMATION
t 10
t 10
t 10
t 10
R/C
t1
t1
CS
t3
t4
BUSY
t6
MODE
ACQUIRE
CONVERT
ACQUIRE
t CONV
HI-Z
DATA BUS
DATA
VALID
t 12
t7
HI-Z
1605 • F09
Figure 9. Using CS to Control Conversion and Read Timing
t 10
t 10
R/C
CS
BYTE
HI-Z
PINS 6 TO 13
HIGH BYTE
t 12
t 12
HI-Z
PINS 15 TO 22
HI-Z
LOW BYTE
t7
LOW BYTE
HI-Z
HIGH BYTE
1605 • F03
MAGNITUDE (dB)
Figure 10. Using CS and BYTE to Control Data Bus Read Timing
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 87.5dB
THD = –101.7dB
0
5
10
15
20
25
30
FREQUENCY (kHz)
35
40
45
50
1605 • F11
Figure 11. LTC1605 Nonaveraged 4096 Point FFT Plot
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11
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APPLICATIONS INFORMATION
a read. Again it is recommended that both R/C and CS
return high within 3µs after the start of the conversion.
Output Data
The output data can be read as a 16-bit word or it can be
read as two 8-bit bytes. The format of the output data is
two’s complement. The digital input pin BYTE is used to
control the two byte read. With the BYTE pin low the first
eight MSBs are output on the D15 to D8 pins and the eight
LSBs are output on the D7 to D0 pins. When the BYTE pin
is taken high the eight LSBs replace the eight MSBs (Figure
10).
Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 11 shows a
typical LTC1605 FFT plot which yields a SINAD of 87.5dB
and THD of – 102dB.
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 11 shows a typical SINAD of 87.5dB
with a 100kHz sampling rate and a 1kHz input.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD = 20log
√V22 + V32 + V42 ... + VN2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
Board Layout, Power Supplies and Decoupling
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best
performance from the LTC1605, a printed circuit board is
required. Layout for the printed circuit board should
ensure the digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC. The analog input should be screened
by AGND.
Figures 12 through 15 show a layout for a suggested
evaluation circuit which will help obtain the best performance from the 16-bit ADC. Pay particular attention to the
design of the analog and digital ground planes. The DGND
pin of the LTC1605 can be tied to the analog ground plane.
Placing the bypass capacitor as close as possible to the
power supply, the reference and reference buffer output is
very important. Low impedance common returns for
these bypass capacitors are essential to low noise operation of the ADC, and the foil width for these tracks should
be as wide as possible. Also, since any potential difference
in grounds between the signal source and ADC appears as
an error voltage in series with the input signal, attention
should be paid to reducing the ground circuit impedance
as much as possible. The digital output latches and the
onboard sampling clock have been placed on the digital
ground plane. The two ground planes are tied together at
the power supply ground connection.
1605fc
12
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APPLICATIONS INFORMATION
Figure 12. Component Side Silkscreen for the Suggested LTC1605 Evaluation Circuit
ANALOG
GROUND PLANE
DIGITAL
GROUND PLANE
Figure 13. Bottom Side Showing Analog Ground Plane
ANALOG
GROUND PLANE
Figure 14. Component Side Showing Separate Analog
and Digital Ground Plane
1605fc
13
2
1
2
1
2
R17
51
GND
NA
OUT
U8
1MHz, OSC
EXT_CLK
1
J1
J2
AIN
GND
E2
3
3
4
3
2
1
2
3
4
5
6
7
10
9
1
8
CLK
LOAD
ENP
ENT
A
B
C
TRIM
OUT
QA
QB
QC
QD
RCO
14
13
12
11
15
5
6
7
8
JP1
R18
200Ω
1%
VCC
R21, 2k
3
15
2
1
JP4
2
CLK
13
CS
VCC 3
VCC
Q
Q
JP5
2
C3
0.1µF
C4
2.2µF
C16
1000pF
C9
0.1µF
C8
0.1µF
C7
10µF
VKK
C5
0.1µF
R19
33.2k
1%
C10
0.1µF
28
27
26
25
24
23
14
5
4
3
2
1
VDIG
VANA
BUSY
CS
R/C
BYTE
DGND
AGND2
CAP
REF
AGND1
VIN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
U1
LTC1605
C11
0.1µF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
U4B
74HC04
3
4
22
21
20
19
18
17
16
15
13
12
11
10
9
8
7
6
C12
0.1µF
R20
1K
C13
0.1µF
4
9
8
7
6
5
1
11
9
C1
15PF
D7
8
D6
6
7
D5
D4
4
5
D2
3
2
11
1
2
3
D3
D1
D0
D8
D9
D10
D11
D12
D13
D14
D15
C14
0.1µF
Figure 15. LTC1605 Suggested Evaluation Circuit Schematic
GND 1
RCEXT
CEXT
B
A
4
C2
2.2µF
U6A
74HC221
NORNAL 1
BYTE
REVERSE 3
C17
10µF
EXT VREF INT
VCC VDD
JP3
2
C6
22µF
10V
R16
20
INT 1 VCC
CLK
EXT 3
U4E
74HC04
11
10
U9
LT1019-2.5
GND
TEMP
CLR
D
NC2
+
VKK
INPUT HEATER
NC1
D16
MBR0520
U7
74HC160
U4D
74HC04
VCC
9
VKK
VIN
U5
LT1121
GND
2
VIN
7V TO 15V
1
E1
VIN
VCC
Q0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
U4C
74HC04
5
6
CLK
OC
D7
D6
D5
D4
D3
D2
D1
D0
U3
74HC574
CLK
OC
D7
D6
D5
D4
D3
D2
D1
D0
U2
74HC574
C15
10µF
19
12
13
14
15
16
17
18
19
1
U4A
74HC04
12
13
14
15
16
17
18
2
R0, 1.2k
R1, 1.2k
R2, 1.2k
R3, 1.2k
R4, 1.2k
R5, 1.2k
R6, 1.2k
R7, 1.2k
R8, 1.2k
R9, 1.2k
R10, 1.2k
R11, 1.2k
R12, 1.2k
R13, 1.2k
R14, 1.2k
1
D13
14
20
19
18
17
16
15
D0
D1
D2
D3
D4
D5
D6
GND
GND
CLK
D15
D0
D1
D2
D3
D4
13
12
D6
D7
D8
D9
D10
D11
D12
D5
D7
D15
D14
11
10
9
8
7
6
5
4
3
2
D8
D9
D10
D11
D12
D13
D14
D15
1605_07d.eps
JP2
LED
ENABLE
U
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DIGITAL I.C. BYPASSING
APPLICATIONS INFORMATION
U
R15, 1.2k
LTC1605
1605fc
LTC1605
U
PACKAGE DESCRIPTION
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
9.90 – 10.50*
(.390 – .413)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
0.42 ±0.03
7.40 – 8.20
(.291 – .323)
0.65 BSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
5.00 – 5.60**
(.197 – .221)
2.0
(.079)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.65
(.0256)
BSC
0.55 – 0.95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
0.05
(.002)
0.22 – 0.38
(.009 – .015)
G28 SSOP 0802
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
N Package
28-Lead PDIP (Narrow 0.300 Inch)
(Reference LTC DWG # 05-08-1510)
1.370*
(34.789)
MAX
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
.255 ± .015*
(6.477 ± 0.381)
.300 – .325
(7.620 – 8.255)
.130 ± .005
(3.302 ± 0.127)
.045 – .065
(1.143 – 1.651)
.020
(0.508)
MIN
.008 – .015
(0.203 – 0.381)
(
+.035
.325 –.015
+0.889
8.255
–0.381
)
.120
(3.048)
MIN
.065
(1.651)
TYP
.005
(0.127)
MIN
.100
(2.54)
BSC
.018 ± .003
(0.457 ± 0.076)
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
N28 1002
1605fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1605
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PACKAGE DESCRIPTION
SW Package
28-Lead Plastic Small Outline (Wide 0.300 Inch)
(Reference LTC DWG # 05-08-1620)
.050 BSC .045 ±.005
.030 ±.005
TYP
.697 – .712
(17.70 – 18.08)
NOTE 4
N
28
26
25
24
23
22
21
20
19
18
17
16
15
N
.325 ±.005
.420
MIN
27
.394 – .419
(10.007 – 10.643)
NOTE 3
1
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT
.005
(0.127)
RAD MIN
.009 – .013
(0.229 – 0.330)
.291 – .299
(7.391 – 7.595)
NOTE 4
.010 – .029 × 45°
(0.254 – 0.737)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
.037 – .045
(0.940 – 1.143)
.093 – .104
(2.362 – 2.642)
0° – 8° TYP
.050
(1.270)
BSC
NOTE 3
.004 – .012
(0.102 – 0.305)
.014 – .019
(0.356 – 0.482)
TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
S28 (WIDE) 0502
RELATED PARTS
PART NUMBER
DESCRIPTION
LT ® 1019-2.5
COMMENTS
Precision Bandgap Reference
0.05% Max, 5ppm/°C Max
LTC1274/LTC1277
Low Power 12-Bit, 100ksps ADCs
10mW Power Dissipation, Parallel/Byte Interface
LTC1415
Single 5V, 12-Bit, 1.25Msps ADC
55mW Power Dissipation, 72dB SINAD
LTC1419
Low Power 14-Bit, 800ksps ADC
True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation
LT1460-2.5
Micropower Precision Series Reference
0.075% Max, 10ppm/°C Max, Only 130µA Supply Current
LTC1594/LTC1598
Micropower 4-/8-Channel 12-Bit ADCs
Serial I/O, 3V and 5V Versions
1605fc
16
Linear Technology Corporation
LT 0106 REV C • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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© LINEAR TECHNOLOGY CORPORATION 2005