GAL®16V8 Device Datasheet September 2010 All Devices Discontinued! Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line GAL16V8C GAL16V8D Ordering Part Number GAL16V8C-5LP GAL16V8C-7LP GAL16V8D-7LP GAL16V8D-7LPN GAL16V8D-10LP GAL16V8D-10LPN GAL16V8D-15LP GAL16V8D-15LPN GAL16V8D-25LP GAL16V8D-25LPN GAL16V8D-7LPI GAL16V8D-7LPNI GAL16V8D-10LPI GAL16V8D-10LPNI GAL16V8D-15LPI GAL16V8D-15LPNI GAL16V8D-25LPI GAL16V8D-25LPNI GAL16V8D-10QP GAL16V8D-10QPN GAL16V8D-15QP GAL16V8D-15QPN GAL16V8D-25QP GAL16V8D-25QPN GAL16V8D-20QPI GAL16V8D-20QPNI GAL16V8D-25QPI GAL16V8D-25QPNI GAL16V8D-3LJ GAL16V8D-3LJN GAL16V8D-5LJ GAL16V8D-5LJN Product Status Reference PCN PCN#06-07 PCN#13-10 PCN#09-10 Discontinued PCN#13-10 PCN#06-07 PCN#13-10 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347 Internet: http://www.latticesemi.com Product Line GAL16V8D (Cont’d) Ordering Part Number GAL16V8D-7LJ GAL16V8D-7LJN GAL16V8D-10LJ GAL16V8D-10LJN GAL16V8D-15LJ GAL16V8D-15LJN GAL16V8D-25LJ GAL16V8D-25LJN GAL16V8D-7LJI GAL16V8D-7LJNI GAL16V8D-10LJI GAL16V8D-10LJNI GAL16V8D-15LJI GAL16V8D-15LJNI GAL16V8D-25LJI GAL16V8D-25LJNI GAL16V8D-10QJ GAL16V8D-10QJN GAL16V8D-15QJ GAL16V8D-15QJN GAL16V8D-25QJ GAL16V8D-25QJN GAL16V8D-20QJI GAL16V8D-20QJNI GAL16V8D-25QJI GAL16V8D-25QJNI GAL16V8D-7LS GAL16V8D-10LS GAL16V8D-15LS GAL16V8D-25LS Product Status Reference PCN PCN#13-10 PCN#09-10 Discontinued PCN#13-10 PCN#06-07 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347 Internet: http://www.latticesemi.com ree Lead-Fage P a c k ns Optio le! b Availa Features • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 3.0 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology GAL16V8 High Performance E2CMOS PLD Generic Array Logic™ Functional Block Diagram I/CLK CLK 8 OLMC I/O/Q 8 OLMC I/O/Q I A D LL IS C DE O N VIC TI N ES U ED • 50% to 75% REDUCTION IN POWER FROM BIPOLAR — 75mA Typ Icc on Low Power Device — 45mA Typ Icc on Quarter Power Device I • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention PROGRAMMABLE AND-ARRAY (64 X 32) • ACTIVE PULL-UPS ON ALL PINS I I • EIGHT OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity — Also Emulates 20-pin PAL® Devices with Full Function/Fuse Map/Parametric Compatibility I • APPLICATIONS INCLUDE: — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade • LEAD-FREE PACKAGE OPTIONS OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q I • PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability • ELECTRONIC SIGNATURE FOR IDENTIFICATION 8 I I OE I/OE Pin Configuration PLCC Description I The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. I I/CLK Vcc 2 20 I/O/Q 18 4 I I I I/O/Q GAL16V8 16 6 Top View I The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL16V8 are the PAL architectures listed in the table of the macrocell description section. GAL16V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. 8 14 9 I GND 11 13 I/OE I/O/Q I/O/Q SOIC I/CLK 1 I/O/Q I/O/Q 5 I I I GND GAL 16V8 Top View 1 I/O/Q I/O/Q 15 20 I I GAL 16V8 I I 5 15 Vcc I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q Vcc I I I I/O/Q I/CLK I 20 I I Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. I/O/Q I/O/Q I DIP I/O/Q I I/O/Q I I/O/Q I I/O/Q I/O/Q I/O/Q GND 10 11 I/OE I/O/Q I/O/Q 10 11 I/OE Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 16v8_11 1 August 2006 Specifications GAL16V8 GAL16V8 Ordering Information Conventional Packaging Commercial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) 3.5 2.5 3. 0 115 GAL16V8D-3LJ1 5 3 4 115 1 7 5 GAL16V8C-5LP 115 GAL16V8D-5LJ 115 GAL16V8D-7LP Package 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP A D LL IS C DE O N VIC TI N ES U ED 7.5 Ordering # 10 15 25 10 12 15 7 10 12 115 GAL16V8C-7LP 20-Pin Plastic DIP 115 GAL16V8D-7LJ 20-Lead PLCC 115 GAL16V8D-7LS1 20-Pin SOIC 55 GAL16V8D-10QP 20-Pin Plastic DIP 55 GAL16V8D-10QJ 20-Lead PLCC 1 115 GAL16V8D-10LP 20-Pin Plastic DIP 115 GAL16V8D-10LJ 20-Lead PLCC 115 GAL16V8D-10LS1 20-Pin SOIC 55 GAL16V8D-15QP 20-Pin Plastic DIP 55 GAL16V8D-15QJ 20-Lead PLCC 90 GAL16V8D-15LP 20-Pin Plastic DIP 90 GAL16V8D-15LJ 20-Lead PLCC 90 GAL16V8D-15LS 20-Pin SOIC 55 GAL16V8D-25QP 20-Pin Plastic DIP 55 GAL16V8D-25QJ 20-Lead PLCC 90 GAL16V8D-25LP 20-Pin Plastic DIP 90 GAL16V8D-25LJ 90 1 20-Lead PLCC 1 20-Pin SOIC GAL16V8D-25LS 1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory. Industrial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) 7.5 7 5 Icc (mA) 130 Ordering # Package GAL16V8D-7LPI 20-Pin Plastic DIP 130 GAL16V8D-7LJI 20-Lead PLCC 10 10 7 130 GAL16V8D-10LPI 20-Pin Plastic DIP 130 GAL16V8D-10LJI 20-Lead PLCC 15 12 10 13 0 GAL16V8D-15LPI 20-Pin Plastic DIP 20 13 11 25 15 12 130 GAL16V8D-15LJI 20-Lead PLCC 65 GAL16V8D-20QPI 20-Pin Plastic DIP 65 GAL16V8D-20QJI 20-Lead PLCC 65 GAL16V8D-25QPI 20-Pin Plastic DIP 65 GAL16V8D-25QJI 20-Lead PLCC 130 GAL16V8D-25LPI 20-Pin Plastic DIP 130 GAL16V8D-25LJI 20-Lead PLCC 2 Specifications GAL16V8 Lead-Free Packaging Commercial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # 1 Package 3.5 2.5 3. 0 115 GAL16V8D-3LJN 5 3 4 115 GAL16V8D-5LJN Lead-Free 20-Lead PLCC 7.5 7 5 Lead-Free 20-Pin Plastic DIP 10 7 115 GAL16V8D-7LPN 115 GAL16V8D-7LJN Lead-Free 20-Lead PLCC 55 GAL16V8D-10QPN Lead-Free 20-Pin Plastic DIP 55 GAL16V8D-10QJN Lead-Free 20-Lead PLCC 115 GAL16V8D-10LPN Lead-Free 20-Pin Plastic DIP 115 GAL16V8D-10LJN Lead-Free 20-Lead PLCC 55 GAL16V8D-15QPN Lead-Free 20-Pin Plastic DIP A D LL IS C DE O N VIC TI N ES U ED 10 Lead-Free 20-Lead PLCC 15 12 25 15 10 12 55 GAL16V8D-15QJN Lead-Free 20-Lead PLCC 90 GAL16V8D-15LPN Lead-Free 20-Pin Plastic DIP 90 GAL16V8D-15LJN Lead-Free 20-Lead PLCC 55 GAL16V8D-25QPN Lead-Free 20-Pin Plastic DIP 55 GAL16V8D-25QJN Lead-Free 20-Lead PLCC 90 GAL16V8D-25LPN Lead-Free 20-Pin Plastic DIP 90 GAL16V8D-25LJN Lead-Free 20-Lead PLCC 1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory. Industrial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) 7.5 7 5 130 GAL16V8D-7LJNI Lead-Free 20-Lead PLCC 130 GAL16V8D-7LPNI Lead-Free 20-Pin Plastic DIP 10 10 7 130 GAL16V8D-10LJNI Lead-Free 20-Lead PLCC 130 GAL16V8D-10LPNI Lead-Free 20-Pin Plastic DIP 15 20 25 12 13 15 10 11 12 Ordering # Package 13 0 GAL16V8D-15LJNI Lead-Free 20-Lead PLCC 130 GAL16V8D-15LPNI Lead-Free 20-Pin Plastic DIP 65 GAL16V8D-20QJNI Lead-Free 20-Lead PLCC 65 GAL16V8D-20QPNI Lead-Free 20-Pin Plastic DIP 65 GAL16V8D-25QJNI Lead-Free 20-Lead PLCC 65 GAL16V8D-25QPNI Lead-Free 20-Pin Plastic DIP 130 GAL16V8D-25LJNI Lead-Free 20-Lead PLCC 130 GAL16V8D-25LPNI Lead-Free 20-Pin Plastic DIP Part Number Description XXXXXXXX _ XX X XX X GAL16V8D Device Name Grade Speed (ns) L = Low Power Power Q = Quarter Power Blank = Commercial I = Industrial Package P = Plastic DIP PN = Lead-free Plastic DIP J = PLCC JN = Lead-free PLCC S = SOIC 3 Specifications GAL16V8 Output Logic Macrocell (OLMC) The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. GAL16V8 Global OLMC Mode 16R8 16R6 16R4 16RP8 16RP6 16RP4 Registered Registered Registered Registered Registered Registered A D LL IS C DE O N VIC TI N ES U ED There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes are illustrated in the following pages. Two global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individual architecture bits define all possible configurations in a GAL16V8 . The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. PAL Architectures Emulated by GAL16V8 The following is a list of the PAL architectures that the GAL16V8 can emulate. It also shows the OLMC mode under which the GAL16V8 emulates the PAL architecture. 16L8 16H8 16P8 Complex Complex Complex 10L8 12L6 14L4 16L2 10H8 12H6 14H4 16H2 10P8 12P6 14P4 16P2 Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Compiler Support for OLMC as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. Software compilers support the three different global OLMC modes as different device types. These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types listed in the table can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins ( pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated combinatorial output. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1 and pin 11 are permanently configured ABEL CUPL LOG/iC OrCAD-PLD PLDesigner TANGO-PLD Registered Complex Simple Auto Mode Select P16V8R G16V8MS GAL16V8_R "Registered"1 P16V8R2 G16V8R P16V8C G16V8MA GAL16V8_C7 "Complex"1 P16V8C2 G16V8C P16V8AS G16V8AS GAL16V8_C8 "Simple"1 P16V8C2 G16V8AS3 P16V8 G16V8 GAL16V8 GAL16V8A P16V8A G16V8 1) Used with Configuration keyword. 2) Prior to Version 2.0 support. 3) Supported on Version 1.20 or later. 4 Specifications GAL16V8 Registered Mode In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Dedicated input or output functions can be implemented as subsets of the I/O function. Architecture configurations available in this mode are similar to the common 16R8 and 16RP4 devices with various permutations of polarity, I/O and register placement. Registered outputs have eight product terms per output. I/O's have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page. A D LL IS C DE O N VIC TI N ES U ED All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or I/ O. Up to eight registers or up to eight I/O's are possible in this mode. CLK Registered Configuration for Registered Mode D XOR - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this output configuration. - Pin 1 controls common CLK for the registered outputs. - Pin 11 controls common OE for the registered outputs. - Pin 1 & Pin 11 are permanently configured as CLK & OE for registered output configuration. Q Q OE Combinatorial Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this output configuration. - Pin 1 & Pin 11 are permanently configured as CLK & OE for registered output configuration. XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 5 Specifications GAL16V8 Registered Mode Logic Diagram DIP & PLCC Package Pinouts 1 0 4 8 12 16 20 24 28 2128 PTD 0000 OLMC 0224 19 XOR-2048 AC1-2120 A D LL IS C DE O N VIC TI N ES U ED 2 0256 OLMC 0480 18 XOR-2049 AC1-2121 3 0512 OLMC 0736 17 XOR-2050 AC1-2122 4 0768 OLMC 0992 16 XOR-2051 AC1-2123 5 1024 OLMC 1248 15 XOR-2052 AC1-2124 6 1280 OLMC 1504 14 XOR-2053 AC1-2125 7 1536 OLMC 1760 13 XOR-2054 AC1-2126 8 1792 OLMC 2016 XOR-2055 AC1-2127 9 2191 SYN-2192 AC0-2193 6 12 OE 11 Specifications GAL16V8 Complex Mode bility. Designs requiring eight I/O's can be implemented in the Registered mode. Architecture configurations available in this mode are similar to the common 16L8 and 16P8 devices with programmable polarity in each macrocell. All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 1 and 11 are always available as data inputs into the AND array. Up to six I/O's are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The two outer most macrocells (pins 12 & 19) do not have input capa- The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. A D LL IS C DE O N VIC TI N ES U ED In the Complex mode, macrocells are configured as output only or I/O functions. Combinatorial I/O Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1. - Pin 13 through Pin 18 are configured to this function. XOR Combinatorial Output Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1. - Pin 12 and Pin 19 are configured to this function. XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 7 Specifications GAL16V8 Complex Mode Logic Diagram DIP & PLCC Package Pinouts 1 2128 0 4 8 12 16 20 24 28 PTD 0000 OLMC 19 XOR-2048 AC1-2120 0224 A D LL IS C DE O N VIC TI N ES U ED 2 0256 OLMC 18 XOR-2049 AC1-2121 0480 3 0512 OLMC 17 XOR-2050 AC1-2122 0736 4 0768 OLMC 16 XOR-2051 AC1-2123 0992 5 1024 OLMC 15 XOR-2052 AC1-2124 1248 6 1280 OLMC 14 XOR-2053 AC1-2125 1504 7 1536 OLMC 13 XOR-2054 AC1-2126 1760 8 1792 OLMC 12 XOR-2055 AC1-2127 2016 9 11 2191 SYN-2192 AC0-2193 8 Specifications GAL16V8 Simple Mode Pins 1 and 11 are always available as data inputs into the AND array. The center two macrocells (pins 15 & 16) cannot be used as input or I/O pins, and are only available as dedicated outputs. In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common 10L8 and 12P6 devices with many permutations of generic output polarity or input choices. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram. A D LL IS C DE O N VIC TI N ES U ED All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has programmable polarity. Combinatorial Output with Feedback Configuration for Simple Mode Vcc - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - All OLMC except pins 15 & 16 can be configured to this function. XOR Combinatorial Output Configuration for Simple Mode Vcc - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - Pins 15 & 16 are permanently configured to this function. XOR Dedicated Input Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this configuration. - All OLMC except pins 15 & 16 can be configured to this function. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 9 Specifications GAL16V8 Simple Mode Logic Diagram DIP & PLCC Package Pinouts 1 2128 0 4 8 12 16 20 24 28 PTD 0000 OLMC XOR-2048 AC1-2120 0224 19 A D LL IS C DE O N VIC TI N ES U ED 2 0256 OLMC XOR-2049 AC1-2121 0480 18 3 0512 OLMC XOR-2050 AC1-2122 0736 17 4 0768 OLMC XOR-2051 AC1-2123 0992 16 5 OLMC 1024 XOR-2052 AC1-2124 1248 15 6 OLMC 1280 XOR-2053 AC1-2125 1504 14 7 1536 OLMC XOR-2054 AC1-2126 1760 13 8 1792 OLMC XOR-2055 AC1-2127 2016 9 12 11 2191 SYN-2192 AC0-2193 10 Specifications GAL16V8D Absolute Maximum Ratings(1) Recommended Operating Conditions Supply voltage VCC ...................................... –0.5 to +7V Input voltage applied .......................... –2.5 to VCC +1.0V Off-state output voltage applied ......... –2.5 to VCC +1.0V Storage Temperature ................................ –65 to 150°C Ambient Temperature with Power Applied ........................................ –55 to 125°C Commercial Devices: Ambient Temperature (TA) ............................... 0 to 75°C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V Industrial Devices: Ambient Temperature (TA) ........................... –40 to 85°C Supply voltage (VCC) with Respect to Ground ..................... +4.50 to +5.50V A D LL IS C DE O N VIC TI N ES U ED 1.Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL VIL VIH IIL1 IIH VOL VOH IOL MIN. TYP.3 MAX. UNITS Input Low Voltage Vss – 0.5 — 0.8 V Input High Voltage 2.0 — Vcc+1 V PARAMETER CONDITION Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 μA Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 μA Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V L-3/-5 & -7 (Ind. PLCC) — — 16 mA L-7 (Except Ind. PLCC)/-10/-15/-25 — — 24 mA — — –3.2 mA –30 — –150 mA Low Level Output Current Q-10/-15/-20/-25 IOH IOS2 High Level Output Current Output Short Circuit Current COMMERCIAL ICC Operating Power Supply Current INDUSTRIAL ICC Operating Power Supply Current VCC = 5V VOUT = 0.5V TA= 25°C VIL = 0.5V VIH = 3.0V L -3/-5/-7/-10 — 75 115 mA ftoggle = 15MHz Outputs Open L-15/-25 — 75 90 mA Q-10/-15/-25 — 45 55 mA VIL = 0.5V VIH = 3.0V L -7/-10/-15/-25 — 75 130 mA ftoggle = 15MHz Outputs Open Q -20/-25 — 45 65 mA 1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 °C 11 Specifications GAL16V8D AC Switching Characteristics Over Recommended Operating Conditions PARAMETER COM COM / IND -3 -5 -7 DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNITS A Input or I/O to Comb. Output 1 3.5 1 5 1 7.5 ns A Clock to Output Delay 1 3 1 4 1 5 ns — Clock to Feedback Delay — 2.5 — 3 — 3 ns — Setup Time, Input or Feedback before Clock↑ 2.5 — 3 — 5 — ns — Hold Time, Input or Feedback after Clock↑ 0 — 0 — 0 — ns A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) 182 — 142.8 — 100 — MHz A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) 200 — 166 — 125 — MHz A Maximum Clock Frequency with No Feedback 250 — 166 — 125 — MHz — Clock Pulse Duration, High 24 — 34 — 4 — ns — 3 4 — 4 — ns A D LL IS C DE O N VIC TI N ES U ED tpd tco tcf2 TEST COND1. COM tsu th fmax3 twh twl ten tdis 4 — Clock Pulse Duration, Low 2 B Input or I/O to Output Enabled — 4.5 1 6 1 9 ns B OE to Output Enabled — 4.5 1 6 1 6 ns C Input or I/O to Output Disabled — 4.5 1 5 1 9 ns C OE to Output Disabled — 4.5 1 5 1 6 ns 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. Characterized but not 100% tested. 4) Characterized but not 100% tested. Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. 12 Specifications Specifications GAL16V8D GAL16V8 AC Switching Characteristics Over Recommended Operating Conditions PARAM. TEST COND1. COM / IND IND COM / IND -10 -15 -20 -25 DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. UNITS A Input or I/O to Comb. Output 3 10 3 15 3 20 3 25 ns A Clock to Output Delay 2 7 2 10 2 11 2 12 ns A D LL IS C DE O N VIC TI N ES U ED tpd tco tcf2 tsu th COM / IND fmax3 twh twl ten t tdis t — Clock to Feedback Delay — 6 — 8 — 9 — 10 ns — Setup Time, Input or Fdbk before Clk↑ 7.5 — 12 — 13 — 15 — ns — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — ns A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) 66.7 — 45.5 — 41.6 — 37 — MHz A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) 71.4 — 50 — 45.4 — 40 — MHz A Maximum Clock Frequency with No Feedback 83.3 — 62.5 — 50 — 41.6 — MHz — Clock Pulse Duration, High 6 — 8 — 10 — 12 — ns — Clock Pulse Duration, Low 6 — 8 — 10 — 12 — ns B Input or I/O to Output Enabled 1 10 — 15 — 18 — 20 ns B OE to Output Enabled 1 10 — 15 — 18 — 20 ns C Input or I/O to Output Disabled 1 10 — 15 — 18 — 20 ns C OE to Output Disabled 1 10 — 15 — 18 — 20 ns 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. 13 Specifications GAL16V8 Switching Waveforms INPUT or I/O FEEDBACK VALID INPUT tsu th CLK INPUT or I/O FEEDBACK tco VALID INPUT REGISTERED OUTPUT A D LL IS C DE O N VIC TI N ES U ED tpd 1/fmax (external fdbk) COMBINATIONAL OUTPUT Combinatorial Output Registered Output INPUT or I/O FEEDBACK OE tdis ten tdis COMBINATIONAL OUTPUT ten REGISTERED OUTPUT OE to Output Enable/Disable Input or I/O to Output Enable/Disable twh twl CLK 1/ fmax (internal fdbk) CLK tcf 1/ fmax (w/o fb) REGISTERED FEEDBACK Clock Width fmax with Feedback 14 tsu Specifications GAL16V8 fmax Descriptions CLK CLK LOGIC ARRAY REGISTER LOGIC ARRAY tco REGISTER A D LL IS C DE O N VIC TI N ES U ED tsu fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. t cf t pd CLK fmax with Internal Feedback 1/(tsu+tcf) LOGIC ARRAY REGISTER Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. tsu + th fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Switching Test Conditions Input Pulse Levels Input Rise and Fall Times GND to 3.0V GAL16V8D-10 (and slower) 2 – 3ns 10% – 90% +5V GAL16V8D-3/-5/-7 1.5ns 10% – 90% R1 Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. 1.5V 1.5V See figure at right FROM OUTPUT (O/Q) UNDER TEST Table 2-0003/16V8 TEST POINT R2 C L* GAL16V8D (except -3) Output Load Conditions (see figure above) Test Condition A B C Active High Active Low Active High Active Low R1 R2 CL 200Ω ∞ 200Ω ∞ 200Ω 390Ω 390Ω 390Ω 390Ω 390Ω 50pF 50pF 50pF 5pF 5pF *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE 15 Specifications GAL16V8 Switching Test Conditions (Continued) GAL16V8D-3 Output Load Conditions (see figure at right) Test Condition A B C High Z to Active High at 1.9V High Z to Active Low at 1.0V Active High to High Z at 1.9V Active Low to High Z at 1.0V R1 CL 50Ω 50Ω 50Ω 50Ω 50Ω 35pF 35pF 35pF 35pF 35pF +1.45V TEST POINT FROM OUTPUT (O/Q) UNDER TEST R1 Z0 = 50Ω, CL = 35pF* A D LL IS C DE O N VIC TI N ES U ED *CL includes test fixture and probe capacitance. Electronic Signature Output Register Preload An electronic signature is provided in every GAL16V8 device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the checksum. Security Cell GAL16V8 devices include circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing text vectors perform output register preload automatically. A security cell is provided in the GAL16V8 devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. Input Buffers GAL16V8 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. Latch-Up Protection GAL16V8 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential of latch-up caused by negative input undershoots. Additionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups in order to eliminate latch-up due to output overshoots. The GAL16V8 input and I/O pins have built-in active pull-ups. As a result, unused inputs and I/O's will float to a TTL "high" (logical "1"). Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to another active input, VCC, or Ground. Doing this will tend to improve noise immunity and reduce ICC for the device. Device Programming GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. I n p u t C u r r e n t (u A ) Typical Input Pull-up Characteristic 0 -20 -40 -60 0 1.0 2.0 3.0 In p u t V o lt ag e ( V o lt s) 16 4.0 5.0 Specifications GAL16V8 Power-Up Reset Vcc Vcc (min.) t su t wl CLK t pr INTERNAL REGISTER Q - OUTPUT A D LL IS C DE O N VIC TI N ES U ED Internal Register Reset to Logic "0" FEEDBACK/EXTERNAL OUTPUT REGISTER Device Pin Reset to Logic "1" Circuitry within the GAL16V8 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1μs MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Input/Output Equivalent Schematics INPUT/OUTPUT EQUIVALENT SCHEMATICS PIN PIN Feedback Vcc Active Pull-up Circuit Active Pull-up Circuit Vcc ESD Protection Circuit Vref Tri-State Control Vcc Vcc Vref Data Output PIN PIN ESD Protection Circuit Typ. Vref = 3.2V Typ. Vref = 3.2V Typical Input Feedback (To Input Buffer) Typical Output 17 Specifications GAL16V8 GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams Normalized Tco vs Vcc Normalized Tpd vs Vcc Normalized Tsu vs Vcc 1.2 1.2 1 0.9 RISE FALL 1.1 Normalized Tsu Normalized Tco PT H->L PT L->H 1.1 1 0.9 PT H->L PT L->H 1.1 1 0.9 A D LL IS C DE O N VIC TI N ES U ED Normalized Tpd 1.2 0.8 4.50 4.75 5.00 5.25 0.8 4.50 5.50 4.75 Supply Voltage (V) Normalized Tpd vs Temp 0.9 0.8 25 50 75 100 1.2 1 0.9 0.8 0.7 -55 125 Temperature (deg. C) -25 0 25 50 75 Delta Tpd (ns) 100 1.2 1.1 1 0.9 0.8 0.7 -55 125 -25 0 0 -0.1 -0.1 -0.2 RISE FALL -0.3 -0.4 -0.2 RISE FALL -0.3 -0.4 3 4 5 6 7 8 1 Number of Outputs Switching 2 3 4 5 6 7 8 Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading 14 14 12 12 Delta Tco (ns) RISE FALL 10 8 6 4 2 RISE FALL 10 8 6 4 2 0 0 -2 -2 0 50 100 150 200 250 0 3 00 50 100 150 200 Output Loading (pF) Output Loading (pF) 18 25 50 75 Temperature (deg. C) Delta Tco vs # of Outputs Switching 0 2 5.50 PTH->L PT L->H Temperature (deg. C) Delta Tpd vs # of Outputs Switching 1 5.25 Normalized Tsu vs Temp RISE FALL 1.1 Delta Tco (ns) 0 5.00 1.3 Normalized Tsu Normalized Tco PT H->L PT L->H -25 4.75 Supply Voltage (V) Normalized Tco vs Temp 1 0.7 -55 0.8 4.50 5.50 1.3 Delta Tpd (ns) Normalized Tpd 1.1 5.25 Supply Voltage (V) 1.3 1.2 5.00 250 3 00 1 00 1 25 Specifications GAL16V8 GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams Voh vs Ioh Voh vs Ioh Vol vs Iol 1 3.25 5 4 0.75 0.5 2 2.75 A D LL IS C DE O N VIC TI N ES U ED 0.25 Voh (V) Voh (V) Vol (V) 3 3 1 0 0 0 10 20 30 2.5 0 40 10 20 30 40 50 0 Normalized Icc vs Vcc Normalized Icc vs Temp 0.9 5.00 5.25 1.15 1.1 1 0.9 0.8 -55 5.50 Supply Voltage (V) 0 25 50 75 100 125 10 Iik (mA) Delta Icc (mA) 20 6 4 30 40 50 60 70 2 80 0 0 0.5 1 1.5 2 2.5 Vin (V) 3 3.5 4 90 -2 1 -1.5 -1 Vik (V) 19 -0.5 0 25 50 75 Frequency (MHz) 0 8 1.05 0.9 -25 Input Clamp (Vik) Delta Icc vs Vin (1 input) 1.1 0.95 Temperature (deg. C) 10 4 Normalized Icc vs Freq. Normalized Icc Normalized Icc Normalized Icc 1 3 1.2 1.2 1.1 4.75 2 Ioh (mA) 1.3 1.2 0.8 4.50 1 Ioh (mA) Iol (mA) 0 1 00 Specifications GAL16V8 GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.15 1.05 Normalized Tco RISE FALL 1 0.95 RISE FALL 1.1 Normalized Tsu 1.1 1.05 1 0.95 RISE FALL 1.1 1 0.9 A D LL IS C DE O N VIC TI N ES U ED Normalized Tpd Normalized Tsu vs Vcc Normalized Tco vs Vcc 1.15 0.9 4.5 0.8 0.9 4.75 5 5.25 5.5 4.5 4.75 Supply Voltage (V) Normalized Tpd vs Temp 4.5 5.5 1 0.9 0 25 50 75 100 RISE FALL 1.2 1.1 1 0.9 0.8 -55 125 -25 Temperature (deg. C) 0 25 50 Delta Tpd (ns) Delta Tpd vs # of Outputs Switching 75 100 1.1 1 0.9 0.8 -55 125 -25 0 -0.1 -0.1 -0.2 -0.2 -0.3 -0.4 -0.5 -0.6 RISE FALL -0.7 -0.8 0 -0.3 -0.4 -0.5 -0.6 RISE FALL -0.7 -0.8 -0.9 -0.9 -1 -1 2 3 4 5 6 7 8 1 Number of Outputs Switching 2 3 4 5 6 7 8 Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading 12 12 Delta Tco (ns) RISE FALL 8 4 0 RISE FALL 8 4 0 -4 -4 0 50 100 150 200 250 0 3 00 50 100 150 200 250 Output Loading (pF) Output Loading (pF) 20 25 50 75 1 00 Temperature (deg. C) Delta Tco vs # of Outputs Switching 0 1 5.5 RISE FALL 1.2 Temperature (deg. C) Delta Tco (ns) -25 5.25 1.3 Normalized Tsu Normalized Tco 1.1 5 Normalized Tsu vs Temp Normalized Tco vs Temp RISE FALL 1.2 4.75 Supply Voltage (V) 1.3 Delta Tpd (ns) Normalized Tpd 5.25 Supply Voltage (V) 1.3 0.8 -55 5 3 00 1 25 Specifications GAL16V8 GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams Voh vs Ioh Vol vs Iol 0.4 4 3 0.2 Voh (V) 3.5 Voh (V) 0.3 Vol (V) Voh vs Ioh 4 0.5 2 3 1 A D LL IS C DE O N VIC TI N ES U ED 0.1 0 0 1 6 11 16 21 0 26 5 10 Normalized Icc vs Vcc 0.9 0.8 3.45 1.15 1.1 1.1 1 0.9 0.8 -55 3.6 0 8 10 7 20 6 30 Iik (mA) Delta Icc (mA) 25 50 88 1 00 1 25 5 4 3 40 50 60 2 70 1 80 0 90 0.5 1 1.5 2 2.5 3 Vin (V) 3.5 4 4.5 5 -3 4.00 5.00 1.05 1 -2.5 -2 -1.5 Vik (V) 21 -1 -0.5 1 15 25 50 Frequency (MHz) Input Clamp (Vik) Delta Icc vs Vin (1 input) 0 3.00 0.95 -25 Temperature (deg. C) 9 2.00 Normalized Icc vs Freq 1.2 Supply Voltage (V) 0 1.00 Ioh (mA) Normalized Icc Normalized Icc Normalized Icc 1 3.3 2.5 0.00 25 Normalized Icc vs Temp 1.1 3.15 20 Ioh (mA) Iol (mA) 3 15 0 75 1 00 Specifications GAL16V8 GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 PT H->L PT L->H 1.1 1 0.9 RISE FALL 1.1 Normalized Tsu Normalized Tco 1.2 1 0.9 1.1 PT H->L PT L->H 1 0.9 A D LL IS C DE O N VIC TI N ES U ED Normalized Tpd Normalized Tsu vs Vcc Normalized Tco vs Vcc 1.2 0.8 4.50 4.75 5.00 5.25 0.8 4.50 5.50 4.75 Supply Voltage (V) 0.8 4.50 5.50 0.8 25 50 75 100 1.1 1 0.9 0.8 0.7 -55 125 -25 Temperature (deg. C) 0 25 50 75 Delta Tpd vs # of Outputs Switching Delta Tpd (ns) 100 1.2 1 0.9 0.8 0.7 -55 125 -25 0 -0.2 -0.2 -0.4 -0.6 -0.8 RISE FALL -1 0 -0.4 -0.6 -0.8 RISE FALL -1 -1.2 -1.2 2 3 4 5 6 7 1 8 Number of Outputs Switching 2 3 4 5 6 7 8 Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading 12 12 10 10 RISE FALL 8 6 4 2 0 -2 RISE FALL 8 6 4 2 0 -2 -4 -4 -6 0 50 100 150 200 250 0 300 50 100 150 200 250 Output Loading (pF) Output Loading (pF) 22 25 50 75 100 Temperature (deg. C) Delta Tco vs # of Outputs Switching 0 1 5.50 PT H->L PT L->H 1.1 Temperature (deg. C) Delta Tco (ns) 0 Delta Tpd (ns) -25 Normalized Tsu 1 0.9 RISE FALL Delta Tco (ns) 1.1 5.25 1.3 1.2 Normalized Tco PT H->L PT L->H 5.00 Normalized Tsu vs Temp 1.3 1.2 4.75 Supply Voltage (V) Normalized Tco vs Temp Normalized Tpd vs Temp Normalized Tpd 5.25 Supply Voltage (V) 1.3 0.7 -55 5.00 300 125 Specifications GAL16V8 GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams Voh vs Ioh Vol vs Iol Vol (V) Voh (V) 0.4 0.2 Voh vs Ioh 5 4 4 3.8 Voh (V) 0.6 3 2 3.6 3.4 3.2 A D LL IS C DE O N VIC TI N ES U ED 1 0 0 0 10 20 30 3 0 40 10 20 40 50 Normalized Icc vs Vcc 1 0.9 1.4 1.2 1.3 1.1 1 0.9 0.8 5.00 5.25 0.7 -55 5.50 Supply Voltage (V) 0 25 50 75 100 125 Iik (mA) Delta Icc (mA) 10 6 20 30 40 2 50 0 0 0.5 1 1.5 2 2.5 Vin (V) 3 3.5 4 60 -2 1.2 1.1 1 -1.5 -1 Vik (V) 23 -0.5 0 25 50 75 Frequency (MHz) 0 4 4 0.8 -25 Input Clamp (Vik) 8 3 0.9 Temperature (deg. C) Delta Icc vs Vin (1 input) 2 Normalized Icc vs Freq. 1.3 Normalized Icc Normalized Icc 1.1 4.75 1 Ioh (mA) Normalized Icc vs Temp 1.2 0.8 4.50 0 Ioh (mA) Iol (mA) Normalized Icc 30 0 100 Specifications GAL16V8 Revision History Version Change Summary - 16v8_10 Previous Lattice release. August 2006 16v8_11 Updated for lead-free package options. A D LL IS C DE O N VIC TI N ES U ED Date 24