TI1 INA188 Precision, zero-drift, rail-to-rail out, high-voltage instrumentation amplifier Datasheet

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INA188
SBOS632 – SEPTEMBER 2015
INA188
Precision, Zero-Drift, Rail-to-Rail Out, High-Voltage Instrumentation Amplifier
1 Features
3 Description
•
The INA188 is a precision instrumentation amplifier
that uses TI proprietary auto-zeroing techniques to
achieve low offset voltage, near-zero offset and gain
drift, excellent linearity, and exceptionally low-noise
density (12 nV/√Hz) that extends down to dc.
1
•
•
•
•
•
•
•
•
•
Excellent DC Performance:
– Low Input Offset Voltage: 55 μV (max)
– Low Input Offset Drift: 0.2 μV/°C (max)
– High CMRR: 104 dB, G ≥ 10 (min)
Low Input Noise:
– 12 nV/√Hz at 1 kHz
– 0.25 μVPP (0.1 Hz to 10 Hz)
Wide Supply Range:
– Single Supply: 4 V to 36 V
– Dual Supply: ±2 V to ±18 V
Gain Set with a Single External Resistor:
– Gain Equation: G = 1 + (50 kΩ / RG)
– Gain Error: 0.007%, G = 1
– Gain Drift: 5 ppm/°C (max) G = 1
Input Voltage: (V–) + 0.1 V to (V+) – 1.5 V
RFI-Filtered Inputs
Rail-to-Rail Output
Low Quiescent Current: 1.4 mA
Operating Temperature: –55°C to +150°C
SOIC-8 and DFN-8 Packages
2 Applications
•
•
•
•
•
•
•
•
•
Bridge Amplifiers
ECG Amplifiers
Pressure Sensors
Medical Instrumentation
Portable Instrumentation
Weigh Scales
Thermocouple Amplifiers
RTD Sensor Amplifiers
Data Acquisition
The INA188 is optimized to provide excellent
common-mode rejection of greater than 104 dB (G ≥
10). Superior common-mode and supply rejection
supports high-resolution, precise measurement
applications. The versatile three op-amp design offers
a rail-to-rail output, low-voltage operation from a 4-V
single supply as well as dual supplies up to ±18 V,
and a wide, high-impedance input range. These
specifications make this device ideal for universal
signal measurement and sensor conditioning (such
as temperature or bridge applications).
A single external resistor sets any gain from 1 to
1000. The INA188 is designed to use an industrystandard gain equation: G = 1 + (50 kΩ / RG). The
reference pin can be used for level-shifting in singlesupply operation or for an offset calibration.
The INA188 is specified over the temperature range
of –40°C to +125°C .
Device Information
ORDER NUMBER
PACKAGE
BODY SIZE
INA188
SOIC (8)
4.90 mm × 3.91 mm
INA188
WSON (8)(2)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) The DRJ package (WSON-8) is a preview device.
Simplified Schematic
V+
VIN-
RFI Filter Inputs
+
20 k
20 k
A1
RFI Filtered Inputs
25 k
A3
25 k
RG
20 k
RFI Filtered Inputs
20 k
A2
VIN+
RFI Filtered Inputs
REF
+
V-
VOUT
VIN
VOUT
+
VIN u G VREF
G 1
50 k:
RG
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
INA188
SBOS632 – SEPTEMBER 2015
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 21
1
1
1
2
3
4
8
8.1 Application Information............................................ 27
8.2 Typical Application .................................................. 27
9 Power Supply Recommendations...................... 29
10 Layout................................................................... 29
6.1
6.2
6.3
6.4
6.5
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics: VS = ±4 V to ±18 V (VS =
8 V to 36 V)................................................................ 5
6.6 Electrical Characteristics: VS = ±2 V to < ±4 V (VS =
4 V to < 8 V)............................................................... 7
6.7 Typical Characteristics .............................................. 9
7
Application and Implementation ........................ 27
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 30
11 Device and Documentation Support ................. 31
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
Device Support ....................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
2
DATE
REVISION
NOTES
September 2015
*
Initial release.
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5 Pin Configuration and Functions
D Package
SOIC-8
Top View
DRJ Package
WSON-8
Top View
RG
1
8
RG
VIN-
2
7
V+
VIN+
3
6
VOUT
V-
4
5
REF
RG
1
VIN-
2
VIN+
3
V-
4
Exposed
Thermal
Die Pad on
Underside
8
RG
7
V+
6
VOUT
5
REF
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
REF
5
I
RG
1, 8
—
Reference input. This pin must be driven by low impedance or connected to ground.
Gain setting pin. For gains greater than 1, place a gain resistor between pin 1 and pin 8.
V–
4
—
Negative supply
V+
7
—
Positive supply
VIN–
2
I
Negative input
VIN+
3
I
Positive input
VOUT
6
O
Output
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SBOS632 – SEPTEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Supply
Voltage
40 (single supply)
Current
Output short-circuit
Analog input range (2)
(V–) – 0.5
Operating range, TA
–55
(3)
(3)
±10
mA
(V+) + 0.5
V
150
Junction, TJ
150
Storage temperature, Tstg
(2)
V
Continuous
Temperature
(1)
UNIT
±20
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Supply voltage
Specified temperature
NOM
MAX
UNIT
4 (±2)
36 (±18)
V
-40
125
°C
6.4 Thermal Information
INA188
THERMAL METRIC
(1)
D (SOIC)
DRG (WSON)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
125
145
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
80
75
°C/W
RθJB
Junction-to-board thermal resistance
68
39
°C/W
ψJT
Junction-to-top characterization parameter
32
14
°C/W
ψJB
Junction-to-board characterization parameter
68
105
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
At TA = 25°C, RL = 10 kΩ, VREF = VS / 2, and G = 1, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT (1)
VOSI
Input stage offset voltage
VOSO
Output stage offset voltage
VOS
Offset voltage
PSRR
Power-supply rejection ratio
At RTI (2)
At RTI, TA = –40°C to +125°C
Differential input impedance
Common-mode input impedance
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
μV
μV/°C
±60
±170
μV
At RTI, TA = –40°C to +125°C
±0.2
±0.35
μV/°C
At RTI
±55 ±170 / G
μV
±0.2 ±0.35 / G
μV/°C
±25 ±60 / G
At RTI, TA = –40°C to +125°C
G = 1, VS = 4 V to 36 V, VCM = VS / 2
±0.7
G = 10, VS = 4 V to 36 V, VCM = VS / 2
±0.6
G = 100, VS = 4 V to 36 V, VCM = VS / 2
±0.45
G = 1000, VS = 4 V to 36 V, VCM = VS / 2
±0.3
±2.25
µV/V
±0.8
1 (3)
Turn-on time to specified VOSI
zic
±55
±0.2
At RTI
Long-term stability
zid
±25
±0.08
µV
See the Typical Characteristics
100 || 6
GΩ || pF
100 || 9.5
The input signal common-mode range can be
calculated with this tool
(V–) + 0.1
(V+) – 1.5
G = 1, at dc to 60 Hz, VCM = (V–) + 1.0 V to
(V+) – 2.5 V
84
90
G = 10, at dc to 60 Hz, VCM = (V–) + 1.0 V to
(V+) – 2.5 V
104
110
G = 100, at dc to 60 Hz, VCM = (V–) + 1.0 V to
(V+) – 2.5 V
118
130
G = 1000, at dc to 60 Hz, VCM = (V–) + 1.0 V to
(V+) – 2.5 V
118
130
V
dB
INPUT BIAS CURRENT
IIB
Input bias current
IOS
Input offset current
±850
TA = –40°C to +125°C
See Figure 10
TA = –40°C to +125°C
See Figure 11
±2500
pA
pA/°C
±850
±2500
pA
pA/°C
INPUT VOLTAGE NOISE
eNI
Input voltage noise
eNO
Output voltage noise
iN
Input current noise
f = 1 kHz, G = 100, RS = 0 Ω
12.5
f = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω
0.25
μVPP
f = 1 kHz, G = 100, RS = 0 Ω
118
nV/√Hz
f = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω
2.5
μVPP
f = 1 kHz
440
fA/√Hz
10
pAPP
f = 0.1 Hz to 10 Hz
nV/√Hz
GAIN
G
Gain equation
1 + (50 kΩ / RG)
Gain range
EG
Gain error
Gain versus temperature
Gain nonlinearity
(1)
(2)
(3)
(4)
V/V
1
1000
G = 1, (V–) + 0.5 V ≤ VO ≤ (V+) – 1.5 V
±0.007%
±0.025%
G = 10, (V–) + 0.5 V ≤ VO ≤ (V+) – 1.5 V
±0.05%
±0.20%
G = 100, (V–) + 0.5 V ≤ VO ≤ (V+) – 1.5 V
±0.06%
±0.20%
G = 1000, (V–) + 0.5 V ≤ VO ≤ (V+) – 1.5 V
±0.2%
±0.50%
G = 1, TA = –40°C to +125°C
G > 1 (4) , TA = –40°C to +125°C
G = 1, VO = –10 V to +10 V
G > 1, VO = –10 V to +10 V
1
5
15
50
3
8
See Figure 42 to Figure 45
V/V
ppm/°C
ppm
Total VOS, referred-to-input = (VOSI) + (VOSO / G).
RTI = Referred-to-input.
300-hour life test at 150°C demonstrated a randomly distributed variation of approximately 1 μV.
Does not include effects of external resistor RG.
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Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) (continued)
At TA = 25°C, RL = 10 kΩ, VREF = VS / 2, and G = 1, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
220
250
mV
OUTPUT
Output voltage swing from rail (5)
RL = 10 kΩ (5)
Capacitive load drive
ISC
Short-circuit current
1
nF
Continuous to common
±18
mA
G=1
600
G = 10
95
G = 100
15
G = 1000
1.5
FREQUENCY RESPONSE
BW
SR
Bandwidth, –3 dB
G = 1, VS = ±18 V, VO = 10-V step
Slew rate
tS
0.9
G = 100, VS = ±18 V, VO = 10-V step
To 0.1%
Settling time
To 0.01%
Overload recovery
kHz
V/μs
0.17
G = 1, VS = ±18 V, VSTEP = 10 V
50
G = 100, VS = ±18 V, VSTEP = 10 V
μs
400
G = 1, VS = ±18 V, VSTEP = 10 V
60
G = 100, VS = ±18 V, VSTEP = 10 V
μs
500
50% overdrive
μs
75
REFERENCE INPUT
RIN
Input impedance
40
Voltage range
V–
kΩ
V+
V
POWER SUPPLY
Voltage range
IQ
Single
Dual
Quiescent current
4
36
±2
±18
VIN = VS / 2
1.4
TA = –40°C to +125°C
1.6
1.8
V
mA
TEMPERATURE RANGE
(5)
6
Specified temperature range
–40
125
°C
Operating temperature range
–55
150
°C
See Typical Characteristics curves, Output Voltage Swing vs Output Current (Figure 19 to Figure 22).
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6.6 Electrical Characteristics: VS = ±2 V to < ±4 V (VS = 4 V to < 8 V)
At TA = 25°C, RL = 10 kΩ, VREF = VS / 2, and G = 1, unless otherwise noted. Specifications not shown are identical to the
Electrical Characteristics table for VS = ±2 V to ±18 V (VS = 8 V to 36 V).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT (1)
VOSI
Input stage offset voltage
VOSO
Output stage offset voltage
VOS
Offset voltage
At RTI (2)
At RTI, TA = –40°C to +125°C
±25
±55
μV
±0.08
±0.2
μV/°C
At RTI
±60
±170
μV
At RTI, TA = –40°C to +125°C
±0.2
±0.35
μV/°C
±25 ±60 / G
±55 ±170 /
G
At RTI
At RTI, TA = –40°C to +125°C
Turn-on time to specified VOSI
Differential input impedance
zic
Common-mode input impedance
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
μV/°C
±0.2 ±0.35 / G
1 (3)
Long-term stability
zid
μV
µV
See the Typical Characteristics
100 || 6
GΩ || pF
100 || 9.5
VO = 0 V, the input signal common-mode range can
be calculated with this tool
(V–)
(V+) – 1.5
G = 1, at dc to 60 Hz, VCM = (V–) + 1.0 V to
(V+) – 2.5 V
80
90
G = 10, at dc to 60 Hz, VCM = (V–) + 1.0 V to
(V+) – 2.5 V
94
110
G = 100, at dc to 60 Hz, VCM = (V–) + 1.0 V to
(V+) – 2.5 V
102
120
G = 1000, at dc to 60 Hz, VCM = (V–) + 1.0 V to
(V+) – 2.5 V
102
120
V
dB
INPUT BIAS CURRENT
IIB
Input bias current
IOS
Input offset current
±850
TA = –40°C to +125°C
See Figure 10
TA = –40°C to +125°C
See Figure 11
±850
±2500
pA
pA/°C
±2500
pA
pA/°C
INPUT VOLTAGE NOISE
eNI
Input voltage noise
eNO
Output voltage noise
iN
Input current noise
f = 1 kHz, G = 100, RS = 0 Ω
12.5
f = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω
0.25
μVPP
f = 1 kHz, G = 100, RS = 0 Ω
118
nV/√Hz
nV/√Hz
f = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω
2.5
μVPP
f = 1 kHz
430
fA/√Hz
10
pAPP
f = 0.1 Hz to 10 Hz
GAIN
G
Gain equation
1 + (50 kΩ / RG)
Gain range
EG
Gain error
Gain versus temperature
Gain nonlinearity
(1)
(2)
(3)
(4)
1
V/V
1000
G = 1, (V–) + 0.5 V ≤ VO ≤ (V+) – 1.5 V
±0.007%
±0.05%
G = 10, (V–) + 0.5 V ≤ VO ≤ (V+) – 1.5 V
±0.07%
±0.2%
G = 100, (V–) + 0.5 V ≤ VO ≤ (V+) – 1.5 V
±0.07%
±0.2%
G = 1000, (V–) + 0.5 V ≤ VO ≤ (V+) – 1.5 V
±0.25%
±0.5%
G = 1, TA = –40°C to +125°C
G > 1 (4), TA = –40°C to +125°C
G = 1, VO = (V–) + 0.5 V ≤ VO ≤ (V+) – 1.5 V
1
5
15
50
3
8
V/V
ppm/°C
ppm
Total VOS, referred-to-input = (VOSI) + (VOSO / G).
RTI = Referred-to-input.
300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 μV.
Does not include effects of external resistor RG.
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Electrical Characteristics: VS = ±2 V to < ±4 V (VS = 4 V to < 8 V) (continued)
At TA = 25°C, RL = 10 kΩ, VREF = VS / 2, and G = 1, unless otherwise noted. Specifications not shown are identical to the
Electrical Characteristics table for VS = ±2 V to ±18 V (VS = 8 V to 36 V).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
220
250
mV
OUTPUT
Output voltage swing from rail (5)
RL = 10 kΩ
Capacitive load drive
ISC
Short-circuit current
1
nF
Continuous to common
±18
mA
G=1
600
G = 10
95
G = 100
15
G = 1000
1.5
FREQUENCY RESPONSE
BW
SR
Bandwidth, –3 dB
G = 1, VS = 5 V, VO = 4-V step
Slew rate
tS
0.9
G = 100, VS = 5 V, VO = 4-V step
To 0.1%
Settling time
To 0.01%
Overload recovery
kHz
V/μs
0.17
G = 1, VS = 5 V, VSTEP = 4 V
50
G = 100, VS = 5 V, VSTEP = 4 V
μs
400
G = 1, VS = 5 V, VSTEP = 4 V
60
G = 100, VS = 5 V, VSTEP = 4 V
μs
500
50% overdrive
μs
75
REFERENCE INPUT
RIN
Input impedance
40
Voltage range
V–
kΩ
V+
V
POWER SUPPLY
Voltage range
IQ
Single
Dual
Quiescent current
4
36
±2
±18
VIN = VS / 2
1.4
TA = –40°C to +125°C
1.6
1.8
V
mA
TEMPERATURE RANGE
(5)
8
Specified temperature range
–40
125
°C
Operating temperature range
–55
150
°C
See Typical Characteristics curves, Output Voltage Swing vs Output Current (Figure 19 to Figure 22).
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6.7 Typical Characteristics
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = midsupply, and G = 1, unless otherwise noted.
0.105
D001
0.09
VOSI (µV)
0
30
25
20
15
5
10
0
-5
-10
-15
-20
-25
-30
0
0.0975
50
0.075
100
0.0825
150
0.06
200
0.0675
250
0.045
300
0.0525
350
0.03
Population (%)
Count
400
0.0375
450
0.015
500
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0.0225
550
0.0075
600
Input Voltage Offset Drift (µV/°C)
–40°C to +125°C
Figure 2. Input Voltage Offset Drift Distribution
Figure 1. Input Voltage Offset Distribution
1000
45
900
40
800
35
700
30
Population (%)
20
0.3825
0.34
0.2975
0.255
0
D001
0.2125
VOSO (µV)
100
80
60
40
20
0
-100
-20
0
-40
5
0
-60
10
100
-80
200
0.17
15
300
0.1275
400
25
0.085
500
0.0425
Count
600
VOSO (µV/°C)
–40°C to +125°C
Figure 3. Output Voltage Offset Distribution
20
18
18
16
16
14
Population (%)
14
12
10
8
12
10
6
8
6
4
4
0.98
0.84
0.7
0.56
0.42
0.28
0
0.14
-0.14
-0.28
-0.42
-0.56
-0.7
-0.84
-0.98
-1.12
0
-1.4
2
0
-1.26
2
Input Bias Current (nA)
-1.7
-1.53
-1.36
-1.19
-1.02
-0.85
-0.68
-0.51
-0.34
-0.17
0
0.17
0.34
0.51
0.68
0.85
1.02
1.19
1.36
1.53
1.7
Population (%)
Figure 4. Output Voltage Offset Drift Distribution
IOS (nA)
Figure 5. Input Bias Current Distribution
Figure 6. Input Offset Current Distribution
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = midsupply, and G = 1, unless otherwise noted.
27.5
45
25
40
22.5
35
Population (%)
Population (%)
20
17.5
15
12.5
10
30
25
20
15
7.5
10
5
5
0
0
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
-0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
2.5
Common-Mode Rejection (µV/V)
Common-Mode Rejection (µV/V)
G=1
G = 100
Figure 8. CMRR Distribution
18000
16000
14000
Input Bias Current (nA)
Input Bias Current (nA)
Figure 7. CMRR Distribution
0.95
0.9
0.85
0.8
0.75
0.7
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
-15
12000
10000
8000
6000
4000
2000
IIB ±2 V
IIB ±15 V
-12
-9
-6
-3
0
3
6
Common-Mode Voltage (V)
9
12
0
-2000
-75
15
Figure 9. Input Bias Current vs Common-Mode Voltage
0
25
50
75 100
Temperature (°C)
125
150
175
D001
Figure 10. Input Bias Current vs Temperature
Change in Input Offset Voltage (µV)
Input Offset Current (pA)
650
600
550
500
450
400
350
4
2
0
-2
-4
-6
-50
-25
0
25
50
75 100
Temperature (°C)
125
150
175
0
D001
Figure 11. Input Offset Current vs Temperature
10
-25
6
700
300
-75
-50
10
20
30
40
50
60
Time (s)
70
80
90
100
D001
Figure 12. Change in Input Offset Voltage vs Warm-Up Time
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Typical Characteristics (continued)
150
G=1
G = 10
G = 100
G = 1000
130
110
90
70
50
30
10
-10
10
100
1k
10k
Frequency (Hz)
100k
Negative Power-Supply Rejection Ratio (dB)
Positive Power-Supply Rejection Ratio (dB)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = midsupply, and G = 1, unless otherwise noted.
1M
150
G=1
G = 10
G = 100
G = 1000
130
110
90
70
50
30
10
-10
10
100
1k
10k
Frequency (Hz)
100k
1M
At RTI
Figure 14. Negative PSRR vs Frequency
G=1
G=10
G=100
G=1000
100
1k
10k
100k
Frequency (Hz)
1M
Common-Mode Rejection Ratio (dB)
Gain (dB)
Figure 13. Positive PSRR vs Frequency
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
-5
-10
10
10M
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
10
G=1
G=10
G=100
G=1000
100
D001
At RTI
100k
D001
Figure 16. CMRR vs Frequency
50
Common-Mode Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
10k
At RTI
Figure 15. Gain vs Frequency
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
10
1k
Frequency (Hz)
G=1
G=10
G=100
G=1000
100
1k
Frequency (Hz)
10k
100k
G=1
G>1
40
30
20
10
0
-10
-20
-30
-40
-50
-75
D001
-45
-15
15
45
75
Temperature (ºC)
105
135
D001
At RTI, 1-kΩ Source Imbalance
Figure 17. CMRR vs Frequency
Figure 18. Common-Mode Rejection Ratio vs Temperature
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Typical Characteristics (continued)
18
0
16
-2
14
-4
12
Output Voltage (V)
Output Voltage (V)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = midsupply, and G = 1, unless otherwise noted.
10
8
6
4
2
-6
-8
-10
-12
-14
-40°C
125°C
25°C
0
-40°C
125°C
25°C
-16
-2
-18
0
2.5
5
7.5
10 12.5 15 17.5
Output Current (mA)
20
22.5
25
0
3
6
9
12
15
18
21
Output Current (mA)
D001
VS = ±18 V
0
-0.2
1.6
-0.4
1.4
-0.6
Output Voltage (V)
Output Voltage (V)
2
1.2
1
0.8
0.6
D001
-40°C
125°C
25°C
-0.8
-1
-1.2
-1.4
-1.6
-40°C
125°C
25°C
-1.8
0
-2
0
2
4
6
8
10
12
14
Output Current (mA)
16
18
20
0
2.5
5
D001
7.5
10 12.5
15
Output Current (mA)
VS = ±2 V
17.5
20
22.5
D001
VS = ±2 V
Figure 21. Positive Output Voltage Swing vs
Output Current
Figure 22. Negative Output Voltage Swing vs
Output Current
100
2
50
1.6
20
1.2
10
0.8
5
Noise (µV)
Voltage Noise (nV/—Hz)
30
Figure 20. Negative Output Voltage Swing vs
Output Current
1.8
0.2
27
VS = ±18 V
Figure 19. Positive Output Voltage Swing vs
Output Current
0.4
24
2
1
0.5
0.4
0
-0.4
-0.8
0.2
G=1
G = 10
G = 100
G = 1000
0.1
0.05
-1.2
-1.6
-2
0.02
1
10
100
1k
Frequency (Hz)
10k
100k
0
1
2
3
4
5
6
Time (s/div)
7
8
9
10
G=1
Figure 23. Voltage Noise Spectral Density vs Frequency
12
Figure 24. 0.1-Hz to 10-Hz RTI Voltage Noise
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = midsupply, and G = 1, unless otherwise noted.
200
160
Current Noise (fa/—Hz)
120
Noise (µV)
80
40
0
-40
-80
-120
-160
-200
0
1
2
3
4
5
6
Time (s/div)
7
8
9
10
700
680
660
640
620
600
580
560
540
520
500
480
460
440
420
400
10
G=1
G = 10
G = 100
G = 1000
100
1k
Frequency (Hz)
10k
100k
G = 1000
Figure 25. 0.1-Hz to 10-Hz RTI Voltage Noise
Figure 26. Current Noise Spectral Density vs Frequency
10
8
6
Output Voltage (V)
Noise (pA)
4
2
0
-2
-4
-6
-8
-10
0
1
2
3
4
5
6
Time (s/div)
7
8
9
10
35
32.5
30
27.5
25
22.5
20
17.5
15
12.5
10
7.5
5
2.5
0
10
100
1k
Frequency (Hz)
10k
100k
D001
Figure 28. Large-Signal Response vs Frequency
6
6
4
4
2
2
Amplitude (V)
Amplitude (V)
Figure 27. 0.1-Hz to 10-Hz RTI Current Noise
VS = 30 V
VS = 4 V
0
-2
-4
0
-2
-4
-6
-6
0
50
100
150
200
250
Time (µs)
300
350
400
0
D001
RL = 10 kΩ, CL = 100 pF, G = 1
50
100
150
200
250
Time (µs)
300
350
400
D001
RL = 10 kΩ, CL = 100 pF, G = 10
Figure 29. Large-Signal Pulse Response
Figure 30. Large-Signal Pulse Response
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Typical Characteristics (continued)
6
6
4
4
2
2
Amplitude (V)
Amplitude (V)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = midsupply, and G = 1, unless otherwise noted.
0
-2
-4
0
-2
-4
-6
-6
0
50
100
150
200
250
Time (µs)
300
350
400
0
0.5
1
1.5
D001
RL = 10 kΩ, CL = 100 pF, G = 100
2
2.5
Time (µs)
3
3.5
4
D001
RL = 10 kΩ, CL = 100 pF, G = 1000
Figure 31. Large-Signal Pulse Response
Figure 32. Large-Signal Pulse Response
100
60
75
40
Amplitude (mV)
Amplitude (mV)
50
25
0
-25
20
0
-20
-50
-40
-75
-100
-60
0
50
100
150
200
250
Time (µs)
300
350
400
0
RL = 10 kΩ, CL = 100 pF, G = 1
150
200
250
Time (µs)
300
350
400
D001
Figure 34. Small-Signal Pulse Response
60
60
40
40
20
20
Amplitude (mV)
Amplitude (mV)
100
RL = 10 kΩ, CL = 100 pF, G = 10
Figure 33. Small-Signal Pulse Response
0
-20
-40
0
-20
-40
-60
-60
0
50
100
150
200
250
Time (µs)
300
350
400
0
D001
RL = 10 kΩ, CL = 100 pF, G = 100
0.5
1
1.5
2
2.5
Time (µs)
3
3.5
4
D001
RL = 10 kΩ, CL = 100 pF, G = 1000
Figure 35. Small-Signal Pulse Response
14
50
D001
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Figure 36. Small-Signal Pulse Response
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = midsupply, and G = 1, unless otherwise noted.
1
0 pF
100 pF
220 pF
500 pF
1000 pF
Amplitude (mV)
100
50
0
-50
Total Harmonic Distortion + Noise (%)
150
G = 1, 1-Vrms out, 2-k: load
G = 10, 1-Vrms out, 2-k: load
0.5
0.3
0.2
0.1
0.05
0.03
0.02
0.01
0.005
0.003
0.002
0.001
-100
0
20
40
60
Time (µs)
80
100
100
120
1k
Frequency (Hz)
10k
G=1
Figure 38. Total Harmonic Distortion + Noise vs Frequency
1.38
1.45
1.36
1.34
1.4
Supply Current (mA)
Supply Current (mA)
Figure 37. Small-Signal Response vs Capacitive Load
1.5
1.35
1.3
1.25
1.2
1.32
1.3
1.28
1.26
1.24
1.15
1.22
1.1
-75
1.2
-50
-25
0
25
50
75
Temperature (°C)
100
125
150
0
5
10
15
20
25
30
Supply Voltage (V)
D001
Figure 39. Supply Current vs Temperature
35
40
45
D001
Figure 40. Supply Current vs Supply Voltage
4
10k
3.2
2.4
Nonlinearity (ppm)
ZO (W)
1k
100
10
1.6
0.8
0
-0.8
-1.6
1
-2.4
-3.2
0.1
1
10
100
1k
10k
100k
1M
Frequency (Hz)
10M
-4
-10
-8
-6
-4
-2
0
2
Output Voltage (V)
4
6
8
10
D001
G=1
Figure 41. Open-Loop Output Impedance
Figure 42. Gain Nonlinearity
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Typical Characteristics (continued)
4
15
3.2
12
2.4
9
1.6
6
Nonlinearity (ppm)
Nonlinearity (ppm)
At TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = midsupply, and G = 1, unless otherwise noted.
0.8
0
-0.8
-1.6
0
-3
-6
-9
-2.4
-12
-3.2
-4
-10
3
-8
-6
-4
-2
0
2
Output Voltage (V)
4
6
8
-15
-10
10
D001
G = 10
Figure 43. Gain Nonlinearity
-4
-2
0
2
Output Voltage (V)
4
6
8
10
D001
Figure 44. Gain Nonlinearity
180
8
160
6
140
EMI Rejection-Ratio (dB)
Nonlinearity (ppm)
-6
G = 100
10
4
2
0
-2
-4
-6
Single-Ended Input
Common-Mode Input
120
100
80
60
40
20
-8
-10
-10
-8
-8
-6
-4
-2
0
2
Output Voltage (V)
4
6
8
10
0
10M
D001
100M
1G
Frequency (Hz)
10G
D001
G = 1000
Figure 46. EMIRR
Figure 45. Gain Nonlinearity
16
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7 Detailed Description
7.1 Overview
The INA188 is a monolithic instrumentation amplifier (INA) based on the 36-V, precision zero-drift OPA188
(operational amplifier) core. The INA188 also integrates laser-trimmed resistors to ensure excellent commonmode rejection and low gain error. The combination of the zero-drift amplifier core and the precision resistors
allows this device to achieve outstanding dc precision and makes the INA188 ideal for many high-voltage
industrial applications.
7.2 Functional Block Diagram
V1 = VCM ± G1 (VDIFF / 2)
V+
VIN- = VCM ± VDIFF / 2
VDIFF / 2
±
+
V+
RFI Filter
+ A1
Zero-Drift
- Amp
VINV+
20 k
V-
V+
RFI Filter
25 k
RG
V-
+
VCM
±
20 k
- A3
Zero-Drift
+ Amp
V+
25 k
VOUT
20 k
+
RFI Filter
VV+
RLOAD
V+
V+
±
VDIFF / 2
VO = G1 x G2 (VIN+ - VIN-)
-
20 k
- A2
Zero-Drift
+ Amp
VIN+
REF
RFI Filter
G1 = 1 + 2RF / RG
G2 = R2 / R1
V-
VV-
VIN+ = VCM + VDIFF / 2
V2 = VCM + G1 (VDIFF / 2)
VININA188
Simplified
Form
RG
VIN+
VOUT
+
REF
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7.3 Feature Description
7.3.1 Inside the INA188
The Functional Block Diagram section provides a detailed diagram for the INA188, including the ESD protection
and radio frequency interference (RFI) filtering. Instrumentation amplifiers are commonly represented in a
simplified form, as shown in Figure 47.
VININA188
Simplified
Form
RG
VIN+
VOUT
+
REF
Figure 47. INA Simplified Form
A brief description of the internal operation is as follows:
The differential input voltage applied across RG causes a signal current to flow through the RG resistor and both
RF resistors. The output difference amplifier (A3) removes the common-mode component of the input signal and
refers the output signal to the REF pin.
The equations shown in the Functional Block Diagram section describe the output voltages of A1 and A2.
Understanding the internal node voltages is useful to avoid saturating the device and to ensure proper device
operation.
7.3.2 Setting the Gain
The gain of the INA188 is set by a single external resistor, RG, connected between pins 1 and 8. The value of RG
is selected according to Equation 1:
50 k:
G 1
RG
(1)
Table 1 lists several commonly-used gains and resistor values. The 50-kΩ term in Equation 1 comes from the
sum of the two internal 25-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute
values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift
specifications of the INA188.
Table 1. Commonly-Used Gains and Resistor Values
(1)
18
DESIRED GAIN
RG (Ω)
NEAREST 1% RG (Ω)
1
NC (1)
NC
2
50k
49.9k
5
12.5k
12.4k
10
5.556k
5.49k
20
2.632k
2.61k
50
1.02k
1.02k
100
505.1
511
200
251.3
249
500
100.2
100
1000
50.05
49.9
NC denotes no connection. When using the SPICE model, the simulation does not converge unless a resistor is connected to the RG
pins; use a very large resistor value.
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7.3.2.1 Gain Drift
The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of
RG to gain accuracy and drift can be determined from Equation 1.
The best gain drift of 5 ppm/℃ can be achieved when the INA188 uses G = 1 without RG connected. In this case,
gain drift is limited only by the slight mismatch of the temperature coefficient of the integrated 20-kΩ resistors in
the differential amplifier (A3). At gains greater than 1, gain drift increases as a result of the individual drift of the
25-kΩ resistors in the feedback of A1 and A2, relative to the drift of the external gain resistor RG. The low
temperature coefficient of the internal feedback resistors significantly improves the overall temperature stability of
applications using gains greater than 1 V/V over competing alternate solutions.
Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring
resistance and contribute additional gain error (such as a possible unstable gain error) at gains of approximately
100 or greater. To ensure stability, avoid parasitic capacitance of more than a few picofarads at RG connections.
Careful matching of any parasitics on both RG pins maintains optimal CMRR over frequency; see Typical
Characteristics curve, Figure 17.
7.3.3 Zero Drift Topology
7.3.3.1 Internal Offset Correction
Figure 48 shows a simple representation of the proprietary zero-drift architecture for one of the three amplifiers
that comprise the INA188. These high-precision input amplifiers enable very low dc error and drift as a result of a
modern chopper technology with an embedded synchronous filter that removes nearly all chopping noise. The
chopping frequency is approximately 750 kHz. This amplifier is zero-corrected every 3 μs using a proprietary
technique. This design has no aliasing.
C2
Zero-Drift Amplifier Inside the INA188
GM1
CHOP1
CHOP2
Notch
Filter
GM2
GM3
OUT
+IN
-IN
C1
GM_FF
Figure 48. Zero-Drift Amplifier Functional Block Diagram
7.3.3.2 Noise Performance
This zero-drift architecture reduces flicker (1/f) noise to a minimum, and therefore enables the precise
measurement of small dc-signals with high resolution, accuracy, and repeatability. The auto-calibration technique
used by the INA188 results in reduced low-frequency noise, typically only 12 nV/√Hz (at G = 100). The spectral
noise density is detailed in Figure 53. Low-frequency noise of the INA188 is approximately 0.25 μVPP measured
from 0.1 Hz to 10 Hz (at G = 100).
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7.3.3.3 Input Bias Current Clock Feedthrough
Zero-drift amplifiers, such as the INA188, use switching on their inputs to correct for the intrinsic offset and drift of
the amplifier. Charge injection from the integrated switches on the inputs can introduce very short transients in
the input bias current of the amplifier. The extremely short duration of these pulses prevents them from being
amplified; however, the pulses can be coupled to the output of the amplifier through the feedback network. The
most effective method to prevent transients in the input bias current from producing additional noise at the
amplifier output is to use a low-pass filter (such as an RC network).
7.3.4
EMI Rejection
180
160
160
140
140
120
120
EMIRR (dB)
EMIRR (dB)
The INA188 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources (such as wireless communications) and densely-populated boards with a mix of analog signal-chain and
digital components. The INA188 is specifically designed to minimize susceptibility to EMI by incorporating an
internal low-pass filter. Depending on the end-system requirements, additional EMI filters may be required near
the signal inputs of the system, as well as incorporating known good practices such as using short traces, lowpass filters, and damping resistors combined with parallel and shielded signal routing. Texas Instruments
developed a method to accurately measure the immunity of an amplifier over a broad frequency spectrum,
extending from 10 MHz to 6 GHz. This method uses an EMI rejection ratio (EMIRR) to quantify the INA188 ability
to reject EMI. Figure 49 and Figure 50 show the INA188 EMIRR graph for both differential and common-mode
EMI rejection across this frequency range. Table 2 shows the EMIRR values for the INA188 at frequencies
commonly encountered in real-world applications. Applications listed in Table 2 can be centered on or operated
near the particular frequency shown.
100
80
60
100
80
60
40
40
20
20
0
10M
100M
1G
10G
Frequency (Hz)
0
10M
100M
Figure 49. Common Mode EMIRR Testing
1G
10G
Frequency (Hz)
C035
C036
Figure 50. Differential Mode (VIN+) EMIRR Testing
Table 2. INA188 EMIRR for Frequencies of Interest
FREQUENCY
20
APPLICATION OR ALLOCATION
DIFFERENTIAL
(IN-P) EMIRR
COMMON-MODE
EMIRR
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultrahighfrequency (UHF) applications
83 dB
101 dB
900 MHz
Global system for mobile communications (GSM) applications, radio
communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF
applications
103 dB
118 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite,
L-band (1 GHz to 2 GHz)
112 dB
125 dB
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications,
industrial, scientific and medical (ISM) radio band, amateur radio and satellite,
S-band (2 GHz to 4 GHz)
114 dB
123 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
110 dB
121 dB
5.0 GHz
802.11a, 802.11n, aero communication and navigation, mobile communication,
space and satellite operation, C-band (4 GHz to 8 GHz)
119 dB
123 dB
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7.3.5 Input Protection and Electrical Overstress
Designers often ask questions about the capability of an amplifier to withstand electrical overstress. These
questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output pin. Each
of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics
of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal
ESD protection is built into these circuits to protect them from accidental ESD events both before and during
product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. The Functional Block Diagram section illustrates the ESD circuits contained in the INA188. The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines. This protection circuitry is intended to remain inactive during normal
circuit operation.
The input pins of the INA188 are protected with internal diodes connected to the power-supply rails. These
diodes clamp the applied signal to prevent the input circuitry from being damaged. If the input signal voltage can
exceed the power supplies by more than 0.3 V, limit the input signal current to less than 10 mA to protect the
internal clamp diodes. This current limiting can generally be done with a series input resistor. Some signal
sources are inherently current-limited and do not require limiting resistors.
7.3.6 Input Common-Mode Range
The linear input voltage range of the INA188 input circuitry extends from 100 mV inside the negative supply
voltage to 1.5 V below the positive supply, and maintains 84-dB (minimum) common-mode rejection throughout
this range. The common-mode range for most common operating conditions is best calculated using the INA
common-mode range calculating tool. The INA188 can operate over a wide range of power supplies and VREF
configurations, thus providing a comprehensive guide to common-mode range limits for all possible conditions is
impractical.
The most commonly overlooked overload condition occurs when a circuit exceeds the output swing of A1 and A2,
which are internal circuit nodes that cannot be measured. Calculating the expected voltages at the output of A1
and A2 (see the Functional Block Diagram section) provides a check for the most common overload conditions.
The designs of A1 and A2 are identical and the outputs can swing to within approximately 250 mV of the powersupply rails. For example, when the A2 output is saturated, A1 can continue to be in linear operation, responding
to changes in the noninverting input voltage. This difference can give the appearance of linear operation but the
output voltage is invalid.
7.4 Device Functional Modes
7.4.1 Single-Supply Operation
The INA188 can be used on single power supplies of 4 V to 36 V. Use the output REF pin to level shift the
internal output voltage into a linear operating condition. Ideally, connecting the REF pin to a potential that is midsupply avoids saturating the output of the input amplifiers (A1 and A2). Actual output voltage swing is limited to
250 mV above ground when the load is referred to ground. The typical characteristic curves, Output Voltage
Swing vs Output Current (Figure 19 to Figure 22) illustrates how the output voltage swing varies with output
current. See the Driving the Reference Pin section for information on how to adequately drive the reference pin.
With single-supply operation, VIN+ and VIN– must both be 0.1 V above ground for linear operation. For instance,
the inverting input cannot be connected to ground to measure a voltage connected to the noninverting input.
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Device Functional Modes (continued)
7.4.2 Offset Trimming
Most applications require no external offset adjustment; however, if necessary, adjustments can be made by
applying a voltage to the REF pin. Figure 51 shows an optional circuit for trimming the output offset voltage. The
voltage applied to the REF pin is summed at the output. The op amp buffer provides low impedance at the REF
pin to preserve good common-mode rejection.
VIN-
-
RG
VIN+
V+
INA188
100 µA
½ REF200
+
REF
100
OPA333
10 k
+
±10 mV Adjustment
Range
100
100 µA
½ REF200
V-
Figure 51. Optional Trimming of the Output Offset Voltage
22
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Device Functional Modes (continued)
7.4.3 Input Bias Current Return Path
The input impedance of the INA188 is extremely high—approximately 20 GΩ. However, a path must be provided
for the input bias current of both inputs. This input bias current is typically 750 pA. High input impedance means
that this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 52 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA188, and the input amplifiers saturate. If the differential source resistance is
low, the bias current return path can be connected to one input (as shown in the thermocouple example in
Figure 52). With a higher source impedance, using two equal resistors provides a balanced input with possible
advantages of a lower input offset voltage as a result of bias current and better high-frequency common-mode
rejection.
Microphone,
hydrophone,
and so forth.
RG
INA188
+
47 k
47 k
RG
Thermocouple
INA188
+
10 k
RG
INA188
+
Center tap provides
bias current return.
Figure 52. Providing an Input Common-Mode Current Path
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Device Functional Modes (continued)
7.4.4 Driving the Reference Pin
The output voltage of the INA188 is developed with respect to the voltage on the reference pin. Often, the
reference pin (pin 5) is connected to the low-impedance system ground in dual-supply operation. In single-supply
operation, offsetting the output signal to a precise mid-supply level (for example, 2.5 V in a 5-V supply
environment) can be useful. To accomplish this, a voltage source can be tied to the REF pin to level-shift the
output so that the INA188 can drive a single-supply analog-to-digital converter (ADC).
For best performance, keep the source impedance to the REF pin below 5 Ω. As illustrated in the Functional
Block Diagram section, the reference pin is internally connected to a 20-kΩ resistor. Additional impedance at the
REF pin adds to this 20-kΩ resistor. The imbalance in the resistor ratios results in degraded common-mode
rejection ratio (CMRR).
Figure 53 shows two different methods of driving the reference pin with low impedance. The OPA330 is a lowpower, chopper-stabilized amplifier, and therefore offers excellent stability over temperature. The OPA330 is
available in a space-saving SC70 and an even smaller chip-scale package. The REF3225 is a precision
reference in a small SOT23-6 package.
5V
5V
VIN-
VIN-
RG
VOUT
INA188
RG
REF
VIN+
+
VOUT
INA188
REF
5V
VIN+
5V
+
2.5 V
+
a) Level shifting using the OPA330 as a low-impedance buffer.
REF3225
b) Level shifting using the low-impedance output of the REF3225.
Figure 53. Options for Low-Impedance Level Shifting
24
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Device Functional Modes (continued)
7.4.5 Error Sources Example
Most modern signal-conditioning systems calibrate errors at room temperature. However, calibration of errors
that result from a change in temperature is normally difficult and costly. Therefore, minimizing these errors is
important and can be done by choosing high-precision components (such as the INA188 that has improved
specifications in critical areas that impact the precision of the overall system). Figure 54 shows an example
application.
15 V
10 k
+
RG
5.49 k
VDIFF = 1 V
-
INA188
10 k
REF
+
VCM = 10 V
VOUT
Signal Bandwidth = 5 kHz
-15 V
Figure 54. Example Application with G = 10 V/V and a 1-V Differential Voltage
Resistor-adjustable INAs such as the INA188 show the lowest gain error in G = 1 because of the inherently wellmatched drift of the internal resistors of the differential amplifier. At gains greater than 1 (for instance, G = 10 V/V
or G = 100 V/V) the gain error becomes a significant error source because of the contribution of the resistor drift
of the 25-kΩ feedback resistors in conjunction with the external gain resistor. Except for very high-gain
applications, gain drift is by far the largest error contributor compared to other drift errors, such as offset drift. The
INA188 offers the lowest gain error over temperature in the marketplace for both G > 1 and G = 1 (no external
gain resistor). Table 3 summarizes the major error sources in common INA applications and compares the two
cases of G = 1 (no external resistor) and G = 10 (5.49-kΩ external resistor). As explained in Table 3, although
the static errors (absolute accuracy errors) in G = 1 are almost twice as great as compared to G = 10, there are
much fewer drift errors because of the much lower gain error drift. In most applications, these static errors can
readily be removed during calibration in production. All calculations refer the error to the input for easy
comparison and system evaluation.
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Device Functional Modes (continued)
Table 3. Error Calculation
ERROR SOURCE
ERROR CALCULATION
SPECIFICATION
G = 10 ERROR
(ppm)
G = 1 ERROR
(ppm)
ABSOLUTE ACCURACY AT 25°C
Input offset voltage
VOSI / VDIFF
65 μV
65
65
Output offset voltage
VOSO / (G × VDIFF)
180 μV
18
180
Input offset current
IOS × maximum (RS+, RS–) / VDIFF
5 nA
50
50
104 dB (G = 10),
84 dB (G = 1)
20
501
153
796
2800
80
Common-mode rejection ratio
CMRR/20
VCM / (10
× VDIFF)
Total absolute accuracy error (ppm)
DRIFT TO 105°C
35 ppm/°C (G = 10),
1 ppm/°C (G = 1)
Gain drift
GTC × (TA – 25)
Input offset voltage drift
(VOSI_TC / VDIFF) × (TA – 25)
0.15 μV/°C
12
12
Output offset voltage drift
[VOSO_TC / ( G × VDIFF)] × (TA – 25)
0.85 μV/°C
6.8
68
Offset current drift
IOS_TC × maximum (RS+, RS–) ×
(TA – 25) / VDIFF
60 pA/°C
48
48
2867
208
5 ppm of FS
5
5
eNI = 18,
eNO = 110
9
47
14
52
3034
1056
Total drift error (ppm)
RESOLUTION
Gain nonlinearity
Voltage noise (1 kHz)
BW ´
(eNI2 +
eNO
G
2
6
´
VDIFF
Total resolution error (ppm)
TOTAL ERROR
Total error (ppm)
26
Total error = sum of all error sources
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The INA188 measures a small differential voltage with a high common-mode voltage developed between the
noninverting and inverting input. The low offset drift in conjunction with no 1/f noise makes the INA188 suitable
for a wide range of applications. The ability to set the reference pin to adjust the functionality of the output signal
offers additional flexibility that is practical for multiple configurations.
8.2 Typical Application
Figure 55 shows the basic connections required for operating the INA188. Applications with noisy or highimpedance power supplies may require decoupling capacitors close to the device pins. The output is referred to
the output reference (REF) pin that is normally grounded. The reference pin must be a low-impedance
connection to assure good common-mode rejection.
15 V
±10 V
100 k
4.87 k
4 mA to 20 mA
±20 mA
RG
12.4 k
VOUT = 2.5 V ± 2.3 V
INA188
+
REF
20
2.5 V
REF3225
5V
15 V
10 F
Figure 55. PLC Input (±10 V, 4 mA to 20 mA)
8.2.1 Design Requirements
For this application, the design requirements are:
• 4-mA to 20-mA input with less than 20-Ω burden
• ±20-mA input with less than 20-Ω burden
• ±10-V input with impedance of approximately 100 kΩ
• Maximum 4-mA to 20-mA or ±20mA burden voltage equal to ±0.4 V
• Output range within 0 V to 5 V
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Typical Application (continued)
8.2.2 Detailed Design Procedure
The following steps must be applied for proper device functionality:
• For a 4-mA to 20-mA input, the maximum burden of 0.4 V must have a burden resistor equal to 0.4 / 0.02 =
20 Ω.
• To center the output within the 0-V to 5-V range, VREF must equal 2.5 V.
• To keep the ±20-mA input linear within 0 V to 5 V, the gain resistor (RG) must be 12.4 kΩ.
• To keep the ±10-V input within the 0-V to 5-V range, attenuation must be greater than 0.05.
• A 100-kΩ resistor in series with a 4.87-kΩ resistor provides 0.0466 attenuation of ±10 V, well within the ±2.5V linear limits.
8.2.3 Application Curve
5
4.5
4
Output (V)
3.5
3
2.5
2
1.5
1
0.5
0
-10
-8
-6
-4
-2
0
2
Input (V)
4
6
8
10
D001
Figure 56. Plot of PLC Input Transfer Function
28
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9 Power Supply Recommendations
The minimum power-supply voltage for the INA188 is ±2 V and the maximum power-supply voltage is ±18 V.
This minimum and maximum range covers a wide range of power supplies. However, for optimum performance,
±15 V is recommended. A 0.1-µF bypass capacitor is recommended to be added at the input to compensate for
the layout and power-supply source impedance.
10 Layout
10.1 Layout Guidelines
Attention to good layout practices is always recommended. For best operational performance of the device, use
good printed circuit board (PCB) layout practices, including:
• Care must be taken to ensure that both input paths are well-matched for source impedance and capacitance
to avoid converting common-mode signals into differential signals. In addition, parasitic capacitance at the
gain-setting pins can also affect CMRR over frequency. For example, in applications that implement gain
switching using switches or PhotoMOS® relays to change the value of RG, select the component so that the
switch capacitance is as small as possible.
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the device
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, see
SLOA089, Circuit Board Layout Techniques.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better
than in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 57, keeping RG
close to the pins minimizes parasitic capacitance.
• Keep the traces as short as possible.
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10.2 Layout Example
Gain Resistor
Bypass
Capacitor
VIN
VIN
–
+
R6
R6
V–IH
V+
V+IH
VO
V–
REF
V+
VOUT
GND
Bypass
Capacitor
V–
GND
Figure 57. PCB Layout Example
30
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
Table 4. Table 1. Design Kits and Evaluation Modules
NAME
PART NUMBER
TYPE
DIP Adapter Evaluation Module
DIP-ADAPTER-EVM
Evaluation Module and Boards
Universal Instrumentation Amplifier Evaluation Module
INAEVM
Evaluation Module and Boards
Table 5. Table 2. Development Tools
NAME
PART NUMBER
TYPE
Calculate Input Common-Mode Range of Instrumentation Amplifiers
INA-CMV-CALC
Calculation Tools
SPICE-Based Analog Simulation Program
TINA-TI
Circuit Design and Simulation
11.2 Documentation Support
11.2.1 Related Documentation
OPA188 Data Sheet, SBOS642
OPA330 Data Sheet, SBOS432
REF3225 Data Sheet, SBVS058
Circuit Board Layout Techniques, SLOA089
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
PhotoMOS is a registered trademark of Panasonic Electric Works Europe AG.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
INA188ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA188
INA188IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA188
INA188IDRJR
PREVIEW
SON
DRJ
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA188
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Dec-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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