Anpec APW8802QBI-TRL High input voltage 8a pwm dc/dc converter Datasheet

APW8802
High Input Voltage 8A PWM DC/DC Converter
Features
General Description
•
Operates from An Input Battery Voltage Range of
The APW8802 is a 8A, synchronous, step-down converter
+3V to +25V
with integrated 12mΩ N-channel High-Side MOSFET and
12mΩ Low-Side MOSFET. The APW8802 steps down
•
±1.6% 0.75V Reference
high voltage to generate low-voltage chipset or RAM supplies in notebook computers.
- Over Line, Load Regulation, and Operating Temp.
•
High Efficiency all Over 90% at VOUT=1V, VIN=19V
The APW8802 provides excellent transient response and
accurate DC voltage output in either PFM or PWM Mode.
Condition
•
Power-On-Reset Monitoring on PVCC and VCC Pins
•
Excellent Line and Load Transient Responses
•
Integrated 12mΩ @ VCC=5V N-Channel MOSFET
In Pulse Frequency Mode (PFM), the APW8802 provides
very high efficiency over light to heavy loads with loadingmodulated switching frequencies. In PWM Mode, the converter works nearly at constant frequency for low-noise
For High Side
•
Integrated 12mΩ @ VCC=5V N-Channel MOSFET
requirements.
The APW8802 is equipped with accurate current-limit,
For Low Side
•
output under-voltage, and output over-voltage protections,
perfect for NB applications. A Power-On-Reset function
Programmable PWM Frequency from 100kHz to
500kHz
•
Built-in 1.2ms Digital Soft-Start & Soft-Stop
•
Built-in COT Mode Control for Fast Response and
monitors the voltage on VPVCC and VCC to prevent wrong
operation during power-on. The APW8802 has a 1.2ms
digital soft-start and built-in an integrated output discharge
device for soft-stop. An internal integrated soft-start ramps
MLCC Supports
•
Power Good Monitoring
•
70% Under-Voltage Protection
•
125% Over-Voltage Protection
•
Adjustable Current-Limit Protection
discharges the output capacitors.
The APW8802 is available in TQFN5x6-28 (Power PAK)
- Using Built-in Low-Side MOSFET’s RDS(ON)
package.
•
Over-Temperature Protection
•
TQFN5x6-28 (Power PAK) Package
•
Lead Free and Green Devices Available
up the output voltage with programmable slew rate to
reduce the start-up current. A soft-stop function actively
Simplified Application Circuit
(RoHS Compliant)
5V
Applications
VCC
•
Notebook
•
Table PC
•
Hand-Held Portable
•
AIO PC
VIN
PVCC
BOOT
LOUT
VOUT
LX
EN
RTON
ROCSET
TON
OCSET
FB
APW8802
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jan., 2013
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APW8802
Ordering and Marking Information
Package Code
QB : TQFN5x6-28
Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW8802
Assembly Material
Handling Code
Temperature Range
Package Code
APW8802 QB :
APW8802
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
23 EN
24 TON
25 VOUT
26 OCSET
27 PVCC
28 VCC
Pin Configuration
FB 1
22 PGND
POK 2
21 BOOT
GND 3
20 VIN
PGND
VIN
PGND 4
19 VIN
PGND 5
18 VIN
17 LX
NC 6
LX
NC 7
16 LX
15 LX
LX 14
LX 13
LX 12
LX 11
LX 10
LX 9
LX 8
TQFN5x6-28
(Top View)
= Thermal Pad (connected to GND plane for better heat dissipation)
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APW8802
Absolute Maximum Ratings (Note 1)
Symbol
VCC
Parameter
VCC Supply Voltage (VCC to GND)
Rating
Unit
-0.3 ~ 7
V
VPVCC
PVCC Supply Voltage (PVCC to PGND)
-0.3 ~ 7
V
VBOOT-GND
BOOT Supply Voltage (BOOT to GND)
-0.3 ~ 35
V
BOOT Supply Voltage (BOOT to LX)
-0.3 ~ 7
V
VBOOT
VIN
Input Power Voltage (VIN to GND)
All Other Pins (VOUT, TON, EN, OCSET and FB to GND)
-0.3 ~ 25
V
-0.3 ~ VCC+0.3
V
-5 ~ 35
-1 ~ 28
V
LX Voltage (LX to GND)
VLX
<400ns Pulse Width
>400ns Pulse Width
VPOK
POK Supply Voltage (POK to GND)
VPGND
PGND to GND Voltage
PD
TJ
Package Power Dissipation, TA=25 oC
Maximum Junction Temperature
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
-0.3 ~ 7
V
-0.3 ~ 0.3
V
2.5
W
150
o
-65 ~ 150
o
260
o
C
C
C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
θJA
Parameter
Thermal Resistance -Junction to Ambient
Typical Value
Unit
40
°C/W
(Note 2)
TQFN5x6-28
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
is soldered directly on the PCB.
Recommended Operating Conditions (Note 3)
Symbol
VIN
Parameter
Unit
3 ~ 25
V
VCC, PVCC Supply Voltage
4.5 ~ 5.5
V
VOUT
Converter Output Voltage
0.75 ~ 5.5
V
IOUT
Converter Output Current
TA
Ambient Temperature
VCC, VPVCC
TJ
Converter Input Voltage
Range
0~8
Junction Temperature
A
-40 ~ 85
o
-40 ~ 125
o
C
C
Note 3: Refer to the typical application circuit.
Copyright  ANPEC Electronics Corp.
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APW8802
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VCC=5V, VPVCC=5V, and TA= -40 ~ 85 °C, unless
otherwise specified. Typical values are at TA=25°C.
Symbol
Parameter
APW8802
Test Conditions
Min.
Unit
Typ.
Max.
0.75
-
5.5
V
-
0.75
-
V
-0.9
-
+0.9
%
TA=0 C~85 C
-1.3
-
+1.3
%
TA=-40 oC~85 oC
-1.6
-
+1.6
%
OUTPUT AND REFERENCE VOLTAGES
VOUT
Output Voltage
VREF
Reference Voltage
Adjustable output range
o
TA=25 C
Regulation Accuracy
IFB
RDIS
o
o
FB Input Bias Current
VFB=0.75V
-
0.02
0.1
µA
VOUT Discharge Resistance
VEN=0V, VOUT=0.5V
-
20
32
Ω
VCC Plus PVCC Current, PWM,
EN is Floating, VFB=0.77V, VLX=-0.1V
-
400
750
µA
VCC Plus PVCC Current, PFM, VEN=5V,
VFB=0.77V, VLX=0.5V
-
250
470
µA
SUPPLY CURRENT
IVCC
VCC Input Bias Current
IVCC_SHDN
VCC Shutdown Current
EN=GND, VCC=5V
-
0
1.0
µA
IPVCC_SHDN
PVCC Shutdown Current
EN=GND, VPVCC=5V
-
4.5
7.5
µA
ON-TIME TIMER AND INTERNAL SOFT-START
TONN
Nominal on Time
VLX=12V, VOUT=2.5V, RTON=250kΩ
-
749
-
ns
TONF
Fast on Time
VLX=12V, VOUT=2.5V, RTON=100kΩ
280
330
380
ns
TONS
Slow on Time
VLX=12V, VOUT=2.5V, RTON=400kΩ
-
1170
-
ns
TON(MIN)
Minimum on Time
TOFF(MIN)
Minimum off Time
TSS
Internal Soft-Start Time
VFB=0.7V, VLX= -0.1V, OCSET is Open
EN High to VOUT Regulation
80
110
140
ns
350
450
550
ns
0.9
1.2
1.5
ms
INTERNAL POWER MOSFETs
High Side Switch Resistance
VCC=5V, Guaranteed by design
-
12
15
mΩ
Low Side Switch Resistance
VCC=5V, Guaranteed by design
-
12
15
mΩ
V
PVCC AND VCC POWER-ON-RESET THRESHOLD
VPVCC_THR
Rising PVCC POR Threshold Voltage
4.25
4.35
4.45
VCC_THR
Rising VCC POR Threshold Voltage
4.25
4.35
4.45
V
-
100
-
mV
EN High Logic Level (Set in
Automatic PFM/PWM Mode)
2.5
2.65
2.8
V
Hysteresis
100
175
225
mV
1.3
1.95
2.39
V
0.7
1.0
1.3
V
150
200
250
mV
-
0.1
1.0
µA
VCC POR Hysteresis
CONTROL INPUTS
EN Floating Level (Set in
Forced-PWM Mode)
EN Low Logic Level (Set in
Shutdown)
Hysteresis
EN Leakage
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jan., 2013
VEN=0V
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APW8802
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VCC=5V, VPVCC=5V, and TA= -40 ~ 85 °C, unless
otherwise specified. Typical values are at TA=25°C.
Symbol
Parameter
APW8802
Test Conditions
Unit
Min.
Typ.
Max.
87
90
93
%
POK Low Hysteresis
(POK Goes Low)
-
3
-
%
POK out from Normal
(POK Goes Low)
120
125
130
%
-
0.1
1.0
µA
POWER-OK INDICATOR
POK in from Lower
(POK Goes High)
VPOK
IPOK
POK Threshold
POK Leakage Current
VPOK=5V
POK Sink Current
VPOK=0.5V
2.5
7.5
-
mA
POK Enable Delay Time
EN high to POK high
1.4
2.0
2.6
ms
9
10
11
µA
-
4500
-
ppm/oC
CURRENT SENSE
IOCSET
IOCSET Sourcing Current
TCIOCSET
IOCSET Temperature Coefficient
On The Basis of 25°C
VROCSET
Current-Limit Threshold
Setting Range
VOCSET-GND Voltage, Over All
Temperature
30
-
200
mV
Over Current-Limit
Comparator Offset
(VOCSET-GND-VPGND-LX) Voltage,
VOCSET-GND=60mV
-10
0
10
mV
Negative Over Current-Limit
Comparator Offset
(VOCSET-GND-VPGND- LX) Voltage,
VOCSET-GND=60mV, EN is Floating
-9.5
0.5
10.5
mV
Zero Crossing Comparator
Offset
VPGND- LX Voltage, VEN=3.3V
-9.5
0.5
10.5
mV
60
70
80
%
Under-Voltage Protection
Hysteresis
-
3
-
%
Under-Voltage Debounce
Interval
-
16
-
µs
1.4
2
2.6
ms
120
125
130
%
-
1.5
-
µs
Over-Temperature Protection
Rising Threshold (Note 4)
-
160
-
o
Over-Temperature Protection
Hysteresis (Note 4)
-
25
-
o
PROTECTIONS
VUV
Under-Voltage Protection
Threshold
Under-Voltage Protection
Enable Delay
VOVR
EN High to UVP Workable
Over-Voltage Protection Rising
Threshold
Over-Voltage Protection
Propagation Delay
TOTR
VFB Falling
VFB Rising, DV=10mV
C
C
Note 4: Guaranteed by design.
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APW8802
Typical Operating Characteristics
Junction Temperature
0.760
OCSET Sourcing Current, IOCSET (µA)
Reference Voltage Accuracy, VREF (V)
Reference Voltage Accuracy vs.
0.755
0.750
0.745
0.740
-50
-30
-10
10
30
50
70
90
110
OCSET Sourcing Current vs.
Junction Temperature
16
14
12
10
8
6
4
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature, TJ (oC)
Junction Temperature, TJ (oC)
100
10
VIN=19V,
VOUT=1.05V,
FSW=300kHz
1
Automatic PFM/PWM Mode
0.1
0.001
Forced-PWM Mode
0.01
0.1
1
Switching Frequency vs.
Converter Input Voltage
340
Switching Frequency, FSW (kHz)
Switching Frequency, FSW (kHz)
1000
Switching Frequency vs.
Converter Output Current
320
300
280
Forced-PWM MODE
260
10
7
Efficiency vs.
Load Current FSW=300kHz, VOUT=1.05V
800
Switching Frequency, FSW (kHz)
100
Efficiency (%)
90
80
70
60
50
0.100
VIN=19V,
Automatic PFM/PWM Mode
11
13
15
17
19
21
Switching Frequency vs.
TON Resistance
VIN=19V, Forced-PWM Mode
700
600
500
400
300
200
100
0
100
10.000
1.000
Converter Output Current, IOUT (A)
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Converter Input Voltage, VIN (V)
Converter Output Current, IOUT (A)
VOUT=1.05V
VOUT=2.5V
200
300
400
500
600
700
TON Resistance, RTON (kΩ)
6
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APW8802
Typical Operating Characteristics (Cont.)
Converter Output Voltage vs.
Converter Output Current
1.09
VIN=19V,
VOUT=1.05V,
FSW=300kHz
1.055
Converter Output Voltage, VOUT (V)
Converter Output Voltage, VOUT (V)
1.060
1.050
1.045
1.040
1.035
1.030
Automatic PFM/PWM Mode
Forced-PWM Mode
0
1
2
3
4
5
6
7
VOUT=1.05V,
Automatic PFM/PWM Mode
1.08
1.07
1.06
1.05
1.04
1.03
IOUT=0A
1.02
1.01
8
IOUT=8A
5
7
9
11 13 15
17 19 21 23 25
Converter Input Voltage, VIN (V)
Converter Output Current, IOUT (A)
Copyright  ANPEC Electronics Corp.
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Converter Output Voltage vs.
Converter Input Voltage
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APW8802
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=19V, TA=25oC unless otherwise specified.
VOUT=1.05V, Load Transient 1A->8A->1A
Switching Waveform
1
1
2
2
3
3
CH1: VLX, 20V/Div, AC
CH2: VOUT, 20mV/Div, AC
CH3: IL, 5A/Div, DC
TIME: 2µs/Div
CH1: VLX, 10V/Div, DC
CH2: VOUT, 100mV/Div, AC
CH3: IL, 5A/Div, DC
TIME: 20µs/Div
Mode Transient from PFM to PWM
Mode Transient from PWM to PFM
1
1
2
2
3
3
4
4
CH1: V EN, 2V/Div, DC
CH2: VLX, 20V/Div, DC
CH3: VOUT, 20mV/Div, AC
CH4: IL, 2A/Div, DC
TIME: 10µs/Div
CH1: V EN, 2V/Div, DC
CH2: VLX, 20V/Div, DC
CH3: VOUT, 20mV/Div, AC
CH4: IL, 2A/Div, DC
TIME: 10µs/Div
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APW8802
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=19V, TA=25oC unless otherwise specified.
Enable at Zero Initial Voltage of VOUT
Enable Before End of Soft-Stop
ILOAD =8A
No Load
1
1
2
2
3
3
4
4
CH1: V EN, 5V/Div, DC
CH2: VLX, 20V/Div, DC
CH3: V OUT, 500mV/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 1ms/Div
CH1: VEN, 5V/Div, DC
CH2: VLX, 20V/Div, DC
CH3: VOUT, 500mV/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 1ms/Div
Shutdown at IOUT=8A
Shutdown with Soft-Stop at No Load
1
1
2
2
3
3
4
4
CH1: VEN, 2V/Div, DC
CH2: VLX, 20V/Div, DC
CH3: VOUT, 500mV/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 5ms/Div
CH1: VEN, 5V/Div, DC
CH2: VLX, 20V/Div, DC
CH3: VOUT, 500mV/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 1ms/Div
Copyright  ANPEC Electronics Corp.
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APW8802
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=19V, TA=25oC unless otherwise specified.
Current-Limit and Under-Voltage Protection
Short Circuit Test
In PFM Mode
1
1
2
2
3
3
4
4
CH1: VPOK, 5V/Div, DC
CH2: VLX, 20V/Div, DC
CH3: VOUT, 500mV/Div, DC
CH4: IL, 10A/Div, DC
TIME: 10µs/Div
CH1: VPOK, 5V/Div, DC
CH2: VLX, 20V/Div, DC
CH3: VOUT, 500mV/Div, DC
CH4: IL, 10A/Div, DC
TIME: 100µs/Div
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APW8802
Pin Description
PIN
FUNCTION
NO.
NAME
1
FB
Output Voltage Feedback Pin. This pin is connected to the resistive divider that set the desired output
voltage. The POK, UVP, and OVP circuits detect this signal to report output voltage status.
2
POK
Power Good Output. POK is an open drain output used to indicate the status of the output voltage. Connect
the POK in to +5V through a pull-high resistor.
Signal Ground for The IC.
3
GND
4, 5, 22
PGND
6, 7
NC
No Connection.
8 ~ 17
LX
Junction Point of The High-side MOSFET Source, Output Filter Inductor And The Low-side MOSFET Drain.
Connect this pin to the output inductor. LX serves as the lower supply rail for the high-side gate driver.
18, 19, 20
VIN
Battery voltage input pin.
21
BOOT
Supply Input for The High-side MOSFET Gate Driver And An Internal Level-shift Circuit. Connect to an
external capacitor to create a boosted voltage suitable to drive a logic-level N-channel MOSFET.
23
EN
Enable Pin of The PWM Controller. When the EN is above high logic level, the device is in automatic
PFM/PWM Mode. When the EN is floating, the device is in Forced-PWM Mode. When the EN is below low
logic level, the device is in shutdown and only low leakage current is taken from VCC and VIN.
24
TON
This pin is allowed to adjust the switching frequency. Connect a resistor RTON = 100kΩ ~ 600kΩ from TON
to LX.
25
VOUT
The VOUT Pin Makes A Direct Measurement for On-Time Generator. The VOUT should be connected to the
top feedback resistor at the converter output.
26
OCSET
Current-Limit Threshold Setting Pin. There is an internal source current 10µA through a resistor from
OCSET to GND. This pin is used to monitor the voltage drop across the Drain and Source of the low-side
MOSFET for current-limit.
27
PVCC
Supply Voltage Input Pin for The Low-side MOSFET Gate Driver. Connect +5V from the PVCC to the
PGND. Decoupling at least 1µF of a MLCC capacitor from the PVCC to the PGND.
28
VCC
Supply Voltage Input Pin for Control Circuitry. Connect +5V from the VCC to the GND. Decoupling at least
1µF of a MLCC capacitor from the VCC to the GND.
Power Ground of The Low-side MOSFET Driver and the Source of Internal Low-side MOSFET.
Copyright  ANPEC Electronics Corp.
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APW8802
Block Diagram
POK
VIN VOUT
GND
VIN
125% VREF
Current- Limit
Delay
OCSET
10µA
90% VREF
Frequency
Adjustable
OV
Fault
Latch
Logic
UV
70% VREF
Digital
Soft-Start/
Soft-Stop
On-Time
Generator
ZC
Error
Comparator
TON
UGATE
Gate
Driver
VLX
LX
PVCC
PVCC
LX
VREF
LGATE
VCC
POR
VIN
BOOT
Thermal
Shutdown
FB
VCC
PVCC
PWM Signal Controller
125% VREF
VPVCC
Force PWM or
Automatic PFM/
PWM Selection
Gate
Driver
PGND
EN
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APW8802
Typical Application Circuit
APW8802
VIN
EN
BOOT
+5V
CBOOT
0.1µF
LOUT
2.2µH
PVCC
LX
RVCC
2.2
RPOK
100k
CVCC
1µF
TON
VCC
10k
RTON
200k
100nF
VIN
CIN
10µF/25V
(MLCC)
VOUT
1.05V, 8A
100nF
RTOP
390
COUT
47µFx3
GND
FB
POK
OCSET
RGND
1k
ROCSET
VOUT
PGND
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APW8802
Function Description
Constant-On-Time PWM Controller with Input Feed-Forward
Where FSW is the nominal switching frequency of the converter in PWM mode.
The constant-on-time control architecture is a pseudofixed
The load current at handoff from PFM to PWM mode is
given by:
frequency with input voltage feed-forward. This architecture relies on the output filter capacitor’s effective series
1 VIN − VOUT
×
× TON-PFM
2
L
V − VOUT
1
V
= IN
×
x OUT
2L
FSW
VIN
ILOAD(PFM to PWM) =
resistance (ESR) to act as a current-sense resistor, so
the output ripple voltage provides the PWM ramp signal.
In PFM operation, the high-side switch on-time controlled
by the on-time generator is determined solely by a oneshot
Forced-PWM Mode
The Forced-PWM mode disables the zero-crossing
whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. In PWM
comparator, which truncates the low-side switch on-time
at the inductor current zero crossing. This causes the
operation, the high-side switch on-time is determined by
a switching frequency control circuit in the on-time gen-
low-side gate-drive waveform to become the complement
of the high-side gate-drive waveform. This in turn causes
erator block.
The switching frequency control circuit senses the switch-
the inductor current to reverse at light loads while UGATE
maintains a duty factor of VOUT/VIN. The benefit of Forced-
ing frequency of the high-side switch and keeps regulating it at a constant frequency in PWM mode. The design
PWM mode is to keep the switching frequency fairly
constant. The Forced-PWM mode is most useful for re-
improves the frequency variation and is more outstanding than a conventional constant-on-time controller, which
ducing audio frequency noise, improving load-transient
response, and providing sink-current capability for dy-
has large switching frequency variation over input voltage,
output current, and temperature. Both in PFM and PWM,
namic output voltage adjustment.
the on-time generator, which senses input voltage on
PHASE pin, provides very fast on-time response to input
Power-On-Reset
A Power-On-Reset (POR) function is designed to prevent
line transients.
Another one-shot sets a minimum off-time (450ns,
wrong logic controls when the PVCC or VCC voltage is
low. The POR function continually monitors the bias sup-
typical). The on-time one-shot is triggered if the error comparator is high, the low-side switch current is below the
ply voltage on the PVCC and VCC pins if at least one of
the enable pins is set high. When the rising PVCC volt-
current-limit threshold, and the minimum off-time oneshot
has timed out.
age reaches the rising PVCC POR voltage threshold
(4.35V, typical) and the rising VCC voltage reaches the
Pulse-Frequency Modulation (PFM)
rising VCC POR Threshold (4.35V, typical), the POR signal goes high and the chip initiates soft-start operations.
In PFM mode, an automatic switchover to pulse-frequency
modulation (PFM) takes place at light loads. This
There is almost no hysteresis to POR voltage threshold
(about 100mV typical). When PVCC voltage drops lower
switchover is affected by a comparator that truncates the
low-side switch on-time at the inductor current zero
than 4.25V (typical) or VCC voltage drops lower than
4.25V (typical), the POR disables the chip.
crossing. This mechanism causes the threshold between
PFM and PWM operation to coincide with the boundary
EN Pin Control
between continuous and discontinuous inductor-current
operation (also known as the critical conduction point).
When V EN is above the EN high threshold (2.65V, typical),
the converter is enabled in automatic PFM/PWM opera-
The on-time of PFM is given by:
TON-PFM =
1
FSW
×
tion mode. When EN pin is floating, APW8802 internal
circuit will pull VEN up to 1.95V (typical). Furthermore,
VOUT
VIN
APW8802 is in Forced-PWM operation mode. When VEN
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jan., 2013
14
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APW8802
Function Description (Cont.)
EN Pin Control (Cont.)
temperature, or shutdown, the chip enables the soft-stop
function. The soft-stop function discharges the output
is below the EN low threshold (1V, typical), the chip is in
the shutdown and only low leakage current is taken from
voltages to the PGND through an internal 20Ω switch.
VCC.
Power OK Indicator
Digital Soft-Start
The APW8802 integrates digital soft-start circuits to ramp
The APW8802 features an open-drain POK pin to indicate output regulation status. In normal operation, when
up the output voltage of the converter to the programmed
regulation setpoint at a predictable slew rate. The slew
the output voltage rises 90% of its target value, the POK
goes high after 63us internal delay. When the output volt-
rate of output voltage is internally controlled to limit the
inrush current through the output capacitors during soft-
age outruns 70% or 125% of the target voltage, POK signal will be pulled low immediately.
start process. The figure 1 shows soft-start sequence.
When the EN pin is pulled above the rising EN threshold
Since the FB pin is used for both feedback and monitoring purposes, the output voltage deviation can be coupled
voltage, the device initiates a soft-start process to ramp
up the output voltage. The soft-start interval is 1.2ms
directly to the FB pin by the capacitor in parallel with the
voltage divider as shown in the typical applications. In
(typical) and independent of the UGATE switching
frequency.
order to prevent false POK from dropping, capacitors need
to parallel at the output to confine the voltage deviation
with severe load step transient.
Under-Voltage Protection (UVP)
2ms
In the operational process, if a short-circuit occurs, the
VCC and VPVCC
output voltage will drop quickly. When load current is big-
1.2ms
ger than current-limit threshold value, the output voltage
will fall out of the required regulation range. The under-
VOUT
voltage protection circuit continually monitors the FB voltage after soft-start is completed. If a load step is strong
EN
enough to pull the output voltage lower than the undervoltage threshold, the under-voltage threshold is 70% of
the nominal output voltage, the internal UVP delay counter
starts to count. After 16µs debounce time, the device turns
off both high-side and low-side MOSEFET with latched
and starts a soft-stop process to shut down the output
VPGOOD
gradually. Toggling enable pin to low or recycling PVCC
or VCC, will clear the latch and bring the chip back to
Figure 1. Soft-Start Sequence
During soft-start stage before the PGOOD pin is ready,
operation.
the under-voltage protection is prohibited. The over-voltage and current-limit protection functions are enabled. If
Over-Voltage Protection (OVP)
the output capacitor has residue voltage before start-up,
both low-side and high-side MOSFETs are in off-state
The over-voltage function monitors the output voltage by
FB pin. When the FB voltage increases over 125% of the
until the internal digital soft-start voltage equals to the VFB
voltage. This will ensure that the output voltage starts
reference voltage due to the high-side MOSFET failure or
for other reasons, the over-voltage protection compara-
from its existing voltage level.
In the event of under-voltage, over-voltage, over-
tor designed with a 1.5µs noise filter will force the lowside MOSFET gate driver fully turn on and latch high. This
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jan., 2013
15
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APW8802
Function Description (Cont.)
Over-Voltage Protection (OVP) (Cont.)
resistor for adjusting current-limit threshold. The voltage
at OCSET pin is equal to 10µA x ROCSET. The relationship
action actively pulls down the output voltage. In the
meantime, the output voltage is also pulled low by inter-
between the sampled voltage VOCSET and the current-limit
threshold ILIMIT is given by:
nal discharge transistor.
This OVP scheme only clamps the voltage overshoot and
10µA x ROCSET = ILIMIT x RDS(ON)
Where R OCSET is the resistor of current-limit setting
does not invert the output voltage when otherwise activated with a continuously high output from low-side
threshold. RDS(ON) is the low side MOSFETs conducive
resistance. ILIMIT is the setting current-limit threshold. ILIMIT
MOSFET driver. It’s a common problem for OVP schemes
with a latch. Once an over-voltage fault condition is set, it
can be expressed as IOUT minus half of peak-to-peak inductor current.
can only be reset by toggling EN, PVCC or VCC poweronreset signal.
The PCB layout guidelines should ensure that noise and
DC errors do not corrupt the current-sense signals at
Current-Limit
PHASE. Place the hottest power MOSEFTs as close to
the IC as possible for best thermal coupling. When com-
The current-limit circuit employs a “valley” current-sensing algorithm (See Figure 2). The APW8802 uses the
low-side MOSFET’s RDS(ON) of the synchronous rectifier
bined with the under-voltage protection circuit, this current-limit method is effective in almost every circumstance.
as a current-sensing element. If the magnitude of the
current-sense signal at PHASE pin is above the current-
Over-Temperature Protection (OTP)
When the junction temperature increases above the ris-
limit threshold, the PWM is not allowed to initiate a new
cycle. The actual peak current is greater than the currentlimit threshold by an amount equals to the inductor ripple
ing threshold temperature TOTR, the IC will enter the overtemperature protection state that suspends the PWM,
current. Therefore, the exact current-limit characteristic
and maximum load capability are the functions of the
which forces the UGATE and LGATE gate drivers output
low. The thermal sensor allows the converters to start a
sense resistance, inductor value, and input voltage.
start-up process and regulate the output voltage again
after the junction temperature cools by 25oC. The OTP is
designed with a 25oC hysteresis to lower the average TJ
during continuous thermal overload conditions, which in-
INDUCTOR CURRENT, IL
IPEAK
IOUT
creases lifetime of the APW8802.
∆I
Programming the On-Time Control and PWM SwitchILIMIT
ing Frequency
The APW8802 does not use a clock signal to produce
0
PWM. The device uses the constant-on-time control architecture to produce pseudo-fixed frequency with input
Time
Figure 2. Current-Limit Algorithm
voltage feed-forward. The on-time pulse width is proportional to output voltage VOUT and inverses proportional to
The PWM controller uses the low-side MOSFETs on-re-
input voltage VIN. In PWM, the on-time calculation is written as below :
sistance R DS(ON) to monitor the current for protection
against shortened outputs. The MOSFET’s RDS(ON) is var-
( )
 2 VOUT + 0.1V 
 + 50ns
TON = 19 × 10 −12 × R TON  3


VIN


ied by temperature and gate to source voltage, the user
should determine the maximum RDS(ON) in manufacture’s
Where:
datasheet.
The OCSET pin can source 10µA through an external
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jan., 2013
RTON is the resistor connected from TON pin to PHASE
16
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APW8802
Function Description (Cont.)
Programming the On-Time Control and PWM Switching Frequency (Cont.)
pin. Furthermore, the approximate PWM switching frequency is written as :
TON =
D
⇒ FSW =
FSW
VOUT
VIN
TON
Where:
FSW is the PWM switching frequency.
Monitoring VPHASE voltage as input voltage to calculate ontime when the high-side MOSFET is turned on. And then,
use the relationship between ontime and duty cycle to
obtain the switching frequency. The curve below is the
relationship between RTON and the switching frequency
FSW.
Switching Frequency vs. TON Resistance
Switching Frequency, FSW (kHz)
800
VIN=19V, Forced-PWM Mode
700
600
500
400
300
200
100
0
100
VOUT=1.05V
VOUT=2.5V
200
300
400
500
600
TON Resistance, RTON (kΩ)
700
Figure 3.
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jan., 2013
17
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APW8802
Application Information
Output Voltage Setting
saturation. In some types of inductors, especially core
The output voltage is adjustable from 0.75V to 5.5V with a
resistor-divider connected with FB, GND, and converter’s
that is made of ferrite, the ripple current will increase
abruptly when it saturates. This results in a larger output
output. Using 1% or better resistors for the resistor-divider is recommended. The output voltage is determined
ripple voltage. Besides, the inductor needs to have low
DCR to reduce the loss of efficiency.
by:
Output Capacitor Selection
VOUT
R TOP 

= 0.75 ×  1 +

R
GND 

Output voltage ripple and the transient voltage devia-
Where 0.75 is the reference voltage, RTOP is the resistor
tion are factors which have to be taken into consideration when selecting an output capacitor. Higher capaci-
connected from converter’s output to FB, and RGND is the
resistor connected from FB to GND. Suggested RGND is in
tor value and lower ESR reduce the output ripple and
the load transient drop. Therefore, selecting high per-
the range from 1k to 20kΩ. To prevent stray pickup, locate
resistors RTOP and RGND close to APW8802.
formance low ESR capacitors is recommended for
switching regulator applications. In addition to high
Output Inductor Selection
frequency noise related to MOSFET turn-on and turnoff, the output voltage ripple includes the capacitance
The duty cycle (D) of a buck converter is the function of the
input voltage and output voltage. Once an output voltage
voltage drop ∆VCOUT and ESR voltage drop ∆VESR caused
by the AC peak-to-peak inductor’s current. These two
is fixed, it can be written as:
voltages can be represented by:
V
D = OUT
VIN
The inductor value (L) determines the inductor ripple
∆VESR
current, IRIPPLE, and affects the load transient reponse.
Higher inductor value reduces the inductor’s ripple cur-
These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
rent and induces lower output ripple voltage. The ripple
current and ripple voltage can be approximated by:
IRIPPLE =
IRIPPLE
8COUTFSW
= IRIPPLE × RESR
∆VCOUT =
capacitors have to be paralleled to achieve the desired
ESR value. If the output of the converter has to support
VIN - VOUT VOUT
×
VIN
FSW × L
another load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR
Where FSW is the switching frequency of the regulator.
Although the inductor value and frequency are increased
and the ripple current and voltage are reduced, a tradeoff
and suppress the voltage ripple to a tolerable level. A
small decoupling capacitor (1µF) in parallel for bypass-
exists between the inductor’s ripple current and the regulator load transient response time.
ing the noise is also recommended, and the voltage rating of the output capacitors are also must be considered.
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple current.
To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing
Increasing the switching frequency (F SW ) also reduces
the ripple current and voltage, but it will increase the
the voltage excursion during load step change. Another
aspect of the capacitor selection is that the total AC cur-
switching loss of the MOSFETs and the power dissipation of the converter. The maximum ripple current occurs
rent going through the capacitors has to be less than the
rated RMS current specified on the capacitors in order to
at the maximum input voltage. A good starting point is to
choose the ripple current to be approximately 30% of the
prevent the capacitor from over-heating.
Input Capacitor Selection
maximum output current. Once the inductance value has
been chosen, selecting an inductor which is capable of
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, selecting the capacitor voltage rating to be at least 1.3 times
carrying the required peak current without going into
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jan., 2013
18
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APW8802
Application Information (Cont.)
Input Capacitor Selection (Cont.)
VDS
where IOUT is the load current. During power-up, the input
capacitors have to handle great amount of surge current.
Voltage across
For low-duty notebook appliactions, ceramic capacitor is
recommended. The capacitors must be connected between the drain of high-side MOSFET and the source of
low-side MOSFET with very low-impeadance PCB layout.
Thermal Consideration
Because the APW8802 build-in high-side and low-side
MOSFET, the heat dissipated may exceed the maximum
drain and source of MOSFET
higher than the maximum input voltage. The maximum
RMS current rating requirement is approximately IOUT/2,
junction temperature of the part in applications. If the junction temperature reaches approximately 150 oC, both
tsw
Time
Figure 4. Switching waveform across MOSFET
power switches will be turned off and the LX node will
become high impedance.
Layout Consideration
To avoid the APW8802 from exceeding the maximum junction temperature, the user will need to do some thermal
In any high switching frequency converter, a correct layout
is important to ensure proper operation of the regulator.
analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maxi-
With power devices switching at higher frequency, the
resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit
mum junction temperature of the part. The main power
dissipated by the part is approximated:
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off condition, the
PUPPER=IOUT2 (1+TC)(RDS(ON))D+(0.5)(IOUT)(VIN)(tSW )FSW
PLOWER=IOUT2 (1+TC)(RDS(ON))(1-D)
MOSFET is carrying the full load current. During turn-off,
current stops flowing in the MOSFET and is freewheeling
IOUT is the load current
TC is the temperature dependency of RDS(ON)
by the low side MOSFET and parasitic diode. Any parasitic
inductance of the circuit generates a large voltage spike
FSW is the switching frequency
tSW is the switching interval
during the switching interval. In general, using short and
wide printed circuit traces should minimize interconnect-
D is the duty cycle
Note that both internal MOSFETs have conduction losses
ing impedances and the magnitude of voltage spike.
Besides, signal and power grounds are to be kept sepa-
while the upper MOSFET include an additional transition
loss. The switching internal, tSW , is the function of the
rate and finally combined using ground plane construction or single point grounding. The best tie-point between
reverse transfer capacitance CRSS. Figure 4 illustrates the
switching waveform internal of the MOSFET. The (1+TC)
the signal ground and the power ground is at the negative side of the output capacitor on each channel, where
term factors in the temperature dependency of the RDS(ON)
and can be extracted from the "RDS(ON) vs. Temperature"
there is less noise. Noisy traces beneath the IC are not
recommended. Below is a checklist for your layout:
curve of the power MOSFET. In APW8802 case, the maximum RDS(ON) is about 15mΩ from specification table.
• Keep the switching nodes (BOOT and LX) away from
sensitive small signal nodes since these nodes are fast
moving signals.
Therefore, keep traces to these nodes as short as pos-
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jan., 2013
19
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APW8802
Application Information (Cont.)
Power
Ground
Grou
nd
23 EN
24 TON
25 VOUT
26 OCSET
28 VCC
sible and there should be no other weak signal traces in
parallel with theses traces on any layer.
• The large layout plane between the drain of the MOSFETs
(VIN and LX nodes) can get better heat sinking.
27 PVCC
Layout Consideration (Cont.)
CIN VIN
FB 1
• The current sense resistor should be close to OCSET
22 PGND
21 BOOT
POK 2
GND 3
pin to avoid parasitic capacitor effect and noise coupling.
• Decoupling capacitors, the resistor-divider, and boot
COUT
VIN
PGND 4
17 LX
NC 6
• The output bulk capacitors should be close to the loads.
LX
NC 7
16 LX
15 LX
mize the high impedance trace. In addition, FB pin traces
can’t be close to the switching signal traces (BOOT and
LX 13
LX 14
LX 12
LX 11
LX 9
LOUT
grounds of the output capacitors.
• Locate the resistor-divider close to the FB pin to mini-
LX 10
LX 8
The input capacitor’s ground should be close to the
19 VIN
18 VIN
PGND 5
VOUT
capacitor should be close to their pins.
20 VIN
PGND
For dissipating heat
LX).
Figure6. Recommended Layout Diagram
5mm
20
EN
BOOT
APW8802
PGND
26 OCSET
FB
ROCSET
AGND
3
+
COUT L
o V
OUT
a
d
-
21 CBOOT
4, 5, 22
4
RTOP
RGND CTOP
0.265mm
Feedback
Divider
Figure5. Current Path Diagram
PGND
VIN
6mm
LX
23
0.34mm
1.85mm
1.38mm
CIN L
OUT
8~17
1.85mm
VIN
0.65mm
18 19
0.34mm
1.55mm
2.76mm
+
VIN
-
LX
*Just
Recommend
0.265mm
3.57mm
0.45 0.45
mm mm*
Figure7. Recommended Minimum Footprint
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jan., 2013
20
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APW8802
Package Information
TQFN5x6-28
A
b
E
D
Pin 1
D1
H
A1
D2
A3
NX
E1
aaa
c
L K
E3
H
E2
Pin 1
Corner
D3
e
TQFN5x6-28
S
Y
M
B
O
L
A
MIN.
MAX.
MIN.
0.70
0.80
0.028
0.032
A1
0.00
0.05
0.000
0.002
INCHES
MILLIMETERS
A3
0.20 REF
MAX.
0.008 REF
b
0.25
0.35
0.010
0.014
D
5.90
6.10
0.232
0.240
D1
2.71
2.81
0.107
0.111
0.059
0.063
D2
1.50
1.60
D3
E
1.80
1.90
0.071
0.075
4.90
5.10
0.193
0.201
E1
1.80
1.90
0.071
0.075
E2
3.52
3.62
0.139
0.143
1.43
0.052
0.056
0.45
0.014
E3
1.33
e
0.65 BSC
L
0.35
K
0.20
H
aaa
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jan., 2013
0.026 BSC
0.018
0.008
0.34 REF
0.08
0.013 REF
0.003
21
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APW8802
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TQFN5x6-28
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.10
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.10
1.5+0.10
-0.00
1.5 MIN.
0.3±0.05
6.5±0.10
5.3±0.10
1.4±0.10
4.0±0.10
8.0±0.10
(mm)
Devices Per Unit
Package Type
TQFN5x6-28
Unit
Tape & Reel
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jan., 2013
Quantity
2500
22
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APW8802
Taping Direction Information
TQFN5x6-28
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jan., 2013
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APW8802
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3 °C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jan., 2013
24
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
www.anpec.com.tw
APW8802
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Jan., 2013
25
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