TI1 ISO7242MDWG4 High-speed, quad-channel digital isolator Datasheet

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ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M, ISO7242C, ISO7242M
SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015
ISO724x High-Speed, Quad-Channel Digital Isolators
1 Features
3 Description
•
The ISO7240, ISO7241 and ISO7242 are quadchannel digital isolators with multiple channel
configurations and output enable functions. These
devices have logic input and output buffers separated
by TI’s silicon dioxide (SiO2) isolation barrier. Used in
conjunction with isolated power supplies, these
devices block high voltage, isolate grounds, and
prevent noise currents from entering the local ground
and interfering with or damaging sensitive circuitry.
1
•
•
•
•
•
•
•
25 and 150-Mbps Signaling Rate Options
– Low Channel-to-Channel Output Skew;
1 ns Max
– Low Pulse-Width Distortion (PWD);
2 ns Max
– Low Jitter Content; 1 ns Typ at 150 Mbps
Selectable Default Output (ISO7240CF)
> 25-Year Life at Rated Working Voltage
(See Application Note SLLA197 and Figure 16)
4 kV ESD Protection
Operates With 3.3-V or 5-V Supplies
High Electromagnetic Immunity
(See Application Report SLLA181)
–40°C to 125°C Operating Temperature Range
Safety and Regulatory Approvals:
– VDE 4000 VPK Basic Insulation per DIN V VDE
V 0884-10 (VDE V 0884-10):2006-12
– 2.5 kVRMS Isulation for 1 minute per UL 1577
– CSA Component Acceptance Notice #5A and
IEC 60950-1 End Equipment Standard
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SOIC (16)
10.30 mm x 7.50 mm
ISO7240CF
ISO7240C
ISO7240M
ISO7241C
ISO7241M
ISO7242C
ISO7242M
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
•
The ISO7240 has all four channels in the same
direction while the ISO7241 has three channels in the
same direction and one channel in opposition. The
ISO7242 has two channels in each direction.
Industrial Fieldbus
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
Simplified Schematic
VCCO
VCCI
Isolation
Capacitor
OUTx
INx
DISABLE
ENx
(ISO7240CF-only)
or
GNDI
GNDO
(1)
VCCI and GNDI are supply and ground connections respectively for the input channels.
(2)
VCCO and GNDO are supply and ground connections respectively for the output channels.
CTRL (ISO7240CF-only)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M, ISO7242C, ISO7242M
SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configurations and Functions .......................
Specifications.........................................................
1
1
1
2
6
7
8
7.1
7.2
7.3
7.4
7.5
Absolute Maximum Ratings ..................................... 8
ESD Ratings.............................................................. 8
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 9
Electrical Characteristics: VCC1 and VCC2 at 5-V
Operation .................................................................. 9
7.6 Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V
Operation ................................................................. 10
7.7 Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V
Operation ................................................................. 11
7.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V
Operation ................................................................. 12
7.9 Switching Characteristics: VCC1 and VCC2 at 5-V
Operation ................................................................. 13
7.10 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3V Operation ............................................................. 14
7.11 Switching Characteristics: VCC1 at 3.3-V and VCC2
at 5-V Operation....................................................... 15
7.12 Switching Characteristics: VCC1 and VCC2 at 3.3-V
Operation ................................................................ 16
7.13 Typical Characteristics .......................................... 17
8
9
Parameter Measurement Information ................ 19
Detailed Description ............................................ 22
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
22
22
23
26
10 Application and Implementation........................ 27
10.1 Application Information.......................................... 27
10.2 Typical Application ................................................ 27
11 Power Supply Recommendations ..................... 33
12 Layout................................................................... 33
12.1 Layout Guidelines ................................................. 33
12.2 Layout Example .................................................... 33
13 Device and Documentation Support ................. 34
13.1
13.2
13.3
13.4
13.5
13.6
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
36
36
36
36
36
14 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision Q (January 2015) to Revision R
Page
•
Changed Features From: "Basic Isolation per DIN EN 60747-5-5 (VDE 0884-5) & DIN EN 61010-1" To:"Basic
Insulation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12" ......................................................................................... 1
•
Changed VCC1 To VCCI, VCC2 To VCCO, GND1 To GNDI, and GND2 To GNDO, and added Notes 1 and 2 to the
Simplified Schematic .............................................................................................................................................................. 1
•
Changed VOH MIN values From: VCC - 0.8 To: VCCO - 0.8 and VCC - 0.1 To: VCCO - 0.1 in the Electrical
Characteristics: VCC1 and VCC2 at 5-V (2) Operation ............................................................................................................... 9
•
Changed VOH Test Condition ISO7240 To: 3.3-V side and the MIN value From: VCC - 0.4 To VCCO -0.4 in the
Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V (3) Operation ....................................................................................... 10
•
Changed VOH Test Condition ISO724x (5-V side) To: 5-V side and the MIN value From: VCC - 0.8 To: VCCO - 0.8 in
the Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V (3) Operation ................................................................................. 10
•
Changed VOH, Test Condition IOH = -20 µA MIN value From: VCC - 0.1 To VCCO - 0.1 in the Electrical Characteristics:
VCC1 at 5-V, VCC2 at 3.3-V (3) Operation................................................................................................................................. 10
•
Changed VOH Test Condition ISO7240 To: 3.3-V side and the MIN value From: VCC - 0.4 To VCCO -0.4 in the
Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V (4) Operation ....................................................................................... 11
•
Changed VOH Test Condition ISO724x (5-V side) To: 5-V side and the MIN value From: VCC - 0.8 To: VCCO - 0.8 in
the Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V (4) Operation ................................................................................. 11
•
Changed VOH, Test Condition IOH = -20 µA MIN value From: VCC - 0.1 To VCCO - 0.1 in the Electrical Characteristics:
VCC1 at 3.3-V, VCC2 at 5-V (4) Operation................................................................................................................................. 11
•
Changed VOH MIN values From: VCC - 0.4 To: VCCO - 0.4 and VCC - 0.1 To: VCCO - 0.1 in the Electrical
Characteristics: VCC1 and VCC2 at 3.3 V (5) Operation ........................................................................................................... 12
•
Changed VCC1 To: VCCI and VCC2 To: VCCO in Figure 13 ...................................................................................................... 21
•
Changed section title From: DIN EN 60747-5-5 Insulation Characteristics To: DIN V VDE V 0884-10 (VDE V 0884-
2
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SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015
Revision History (continued)
10):2006-1 Insulation Characteristics (1) ............................................................................................................................... 23
•
Changed RS Test Conditions From: VIO = 500 V at TS To: VIO = 500 V at TS = 150°C in the DIN V VDE V 0884-10
(VDE V 0884-10):2006-1 Insulation Characteristics (6) table................................................................................................. 23
•
Changed the CTI Test Conditions From: IEC 60112/VDE 0303 Part 1 To: DIN EN 60112 (VDE 0303-11); IEC 60112
in the Package Characteristics table ................................................................................................................................... 23
•
Deleted CI - Input capacitance to ground from the Package Characteristics table ............................................................. 23
•
Changed title From: IEC Safety Limiting Values To: Safety Limiting Values ....................................................................... 24
•
Changed Figure 17 title From: Thermal Derating Curve per DIN EN 60747-5-5 To: Thermal Derating Curve per VDE .... 24
•
Changed "DIN EN 60747-5-5 & DIN EN 61010-1" To: DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN
61010-1 (VDE 0411-1): 2011-07 in the Regulatory Information table.................................................................................. 25
(1)
Climatic Classification 40/125/21
Changes from Revision P (August 2014) to Revision Q
Page
•
Changed the VI MAX value in the Absolute Maximum Ratings table From: 6 V To: VCC + 0.5 V .......................................... 8
•
Added Note 3 to the Absolute Maximum Ratings table.......................................................................................................... 8
•
Changed the Handling Rating table to the ESD Ratings table. ............................................................................................. 8
•
Moved TSTG - Storage From the ESD Ratings table to the Absolute Maximum Ratings table .............................................. 8
•
Added one row to Table 2. Values: X, PD, X, X, Undetermined ......................................................................................... 26
•
Added one row to Table 3. Values: X, PD, X, X, X, Undetermined .................................................................................... 26
•
Changed Figure 18 labels From: "ISO7240CF Input" To: "ISO7240CF Input, Disable" and From: "Enable" To:
"Enable, Control" ................................................................................................................................................................. 26
Changes from Revision O (November 2012) to Revision P
Page
•
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
•
Changed ISO7241C minimum supply from 2.8 V to 3.15 V................................................................................................... 8
Changes from Revision N (January 2012) to Revision O
•
Page
Added the Safety Limiting Values section ............................................................................................................................ 24
Changes from Revision M (January 2011) to Revision N
Page
•
Changed Feature From: Operates 3.3-V or 5-V Supplies To: Operates With 2.8-V (ISO7241C), 3.3-V or 5-V Supplies ..... 1
•
Added device options to VCC in the RECOMMENDED OPERATING CONDITIONS table ................................................... 8
•
Changed Table Note (1) ......................................................................................................................................................... 8
•
Changed ICC1 and ICC2 test conditions in the VCC1 and VCC2 at 5-V Electrical Characteristics: VCC1 and VCC2 at 5-V (2)
Operation table ....................................................................................................................................................................... 9
•
Changed Table Note (1) ......................................................................................................................................................... 9
•
Changed ICC1 and ICC2 test conditions in the VCC1 at 5-V, VCC2 at 3.3-V Electrical Characteristics: VCC1 at 5-V, VCC2 at
3.3-V (3) Operation table ........................................................................................................................................................ 10
•
Changed Table Note (1) ....................................................................................................................................................... 10
•
Changed ICC1 and ICC2 test conditions in the VCC1 at 3.3-V, VCC2 at 5-V Electrical Characteristics: VCC1 at 3.3-V, VCC2
at 5-V (4) Operation table ....................................................................................................................................................... 11
•
Changed Table Note (1) ....................................................................................................................................................... 11
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3
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M, ISO7242C, ISO7242M
SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015
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•
Changed ICC1 and ICC2 test conditions in the VCC1 and VCC2 at 3.3 V table .......................................................................... 12
•
Added ELECTRICAL and Switching CHARACTERISTICS tables forVCC1 and VCC2 at 2.8V (ISO722xC-only)................... 12
•
Changed Table Note (1) ....................................................................................................................................................... 12
•
Changed Figure 6 From VCC1 Failsafe Threshold To: VCC Undervoltage Threshold............................................................ 17
•
Changed the CTI MIN value From: ≥175 V To:≥400 V ........................................................................................................ 23
•
Changed the Regulatory Information table........................................................................................................................... 25
Changes from Revision L (January 2010) to Revision M
Page
•
Changed Figure 9, Figure 11, and Figure 12 ....................................................................................................................... 19
•
Changed the CSA File Number From: 1698195 To: 220991 ............................................................................................... 25
Changes from Revision K (Decemberl 2009) to Revision L
Page
•
Added the IEC 60747-5-2 INSULATION CHARACTERISTIC table..................................................................................... 23
•
Added the IEC 60664-1 RATINGS TABLE .......................................................................................................................... 23
•
Added CTI - Tracking resistance (comparative tracking index to the Package Characteristics table.................................. 23
Changes from Revision J (April 2009) to Revision K
Page
•
Changed the Input circuit in the DEVICE I/O SCHEMATICS illustration ............................................................................... 1
•
Added Note 1 to LI01), and changed the MIN value From: 8.34 To 8 mm in the Package Characteristics table .............. 23
•
Added Note 1 to LI02), and changed the MIN value From: 8.1 To 8 mm in the Package Characteristics table ................ 23
Changes from Revision I (December 2008) to Revision J
Page
•
Changed ICC1 for Quiescent and 1Mbps From: 10mA To: 11mA ........................................................................................... 9
•
Changed ICC1 for Quiescent and 1Mbps From: 10mA To: 11mA ......................................................................................... 10
Changes from Revision G (July 2008) to Revision H
Page
•
Added Device number ISO7240CF. ....................................................................................................................................... 1
•
Added Features Bullet: Selectable Failsafe Output (ISO7240CF) ......................................................................................... 1
•
Changed description paragraph 4 text. .................................................................................................................................. 6
•
Changed VI in the Absolute Maximum Ratings table From: Voltage at IN, OUT, EN To: Voltage at IN, OUT, EN,
DISABLE, CTRL ..................................................................................................................................................................... 8
•
Added twake, Wake time from input disable ........................................................................................................................... 13
•
Added twake, Wake time from input disable ........................................................................................................................... 14
•
Added twake, Wake time from input disable ........................................................................................................................... 15
•
Added twake, Wake time from input disable ........................................................................................................................... 16
Changes from Revision F (May 2008) to Revision G
•
4
Page
Changed the Package Characteristics table, line , L(IO1) MIN value from7.7mm to 8.34mm................................................ 23
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ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M, ISO7242C, ISO7242M
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SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015
Changes from Revision E (May 2008) to Revision F
Page
•
Deleted ISO724xA devices. See SLLS905 for the ISO7240A, ISO7241A, and ISO7242A................................................... 1
•
Changed Title From: QUAD DIGITAL ISOLATORS To: HIGH SPEED QUAD DIGITAL ISOLATORS................................. 1
•
Changed Feature Low Jitter Content - From: 1, 25, and 150-Mbps Signaling Rate Options To: 25, and 150-Mbps
Signaling Rate Options ........................................................................................................................................................... 1
•
Added tsk(pp) footnote............................................................................................................................................................. 13
•
Added tsk(o) footnote. ............................................................................................................................................................. 13
•
Added tsk(pp) footnote............................................................................................................................................................. 16
•
Added tsk(o) footnote. ............................................................................................................................................................. 16
Changes from Revision D (April 2008) to Revision E
Page
•
Added Table Note (1): For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. ............................................... 8
•
Added Table Note (1): For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V .............................................. 10
•
Added Table Note (1): For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V .............................................. 11
•
Added Table Note (1): For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V .............................................. 12
Changes from Revision C (April 2008) to Revision D
Page
•
Added tsk(pp) Part-to-part skew .............................................................................................................................................. 13
•
Added tsk(pp) Part-to-part skew .............................................................................................................................................. 14
•
Added tsk(pp) Part-to-part skew .............................................................................................................................................. 15
•
Added tsk(pp) Part-to-part skew .............................................................................................................................................. 16
•
Changed Typical ISO724x Application Circuit Figure 19 .................................................................................................... 27
Changes from Revision B (August 2008) to Revision C
Page
•
Deleted Min = 4.5 V and max = 5.5 V for Supply Voltage of the ROC Table. ....................................................................... 8
•
Changed VCC Supply Voltage in the ROC Table From: 3.6 To: 5.5 ....................................................................................... 8
Changes from Revision A (December 2007) to Revision B
•
Page
Changed VCC Supply Voltage in the ROC Table From: 3.45 To: 3.6 ..................................................................................... 8
Changes from Original (September 2007) to Revision A
Page
•
Changed VCC Supply Voltage in the ROC Table From: 3.6 To: 3.45 ..................................................................................... 8
•
Changed VCC Supply Voltage in the ROC Table From: 3 To: 3.15 ........................................................................................ 8
•
Changed TBDs to actual values. ............................................................................................................................................ 9
•
Changed CI - typ value From: 1 To: 2 in the Electrical Characteristics: VCC1 and VCC2 at 5-V (2) Operation ......................... 9
•
Changed CI - typ value From: 1 To: 2 in the Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V (3) Operation................. 10
•
Changed CI - typ value From: 1 To: 2 in the Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V (4) Operation................. 11
•
Changed typ value From: 1 To: 2 in the Electrical Characteristics: VCC1 and VCC2 at 3.3 V (5) Operation ............................ 12
•
Changed Propagation delay max From: 22 To: 23 .............................................................................................................. 13
•
Changed Propagation delay max From: 46 To: 50 .............................................................................................................. 14
•
Changed Propagation delay max From: 28 To: 29 .............................................................................................................. 14
•
Changed ISO724xA/C max value From: 2.5 To: 3............................................................................................................... 14
•
Changed Propagation delay max From: 26 To: 30 .............................................................................................................. 15
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5
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M, ISO7242C, ISO7242M
SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015
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•
Changed Propagation delay max From: 32 To: 34 .............................................................................................................. 16
•
Changed ISO724xA/C max value From: 3 To: 3.5............................................................................................................... 16
•
Changed Figure 1, Figure 2, and Figure 4. Added Figure 3. ............................................................................................... 17
•
Changed CIO - typ value From: 1 To: 2 ................................................................................................................................ 23
•
Changed the Regulatory Information.................................................................................................................................... 25
6
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ISO7241C, ISO7241M, ISO7242C, ISO7242M
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SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015
5 Description (Continued)
The C option devices have TTL input thresholds and a noise-filter at the input that prevents transient pulses from
being passed to the output of the device. The M option devices have CMOS VCC/2 input thresholds and do not
have the input noise-filter or the additional propagation delay.
The ISO7240CF has an input disable function on pin 7, and a selectable high or low failsafe-output function with
the CTRL pin (pin 10). The failsafe-output is a logic high when a logic-high is placed on the CTRL pin or it is left
unconnected. If a logic-low signal is applied to the CTRL pin, the failsafe-output becomes a logic-low output
state. The ISO7240CF input disable function prevents data from being passed across the isolation barrier to the
output. When the inputs are disabled or VCC1 is powered down, the outputs are set by the CTRL pin.
These devices may be powered from 3.3-V or 5-V supplies on either side in any combination. Note that the
signal input pins are 5-V tolerant regardless of the voltage supply level being used.
These devices are characterized for operation over the ambient temperature range of –40°C to 125°C.
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7
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M, ISO7242C, ISO7242M
SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015
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6 Pin Configurations and Functions
VCC1
GND1
INA
INB
INC
IND
DISABLE
GND1
ISO7240CF
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
ISO7240
VCC2 VCC1
GND2 GND1
OUTA
INA
INB
OUTB
INC
OUTC
OUTD
IND
CTRL
NC
GND2 GND1
1
2
3
4
5
6
7
8
ISO7241
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
OUTC
OUTD
EN
GND2
VCC1
GND1
INA
INB
INC
OUTD
EN1
GND1
1
2
3
4
5
6
7
8
ISO7242
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
OUTC
IND
EN2
GND2
VCC1
GND1
INA
INB
OUTC
OUTD
EN1
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
INC
IND
EN2
GND2
Pin Functions
PIN
NAME
I/O
DESCRIPTION3
ISO7240CF
ISO7240
ISO7241
ISO7242
INA
3
3
3
3
I
Input, channel A
INB
4
4
4
4
I
Input, channel B
INC
5
5
5
12
I
Input, channel C
IND
6
6
11
11
I
Input, channel D
OUTA
14
14
14
14
O
Output, channel A
OUTB
13
13
13
13
O
Output, channel B
OUTC
12
12
12
5
O
Output, channel C
OUTD
11
11
6
6
O
Output, channel D
EN1
–
–
7
7
I
Output enable 1. Output pins on side-1 are enabled when EN1 is
high or open and disabled when EN1 is low.
EN2
–
–
10
10
I
Output enable 2. Output pins on side-2 are enabled when EN2 is
high or open and disabled when EN2 is low.
EN
–
10
–
–
I
Output enable. All output pins are enabled when EN is high or
open and disabled when EN is low.
DISABLE
7
–
–
–
I
Input disable. All input pins are disabled when DISABLE is high
and enabled when DISABLE is low or open.
CTRL
10
–
–
–
I
Failsafe output control. Output state is determined by CTRL pin
when DISABLE is high or VCC1 is powered down. Output is high
when CTRL is high or open and low when CTRL is low.
VCC1
1
1
1
1
–
Power supply, VCC1
VCC2
16
16
16
16
–
Power supply, VCC2
GND1
2,8
2,8
2,8
2, 8
–
Ground connection for VCC1
GND2
9,15
9,15
9,15
9, 15
–
Ground connection for VCC2
–
7
–
–
–
No Connect pins are floating with no internal connection
NC
8
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ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M, ISO7242C, ISO7242M
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SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
VCC
Supply voltage (2), VCC1, VCC2
–0.5
6
V
VI
Voltage at IN, OUT, EN, DISABLE, CTRL
–0.5
VCC + 0.5 (3)
V
IO
Output current
–15
15
mA
TJ
Maximum junction temperature
170
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal and are peak voltage values.
Maximum voltage must not exceed 6 V.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1
Machine Model, per ANSI/ESDS5.2-1996
(1)
(2)
UNIT
V
±200
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
VCC
Supply voltage (1), VCC1, VCC2
IOH
High-level output current
IOL
Low-level output current
tui
Input pulse width
5.5
4
40
ISO724xM
6.67
5
ISO724xC
0
30
(2)
25
ISO724xM
0
200 (2)
150
VIH
High-level input voltage (IN)
VIL
Low-level input voltage (IN)
VIH
High-level input voltage (IN, DISABLE, CTRL, EN)
VIL
Low-level input voltage (IN, DISABLE, CTRL, EN)
TJ
Junction temperature
H
External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9 certification
ISO724xM
ISO724xC
UNIT
V
mA
ISO724xC
Signaling rate
(2)
MAX
-4
1/tui
(1)
TYP
3.15
mA
ns
Mbps
0.7 VCC
VCC
V
0
0.3 VCC
V
2
5.5
V
0
0.8
V
150
°C
1000
A/m
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Typical value at room temperature and well-regulated power supply.
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7.4 Thermal Information
ISO724x
THERMAL METRIC (1)
DW
UNIT
16 PINS
RθJA
Junction-to-ambient thermal
resistance
RθJC(top)
Junction-to-case (top) thermal resistance
39.5
RθJB
Junction-to-board thermal resistance
41.9
ψJT
Junction-to-top characterization parameter
13.5
ψJB
Junction-to-board characterization parameter
41.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
PD
Device power dissipation
(1)
Low-K board
168
High-K board
77.3
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50% duty cycle square wave
°C/W
220
mW
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics: VCC1 and VCC2 at 5-V (1) Operation
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1
3
7
10.5
All channels, no load,
EN1 at 3 V, EN2 at 3 V
6.5
11
12
18
All channels, no load,
EN1 at 3 V, EN2 at 3 V
10
16
15
24
All channels, no load,
EN at 3 V
15
22
17
25
All channels, no load,
EN1 at 3 V, EN2 at 3 V
13
20
18
28
All channels, no load,
EN1 at 3 V, EN2 at 3 V
10
16
15
24
UNIT
SUPPLY CURRENT
ISO7240C/M
ICC1
ISO7241C/M
ISO7242C/M
ISO7240C/M
ICC2
ISO7241C/M
ISO7242C/M
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
All channels, no load,
EN at 3 V
mA
mA
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, Single channel
VCCO – 0.8
IOH = –20 μA, See Figure 9
VCCO – 0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IN at VCCI
IIL
Low-level input current
IN at 0 V
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 13
(1)
10
μA
0
IOH = –4 mA, See Figure 9
V
IOL = 4 mA, See Figure 9
0.4
IOL = 20 μA, See Figure 9
0.1
150
mV
10
–10
25
V
μA
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
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7.6 Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V (1) Operation
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISO7240C/M
ISO7241C/M
ICC1
ISO7242C/M
ISO7240C/M
ISO7241C/M
ICC2
ISO7242C/M
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
1
3
7
10.5
All channels, no load,
EN1 at 3 V,
EN2 at 3 V
6.5
11
12
18
All channels, no load,
EN1 at 3 V,
EN2 at 3 V
10
16
15
24
All channels, no load, EN
at 3 V
All channels, no load, EN
at 3 V
All channels, no load,
EN1 at 3 V,
EN2 at 3 V
All channels, no load,
EN1 at 3 V,
EN2 at 3 V
9.5
15
10.5
17
8
13
11.5
18
6
10
9
14
mA
mA
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
EN at 0 V, Single channel
IOH = –4 mA, See Figure 9
VCCO – 0.4
5-V side
VCCO – 0.8
IOH = –20 μA, See Figure 9
V
VCCO – 0.1
IOL = 4 mA, See Figure 9
0.4
IOL = 20 μA, See Figure 9
0.1
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IN at VCCI
IIL
Low-level input current
IN at 0 V
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 13
(1)
μA
0
3.3-V side
V
150
mV
10
μA
–10
25
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
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7.7 Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V (1) Operation
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
1
3
5
UNIT
SUPPLY CURRENT
ISO7240C/M
ISO7241C/M
ICC1
ISO7242C/M
ISO7240C/M
ISO7241C/M
ICC2
ISO7242C/M
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
All channels, no load,
EN at 3 V
All channels, no load,
EN1 at 3 V,
EN2 at 3 V
4
7
6.5
11
All channels, no load,
EN1 at 3 V,
EN2 at 3 V
6
10
9
14
All channels, no load,
EN at 3 V
15
22
17
25
All channels, no load,
EN1 at 3 V,
EN2 at 3 V
13
20
18
28
All channels, no load,
EN1 at 3 V,
EN2 at 3 V
10
16
15
24
mA
mA
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
EN at 0 V, Single channel
IOH = –4 mA, See Figure 9
IOH = –20 μA, See Figure 9
5-V side
VCCO – 0.8
V
VCCO – 0.1
0.4
IOL = 20 μA, See Figure 9
0.1
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IN at VCCI
IIL
Low-level input current
IN at 0 V
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 13
12
VCCO – 0.4
IOL = 4 mA, See Figure 9
VOL
(1)
μA
0
3.3-V side
150
mV
10
–10
25
V
μA
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
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7.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V (1) Operation
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
1
3
5
UNIT
SUPPLY CURRENT
ISO7240C/M
ISO7241C/M
ICC1
ISO7242C/M
ISO7240C/M
ISO7241C/M
ICC2
ISO7242C/M
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
Quiescent
VI = VCC or 0 V
25 Mbps
12.5 MHz Input Clock Signal
All channels, no load,
EN at 3 V
All channels, no load,
EN1 at 3 V, EN2 at 3 V
4
7
6.5
11
6
10
All channels, no load,
EN1 at 3 V, EN2 at 3 V
All channels, no load,
EN at 3 V
All channels, no load,
EN1 at 3 V, EN2 at 3 V
9
14
9.5
15
10.5
17
8
13
11.5
18
6
10
9
14
All channels, no load,
EN1 at 3 V, EN2 at 3 V
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, single channel
VCCO – 0.4
IOH = –20 μA, See Figure 9
VCCO – 0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IN at VCCI
IIL
Low-level input current
IN at 0 V
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 13
(1)
μA
0
IOH = –4 mA, See Figure 9
V
IOL = 4 mA, See Figure 9
0.4
IOL = 20 μA, See Figure 9
0.1
150
mV
10
–10
25
V
μA
2
pF
50
kV/μs
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
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7.9 Switching Characteristics: VCC1 and VCC2 at 5-V Operation
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 11
12
μs
twake
Wake time from input disable
See Figure 12
15
μs
Peak-to-peak eye-pattern jitter
150 Mbps NRZ data input, Same
polarity input on all channels, See
Figure 14
1
ns
(1)
(2)
(3)
14
ISO724xC
42
UNIT
Propagation delay
tjit(pp)
18
MAX
tPLH, tPHL
2.5
See Figure 9
10
ISO724xM
23
1
ISO724xC
(2)
8
ISO724xM
(3)
0
ISO724xC
3
2
ISO724xM
0
1
2
See Figure 9
ISO724xM
2
ns
ns
ns
ns
2
See Figure 10
ns
ns
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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7.10 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion(1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 11
18
μs
twake
Wake time from input disable
See Figure 12
15
μs
Peak-to-peak eye-pattern jitter
150 Mbps PRBS NRZ data input,
Same polarity input on all
channels, See Figure 14
1
ns
(1)
(2)
(3)
50
UNIT
PWD
tjit(pp)
20
MAX
Propagation delay
ISO724xC
See Figure 9
TYP
tPLH, tPHL
3
12
ISO724xM
29
1
ISO724xC
(2)
(3)
0
ISO724xC
5
3
ISO724xM
0
1
2
See Figure 9
ISO724xM
2
10
ISO724xM
ns
ns
ns
ns
2
See Figure 10
ns
ns
Also known as pulse skew
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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7.11 Switching Characteristics: VCC1 at 3.3-V and VCC2 at 5-V Operation
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
MIN
TYP
22
ISO724xC
MAX
51
3
See Figure 9
ns
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion(1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 11
12
μs
twake
Wake time from input disable
See Figure 12
15
μs
Peak-to-peak eye-pattern jitter
150 Mbps NRZ data input, Same
polarity input on all channels, See
Figure 14
1
ns
tjit(pp)
(1)
(2)
(3)
16
12
UNIT
ISO724xM
30
1
ISO724xC
(2)
10
ISO724xM
(3)
0
ISO724xC
5
2.5
ISO724xM
0
1
2
See Figure 9
ISO724xM
2
ns
ns
ns
2
See Figure 10
ns
ns
Also known as pulse skew
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015
7.12 Switching Characteristics: VCC1 and VCC2 at 3.3-V Operation
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 11
18
μs
twake
Wake time from input disable
See Figure 12
15
μs
Peak-to-peak eye-pattern jitter
150 Mbps PRBS NRZ data input, same
polarity input on all channels, See
Figure 14
1
ns
(1)
(2)
(3)
ISO724xC
56
UNIT
Propagation delay
tjit(pp)
25
MAX
tPLH, tPHL
4
See Figure 9
12
ISO724xM
34
1
ISO724xC
(2)
10
ISO724xM
(3)
0
ISO724xC
5
3.5
ISO724xM
0
See Figure 9
ISO724xM
2
See Figure 10
1
ns
ns
ns
ns
2
ns
2
ns
ns
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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45
45
40
40
ICC - Supply Current - mA/RMS
ICC - Supply Current - mA/RMS
7.13 Typical Characteristics
35
5-V ICC2
30
3.3-V ICC2
25
20
5-V ICC1
15
10
5
35
5-V ICC2
30
25
20
3.3-V ICC2
15
5
3.3-V ICC1
25
50
75
100
Signaling Rate - Mbps
TA = 25°C
125
0
0
150
Load = 15 pF
All Channels
45
45
40
40
35
35
30
5-V ICC1,ICC2
25
20
15
3.3-V ICC1,ICC2
100
125
150
Load = 15 pF
All Channels
3.3-V t pLH , t pHL ( C-grade)
5-V tpLH, tpHL (C-grade)
30
25
3.3-V tpLH, tpHL (M-grade)
20
15
10
10
5
5
5-V tpLH, tpHL (M-grade)
0
25
50
TA = 25°C
75
100
125
150
-40
Load = 15 pF
All Channels
-25
-10
80
65
35
20
50
TA - Free-Air Temperature - °C
95
Load = 15 pF
110
125
All Channels
Figure 4. Propagation Delay vs Free-Air Temperature
3
1.4
5 V Vth+
2.9
VCC - Undervoltage Threshold - V
1.35
1.3
3.3 V Vth+
1.25
1.2
1.15
5 V Vth1.1
1.05
-25
-10
Air Flow at 7 cf/m
2.8
VCC Rising
2.7
2.6
2.5
VCC Falling
2.4
2.3
2.2
2.1
3.3 V Vth1
-40
5
TA = 25°C
Figure 3. ISO7242C/M RMS Supply Current vs Signaling
Rate
Input Voltage Threshold - V
75
Figure 2. ISO7241C/M RMS Supply Current vs Signaling
Rate
Signaling Rate - Mbps
5
20
35
50
65
80
TA - Free-Air Temperature - °C
95
110
125
2
-40
-25
-10
5
20
35
50
65
80
95
110
125
TA - Free-Air Temperature - °C
Low_K Board
Figure 5. Input Voltage Threshold vs Free-Air Temperature
18
50
TA = 25°C
Propagation Delay - ns
ICC - Supply Current - mA/RMS
25
Signaling Rate - Mbps
Figure 1. ISO7240C/M RMS Supply Current vs Signaling
Rate
0
0
3.3-V ICC1
10
0
0
5-V ICC1
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Figure 6. VCC Undervoltage Threshold vs Free-Air
Temperature
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Typical Characteristics (continued)
50
50
VCC = 5 V
45
40
IO - Output Current - mA
IO - Output Current - mA
40
VCC = 3.3 V
30
20
10
35
VCC = 3.3 V
30
25
VCC = 5 V
20
15
10
5
0
0
2
TA = 25°C
4
VO - Output Voltage - V
6
Load = 15 pF
Figure 7. High-Level Output Current vs High-Level Output
Voltage
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0
0
1
TA = 25°C
2
3
VO - Output Voltage - V
4
5
Load = 15 pF
Figure 8. Low-Level Output Current vs Low-Level Output
Voltage
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ISOLATION BARRIER
8 Parameter Measurement Information
IN
Input
Generator
VI
50 W
NOTE A
VCC
VI
VCC/2
VCC/2
OUT
0V
tPHL
tPLH
CL
NOTE B
VO
VO
VOH
90%
50%
50%
10%
tr
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9. Switching Characteristic Test Circuit and Voltage Waveforms
Vcc
VCC
ISOLATION BARRIER
0V
RL = 1 kW ±1%
IN
Input
Generator
VI
OUT
EN
VCC/2
VI
t PZL
VO
VO
CL
VCC/2
0V
t PLZ
VCC
0.5 V
50%
NOTE
B
50 W
VOL
3V
ISOLATION BARRIER
NOTE A
IN
Input
Generator
VI
OUT
VO
VCC
VCC/2
VI
VCC/2
0V
EN
50 W
t PZH
CL
NOTE
B
RL = 1 kW ±1%
VO
VOH
50%
0.5 V
t PHZ
0V
NOTE A
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Enable/Disable Propagation Delay Time Test Circuit and Waveform
20
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Parameter Measurement Information (continued)
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
3V
IN
DISABLE
ISOLATION BARRIER
Figure 11. Failsafe Delay Time Test Circuit and Voltage Waveforms
OUT
VCC
VO
VI
0V
CTRL
t wake
VCC
CL
Input
VI
Generator
0V
50 %
( Note B)
50 W
VO
IN
0V
DISABLE
ISOLATION BARRIER
( Note A)
0V
VCC
OUT
VO
VI
VCC/2
0V
t wake
CTRL
VCC2
CL
Input
Generator
VCC/2
VI
3V
50 W
(Note B )
50 %
VO
( Note A )
0V
NOTE: Which ever test yields the longest time is used in this data sheet
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 12. Wake Time From Input Disable Test Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
IN
S1
C = 0.1 µF ±1%
Isolation Barrier
VCCI
GNDI
VCCO
C = 0.1 µF ±1%
Pass-fail criteria –
output must remain
stable.
OUT
+
CL
See Note A
GNDO
VOH or VOL
–
+ VCM –
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
Figure 13. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
VCC
DUT
Tektronix
HFS9009
IN
OUT
0V
Tektronix
784D
PATTERN
GENERATOR
VCC/2
Jitter
NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s
or 0s.
Figure 14. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
22
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9 Detailed Description
9.1 Overview
The isolator in Figure 15 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to 150
Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a singleended input signal entering the HF-channel is split into a differential signal via the inverter gate at the input. The
following capacitor-resistor networks differentiate the signal into transients, which then are converted into
differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an
output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between
signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case
of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low-frequency
channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass
filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
9.2 Functional Block Diagram
Isolation Barrier
OSC
LPF
Low t Frequency
Channel
(DC...100 kbps)
PWM
VREF
0
OUT
1 S
IN
DCL
High t Frequency
Channel
(100 kbps...150 Mbps)
VREF
Figure 15. Conceptual Block Diagram of a Digital Capacitive Isolator
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9.3 Feature Description
ISO724x are available in multiple channel configurations and default output state options to enable wide variety
of application uses.
PRODUCT
SIGNALING
RATE
INPUT
THRESHOLD
ISO7240C
25 Mbps
~1.5 V (TTL)
ISO7240CF
25 Mbps
~1.5 V (TTL)
ISO7240M
150 Mbps
VCC/ 2 (CMOS)
ISO7241C
25 Mbps
~1.5 V (TTL)
ISO7241M
150 Mbps
VCC/ 2 (CMOS)
ISO7242C
25 Mbps
~1.5 V (TTL)
ISO7242M
150 Mbps
VCC/ 2 (CMOS)
CHANNEL
CONFIGURATION
4/0
3/1
2/2
9.3.1 DIN V VDE V 0884-10 (VDE V 0884-10):2006-1 Insulation Characteristics (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIORM
VPR
Input to output test voltage
VIOTM
RS
TEST CONDITIONS
SPECIFICATIONS
Maximum working insulation voltage
Maximum transient isolation voltage
Insulation resistance
VPK
After Input/Output Safety Test Subgroup 2/3
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
672
VPK
Method a, VPR = VIORM × 1.6,
Type and sample test with t = 10 s,
Partial discharge < 5 pC
896
VPK
Method b1, VPR = VIORM × 1.875,
100 % Production test with t = 1 s,
Partial discharge < 5 pC
1050
VPK
t = 60 s
4000
VPK
9
VIO = 500 V at TS = 150°C
Ω
>10
Pollution degree
(1)
UNIT
560
2
Climatic Classification 40/125/21
Table 1. IEC 60664-1 Ratings Table
PARAMETER
Basic isolation group
Installation classification
TEST CONDITIONS
SPECIFICATION
Material group
II
Rated mains voltage ≤150 VRMS
I-IV
Rated mains voltage ≤300 VRMS
I-III
9.3.2 Package Characteristics
TEST CONDITIONS
MIN
L(I01)
Minimum air gap
(Clearance) (1)
PARAMETER
Shortest pin-to-pin distance through air
8
mm
L(I02)
Minimum external tracking
(Creepage) (1)
Shortest pin-to-pin distance across the package surface
8
mm
CTI
Tracking resistance
(comparative tracking index)
DIN EN 60112 (VDE 0303-11); IEC 60112
≥ 400
V
Minimum Internal Gap
(Internal Clearance)
Distance through the insulation
0.008
mm
RIO
Isolation resistance
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device
CIO
Barrier capacitance Input to output
VI = 0.4 sin (4E6πt)
(1)
24
TYP MAX
UNIT
> 1012
Ω
2
pF
Per JEDEC package dimensions
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9.3.3 Life Expectancy vs. Working Voltage
WORKING LIFE -- YEARS
100
VIORM at 560-VPK
28 Years
10
0
250
120
500
750
1000
880
WORKING VOLTAGE (VIORM) -- VPK
Figure 16. Time-Dependant Dielectric Breakdown Testing Results
9.3.4 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or
supply current
SOIC16
TS
Maximum case temperature
SOIC16
MIN
TYP
MAX
θJA = 168°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
156
θJA = 168°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
239
150
UNIT
mA
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity
Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum
input voltage times the current. The junction temperature is then the ambient temperature plus the power times
the junction-to-air thermal resistance.
300
VCC1,2 at 3.6 V
Safety Limiting Current - mA
250
200
150
VCC1,2 at 5.5 V
100
50
0
0
50
100
150
TC - Case Temperature - °C
200
Figure 17. SOIC-16 ΘJC Thermal Derating Curve per VDE
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9.3.5 Regulatory Information
VDE
CSA
UL
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 and DIN EN
61010-1 (VDE 0411-1): 2011-07
Approved under CSA Component
Acceptance Notice 5A
Recognized under UL 1577 Component
Recognition Program
Basic Insulation
Maximum Transient Overvoltage, 4000 VPK
Maximum Surge Votlage, 4000 VPK
Maximum Working Voltage, 560 VPK
Basic insulation per CSA 60950-1-07 and
IEC 60950-1 (2nd Ed), 395 VRMS maximum
working voltage, 4000 VPK maximum
isolation rating
Single protection, 2500 VRMS (1)
Certificate Number: 40016131
Master Contract Number: 220991
File Number: E181974
(1)
26
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
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9.4 Device Functional Modes
Table 2. Device Function Table ISO724x (1)
INPUT VCC
OUTPUT VCC
PU
(1)
INPUT
(IN)
OUTPUT ENABLE
(EN)
OUTPUT
(OUT)
H
H or Open
H
L
H or Open
L
PU
X
L
Z
Open
H or Open
H
H or Open
H
PD
PU
X
PD
PU
X
L
Z
X
PD
X
X
Undetermined
PU = Powered Up; PD = Powered Down; X = Irrelevant; H = High Level; L = Low Level; Z = High
Impedance; Open = Not Connected
Table 3. ISO7240CF Functions Table (1)
(1)
VCC1
VCC2
DATA INPUT
(IN)
DISABLE INPUT
(DISABLE)
FAILSAFE CONTROL
(CTRL)
DATA OUTPUT
(OUT)
PU
PU
H
L or Open
X
H
PU
PU
L
L or Open
X
L
X
PU
X
H
H or Open
H
X
PU
X
H
L
L
PD
PU
X
X
H or Open
H
PD
PU
X
X
L
L
X
PD
X
X
X
Undetermined
PU = Powered Up; PD = Powered Down; X = Irrelevant; H = High Level; L = Low Level; Z = High Impedance; Open = Not Connected
9.4.1 Device I/O Schematics
Output
Input
VCC
VCC
VCC
VCC
1 MW
IN
8W
500 W
OUT
13 W
ISO7240CF
Enable, Control
Input, Disable
VCC
VCC
VCC
VCC
VCC
1 MW
IN
or
DISABLE
500 W
EN
or
CTRL
500 W
1 MW
Figure 18. Device I/O Schematics
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
ISO724x use single-ended TTL or CMOS-logic switching technology. Its supply voltage range is from 3.15 V to
5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that
due to the single-ended design structure, digital isolators do not conform to any specific interface standard and
are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed
between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the
interface type or standard.
10.2 Typical Application
10.2.1 Isolated Data Acquisition System for Process Control
ISO724x can be used with Texas Instruments' precision analog-to-digital converter and mixed signal microcontroller to create an advanced isolated data acquisition system as shown in Figure 19.
Figure 19. Isolated Data Acquisition System for Process Control
10.2.1.1 Design Requirements
Unlike optocouplers, which need external components to improve performance, provide bias, or limit current,
ISO724x only needs two external bypass capacitors to operate.
28
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Typical Application (continued)
10.2.1.2 Detailed Design Procedure
Figure 20. ISO7240 Typical Circuit Hook-Up
Figure 21. ISO7240CF Typical Circuit Hook-Up
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Typical Application (continued)
Figure 22. ISO7241 Typical Circuit Hook-Up
Figure 23. ISO7242 Typical Circuit Hook-Up
30
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Typical Application (continued)
10.2.1.3 Application Curve
Figure 24. ISO7242M Eye Diagram at 25 Mbps, 3.3 V and
25°C
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Figure 25. ISO7242M Eye Diagram at 150 Mbps, 3.3 V and
25°C
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Typical Application (continued)
10.2.2 Isolated SPI Interface for an Analog Input Module with 16 Inputs
ISO7241 and several other components from Texas Instruments can be used to create an isolated SPI interface
for input module with 16 inputs.
Figure 26. Isolated SPI Interface for an Analog Input Module with 16 Inputs
10.2.2.1 Design Requirements
See previous Design Requirements.
10.2.2.2 Detailed Design Procedure
See previous Detailed Design Procedure.
10.2.2.3 Application Curve
See previous Application Curve.
32
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Typical Application (continued)
10.2.3 Isolated RS-232 Interface
Typical isolated RS-232 interface implementation is shown in Figure 27.
Figure 27. Isolated RS-232 Interface
10.2.3.1 Design Requirements
See previous Design Requirements.
10.2.3.2 Detailed Design Procedure
See previous Detailed Design Procedure.
10.2.3.3 Application Curve
See previous Application Curve.
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11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1 μF bypass capacitor is recommended at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments SN6501 data
sheet . For such applications, detailed power supply design and transformer selection recommendations are
available in SN6501 data sheet (SLLSEA0).
12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 28). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly. For detailed layout recommendations, see Application Note SLLA284, Digital
Isolator Design Guide.
12.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics.
12.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 28. Recommended Layer Stack
34
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Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M, ISO7242C, ISO7242M
www.ti.com
SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015
13 Device and Documentation Support
13.1 Device Support
13.1.1 Isolation Glossary
Primary Circuit — A circuit that is directly connected to an external mains supply for its power needs.
Secondary Circuit — A circuit that has no direct connection to a primary circuit and derives its power from a
transformer, converter or equivalent isolation device, or from a battery.
Creepage — The shortest distance between two conductive parts measured along the surface of a solid
insulation. The shortest path is typically found around the end of the package body.
Clearance — The shortest distance between two conductive parts measured through air.
Isolation Capacitance (CIO) — The total capacitance between the terminals on a first side of the isolation barrier
connected together and the terminals on a second side of the isolation barrier connected together forming a twoterminal device.
Isolation Resistance (RIO) — The resistance between the terminals on a first side of the isolation barrier
connected together and all the terminals on a second side of the isolation barrier connected together forming a
two-terminal device.
Rated Isolation Voltages — The maximum voltage between all input terminals (connected together) and all
output terminals (connected together) respectively.
Maximum Rated Isolation Working Voltage (VIOWM) — An r.m.s or equivalent d.c. voltage assigned by the
manufacturer, characterizing the specified long term withstand capability of its isolation.
Maximum Rated Repetitive Peak Isolation Voltage (VIORM) — A peak voltage assigned by the manufacturer,
characterizing the specified withstand capability of its isolation against repetitive peak voltages. It includes all
repetitive transient voltages, but excludes all non-repetitive transient voltages.
Maximum Rated Transient Isolation Voltage (VIOTM) — A peak impulse voltage assigned by the manufacturer,
characterizing the specified withstand capability of its isolation against transient overvoltages.
Withstand Isolation Voltage (VISO) — Maximum AC r.m.s. isolation voltage for one minute.
Surge Isolation Voltage (VIOSM) — The highest instantaneous value of an isolation voltage pulse with short time
duration and of specified wave shape.
Partial Discharge — Localized electrical discharge which occurs in the insulation between all terminals of the
first side and all terminals of the second side of the coupler.
Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M
35
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M, ISO7242C, ISO7242M
SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015
www.ti.com
Device Support (continued)
Comparative Tracking Index (CTI) — CTI is an index used for electrical insulating materials that is defined as
the numerical value of the voltage which causes failure by tracking during standard testing. Tracking is the
process that produces a partially conducting path of localized deterioration on or through the surface of an
insulating material as a result of the action of electric discharges on or close to an insulation surface -- the higher
the CTI value of the insulating material, the smaller the minimum creepage distance required.
Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may
arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such
sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting
break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is
generated. These sparks often cause carbonization on insulation material and lead to a carbon track between
points of different potential. This process is known as tracking.
Material Groups — Materials are classified into four groups according to their CTI values. These values are
determined in accordance with IEC 60112. The groups are as follows:
•
•
•
•
Material
Material
Material
Material
group
group
group
group
I: 600V ≤ CTI
II: 400V ≤ CTI < 600
II: 175V ≤ CTI < 400
II: 100V ≤ CTI < 175
13.1.1.1 Insulation:
Functional insulation — Insulation needed for the correct operation of the equipment.
Basic insulation — Insulation that provides basic protection against electric shock.
Supplementary insulation — Independent insulation applied in addition to basic insulation in order to ensure
protection against electric shock in the event of a failure of the basic insulation.
Double insulation — Insulation comprising both basic and supplementary insulation.
Reinforced insulation — A single insulation system which provides a degree of protection against electric shock
equivalent to double insulation.
13.1.1.2 Pollution Degree:
Pollution is any addition of foreign matter, solid, liquid, or gaseous that can result in a reduction of electric
strength or surface resistivity of the insulation. There are four categories of pollution:
Pollution Degree 1 — No pollution or only dry, nonconductive pollution occurs. The pollution has no influence.
Pollution Degree 2 — Only nonconductive pollution occurs. However, a temporary conductivity caused by
condensation is to be expected.
Pollution Degree 3 — Conductive pollution occurs or dry non-conductive pollution occurs which becomes
conductive due to condensation which is to be expected.
Pollution Degree 4 – Continuous conductivity occurs due to conductive dust, rain, or other wet conditions.
13.1.1.3 Overvoltage Categories and Installation Classification:
Overvoltage Categories define transient overvoltage conditions. There are four different levels as indicated in IEC
60664.
I: Signal level — Special protected equipment or parts of equipment, e.g., circuit board inside a DVD player.
II: Local level — Portable equipment that is supplied from the wall outlet, e.g., a DVD player
III: Distribution level — Equipment in fixed installation such as HVAC system, Washers / Dryers, etc.
IV: Primary supply level — Equipment for use at the origin of the installations such as overhead lines, cable
systems, etc.
Lower level category is subject to smaller transients than the category above.
36
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M, ISO7242C, ISO7242M
www.ti.com
SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015
13.2 Documentation Support
13.2.1 Related Documentation
•
•
•
•
SLLA197, High-Voltage Lifetime of the ISO72x Family of Digital Isolators
SLLA181, ISO72x Digital Isolator Magnetic-Field Immunity
SLLSEA0,SN6501 Transformer Driver for Isolated Power Supplies
SLLA284, Digital Isolator Design Guide
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7240CF
Click here
Click here
Click here
Click here
Click here
ISO7240C
Click here
Click here
Click here
Click here
Click here
ISO7240M
Click here
Click here
Click here
Click here
Click here
ISO7241C
Click here
Click here
Click here
Click here
Click here
ISO7241M
Click here
Click here
Click here
Click here
Click here
ISO7242C
Click here
Click here
Click here
Click here
Click here
ISO7242M
Click here
Click here
Click here
Click here
Click here
13.4 Trademarks
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M
37
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
PIN 1 ID
AREA
A
10.63
TYP
9.97
SEATING PLANE
0.1 C
16
1
14X 1.27
2X
8.89
10.5
10.1
NOTE 3
8
9
B
7.6
7.4
NOTE 4
0.51
0.31
0.25
C A
16X
2.65 MAX
B
0.38
TYP
0.25
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
(1.4)
DETAIL A
TYPICAL
4221009/A 08/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MO-013, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
16X (2)
1
SYMM
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/A 08/2013
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
16X (2)
SYMM
16X (1.65)
1
1
16
16X (0.6)
16
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/A 08/2013
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7240CDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7240C
ISO7240CDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7240C
ISO7240CDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7240C
ISO7240CDWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7240C
ISO7240CFDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7240CF
ISO7240CFDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7240CF
ISO7240CFDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7240CF
ISO7240MDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7240M
ISO7240MDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7240M
ISO7240MDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7240M
ISO7240MDWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7240M
ISO7241CDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7241C
ISO7241CDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7241C
ISO7241CDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7241C
ISO7241CDWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7241C
ISO7241MDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7241M
ISO7241MDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7241M
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
12-Sep-2015
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7241MDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7241M
ISO7241MDWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7241M
ISO7242CDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7242C
ISO7242CDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7242C
ISO7242CDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7242C
ISO7242MDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7242M
ISO7242MDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7242M
ISO7242MDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7242M
ISO7242MDWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7242M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
12-Sep-2015
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7240CF, ISO7241C, ISO7242C :
• Automotive: ISO7240CF-Q1, ISO7241C-Q1, ISO7242C-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7240CDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7240CFDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7240MDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7241CDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7241MDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7242CDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7242MDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7240CDWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7240CFDWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7240MDWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7241CDWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7241MDWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7242CDWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7242MDWR
SOIC
DW
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
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