TI1 LM46002 3.5-v to 60-v, 2-a, synchronous step-down voltage converter Datasheet

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LM46002-Q1, LM46002A-Q1
SNVSAA2B – JULY 2015 – REVISED JULY 2017
LM46002-Q1 3.5-V to 60-V, 2-A, Synchronous Step-Down Voltage Converter
1 Features
3 Description
•
•
The LM46002-Q1 regulator is an easy-to-use
synchronous step-down DC-DC converter capable of
driving up to 2 A of load current from an input voltage
ranging from 3.5 V to 60 V. The LM46002-Q1
provides exceptional efficiency, output accuracy and
drop-out voltage in a very small solution size. An
extended family is available in various load-current
options and 36-V maximum input voltage. The device
is pin-to-pin compatible package with LM4360x and
LM4600x family. Peak-current-mode control is
employed
to
achieve
simple
control-loop
compensation and cycle-by-cycle current limiting.
Optional features such as programmable switching
frequency,
synchronization,
power-good
flag,
precision enable, internal soft-start, extendable softstart, and tracking provide a flexible and easy-to-use
platform for a wide range of applications.
Discontinuous conduction and automatic frequency
reduction at light loads improve light load efficiency.
The family requires few external components. Pin
arrangement allows simple, optimum PCB layout.
Protection features include thermal shutdown, VCC
undervoltage lockout, cycle-by-cycle current limit, and
output short-circuit protection. The LM46002A-Q1
version is optimized for PFM operation and
recommended for new designs. The LM46002-Q1
device is available in the 16-lead HTSSOP (PWP)
package (6.6 mm × 5.1 mm × 1.2 mm) with 0.65-mm
lead pitch.
1
•
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•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
27-µA Quiescent Current in Regulation
High Efficiency at Light Load (DCM and PFM)
Tested to EN55022/CISPR 22 EMI standards
Integrated Synchronous Rectification
Adjustable Frequency Range: 200 kHz to 2.2 MHz
(500-kHz default)
Frequency Synchronization to External Clock
Internal Compensation
Stable With Almost Any Combination of Ceramic,
Polymer, Tantalum, and Aluminum Capacitors
Power-Good Flag
Soft Start into Pre-Biased Load
Internal and Adjustable External Soft Start
Output Voltage Tracking Capability
Precision Enable to Program System UVLO
Output Short-Circuit Protection With Hiccup Mode
Overtemperature Thermal Shutdown Protection
Create a Custom Design Using the LM46002-Q1
With the WEBENCH® Power Designer
Device Information(1)
2 Applications
•
•
•
•
•
PART NUMBER
Sub-AM Band 12-V and 24-V Automotive
Telecommunications Systems
Commercial Vehicle Power Supplies
General Purpose Wide VIN Regulation
High Efficiency Point-Of-Load Regulation
PACKAGE
BODY SIZE (NOM)
LM46002-Q1
HTSSOP (16)
6.60 mm × 5.10 mm
LM46002A-Q1
HTSSOP (16)
6.60 mm × 5.10 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
white
white
Simplified Schematic
Radiated Emission Graph
VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz, IOUT = 2 A
VIN
CIN
VOUT
SW
LM46002-Q1
ENABLE
PGOOD
CBOOT
CBOOT
BIAS
CBIAS
SS/TRK
RT
COUT
CFF
RFBT
FB
SYNC
VCC
AGND
PGND
CVCC
RFBB
Radiated EMI Emissions (dBµV/m)
80
L
VIN
Evaluation Board
70
EN 55022 Class B Limit
EN 55022 Class A Limit
60
50
40
30
20
10
0
0
200
400
600
Frequency (MHz)
800
1000
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM46002-Q1, LM46002A-Q1
SNVSAA2B – JULY 2015 – REVISED JULY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 23
8
Applications and Implementation ...................... 24
8.1 Application Information............................................ 24
8.2 Typical Applications ................................................ 24
9 Power Supply Recommendations...................... 40
10 Layout................................................................... 40
10.1 Layout Guidelines ................................................. 40
10.2 Layout Example .................................................... 43
11 Device and Documentation Support ................. 44
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
44
44
44
44
44
44
12 Mechanical, Packaging, and Orderable
Information ........................................................... 45
4 Revision History
Changes from Revision A (August 2015) to Revision B
Page
•
Editorial changes to meet writing/editing standards .............................................................................................................. 1
•
Added LM46002A-Q1 version information throughout data sheet ......................................................................................... 1
•
Added WEBENCH® content and links .................................................................................................................................... 1
•
Added maximum operating junction temperature................................................................................................................... 4
•
Added standard note 1 to Thermal Information table ............................................................................................................ 5
•
Updating the Soft-start charge current (ISSC) minimum from 1.25 µA to 1.17 µA and typical from 2.2 µA to 2 µA ............... 6
•
Updating RPGOOD value on EN = 3.3 V and EN = 0 V ........................................................................................................ 6
•
Updating Equation 16 ........................................................................................................................................................... 27
Changes from Original (July 2015) to Revision A
•
2
Page
Changed from Preview to Production Data ............................................................................................................................ 1
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SNVSAA2B – JULY 2015 – REVISED JULY 2017
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
SW
1
SW
2
16
15
PGND
PGND
CBOOT
VCC
3
4
14
VIN
13
BIAS
5
VIN
12
SYNC
EN
6
11
RT
PGOOD
SS/TRK
7
8
10
AGND
PAD
9
FB
Pin Functions
PIN
DESCRIPTION
NUMBER
1, 2
SW
P
Switching output of the regulator. Internally connected to both power MOSFETs. Connect to power
inductor.
3
CBOOT
P
Boot-strap capacitor connection for high-side driver. Connect a high quality 470-nF capacitor from
CBOOT to SW.
4
VCC
P
Internal bias supply output for bypassing. Connect bypass capacitor from this pin to AGND. Do not
connect external load to this pin. Never short this pin to ground during operation.
5
BIAS
P
Optional internal LDO supply input. To improve efficiency, TI recommends tying to VOUT when 3.3 V ≤
VOUT ≤ 28 V, or tie to an external 3.3-V or 5-V rail if available. When used, place a bypass capacitor (1
to 10 µF) from this pin to ground. Tie to ground when not in use.
6
SYNC
A
Clock input to synchronize switching action to an external clock. Use proper high speed termination to
prevent ringing. Connect to ground if not used.
7
RT
A
Connect a resistor RT from this pin to AGND to program switching frequency. Leave floating for 500-kHz
default switching frequency.
8
PGOOD
A
Open drain output for power-good flag. Use a 10-kΩ to 100-kΩ pullup resistor to logic rail or other DC
voltage no higher than 12 V.
9
FB
A
Feedback sense input pin. Connect to the midpoint of feedback divider to set VOUT. Do not short this pin
to ground during operation.
10
AGND
G
Analog ground pin. Ground reference for internal references and logic. Connect to system ground.
11
SS/TRK
A
Soft-start control pin. Leave floating for internal soft-start slew rate. Connect to a capacitor to extend
soft start time. Connect to external voltage ramp for tracking.
12
EN
A
Enable input to the LM46002-Q1: High = ON and Low = OFF. Connect to VIN, or to VIN through
resistor divider, or to an external voltage or logic source. Do not float.
13,14
VIN
P
Supply input pins to internal LDO and high side power FET. Connect to power supply and bypass
capacitors CIN. Path from VIN pin to high frequency bypass CIN and PGND must be as short as
possible.
15,16
PGND
G
Power ground pins, connected internally to the low side power FET. Connect to system ground, PAD,
AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible.
PAD
G
Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation path of the die.
Must be used for heat sinking to ground plane on PCB.
(1)
I/O
(1)
NO.
P = Power, G = Ground, A = Analog
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VIN to PGND
PARAMETER
–0.3
65
EN to PGND
–0.3
VIN + 0.3
FB, RT, SS/TRK to AGND
–0.3
3.6
PGOOD to AGND
–0.3
15
SYNC to AGND
–0.3
5.5
BIAS to AGND
–0.3
30
AGND to PGND
–0.3
0.3
SW to PGND
–0.3
VIN + 0.3
SW to PGND less than 10ns Transients
–3.5
65
CBOOT to SW
–0.3
5.5
VCC to AGND
–0.3
3.6
Storage temperature range, Tstg
–65
150
°C
Operating junction temperature
–40
150
°C
Input voltages
Output voltages
(1)
UNIT
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
MIN
MAX
3.5
60
EN
–0.3
VIN
FB
–0.3
1.1
PGOOD
–0.3
12
BIAS input not used
–0.3
0.3
VIN to PGND
Input voltages
BIAS input used
3.3
28
AGND to PGND
–0.1
0.1
UNIT
V
Output voltage
VOUT
1
28
Output current
IOUT
0
2
A
Temperature
Operating junction temperature range, TJ
–40
125
°C
(1)
4
V
Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For
verified specifications, see Electrical Characteristics.
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SNVSAA2B – JULY 2015 – REVISED JULY 2017
6.4 Thermal Information
LM46002-Q1
THERMAL METRIC
(1) (2)
PWP (HTSSOP)
UNIT
(16 PINS)
38.9 (3)
°C/W
Junction-to-case (top) thermal resistance
24.3
°C/W
Junction-to-board thermal resistance
19.9
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
19.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.7
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package thermal impedance is calculated in accordance with JESD 51-7 standard with a 4-layer board and 2-W power dissipation.
RθJA is highly related to PCB layout and heat sinking. Please refer to Figure 101 for measured RθJA vs PCB area from a 2-layer board
and a 4-layer board.
6.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PINS)
VIN-MIN-ST
Minimum input voltage for start-up
ISHDN
Shutdown quiescent current
VEN = 0 V
IQ-NONSW
Operating quiescent current (nonswitching) from VIN
IBIAS-NONSW
IQ-SW
3.8
V
2.3
5
µA
VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external
7
12
µA
Operating quiescent current (nonswitching) from external VBIAS
VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external
87
135
µA
Operating quiescent current (switching)
VEN = VIN
IOUT = 0 A
RT = open
VBIAS = VOUT = 3.3 V
RFBT = 1 Meg
27
µA
ENABLE (EN PIN)
VEN-VCC-H
Voltage level to enable the internal
LDO output VCC
VENABLE high level
VEN-VCC-L
Voltage level to disable the internal
LDO output VCC
VENABLE low level
VEN-VOUT-H
Precision enable level for switching and
VENABLE high level
regulator output: VOUT
VEN-VOUT-HYS
Hysteresis voltage between VOUT
V
hysteresis
precision enable and disable thresholds ENABLE
ILKG-EN
Enable input leakage current
1.2
2
V
2.1
0.4
V
2.42
V
–294
mV
VEN = 3.3 V
0.8
1.7
µA
VIN ≥ 3.8 V
3.2
V
VCC rising threshold
3.15
V
Hysteresis voltage between rising and
falling thresholds
–575
mV
VBIAS rising threshold
2.94
Hysteresis voltage between rising and
falling thresholds
–67
INTERNAL LDO (VCC PIN AND BIAS PIN)
VCC
Internal LDO output voltage VCC
VCC-UVLO
Undervoltage lock out (UVLO)
thresholds for VCC
VBIAS-ON
Internal LDO input change over
threshold to BIAS
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3.15
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V
mV
5
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SNVSAA2B – JULY 2015 – REVISED JULY 2017
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Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TJ = 25°C
1.004
1.011
1.018
TJ = –40°C to 125°C
0.994
1.011
1.030
FB = 1.011 V
0.2
65
Shutdown threshold
160
°C
Recovery threshold
150
°C
VOLTAGE REFERENCE (FB PIN)
VFB
Feedback voltage
ILKG-FB
Input leakage current at FB pin
V
nA
THERMAL SHUTDOWN
TSD
(1)
Thermal shutdown
CURRENT LIMIT AND HICCUP
IHS-LIMIT
Peak inductor current limit
3.6
4.5
5
A
ILS-LIMIT
Valley inductor current limit
1.8
2.05
2.3
A
2
2.75
µA
SOFT START (SS/TRK PIN)
ISSC
Soft-start charge current
RSSD
Soft-start discharge resistance
1.17
UVLO, TSD, OCP, or EN = 0 V
16
kΩ
POWER GOOD (PGOOD PIN)
VPGOOD-HIGH
Power-good flag overvoltage tripping
threshold
% of FB voltage
VPGOOD-LOW
Power-good flag undervoltage tripping
threshold
% of FB voltage
VPGOOD-HYS
Power-good flag recovery hysteresis
% of FB voltage
PGOOD pin pull down resistance when
power bad
VEN = 3.3 V
RPGOOD
110%
80%
113%
88%
6%
69
150
VEN = 0 V
150
350
Ω
MOSFETS (2)
RDS-ON-HS
High-side MOSFET ON-resistance
IOUT = 1 A
VBIAS = VOUT = 3.3 V
210
mΩ
RDS-ON-LS
Low-side MOSFET ON-resistance
IOUT = 1 A
VBIAS = VOUT = 3.3 V
110
mΩ
(1)
(2)
Ensured by design. Not production tested.
Measured at package pins
6.6 Timing Requirements
PARAMETER
MIN
NOM
MAX
UNIT
CURRENT LIMIT AND HICCUP
NOC
Hiccup wait cycles when LS current limit tripped
32
Cycles
TOC
Hiccup retry delay time
5.5
ms
4.1
ms
TPGOOD-RISE Power-good flag rising transition deglitch delay
220
µs
TPGOOD-FALL Power-good flag falling transition deglitch delay
220
µs
SOFT START (SS/TRK PIN)
TSS
Internal soft-start time when SS pin open circuit
POWER GOOD (PGOOD PIN)
6
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6.7 Switching Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SW (SW PIN)
tON-MIN (1)
Minimum high side MOSFET ONtime
125
165
ns
tOFF-MIN (1)
Minimum high side MOSFET OFFtime
200
250
ns
500
590
kHz
OSCILLATOR (SW PINS AND SYNC PIN)
FOSC-DEFAULT
Oscillator default frequency
RT pin open circuit
410
Minimum adjustable frequency
FADJ
Maximum adjustable frequency
With 1% resistors at RT
pin
Frequency adjust accuracy
200
kHz
2200
kHz
10%
VSYNC-HIGH
Sync clock high level threshold
VSYNC-LOW
Sync clock low level threshold
DSYNC-MAX
Sync clock maximum duty cycle
90%
DSYNC-MIN
Sync clock minimum duty cycle
10%
TSYNC-MIN
Minimum sync clock ON-time and
OFF time
(1)
2
V
0.4
80
V
ns
Ensured by design. Not production tested.
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6.8 Typical Characteristics
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz, L = 10 µH, COUT = 150 µF, CFF = 47 pF. See Application
Performance Curves for Bill of Materials (BOM) for other VOUT and FS combinations.
60
50
40
30
10
0
0.001
0.01
0.1
VOUT = 3.3 V
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
40
20
10
0
0.001
1
Load Current (A)
50
30
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
20
60
0.01
FS = 500 kHz
VOUT = 5 V
90
80
80
70
70
60
50
Efficiency (%)
Efficiency (%)
90
60
50
40
VIN = 12V
30
VIN = 18V
30
20
VIN = 24V
20
10
VIN = 28V
10
VIN = 36V
0.1
40
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
0
0.001
1
Load Current (A)
VOUT = 5 V
0.01
VOUT = 5 V
90
80
80
70
70
60
50
40
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
0.01
0.1
Load Current (A)
VOUT = 12 V
FS = 500 kHz
1
Efficiency (%)
Efficiency (%)
90
0
0.001
60
50
40
30
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
20
10
0
0.001
0.01
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0.1
Load Current (A)
C005
VOUT = 24 V
1
C006
FS = 500 kHz
Figure 5. Efficiency
8
C004
Figure 4. Efficiency
100
10
1
FS = 1 MHz
Figure 3. Efficiency
100
20
0.1
Load Current (A)
C003
FS = 500 kHz
30
C002
Figure 2. Efficiency
100
0.01
1
FS = 200 kHz
Figure 1. Efficiency
100
0
0.001
0.1
Load Current (A)
C001
Figure 6. Efficiency
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Typical Characteristics (continued)
3.35
5.07
3.34
5.06
3.33
5.05
3.32
5.04
3.31
VIN = 12V
3.30
VIN = 18V
3.29
VOUT (V)
VOUT (V)
Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz, L = 10 µH, COUT = 150 µF, CFF = 47 pF. See Application
Performance Curves for Bill of Materials (BOM) for other VOUT and FS combinations.
VIN = 24V
5.03
5.02
5.01
VIN = 28V
3.28
3.27
0.001
5.00
VIN = 36V
0.01
0.1
VOUT = 3.3 V
4.99
0.001
1
Current (A)
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
0.01
0.1
1
Current (A)
C001
FS = 500 kHz
VOUT = 5 V
Figure 7. VOUT Regulation
C008
FS = 200 kHz
Figure 8. VOUT Regulation
5.06
5.05
5.05
5.04
5.03
VIN = 12V
5.01
VOUT (V)
VOUT (V)
5.03
VIN = 18V
VIN = 24V
4.99
VIN = 28V
4.97
VIN = 42V
VIN = 48V
4.95
0.001
0.01
0.1
VIN = 18V
VIN = 24V
4.99
VIN = 28V
4.98
VIN = 36V
4.97
0.001
1
Current (A)
VOUT = 5 V
5.01
5.00
VIN = 36V
VIN = 12V
5.02
0.01
0.1
1
Current (A)
C001
FS = 500 kHz
VOUT = 5 V
Figure 9. VOUT Regulation
C001
FS = 1 MHz
Figure 10. VOUT Regulation
12.15
24.60
12.10
24.50
VIN = 36V
12.00
VIN = 24V
VIN = 28V
VIN = 36V
11.95
11.90
VIN = 48V
24.40
VOUT (V)
VOUT (V)
12.05
VIN = 42V
VIN = 42V
VIN = 60V
24.30
24.20
24.10
VIN = 48V
24.00
VIN = 60V
11.85
0.001
0.01
0.1
Current (A)
VOUT = 12 V
23.90
0.001
1
0.01
FS = 500 kHz
VOUT = 24 V
Figure 11. VOUT Regulation
0.1
1
Current (A)
C001
C001
FS = 500 kHz
Figure 12. VOUT Regulation
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Typical Characteristics (continued)
3.5
5.2
3.3
5.0
3.1
4.8
VOUT (V)
VOUT (V)
Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz, L = 10 µH, COUT = 150 µF, CFF = 47 pF. See Application
Performance Curves for Bill of Materials (BOM) for other VOUT and FS combinations.
2.9
2.7
4.6
4.4
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
2.5
2.3
3.5
4.0
4.5
VOUT = 3.3 V
4.0
5.0
5.0
VIN (V)
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
4.2
5.2
5.6
5.8
6.0
6.2
VIN (V)
FS = 500 kHz
VOUT = 5 V
6.4
C002
FS = 200 kHz
Figure 13. Dropout Curve
Figure 14. Dropout Curve
5.2
5.2
5.0
5.0
4.8
4.8
VOUT (V)
VOUT (V)
5.4
C013
4.6
4.6
4.4
4.4
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
4.2
4.0
5.0
5.2
5.4
5.6
5.8
6.0
6.2
VIN (V)
VOUT = 5 V
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
4.2
4.0
6.4
5.0
5.2
5.4
5.6
5.8
6.0
6.2
VIN (V)
C003
FS = 500 kHz
VOUT = 5 V
Figure 15. Dropout Curve
6.4
C004
FS = 1 MHz
Figure 16. Dropout Curve
12.2
24.4
24.2
12.0
24.0
23.8
VOUT (V)
VOUT (V)
11.8
11.6
11.4
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
11.2
11.0
12.0
12.2
12.4
12.6
12.8
13.0
VIN (V)
VOUT = 12 V
FS = 500 kHz
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13.4
23.4
23.2
23.0
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
22.8
22.6
22.4
24.0
24.5
25.0
25.5
VIN (V)
C005
VOUT = 24 V
Figure 17. Dropout Curve
10
13.2
23.6
26.0
C006
FS = 500 kHz
Figure 18. Dropout Curve
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz, L = 10 µH, COUT = 150 µF, CFF = 47 pF. See Application
Performance Curves for Bill of Materials (BOM) for other VOUT and FS combinations.
1.E+06
1.E+05
Switching Frequency (Hz)
Switching Frequency (Hz)
1.0E+06
Load=0.01A
Load=0.1A
Load=0.5A
Load=1A
Load=0.1A
1.0E+05
Load=0.5A
Load=1A
Load=1.5A
Load=1.5A
Load=2A
Load=2A
1.0E+04
1.E+04
3.5
3.7
3.9
4.1
4.3
VIN (V)
VOUT = 3.3 V
VOUT = 5 V
Radiated Emmisions (dBµV/m)
EN 55022 Class A Limit
60
50
40
30
20
10
0
C005
Evaluation Board
70
EN 55022 Class B Limit
EN 55022 Class A Limit
60
50
40
30
20
10
0
0
200
400
600
800
Frequency (MHz)
1000
0
800
1000
C001
Figure 22. Radiated EMI Curve
100
Peak Emissions
90
Quasi Peak Limit
80
600
VOUT = 5 V
FS = 1 MHz
IOUT = 2 A
Measured on the LM46002QPWPEVM with L = 6.8 µH, COUT = 47
µF, CFF = 47 pF. No input filter used.
Peak Emissions
90
400
Frequency (MHz)
Figure 21. Radiated EMI Curve
100
200
C001
VOUT = 3.3 V
FS = 500 kHz
IOUT = 2 A
Measured on the LM46002QPWPEVM with default BOM. No input
filter used.
Average Limit
Conducted EMI (dBµV)
Conducted EMI (dBµV)
7.0
FS = 1 MHz
80
EN 55022 Class B Limit
6.5
Figure 20. Switching Frequency vs VIN in Dropout Operation
Evaluation Board
70
6.0
VIN (V)
FS = 500 kHz
80
5.5
C009
Figure 19. Switching Frequency vs VIN in Dropout Operation
Radiated EMI Emissions (dBµV/m)
5.0
4.5
70
60
50
40
30
20
10
Quasi Peak Limit
80
Average Limit
70
60
50
40
30
20
10
0
0
0.1
1
10
Frequency (MHz)
100
VOUT = 3.3 V
FS = 500 kHz
IOUT = 2 A
Measured on the LM46002QPWPEVM with default BOM. Input
filter: Lin = 1 µH Cd = 47 µF CIN4 = 68 µF
Figure 23. Conducted EMI Curve
0.1
1
10
Frequency (MHz)
C001
100
C001
VOUT = 5 V
FS = 1 MHz
IOUT = 2 A
Measured on the LM46002QPWPEVM with L = 6.8 µH, COUT = 47
µF, CFF = 47 pF. Input filter Lin = 1 µH Cd = 47 µF CIN4 = 68 µF
Figure 24. Conducted EMI Curve
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz, L = 10 µH, COUT = 150 µF, CFF = 47 pF. See Application
Performance Curves for Bill of Materials (BOM) for other VOUT and FS combinations.
350
3
Shutdown Current ( A)
300
Rdson (mohm)
250
200
150
100
HS
50
2.5
2
1.5
1
VIN = 24V
LS
0
0.5
±50
0
50
100
Temperature (deg C)
150
50
100
150
Temperature (deg C)
Figure 25. High-Side and Low-side On-Resistance vs
Junction Temperature
C001
Figure 26. Shutdown Current vs Junction Temperature
2.5
1.1
2
EN Leakage Current ( A)
Enable Thresholds (V)
0
±50
C001
EN-VOUT Rising TH
EN-VOUT Falling TH
EN-VCC Rising TH
EN-VCC Falling TH
1.5
1
0.5
1
0.9
0.8
0.7
0.6
VEN = 3.3V
0
0.5
±50
0
50
100
Temperature (deg C)
150
0
±50
50
100
150
Temperature (deg C)
C001
Figure 27. Enable Threshold vs Junction Temperature
C001
Figure 28. Enable Leakage Current vs
Junction Temperature
120.00%
1.030
110.00%
1.025
100.00%
VIN=8
VIN=12
90.00%
80.00%
1.015
VIN=24
1.010
1.005
70.00%
OVP Trip Level
OVP Recover Level
UVP Recover Level
UVP Trip Level
60.00%
50.00%
±50
0
50
100
Temperature (deg C)
1.000
0.995
0.990
150
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10
±40
60
Junction Temperature (ƒC)
C001
Figure 29. PGOOD Threshold vs Junction Temperature
12
VIN=5
1.020
VFB (V)
PGOOD Threshold / VOUT (%)
VIN=3.5
110
C009
Figure 30. Feedback Voltage vs Junction Temperature
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz, L = 10 µH, COUT = 150 µF, CFF = 47 pF. See Application
Performance Curves for Bill of Materials (BOM) for other VOUT and FS combinations.
5.0
70
4.5
60
4.0
50
3.0
IQ (µA)
Current (A)
3.5
2.5
2.0
1.5
40
30
20
1.0
IL Peak Limit
0.5
IL Valley Limit
10
0.0
0
0
10
20
30
40
50
VIN (V)
60
0
10
VOUT = 3.3 V
FS = 500 kHz
Figure 31. Peak and Valley Current Limits vs VIN
20
30
40
50
VIN (V)
C002
VOUT = 3.3 V
60
C009
FS = 500 kHz
IOUT = 0 A
EN pin is connected to external 5 V rail
Figure 32. Operation IQ vs VIN with BIAS Connected to VOUT
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7 Detailed Description
7.1 Overview
The LM46002-Q1 regulator is an easy-to-use, synchronous, step-down DC-DC converter that operates from 3.5V to 60-V supply voltage. It is capable of delivering up to 2 A of DC load current with exceptional efficiency and
thermal performance in a very small solution size. An extended family is available in 0.5-A and 1-A load options
in pin-to-pin compatible packages.
The LM46002-Q1 employs fixed frequency peak current mode control with discontinuous conduction mode
(DCM) and pulse frequency modulation (PFM) mode at light load to achieve high efficiency across the load
range. The device is internally compensated, which reduces design time, and requires fewer external
components. The switching frequency is programmable from 200 kHz to 2.2 MHz by an external resistor, RT. It
defaults at 500 kHz without RT. The LM46002-Q1 is also capable of synchronization to an external clock within
the 200-kHz to 2.2-MHz frequency range. The wide switching frequency range allows the device to be optimized
to fit small board space at higher frequency, or high efficient power conversion at lower frequency.
Optional features are included for more comprehensive system requirements, including power-good (PGOOD)
flag, precision enable, synchronization to external clock, extendable soft-start time, and output voltage tracking.
These features provide a flexible and easy-to-use platform for a wide range of applications. Protection features
include overtemperature shutdown, VCC undervoltage lockout (UVLO), cycle-by-cycle current limit, and shortcircuit protection with hiccup mode.
The family requires few external components, and the pin arrangement was designed for simple, optimum PCB
layout. The LM46002-Q1 device is available in the 16-lead HTSSOP (PWP) package (6.6 mm × 5.1 mm× 1.2
mm) with 0.65-mm lead pitch.
7.2 Functional Block Diagram
ENABLE
VCC
Enable
Internal
SS
ISSC
BIAS
VCC
LDO
VIN
Precision
Enable
SS/TRK
CBOOT
HS I Sense
+
EA
REF
RC
+
±
+±
TSD
UVLO
CC
PGOOD
AGND
OV/UV
Detector
FB
SW
PWM CONTROL LOGIC
PFM
Detector
PGood
Slope
Comp
Freq
Foldback
Zero
Cross
HICCUP
Detector
Oscillator
LS I Sense
FB
PGood
SYNC
14
PGND
RT
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7.3 Feature Description
7.3.1 Fixed Frequency Peak Current Mode Controlled Step-Down Regulator
The following operating description of the LM46002-Q1 refer to the Functional Block Diagram and to the
waveforms in Figure 33. The LM46002-Q1 is a step-down buck regulator with both high-side (HS) switch and
low-side (LS) switch (synchronous rectifier) integrated. The LM46002-Q1 supplies a regulated output voltage by
turning on the HS and LS NMOS switches with controlled ON-time. During the HS switch ON-time, the SW pin
voltage VSW swings up to approximately VIN, and the inductor current IL increases with a linear slope (VIN – VOUT)
/ L. When the HS switch is turned off by the control logic, the LS switch is turned on after a anti-shoot-through
dead time. Inductor current discharges through the LS switch with a slope of –VOUT / L. The control parameter of
buck converters are defined as duty cycle D = tON / TSW, where tON is the HS switch ON-time and TSW is the
switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In
an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage: D = VOUT / VIN.
VSW
D = tON / TSW
SW Voltage
VIN
tOFF
tON
0
t
-VD1
Inductor Current
iL
TSW
ILPK
IOUT
0
ûiL
t
Figure 33. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The LM46002-Q1 synchronous buck converter employs peak current mode control topology. A voltage feedback
loop is used to get accurate DC voltage regulation by adjusting the peak current command based on voltage
offset. The peak inductor current is sensed from the HS switch and compared to the peak current to control the
ON-time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer external
components, makes it easy to design, and provides stable operation with almost any combination of output
capacitors. The regulator operates with fixed switching frequency in CCM and DCM . At very light load, the
LM46002-Q1 operates in PFM to maintain high efficiency, and the switching frequency decreases with reduced
load current.
7.3.2 Light Load Operation
DCM operation is employed in the LM46002-Q1 when the inductor current valley reaches zero. The LM46002-Q1
is in DCM when load current is less than half of the peak-to-peak inductor current ripple in CCM. In DCM, the LS
switch is turned off when the inductor current reaches zero. Switching loss is reduced by turning off the LS FET
at zero current, and the conduction loss is lowered by not allowing negative current conduction. Power
conversion efficiency is higher in DCM than CCM under the same conditions.
In DCM, the HS switch ON-time reduces with lower load current. When either the minimum HS switch ON-time
(tON-MIN) or the minimum peak inductor current (IPEAK-MIN) is reached, the switching frequency decreases to
maintain regulation. At this point, the LM46002-Q1 operates in PFM. In PFM, switching frequency is decreased
by the control loop when load current reduces to maintain output voltage regulation. Switching loss is further
reduced in PFM operation due to less frequent switching actions. Figure 34 shows an example of switching
frequency decreases with decreased load current.
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Feature Description (continued)
Switching Frequency (Hz)
1.E+06
1.E+05
1.E+04
VIN = 12V
VIN = 24V
1.E+03
0.001
VIN = 36V
0.010
0.100
1.000
LOAD CURRENT (A)
C007
Figure 34. Switching Frequency Decreases with Lower Load Current in PFM Operation
VOUT = 5 V FS = 1 MHz
In PFM operation, a small positive DC offset is required at the output voltage to activate the PFM detector. The
lower the frequency in PFM, the more DC offset is needed at VOUT. See the Typical Characteristics for typical DC
offset at very light load. If the DC offset on VOUT is not acceptable for a given application, TI recommends a static
load at output to reduce or eliminate the offset. Lowering values of the feedback divider RFBT and RFBB can also
serve as a static load. In conditions with low VIN and/or high frequency, the LM46002-Q1 may not enter PFM
mode if the output voltage cannot be charged up to provide the trigger to activate the PFM detector. Once the
LM46002-Q1 is operating in PFM mode at higher VIN, it remains in PFM operation when VIN is reduced.
7.3.3 Adjustable Output Voltage
The voltage regulation loop in the LM46002-Q1 regulates output voltage by maintaining the voltage on FB pin
(VFB) to be the same as the internal REF voltage (VREF). A resistor divider pair is needed to program the ratio
from output voltage VOUT to VFB. The resistor divider is connected from the VOUT of the LM46002-Q1 to ground
with the mid-point connecting to the FB pin.
VOUT
RFBT
FB
RFBB
Figure 35. Output Voltage Setting
The voltage reference system produces a precise voltage reference overtemperature. The internal REF voltage
is 1.011 V, typically. To program the output voltage of the LM46002-Q1 to be a certain value VOUT, RFBB can be
calculated with a selected RFBT by
VFB
RFBB
RFBT
VOUT VFB
(1)
The choice of the RFBT depends on the application. RFBT in the range from 10 kΩ to 100 kΩ is recommended for
most applications. A lower RFBT value can be used if static loading is desired to reduce VOUT offset in PFM
operation. Lower RFBT will reduce efficiency at very light load. Less static current goes through a larger RFBT and
might be more desirable when light load efficiency is critical. But RFBT larger than 1 MΩ is not recommended
because it makes the feedback path more susceptible to noise. Larger RFBT value requires more carefully
designed feedback path on the PCB. The tolerance and temperature variation of the resistor dividers affect the
output voltage regulation. It is recommended to use divider resistors with 1% tolerance or better and temperature
coefficient of 100 ppm or lower.
16
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Feature Description (continued)
If the resistor divider is not connected properly, output voltage cannot be regulated since the feedback loop is
broken. If the FB pin is shorted to ground, the output voltage is driven close to VIN, since the regulator detects
very low voltage on the FB pin and tries to regulate it up. The load connected to the output could be damaged
under such a condition. Do not short FB pin to ground when the LM46002-Q1 is enabled. It is important to route
the feedback trace away from the noisy area of the PCB. For more layout recommendations, refer to the Layout
section.
7.3.4 Enable (ENABLE)
Voltage on the ENABLE pin (VEN) controls the ON or OFF functionality of the LM46002-Q1. Applying a voltage
less than 0.4 V to the ENABLE input shuts down the operation of the LM46002-Q1. In shutdown mode the
quiescent current drops to typically 2.3 µA at VIN = 24 V.
The internal LDO output voltage VCC is turned on when VEN is higher than 1.2 V. The switching action and output
regulation are enabled when VEN is greater than 2.1 V (typical). The LM46002-Q1 supplies regulated output
voltage when enabled and output current up to 2 A.
The ENABLE pin is an input and cannot be open circuit or floating. The simplest way to enable the operation of
the LM46002-Q1 is to connect the ENABLE pin to VIN pins directly. This allows self-start-up when VIN is within
the operation range.
Many applications will benefit from the employment of an enable divider RENT and RENB in Figure 36 to establish
a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power
as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such
as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection.
VIN
RENT
ENABLE
RENB
Figure 36. System UVLO By Enable Dividers
7.3.5 VCC, UVLO and BIAS
The LM46002-Q1 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The
nominal voltage for VCC is 3.2 V. The VCC pin is the output of the LDO and must be properly bypassed. Place a
high-quality ceramic capacitor with 2.2-µF to 10-µF capacitance and 6.3-V or higher rated voltage as close as
possible to VCC, grounded to the exposed PAD and ground pins. The VCC output pin must not be loaded, left
floating, or shorted to ground during operation. Shorting VCC to ground during operation may cause damage to
the LM46002-Q1.
Undervoltage lockout (UVLO) prevents the LM46002-Q1 from operating until the VCC voltage exceeds 3.15 V
(typical). The VCC UVLO threshold has 575 mV of hysteresis (typically) to prevent undesired shutting down due
to temporary VIN droops.
The internal LDO has two inputs: primary from VIN and secondary from BIAS input. The BIAS input powers the
LDO when VBIAS is higher than the change-over threshold. Power loss of an LDO is calculated by ILDO * (VIN-LDO –
VOUT-LDO). The higher the difference between the input and output voltages of the LDO, the more power loss
occur to supply the same output current. The BIAS input is designed to reduce the difference of the input and
output voltages of the LDO to reduce power loss and improve LM46002-Q1 efficiency, especially at light load. TI
recommends tying the BIAS pin to VOUT when VOUT ≥ 3.3V. Ground the BIAS pin in applications with VOUT less
than 3.3 V. BIAS input can also come from an external voltage source, if available, to reduce power loss. When
used, a TI recommends a 1-µF to 10-µF high-quality ceramic capacitor to bypass the BIAS pin to ground.
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Feature Description (continued)
7.3.6 Soft-Start and Voltage Tracking (SS/TRK)
The LM46002-Q1 has a flexible and easy-to-use start-up rate control pin: SS/TRK. Soft-start feature is to prevent
inrush current impacting the LM46002-Q1 and its supply when power is first applied. Soft-start is achieved by
slowly ramping up the target regulation voltage when the device is first enabled or powered up.
The simplest way to use the device is to leave the SS/TRK pin open circuit or floating. The LM46002-Q1 employs
the internal soft-start control ramp and start-up to the regulated output voltage in 4.1 ms typically.
In applications with a large amount of output capacitors, higher VOUT, or other special requirements, the soft-start
time can be extended by connecting an external capacitor CSS from SS/TRK pin to AGND. Extended soft-start
time further reduces the supply current needed to charge up output capacitors and supply any output loading. An
internal current source (ISSC = 2.2 µA) charges CSS and generates a ramp from 0 V to VFB to control the ramp-up
rate of the output voltage. For a desired soft-start time tSS, the capacitance for CSS can be found by
CSS ISSC u t SS
(2)
The soft start capacitor CSS is discharged by an internal FET when VOUT is shutdown by hiccup protection or
ENABLE = logic low. When a large CSS is applied and ENABLE is toggled low only for a short period of time, the
CSS may not be fully discharged, and the next soft-start ramp will follow internal soft-start ramp before reaching
the leftover voltage on CSS, then follow the ramp programmed by CSS. If this is not acceptable for a certain
application, a R-C low-pass filter can be added to ENABLE to slow down the shutting down of VCC, which allows
more time to discharge CSS.
The LM46002-Q1 is capable of start-up into prebiased output conditions. When the inductor current reaches
zero, the LS switch is turned off to avoid negative current conduction. This operation mode is also called diode
emulation mode. It is built in by the DCM operation in light loads. With a prebiased output voltage, the LM46002Q1 waits until the soft-start ramp allows regulation above the prebiased voltage and then follows the soft-start
ramp to the regulation level.
When an external voltage ramp is applied to the SS/TRK pin, the LM46002-Q1 FB voltage follows the ramp if the
ramp magnitude is lower than the internal soft-start ramp. A resistor divider pair can be used on the external
control ramp to the SS/TRK pin to program the tracking rate of the output voltage. The final voltage detected by
the SS/TRK pin must not fall below 1.2 V to avoid abnormal operation.
EXT RAMP
RTRT
SS/TRK
RTRB
Figure 37. Soft Start Tracking External Ramp
VOUT tracked to an external voltage ramp has the option of ramping up slower or faster than the internal voltage
ramp. VFB always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin.
Figure 38 shows the case when VOUT ramps slower than the internal ramp, while Figure 39 shows when VOUT
ramps faster than the internal ramp. Faster start up time may result in inductor current tripping current protection
during start-up. Use with special care.
Enable
Internal SS Ramp
Ext Tracking Signal to SS pin
VOUT
Figure 38. Tracking With Longer Start-up Time Than Tthe Internal Ramp
18
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Feature Description (continued)
Enable
Internal SS Ramp
Ext Tracking Signal to SS pin
VOUT
Figure 39. Tracking With Shorter Start-up Time Than the Internal Ramp
7.3.7 Switching Frequency (RT) and Synchronization (SYNC)
The switching frequency of the LM46002-Q1 can be programmed by the impedance RT from the RT pin to
ground. The frequency is inversely proportional to the RT resistance. The RT pin can be left floating, and the
LM46002-Q1 will operate at 500-kHz default switching frequency. The RT pin is not designed to be shorted to
ground.
For a desired frequency, typical RT resistance can be found by Equation 3.
RT(kΩ) = 40200 / Freq (kHz) – 0.6
(3)
Figure 40 shows RT resistance vs switching frequency FS curve.
250
RT Resistance (kŸ)
200
150
100
50
0
0
500
1000
1500
2000
Switching Frequency (kHz)
2500
C008
Figure 40. RT Resistance vs Switching Frequency
Table 1 provides typical RT values for a given FS.
Table 1. Typical Frequency Setting RT Resistance
FS (kHz)
RT (kΩ)
200
200
350
115
500
80.6
750
53.6
1000
39.2
1500
26.1
2000
19.6
2200
17.8
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Feature Description (continued)
The LM46002-Q1 switching action can also be synchronized to an external clock from 200 kHz to 2.2 MHz.
Connect an external clock to the SYNC pin, with proper high speed termination, to avoid ringing. Ground the
SYNC pin if not used.
SYNC
EXT CLOCK
RTERM
Figure 41. Frequency Synchronization
The recommendations for the external clock include high level no lower than 2 V, low level no higher than 0.4 V,
duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns. When the
external clock fails at logic high or low, the LM46002-Q1 switches at the frequency programmed by the RT
resistor after a time-out period. TI recommends connecting a resistor RT to the RT pin so that the internal
oscillator frequency is the same as the target clock frequency when the LM46002-Q1 is synchronized to an
external clock. This allows the regulator to continue operating at approximately the same switching frequency if
the external clock fails.
The choice of switching frequency is usually a compromise between conversion efficiency and the size of the
circuit. Lower switching frequency implies reduced switching losses (including gate charge losses, switch
transition losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency allows
use of smaller LC output filters and hence a more compact design. Lower inductance also helps transient
response (higher large signal slew rate of inductor current), and reduces the DCR loss. The optimal switching
frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis.
It is related to the input voltage, output voltage, most frequent load current level(s), external component choices,
and circuit size requirement. The choice of switching frequency may also be limited if an operating condition
triggers TON-MIN or TOFF-MIN.
7.3.8 Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Dropout Conditions
Minimum ON-time, TON-MIN, is the smallest duration of time that the HS switch can be on. tON-MIN is typically 125
ns in the LM46002-Q1. Minimum OFF-time, tOFF-MIN, is the smallest duration that the HS switch can be off. tOFFMIN is typically 200 ns in the LM46002-Q1.
In CCM operation, tON-MIN and tOFF-MIN limits the voltage conversion range given a selected switching frequency.
The minimum duty cycle allowed is
DMIN = tON-MIN × FS
(4)
And the maximum duty cycle allowed is
DMAX = 1 – tOFF-MIN × FS
(5)
Given fixed tON-MIN and tOFF-MIN, the higher the switching frequency the narrower the range of the allowed duty
cycle. In the LM46002-Q1, frequency foldback scheme is employed to extend the maximum duty cycle when tOFFMIN is reached. The switching frequency decreases once longer duty cycle is needed under low VIN conditions.
The switching frequency can be decreased to approximately 1/10 of the programmed frequency by RT or the
synchronization clock. Such a wide range of frequency foldback allows the LM46002-Q1 output voltage to stay in
regulation with a much lower supply voltage VIN. This leads to a lower effective dropout voltage. See Typical
Characteristics for more details.
Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution
size and efficiency. The maximum operational supply voltage can be found by:
VIN-MAX = VOUT / (FS × tON-MIN)
(6)
At lower supply voltage, the switching frequency decreases once tOFF-MIN is tripped. The minimum VIN without
frequency foldback can be approximated by:
VIN-MIN = VOUT / (1 – FS × TOFF-MIN)
(7)
Taking considerations of power losses in the system with heavy load operation, VIN-MIN is higher than the result
calculated in Equation 7 . With frequency foldback, VIN-MIN is lowered by decreased FS. Figure 42 gives an
example of how FS decreases with decreasing supply voltage VIN at dropout operation.
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Feature Description (continued)
Switching Frequency (Hz)
1.0E+06
Load=0.1A
1.0E+05
Load=0.5A
Load=1A
Load=1.5A
Load=2A
1.0E+04
5.0
5.5
6.0
6.5
VIN (V)
7.0
C005
Figure 42. Switching Frequency Decreases in Dropout Operation
VOUT = 5 V FS = 1 MHz
7.3.9 Internal Compensation and CFF
The LM46002-Q1 is internally compensated with RC = 400 kΩ and CC = 50 pF as shown in Functional Block
Diagram. The internal compensation is designed such that the loop response is stable over the entire operating
frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can
be low with all ceramic capacitors. TI recommends an external feed-forward cap CFF be placed in parallel with
the top resistor divider RFBT for optimum transient performance as shown in Figure 43.
VOUT
RFBT
CFF
FB
RFBB
Figure 43. Feed-Forward Capacitor for Loop Compensation
The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the cross over frequency of
the control loop to boost phase margin. The zero frequency can be found by
fZ-CFF = 1 / (2π × RFBT × CFF)
(8)
An additional pole is also introduced with CFF at the frequency of
fP-CFF = 1 / (2π × CFF × (RFBT // RFBB))
(9)
Select the CFF so that the bandwidth of the control loop without the CFF is centered between fZ-CFF and fP-CFF. The
zero fZ-CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF helps
maintaining proper gain margin at frequency beyond the crossover.
Designs with different combinations of output capacitors need different CFF. Different types of capacitors have
different equivalent series resistance (ESR). Ceramic capacitors have the smallest ESR and need the most CFF.
Electrolytic capacitors have much larger ESR than ceramic, and the ESR zero frequency location would be low
enough to boost the phase up around the crossover frequency. Designs that use mostly electrolytic capacitors at
the output may not need any CFF. The location of this ESR zero frequency can be calculated withEquation 10:
fZ-ESR = 1 / (2π × ESR × COUT)
(10)
The CFF creates a time constant with RFBT that couples in the attenuated output voltage ripple to the FB node. If
the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. It could also couple
too much transient voltage deviation and falsely trip PGOOD thresholds. Therefore, CFF should be calculated
based on output capacitors used in the system. At cold temperatures, the value of CFF might change based on
the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB
node. To avoid this, more capacitance can be added to the output or the value of CFF can be reduced. See
Detailed Design Procedure for the calculation of CFF.
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Feature Description (continued)
7.3.10 Bootstrap Voltage (BOOT)
The driver of the HS switch requires a bias voltage higher than VIN when the HS switch is ON. The capacitor
connected between CBOOT and SW pins works as a charge pump to boost voltage on the CBOOT pin to (VSW +
VCC). The boot diode is integrated on the LM46002-Q1 die to minimize the bill of material (BOM). A synchronous
switch is also integrated in parallel with the boot diode to reduce voltage drop on CBOOT. TI recommends a
high-quality ceramic 0.47-µF, 6.3-V or higher capacitor for CBOOT.
7.3.11 Power Good (PGOOD)
The LM46002-Q1 has a built-in power-good flag shown on PGOOD pin to indicate whether the output voltage is
within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault
protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate DC voltage.
Voltage seen by the PGOOD pin must never exceed 12 V. A resistor divider pair can be used to divide the
voltage down from a higher potential. A typical range of pullup resistor value is 10 kΩ to 100 kΩ.
When the FB voltage is within the power-good band, +4% above and –7% below the internal reference VREF
typically, the PGOOD switch is turned off, and the PGOOD voltage is pulled up to the voltage level defined by
the pullup resistor or divider. When the FB voltage is outside of the tolerance band, +10 % above or –13 %
below VREF typically, the PGOOD switchis turned on, and the PGOOD pin voltage is pulled low to indicate power
bad. Both rising and falling edges of the power-good flag have a built-in 220-µs (typical) deglitch delay.
7.3.12 Overcurrent and Short-Circuit Protection
The LM46002-Q1 is protected from overcurrent conditions by cycle-by-cycle current limiting on both peak and
valley of the inductor current. Hiccup modeis activated if a fault condition persists to prevent overheating.
High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The
HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is
compared to the output of the error amplifier (EA) minus slope compensation every switching cycle. See the
Functional Block Diagram for more details. The peak current of the HS switch is limited by the maximum EA
output voltage minus the slope compensation at every switching cycle. The slope compensation magnitude at the
peak current is proportional to the duty cycle.
When the LS switch is turned on, the current going through it is also sensed and monitored. The LS switch is be
turned OFF at the end of a switching cycle if its current is above the LS current limit ILS-LIMIT. The LS switch is
kept ON so that inductor current keeps ramping down, until the inductor current ramps below ILS-LIMIT. The LS
switch is then turned OFF, and the HS switch is turned on after a dead time. If the current of the LS switch is
higher than the LS current limit for 32 consecutive cycles and the power-good flag is low, hiccup-currentprotection mode is activated. In hiccup mode, the regulator is shut down and kept off for 5.5 ms typically before
the LM46002-Q1 tries to start again. If overcurrent or short-circuit fault condition still exist, hiccup repeats until
the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions,
prevents overheating and potential damage to the device.
Hiccup is only activated when power-good flag is low. Under non-severe overcurrent conditions when VOUT has
not fallen outside of the PGOOD tolerance band, the LM46002-Q1 reduces the switching frequency and keeps
the inductor current valley clamped at the LS current limit level. This operation mode allows slight overcurrent
operation during load transients without tripping hiccup. If the power-good flag becomes low, hiccup operation
starts after LS current limit is tripped 32 consecutive cycles.
7.3.13 Thermal Shutdown
Thermal shutdown is a built-in self protection to limit junction temperature and prevent damages due to over
heating. Thermal shutdown turns off the device when the junction temperature exceeds 160°C typically to
prevent further power dissipation and temperature rise. Junction temperature will reduce after thermal shutdown.
The LM46002-Q1 attempts to restart when the junction temperature drops to 150°C.
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the LM46002-Q1. When VEN is below 0.4 V, the device is
in shutdown mode. Both the internal LDO and the switching regulator are off. In shutdown mode the quiescent
current drops to 2.3 µA typically with VIN = 24 V. The LM46002-Q1 also employs UVLO protection. If VCC voltage
is below the UVLO level, the output of the regulator is turned off.
7.4.2 Stand-by Mode
The internal LDO has a lower enable threshold than the regulator. When VEN is above 1.2 V and below the
precision-enable falling threshold (1.8 V typically), the internal LDO regulates the VCC voltage at 3.2 V. The
precision-enable circuitry is turned on once VCC is above the UVLO threshold. The switching action and voltage
regulation are not enabled unless VEN rises above the precision enable threshold (2.1 V typically).
7.4.3 Active Mode
The LM46002-Q1 is in active mode when VEN is above the precision enable threshold and VCC is above its UVLO
level. The simplest way to enable the LM46002-Q1 is to connect the EN pin to VIN. This allows self start-up when
the input voltage is in the operation range: 3.5 V to 60 V. See Enable (ENABLE) and VCC, UVLO and BIAS for
details on setting these operating levels.
In active mode, depending on the load current, the LM46002-Q1 is in one of four modes:
1. CCM with fixed switching frequency when load current is above half of the peak-to-peak inductor current
ripple;
2. DCM with fixed switching frequency when load current is lower than half of the peak-to-peak inductor current
ripple in CCM operation;
3. PFM when switching frequency is decreased at very light load;
4. Foldback mode when switching frequency is decreased to maintain output regulation at lower supply voltage
VIN.
7.4.4 CCM Mode
Continuous conduction mode (CCM) operation is employed in the LM46002-Q1 when the load current is higher
than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed unless the
minimum HS switch ON-time (tON-MIN), the minimum HS switch OFF-time (tON-MAX) or LS current limit is exceeded.
Output voltage ripple is at a minimum in this mode and the maximum output current of 2 A can be supplied by
the LM46002-Q1.
7.4.5 Light Load Operation
When the load current is lower than half of the peak-to-peak inductor current in CCM, the LM46002-Q1 operate
in discontinuous conduction mode (DCM), also known as diode emulation mode (DEM). In DCM operation, the
LS FET is turned off when the inductor current drops to 0 A to improve efficiency. Both switching losses and
conduction losses are reduced in DCM, comparing to forced PWM operation at light load.
At even lighter current loads, PFM is activated to maintain high efficiency operation. When the HS switch ONtime reduces to tON-MIN or peak inductor current reduces to its minimum IPEAK-MIN, the switching frequency reduces
to maintain proper regulation. Efficiency is greatly improved by reducing switching and gate drive losses.
7.4.6 Self-Bias Mode
For highest efficiency of operation, it is recommended that the BIAS pin be connected directly to VOUT when 3.3
V ≤ VOUT ≤ 28 V. In this self-bias mode of operation, the difference between the input and output voltages of the
internal LDO are reduced, and therefore the total efficiency is improved. These efficiency gains are more evident
during light load operation. During this mode of operation, the LM46002-Q1 operates with a minimum quiescent
current of 27 µA (typical). See VCC, UVLO and BIAS for more details.
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM46002-Q1 is a step-down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 2 A. The following design procedure can be used to select
components for the LM46002-Q1. Alternately, the WEBENCH® software may be used to generate complete
designs. When generating a design, the WEBENCH® software utilizes iterative design procedure and accesses
comprehensive databases of components; see Custom Design With WEBENCH® Tools for more details.
This section presents a simplified discussion of the design process.
8.2 Typical Applications
The LM46002-Q1 only requires a few external components to convert from a wide range of supply voltage to
output voltage. Figure 44 shows a basic schematic when BIAS is connected to VOUT . This is recommended for
VOUT ≥ 3.3 V. For VOUT < 3.3 V, connect BIAS to ground, as shown in Figure 45.
L
VIN
VIN
CIN
VOUT
SW
LM46002-Q1
ENABLE
CBOOT
AGND
VOUT
SW
LM46002-Q1
CBOOT
COUT
CBOOT
ENABLE
CBIAS
SS/TRK
SYNC
VIN
CIN
CBOOT
BIAS
PGOOD
RT
COUT
L
VIN
CFF
PGOOD
RFBT
RT
FB
VCC
CVCC
RFBB
PGND
Figure 44. LM46002-Q1 Basic Schematic for
VOUT ≥ 3.3 V, Tie BIAS to VOUT
BIAS
CFF
SS/TRK
SYNC
AGND
RFBT
FB
VCC
CVCC
RFBB
PGND
Figure 45. LM46002-Q1 Basic Schematic for
VOUT < 3.3 V, t-Tie BIAS to Ground
The LM46002-Q1 also integrates a full list of optional features to aid system design requirements, such as
precision enable, VCC UVLO, programmable soft-start, output voltage tracking, programmable switching
frequency, clock synchronization and power-good indication. Each application can select the features for a more
comprehensive design. A schematic with all features utilized is shown in Figure 46.
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Typical Applications (continued)
L
VIN
RENT
VOUT
SW
VIN
COUT
LM46002-Q1
CIN
CBOOT
FB
ENABLE
RENB
CFF
RFBT
CBOOT
VCC
RFBB
CVCC
SS/TRK
CSS
RT
BIAS
RT
CBIAS
PGOOD
SYNC
RPG
RSYNC
AGND
Tie BIAS to PGND
when VOUT < 3.3V
PGND
Figure 46. LM46002-Q1 Schematic with All Features
The external components must fulfill the needs of the application, but also the stability criteria of the device
control loop. The LM46002-Q1 is optimized to work within a range of external components. Inductance and
capacitance of the LC output filter must be considered in conjunction, creating a double pole, responsible for the
corner frequency of the converter. Table 2 can be used to simplify the output filter component selection.
Table 2. L, COUT, and CFF Typical Values
FS (kHz)
L (µH)
(1)
COUT (µF)
(2)
CFF (pF)
(3) (4)
RT (kΩ)
RFBB (kΩ)
(3) (4)
VOUT = 1 V
200
8.2
560
none
200
100
500
3.3
470
none
80.6 or open
100
1000
1.8
220
none
39.2
100
2200
0.68
150
none
17.8
100
200
27
250
56
200
432
500
10
150
47
80.6 or open
432
1000
4.7
100
33
39.2
432
2200
2.2
47
22
17.8
432
200
33
200
68
200
249
500
15
100
47
80.6 or open
249
1000
6.8
47
47
39.2
249
2200
3.3
33
33
17.8
249
200
56
68
200
90.9
500
22
47
68
80.6 or open
90.9
1000
10
33
47
39.2
90.9
VOUT = 3.3 V
VOUT = 5 V
VOUT = 12 V
see note
(5)
VOUT = 24 V
(1)
(2)
(3)
(4)
(5)
Inductor values are calculated based on typical VIN = 24 V.
All the COUT values are after derating. Add more when using ceramics.
RFBT = 0 Ω for VOUT = 1 V. RFBT = 1 MΩ for all other VOUT settings.
For designs with RFBT other than 1 MΩ, adjust CFF such that CFF × RFBT) is unchanged and adjust RFBB such that RFBT / RFBB) is
unchanged.
High ESR COUT gives enough phase boost and CFF not needed.
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Typical Applications (continued)
Table 2. L, COUT, and CFF Typical Values (continued)
FS (kHz)
200
L (µH)
(1)
COUT (µF)
180
(2)
68
(3) (4)
RT (kΩ)
see note
(5)
200
43.2
80.6 or open
43.2
39.2
43.2
CFF (pF)
500
47
47
see note
(5)
1000
22
33
see note
(5)
RFBB (kΩ)
(3) (4)
8.2.1 Design Requirements
A detailed design procedure is described based on a design example. For this design example, use the
parameters listed in Table 3 as the input parameters.
Table 3. Design Example Parameters
DESIGN PARAMETER
VALUE
Input voltage VIN
24 V typical, range from 3.8 V to 60 V
Output voltage VOUT
3.3 V
Input ripple voltage
400 mV
Output ripple voltage
30 mV
Output current rating
2A
Operating frequency
500 kHz
Soft-start time
10 ms
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM46002-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Setpoint
The output voltage of the LM46002-Q1 device is externally adjustable using a resistor divider network. The
divider network is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Equation 11 is
used to determine the output voltage of the converter:
VFB
RFBB
RFBT
VOUT VFB
(11)
Choose the value of the RFBT to be 1 MΩ to minimize quiescent current to improve light load efficiency in this
application. With the desired output voltage set to be 3.3 V and the VFB = 1.011 V, the RFBB value can then be
calculated using Equation 11. The formula yields a value of 434.78 kΩ. Choose the closest available value of 432
kΩ for the RFBB. See Adjustable Output Voltage for more details.
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8.2.2.3 Switching Frequency
The default switching frequency of the LM46002-Q1 device is set at 500 kHz when RT pin is open circuit. The
switching frequency is selected to be 500 kHz in this application for one less passive components. If other
frequency is desired, use Equation 12 to calculate the required value for RT.
RT(kΩ) = 40200 / Freq (kHz) – 0.6
(12)
For 500 kHz, the calculated RT is 79.8 kΩ and standard value 80.6 kΩ can also be used to set the switching
frequency at 500 kHz.
8.2.2.4 Input Capacitors
The LM46002-Q1 device requires high-frequency input decoupling capacitor(s) and a bulk input capacitor,
depending on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7
µF to 10 µF. Ti recommends a high-quality ceramic type X5R or X7R with sufficiency voltage rating. The voltage
rating must be greater than the maximum input voltage. To compensate the derating of ceramic capacitors, a
voltage rating of twice the maximum input voltage is recommended. Additionally, some bulk capacitance can be
required, especially if the LM46002-Q1 circuit is not located within approximately 5 cm from the input voltage
source. This capacitor is used to provide damping to the voltage spiking due to the lead inductance of the cable
or trace. The value for this capacitor is not critical but must be rated to handle the maximum input voltage
including ripple.
For this design, a 10 µF, X7R dielectric capacitor rated for 100 V is used for the input decoupling capacitor. The
ESR is approximately 3 mΩ, and the current-rating is 3 A. Include a capacitor with a value of 0.1 µF for highfrequency filtering and place it as close as possible to the device pins.
NOTE
DC bias effect: High capacitance ceramic capacitors have a DC bias effect, which will
have a strong influence on the final effective capacitance. Therefore, the right capacitor
value must be chosen carefully. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.
8.2.2.5 Inductor Selection
The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is
based on the desired peak-to-peak ripple current, ΔiL, that flows in the inductor along with the DC load current.
As with switching frequency, the selection of the inductor is a tradeoff between size and cost. Higher inductance
gives lower ripple current and hence lower output voltage ripple with the same output capacitors. Lower
inductance could result in smaller, less expensive component. An inductance that gives a ripple current of 20% to
40% of the 2 A at the typical supply voltage is a good starting point. ΔiL = (1/5 to 2/5) × IOUT. The peak-to-peak
inductor current ripple can be found by Equation 13 and the range of inductance can be found by Equation 14
with the typical input voltage used as VIN.
'iL
(VIN
VOUT ) u D
L u FS
(13)
(VIN VOUT ) u D
(V
VOUT ) u D
d L d IN
0.4 u FS u IL MAX
0.2 u FS u IL MAX
(14)
D is the duty cycle of the converter which in a buck converter it can be approximated as D = VOUT / VIN, assuming
no loss power conversion. By calculating in terms of amperes, volts, and megahertz, the inductance value will
come out in micro henries. The inductor ripple current ratio is defined by:
'iL
r
IOUT
(15)
The second criterion is the inductor saturation current rating. The inductor must be rated to handle the maximum
load current plus the ripple current:
IL-PEAK = ILOAD-MAX + Δ iL / 2
(16)
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The LM46002-Q1 has both valley current limit and peak current limit. During an instantaneous short, the peak
inductor current can be high due to a momentary increase in duty cycle. The inductor current rating must be
higher than the HS current limit. It is advised to select an inductor with a larger core saturation margin and
preferably a softer roll off of the inductance value over load current.
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. However,
too low of an inductance can generate too large of an inductor current ripple such that overcurrent protection at
the full load could be falsely triggered. It also generates more conduction loss, since the RMS current is slightly
higher relative that with lower current ripple at the same DC current. Larger inductor current ripple also implies
larger output voltage ripple with the same output capacitors. With peak-current-mode control, it is not
recommended to have an inductor current ripple that is too small. Enough inductor current ripple improves signalto-noise ratio on the current comparator and makes the control loop more immune to noise.
Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low core
losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and
preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when
the peak design current is exceeded. The ‘hard’ saturation results in an abrupt increase in inductor ripple current
and consequent output voltage ripple. Do not allow the core to saturate.
For the design example, a standard 10-μH inductor from Würth, Coiltronics, or Vishay can be used for the 3.3-V
output with plenty of current rating margin.
8.2.2.6 Output Capacitor Selection
The device is designed to be used with a wide variety of LC filters. TI generally recommends using as little output
capacitance as possible to keep cost and size down. Choose the output capacitor (s), COUT, with care as it
directly affects the steady-state output-voltage ripple, loop stability, and the voltage over/undershoot during load
current transients.
The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going
through the ESR of the output capacitors:
ΔVOUT-ESR = ΔiL × ESR
(17)
The other is caused by the inductor current ripple charging and discharging the output capacitors:
ΔVOUT-C = ΔiL / (8 × FS × COUT)
(18)
The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the
sum of the two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation in the presence of large current steps and fast slew rates. When a fast large load transient happens,
output capacitors provide the required charge before the inductor current can slew to the appropriate level. The
initial output voltage step is equal to the load current step multiplied by the ESR. VOUT continues to droop until
the control loop response increases or decreases the inductor current to supply the load. To maintain a small
over- or under-shoot during a transient, small ESR and large capacitance are desired. But these also come with
higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the output voltage
deviation.
For a given input and output requirement, Equation 19 gives an approximation for an absolute minimum output
capacitor required:
COUT !
28
ª§ r 2
·
1
u «¨ u (1 Dc) ¸
¨
¸
(FS u r u 'VOUT / IOUT ) «¬© 12
¹
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º
Dc u (1 r) »
»¼
(19)
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Along with this for the same requirement, calculate the maximum ESR as per Equation 20:
Dc
1
u ( 0.5)
FS u COUT r
ESR
where
•
•
•
•
•
r = Ripple ratio of the inductor ripple current (ΔIL / IOUT)
ΔVOUT = Target output voltage undershoot
D’ = 1 – duty cycle
FS = switching frequency
IOUT = load current
(20)
A general guideline for COUT range is that COUT should be larger than the minimum required output capacitance
calculated by Equation 19, and smaller than 10 times the minimum required output capacitance or 1 mF. In
applications with VOUT less than 3.3 V, it is critical that low ESR output capacitors are selected. This limits
potential output voltage overshoots as the input voltage falls below the device normal operating range. To
optimize the transient behavior a feedforward capacitor could be added in parallel with the upper feedback
resistor. For this design example, three 47 µF,10 V, X7R ceramic capacitors are used in parallel.
8.2.2.7 Feed-Forward Capacitor
The LM46002-Q1 is internally compensated and the internal R-C values are 400 kΩ and 50 pF, respectively.
Depending on the VOUT and frequency FS, if the output capacitor COUT is dominated by low ESR (ceramic types)
capacitors, it could result in low phase margin. To improve the phase boost an external feedforward capacitor
CFF can be added in parallel with RFBT. CFF is chosen such that phase margin is boosted at the crossover
frequency without CFF. A simple estimation for the crossover frequency without CFF (fx) is shown in Equation 21,
assuming COUT has very small ESR.
fx
4.35
VOUT u COUT
(21)
The Equation 22 for CFF was tested:
CFF
1
1
u
2Sfx
RFBT u (RFBT / /RFBB )
(22)
Equation 22 indicates that the crossover frequency is geometrically centered on the zero and pole frequencies
caused by the CFF capacitor.
For designs with higher ESR, CFF is not needed when COUT has very high ESR and CFF calculated from
Equation 22 must be reduced with medium ESR. Table 2 can be used as a quick starting point.
For the application in this design example, a 47-pF COG capacitor is selected.
8.2.2.8 Bootstrap Capacitors
Every LM46002-Q1 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is 0.47
μF and rated at 6.3 V or higher. The bootstrap capacitor is located between the SW pin and the CBOOT pin. The
bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature
stability.
8.2.2.9 VCC Capacitor
The VCC pin is the output of an internal LDO for LM46002-Q1. The input for this LDO comes from either VIN or
BIAS (see refer to Functional Block Diagram for LM46002-Q1). To insure stability of the part, place a minimum of
2.2-µF, 10-V capacitor from this pin to ground.
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8.2.2.10 BIAS Capacitors
For an output voltage of 3.3 V and greater, the BIAS pin can be connected to the output in order to increase light
load efficiency. This pin is an input for the VCC LDO. When BIAS is not connected, the input for the VCC LDO is
internally connected into VIN. Since this is an LDO, the voltage differences between the input and output affects
the efficiency of the LDO. If necessary, a capacitor with a value of 1 μF can be added close to the BIAS pin as
an input capacitor for the LDO.
8.2.2.11 Soft-Start Capacitors
The user can leave the SS/TRK pin floating and the LM46002-Q1 implements a soft-start time of 4.1 ms typically.
In order to use an external soft-start capacitor, the capacitor must be sized such that the soft-start time is longer
than 4.1 ms. Use Equation 23 in order to calculate the soft start capacitor value:
CSS ISSC u t SS
where
•
•
•
CSS = soft-start capacitor value (µF)
ISSC = soft-start charging current (µA)
tSS = desired soft-start time (s)
(23)
For the desired soft-start time of 10 ms and soft-start charging current of 2.2 µA, Equation 23 yield a soft-start
capacitor value of 0.022 µF.
8.2.2.12 Undervoltage Lockout Setpoint
The UVLO is adjusted using the external voltage divider network of RENT and RENB. RENT is connected between
the VIN pin and the EN pin of the LM46002-Q1. RENB is connected between the EN pin and the GND pin. The
UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown
outs when the input voltage is falling. The following equation can be used to determine the VIN UVLO level.
VIN-UVLO-RISING = VENH × (RENB + RENT) / RENB
(24)
The EN rising threshold (VENH) for LM46002-Q1 is set to be 2.1 V (typical). Choose the value of RENB to be 1 MΩ
to minimize input current from the supply. If the desired VIN UVLO level is at 5 V, then the value of RENT can be
calculated using the equation below:
RENT = (VIN-UVLO-RISING / VENH – 1) × RENB
(25)
The above equation yields a value of 1.38 MΩ. The resulting falling UVLO threshold, equals 4.3 V, can be
calculated by below equation, where EN falling threshold (VENL) is 1.8 V (typical).
VIN-UVLO-FALLING = VENL × (RENB + RENT) / RENB
(26)
8.2.2.13 PGOOD
A typical pullup resistor value is 10 kΩ to 100 kΩ from the PGOOD pin to a voltage no higher than 12 V. If it is
desired to pull up the PGOOD pin to a voltage higher than 12 V, a resistor can be added from the PGOOD pin to
ground to divide the voltage seen by the PGOOD pin to a value no higher than 12 V.
30
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8.2.3 Application Performance Curves
See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
100
90
VOUT = 3.3 V FS = 500 kHz
80
L=10 µH
70
VOUT
Efficiency (%)
LM46002-Q1
SW
RT
CBOOT
COUT
CBOOT
0.47 µF
150 µF
BIAS
CVCC
2.2 µF
CBIAS
1 µF
VCC
CFF
47 pF
FB
RFBT
1 MŸ
60
50
40
30
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
20
RFBB
432
kŸ
10
0
0.001
0.01
0.1
1
Load Current (A)
VOUT = 3.3 V
FS = 500 kHz
VIN = 24 V
VOUT = 3.3 V
C001
FS = 500 kHz
Figure 47. BOM for VOUT = 3.3 V FS = 500 kHz
Figure 48. Efficiency
3.5
3.35
3.34
3.3
3.1
3.32
3.31
VIN = 12V
3.30
VIN = 18V
3.29
VOUT (V)
VOUT (V)
3.33
2.7
VIN = 24V
VIN = 28V
3.28
2.9
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
2.5
VIN = 36V
2.3
3.27
0.001
0.01
0.1
Current (A)
VOUT = 3.3 V
3.5
1
4.0
4.5
5.0
VIN (V)
C001
FS = 500 kHz
VOUT = 3.3 V
Figure 49. Output Voltage Regulation
C013
FS = 500 kHz
Figure 50. Dropout Curve
2.5
2.0
VDROP-ON-0.75Ÿ-LOAD (1 A/DIV)
Current (A)
VOUT (200 mV/DIV)
1.5
1.0
R,JA=10ƒC/W
IINDUCTOR (1 A/DIV)
0.5
R,JA=20ƒC/W
R,JA=30ƒC/W
0.0
Time (100 µs/DIV)
50
60
70
80
90
100
110
120
Ta (ƒC)
VOUT = 3.3 V
FS = 500 kHz
VIN = 24 V
Figure 51. Load Transient Between 0.1 A and 2 A
VOUT = 3.3 V
FS = 500 kHz
C013
VIN = 24 V
Figure 52. Derating Curve
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See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
100
90
VOUT = 5 V FS = 500 kHz
80
RT
L=15 µH
70
VOUT
Efficiency (%)
LM46002-Q1
SW
CBOOT
CBOOT
0.47 µF
COUT
100 µF
CBIAS
1 µF
CFF
BIAS
VCC
CVCC
2.2 µF
47 pF
FB
RFBT
1 MŸ
RFBB
249
kŸ
60
50
40
VIN = 12V
30
VIN = 18V
20
VIN = 24V
10
VIN = 28V
VIN = 36V
0
0.001
0.01
0.1
1
Load Current (A)
VOUT = 5 V
FS = 500 kHz
VIN = 24 V
VOUT = 5 V
C003
FS = 500 kHz
Figure 53. BOM for VOUT = 5 V FS = 500 kHz
Figure 54. Efficiency
5.2
5.05
5.0
4.8
VIN = 12V
5.01
VOUT (V)
VOUT (V)
5.03
VIN = 18V
VIN = 24V
4.99
VIN = 28V
4.6
4.4
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
VIN = 36V
4.97
VIN = 42V
4.2
VIN = 48V
4.0
4.95
0.001
0.01
0.1
Current (A)
VOUT = 5 V
5.0
1
5.2
5.4
5.6
5.8
6.0
6.2
6.4
VIN (V)
C001
FS = 500 kHz
VOUT = 5 V
Figure 55. Output Voltage Regulation
C003
FS = 500 kHz
Figure 56. Dropout Curve
2.5
2.0
IINDUCTOR (2 A/DIV)
Current (A)
VOUT (200 mV/DIV)
1.5
1.0
R,JA=10ƒC/W
0.5
VDROP-ON-0.75
-LOAD
R,JA=20ƒC/W
(2 V/DIV)
R,JA=30ƒC/W
0.0
Time (100 µs/DIV)
50
60
70
80
90
100
Ta (ƒC)
VOUT = 5 V
FS = 500 kHz
VIN = 24 V
Figure 57. Load Transient Between 0.1 A and 2 A
32
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VOUT = 5 V
FS = 500 kHz
110
120
C013
VIN = 24 V
Figure 58. Derating Curve
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See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
100
90
VOUT = 5 V FS = 200 kHz
80
VOUT
SW
RT
RT
200
kŸ
70
L=33 µH
Efficiency (%)
LM46002-Q1
CBOOT
COUT
200 µF
CBOOT
0.47 µF
BIAS
CBIAS
1 µF
VCC
CVCC
2.2 µF
CFF
68 pF
FB
60
50
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
40
RFBT
1 MŸ
30
RFBB
249
kŸ
10
20
0
0.001
0.01
0.1
1
Load Current (A)
VOUT = 5 V
FS = 200 kHz
VIN = 24 V
VOUT = 5 V
C002
FS = 200 kHz
Figure 59. BOM for VOUT = 5 V FS = 200 kHz
Figure 60. Efficiency
5.2
5.07
5.06
5.0
5.04
5.03
5.02
5.01
5.00
4.8
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
VOUT (V)
VOUT (V)
5.05
4.6
4.4
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
4.2
4.0
4.99
0.001
0.01
0.1
Current (A)
VOUT = 5 V
5.0
1
5.2
5.4
5.6
5.8
6.0
6.2
6.4
VIN (V)
C008
FS = 200 kHz
VOUT = 5 V
Figure 61. Output Voltage Regulation
C002
FS = 200 kHz
Figure 62. Dropout Curve
2.5
VOUT (200 mV/DIV)
Current (A)
IINDUCTOR (2 A/DIV)
2.0
1.5
1.0
R,JA=10ƒC/W
0.5
VDROP-ON-0.75
-LOAD
R,JA=20ƒC/W
(2 V/DIV)
R,JA=30ƒC/W
0.0
Time (100 µs/DIV)
50
60
70
80
90
100
110
120
Ta (ƒC)
VOUT = 5 V
FS = 200 kHz
VIN = 24 V
Figure 63. Load Transient Between 0.1 A and 2 A
VOUT = 5 V
C013
FS = 200 kHz
Figure 64. Derating Curve
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See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
100
90
VOUT = 5 V FS = 1 MHz
80
VOUT
SW
RT
RT
39.2
kŸ
L=6.8 µH
Efficiency (%)
70
LM46002-Q1
CBOOT
CBOOT
0.47 µF
COUT
47 µF
CBIAS
1 µF
CFF
BIAS
VCC
CVCC
2.2 µF
47 pF
FB
RFBT
1 MŸ
60
50
40
30
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
20
RFBB
249
kŸ
10
0
0.001
0.01
0.1
1
Load Current (A)
VOUT = 5 V
FS = 1 MHz
VIN = 24 V
VOUT = 5 V
C004
FS = 1 MHz
Figure 65. BOM for VOUT = 5 V FS = 1 MHz
VIN = 24 V
Figure 66. Efficiency
5.2
5.06
5.05
5.0
5.04
4.8
VIN = 12V
VOUT (V)
VOUT (V)
5.03
5.02
5.01
5.00
4.99
VIN = 18V
VIN = 24V
4.6
4.4
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
VIN = 28V
4.2
4.98
VIN = 36V
4.0
4.97
0.001
0.01
0.1
Current (A)
VOUT = 5 V
5.0
1
5.2
5.4
5.6
5.8
6.0
6.2
6.4
VIN (V)
C001
FS = 1 MHz
VOUT = 5 V
Figure 67. Output Voltage Regulation
C004
FS = 1 MHz
Figure 68. Dropout Curve
2.5
2.0
Current (A)
VOUT (200 mV/DIV)
1.5
1.0
IINDUCTOR (2 A/DIV)
R,JA=10ƒC/W
0.5
VDROP-ON-0.75
-LOAD
R,JA=20ƒC/W
(2 V/DIV)
R,JA=30ƒC/W
0.0
Time (100 µs/DIV)
40
50
60
70
80
90
100
Ta (ƒC)
VOUT = 5 V
FS = 1 MHz
VIN = 24 V
Figure 69. Load Transient Between 0.1 A and 2 A
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VOUT = 5 V
FS = 1 MHz
110
120
C013
VIN = 24 V
Figure 70. Derating Curve
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SNVSAA2B – JULY 2015 – REVISED JULY 2017
See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
100
90
VOUT = 12 V FS = 500 kHz
80
L=22 µH
70
VOUT
Efficiency (%)
LM46002-Q1
RT
SW
CBOOT
CBOOT
0.47 µF
COUT
47 µF
CBIAS
1 µF
CFF
BIAS
VCC
CVCC
2.2 µF
68 pF
FB
RFBT
1 MŸ
60
50
40
VIN = 24V
VIN = 28V
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
30
20
RFBB
90.9
kŸ
10
0
0.001
0.01
0.1
1
Load Current (A)
VOUT = 12 V
FS = 500 kHz
VIN = 24 V
VOUT = 12 V
Figure 71. BOM for VOUT = 12 V FS = 500 kHz
12.2
12.10
12.0
12.00
11.8
VIN = 24V
VOUT (V)
VOUT (V)
Figure 72. Efficiency
12.15
12.05
VIN = 28V
VIN = 36V
11.95
11.90
C005
FS = 500 kHz
11.6
11.4
VIN = 42V
VIN = 48V
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
11.2
VIN = 60V
11.85
0.001
0.01
0.1
Current (A)
VOUT = 12 V
11.0
12.0
1
12.2
12.4
12.6
12.8
13.0
13.2
13.4
VIN (V)
C001
FS = 500 kHz
VOUT = 12 V
Figure 73. Output Voltage Regulation
C005
FS = 500 kHz
Figure 74. Dropout Curve
2.50
VOUT (1 V/DIV)
Current (A)
IINDUCTOR (1 A/DIV)
2.00
1.50
1.00
,JA=10C/W
0.50
,JA=20C/W
ILOAD (1 A/DIV)
,JA=30C/W
0.00
40
50
60
VOUT = 12 V
VOUT = 12 V
FS = 500 kHz
70
80
90
100
110
120
Ta (deg C)
Time (200 µs/DIV)
VIN = 24 V
FS = 500 kHz
130
C001
VIN = 24 V
Figure 76. Derating Curve
Figure 75. Load Transient Between 0.1 A and 2 A
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See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
100
90
VOUT = 24 V FS = 500 kHz
80
L = 47 µH
70
VOUT
Efficiency (%)
LM46002-Q1
RT
SW
COUT
47 µF
CBOOT
0.47 µF
CBOOT
BIAS
CBIAS
1 µF
VCC
CVCC
2.2 µF
RFBT
1 MŸ
FB
60
50
40
30
VIN = 36V
VIN = 42V
VIN = 48V
VIN = 60V
20
RFBB
43.2
kŸ
10
0
0.001
0.01
0.1
1
Load Current (A)
VOUT = 24 V
FS = 500 kHz
VIN = 48 V
VOUT = 24 V
Figure 77. BOM for VOUT = 24 V FS = 500 kHz
Figure 78. Efficiency
24.4
24.60
VIN = 36V
24.50
24.2
VIN = 42V
24.0
VIN = 48V
24.40
23.8
VIN = 60V
VOUT (V)
VOUT (V)
C006
FS = 500 kHz
24.30
24.20
23.6
23.4
23.2
23.0
24.10
IOUT = 0.1A
IOUT = 0.5A
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
22.8
24.00
22.6
23.90
0.001
0.01
0.1
Current (A)
VOUT = 24 V
22.4
24.0
1
24.5
25.0
25.5
26.0
VIN (V)
C001
FS = 500 kHz
VOUT = 24 V
Figure 79. Output Voltage Regulation
C006
FS = 500 kHz
Figure 80. Dropout Curve
2.50
2.00
IINDUCTOR (1 A/DIV)
Current (A)
VOUT (2 V/DIV)
1.50
1.00
0.50
R,JA=10ƒC/W
R,JA=20ƒC/W
ILOAD (1 A/DIV)
0.00
40
50
60
VOUT = 24 V
VOUT = 24 V
FS = 500 kHz
70
80
90
100
Ta (ƒC)
Time (200 µs/DIV)
VIN = 48 V
FS = 500 kHz
110
120
130
C001
VIN = 48 V
Figure 82. Derating Curve
Figure 81. Load Transient Between 0.1 A and 2 A
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2.5
2.5
2.0
2.0
Current (A)
Current (A)
See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
1.5
1.0
1.5
1.0
VIN=12V
0.5
VIN=12V
0.5
VIN=24V
VIN=24V
VIN=36V
VIN=36V
0.0
0.0
50
60
70
80
90
100
110
120
Ta (ƒC)
VOUT = 3.3 V
50
FS = 500 kHz
RθJA = 20 °C/W
VOUT = 5 V
90
100
110
120
C013
FS = 500 kHz
RθJA = 20 °C/W
Figure 84. Derating Curve with RθJA = 20 °C/W
2.0
2.0
Current (A)
2.5
1.5
1.0
1.5
1.0
VIN=12V
VIN=12V
0.5
VIN=24V
VIN=24V
VIN=36V
VIN=36V
0.0
0.0
50
60
70
80
90
100
110
120
Ta (ƒC)
VOUT = 5 V
40
50
60
70
FS = 200 kHz
80
90
100
RθJA = 20 °C/W
VOUT = 5 V
C013
FS = 1 MHz
RθJA = 20 °C/W
1.E+06
Switching Frequency (Hz)
1.E+05
1.E+04
VIN = 8V
1.E+05
1.E+04
VIN = 12V
VIN = 24V
VIN = 12V
VIN = 24V
0.010
0.100
LOAD CURRENT (A)
VOUT = 3.3 V
120
Figure 86. Derating Curve with RθJA = 20 °C/W
1.E+06
1.E+03
0.001
110
Ta (ƒC)
C013
Figure 85. Derating Curve with RθJA = 20 °C/W
Switching Frequency (Hz)
80
Ta (ƒC)
2.5
0.5
70
C013
Figure 83. Derating Curve with RθJA = 20 °C/W
Current (A)
60
1.000
1.E+03
0.001
Figure 87. Switching Frequency vs IOUT in PFM Operation
0.100
1.000
LOAD CURRENT (A)
C006
FS = 500 kHz
VIN = 36V
0.010
VOUT = 5 V
C007
FS = 1 MHz
Figure 88. Switching Frequency vs IOUT in PFM Operation
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See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
SW Node
(10 V/DIV)
SW Node
(10 V/DIV)
VOUT Ripple
(5 mV/DIV)
VOUT Ripple
(5 mV/DIV)
IINDUCTOR
(2 A/DIV)
IINDUCTOR
(2 A/DIV)
Time (2 µs/DIV)
VOUT = 3.3 V
FS = 500 kHz
Time (2 µs/DIV)
IOUT = 2 A
Figure 89. Switching Waveform in CCM Operation
VOUT = 3.3 V
FS = 500 kHz
IOUT = 130 mA
Figure 90. Switching Waveform in DCM Operation
VOUT (2 V/DIV)
SW Node
(10 V/DIV)
IINDUCTOR (1 A/DIV)
VOUT Ripple
(5 mV/DIV)
PGOOD (5 V/DIV)
IINDUCTOR
(0.5 A/DIV)
Time (1 ms/DIV)
Time (50 µs/DIV)
VOUT = 3.3 V
FS = 500 kHz
IOUT = 5 mA
Figure 91. Switching Waveform in PFM Operation
VIN = 24 V
VOUT = 3.3 V
RLOAD = 1.65 Ω
Figure 92. Startup Into Full Load with Internal Soft-Start
Rate
VOUT (2 V/DIV)
VOUT (2 V/DIV)
IINDUCTOR (500 mA/DIV)
IINDUCTOR (1 A/DIV)
PGOOD (5 V/DIV)
PGOOD (5 V/DIV)
Time (1 ms/DIV)
VIN = 24 V
VOUT = 3.3 V
Time (1 ms/DIV)
RLOAD = 3.3 Ω
Figure 93. Startup Into Half Load with Internal Soft-Start
Rate
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VIN = 24 V
VOUT = 3.3 V
RLOAD = 33 Ω
Figure 94. Startup Into 100 mA with Internal Soft-Start Rate
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SNVSAA2B – JULY 2015 – REVISED JULY 2017
See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
VOUT (5 V/DIV)
VOUT (2 V/DIV)
IINDUCTOR (1 A/DIV)
IINDUCTOR (500 mA/DIV)
PGOOD (5 V/DIV)
PGOOD (5 V/DIV)
Time (1 ms/DIV)
VIN = 24 V
Time (2 ms/DIV)
VOUT = 3.3 V
RLOAD = Open
VIN = 24 V
Figure 95. Startup Into 1.5 V Pre-biased Voltage
VOUT = 12 V
RLOAD = 6 Ω
Figure 96. Startup with External Capacitor CSS
VOUT (200 mV/DIV)
VOUT (200 mV/DIV)
VIN (20 V/DIV)
VIN (20 V/DIV)
IINDUCTOR (1 A/DIV)
IINDUCTOR (1 A/DIV)
Time (500 µs/DIV)
Time (200 µs/DIV)
VOUT = 3.3 V
FS = 500 kHz
IOUT = 2 A
Figure 97. Line Transient: VIN Transitions Between 12 V
and 36 V, 1 V/µs Slew Rate
VOUT = 3.3 V
FS = 500 kHz
IOUT = 0.5 A
Figure 98. Line Transient: VIN Transitions Between 12 V
and 36 V, 1 V/µs Slew Rate
VOUT (2 V/DIV)
PGOOD (5 V/DIV)
IINDUCTOR (2 A/DIV)
Time (2 ms/DIV)
VOUT = 3.3 V
FS = 500 kHz
VIN = 24 V
Figure 99. Short Circuit Protection and Recover
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9 Power Supply Recommendations
The LM46002-Q1 is designed to operate from an input voltage supply range between 3.5 V and 60 V. This input
supply must be able to withstand the maximum input current and maintain a voltage above 3.5 V. The resistance
of the input supply rail must be low enough that an input current transient does not cause a high enough drop at
the LM46002-Q1 supply voltage that can cause a false UVLO fault triggering and system reset.
If the input supply is located more than a few inches from the LM46002-Q1 additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-µF
or 100-µF electrolytic capacitor is a typical choice.
10 Layout
The performance of any switching converter depends as much upon the layout of the PCB as the component
selection. Use the following guidelines to design a PCB with the best power conversion performance, thermal
performance, and minimized generation of unwanted EMI.
10.1 Layout Guidelines
1. Place ceramic high frequency bypass CIN as close as possible to the LM46002-Q1 VIN and PGND pins.
Grounding for both the input and output capacitors should consist of localized top side planes that connect to
the PGND pins and PAD.
2. Place bypass capacitors for VCC and BIAS close to the pins and ground the bypass capacitors to device
ground.
3. Minimize trace length to the FB pin. Locate both feedback resistors, RFBT and RFBB close to the FB pin. Place
CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT sense is made at
the load. Route VOUT sense path away from noisy nodes and preferably through a layer on the other side of
a shielding layer.
4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.
5. Have a single point ground connection to the plane. Route the ground connections for the feedback, softstart, and enable components to the ground plane. This prevents any switched or load currents from flowing
in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or
erratic output voltage ripple behavior.
6. Make VIN, VOUT, and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
7. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the
ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be
connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking
to keep the junction temperature below 125°C.
10.1.1 Compact Layout for EMI Reduction
Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to
minimize radiated EMI is to identify the pulsing current path and minimize the area of the path. In Buck
converters, the pulsing current path is from the VIN side of the input capacitors to HS switch, to the LS switch,
and then return to the ground of the input capacitors, as shown in Figure 100.
BUCK
CONVERTER
VIN
VIN
SW
CIN
L
VOUT
COUT
PGND
High di/dt
current
PGND
Figure 100. Buck Converter High di / dt Path
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Layout Guidelines (continued)
High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of
the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the
key to EMI reduction.
The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load
current without excessive heating. Use short, thick traces or copper pours (shapes) for high-current-conduction
path to minimize parasitic resistance. Place the output capacitors close to the VOUT end of the inductor and
closely grounded to PGND pin and exposed PAD.
Place the bypass capacitors on VCC and BIAS pins as close as possible to the pins respectively and closely
grounded to PGND and the exposed PAD.
10.1.2 Ground Plane and Thermal Considerations
TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for
sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the
AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pins are
connected to the source of the internal LS switch; connect the PGND pins directly to the grounds of the input and
output capacitors. The PGND net contains noise at the switching frequency and may bounce due to load
variations. The PGND trace, as well as PVIN and SW traces, should be constrained to one side of the ground
plane. The other side of the ground plane contains much less noise — use for sensitive routes.
Provide adequate device heat sinking by utilizing the PAD of the device as the primary thermal path. Use a
minimum 4 by 4 array of 10 mil thermal vias to connect the PAD to the system ground plane for heat sinking.
Distribute the vias evenly under the PAD. Use as much copper as possible for system ground plane on the top
and bottom layers for the best heat dissipation. TI recommends using a four-layer board with the copper
thickness, for the four layers, starting from the top one, 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough
copper thickness and proper layout provides low current conduction impedance, proper shielding and lower
thermal resistance.
The thermal characteristics of the LM46002-Q1 are specified using the parameter RθJA, which characterize the
junction temperature of the silicon to the ambient temperature in a specific system. Although the value of RθJA is
dependant on many variables, it still can be used to approximate the operating junction temperature of the
device. To obtain an estimate of the device junction temperature, one may use the following relationship:
TJ = PD× RθJA + TA
where
•
•
•
•
•
TJ = junction temperature in °C
PD = VIN × IIN × (1 − efficiency) − 1.1 × IOUT × DCR
DCR = inductor DC parasitic resistance in Ω
RθJA = junction-to-ambient thermal resistance of the device in °C/W
TA = ambient temperature in °C.
(27)
The maximum operating junction temperature of the LM46002-Q1 is 125°C. RθJA is highly related to PCB size
and layout, as well as environmental factors such as heat sinking and air flow. Figure 101 shows measured
results of RθJA with different copper area on a 2-layer board and a 4-layer board.
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Layout Guidelines (continued)
50.0
1W @ 0fpm - 2 layer
2W @ 0fpm - 2 layer
R,JA (ƒC/W)
45.0
1W @ 0fpm - 4 layer
2W @ 0fpm - 4 layer
40.0
35.0
30.0
25.0
20.0
20mm x 20mm
30mm x 30mm
40mm x 40mm
50mm x 50mm
Copper Area
C007
Figure 101. Measured RθJA vs PCB Copper Area on a 2-layer Board and a 4-layer Board
10.1.3 Feedback Resistors
To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and
CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high
impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces the
trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace
from VOUT to the resistor divider can be long if short path is not available.
If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for
voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to
the feedback resistor divider should be routed away from the SW node path, the inductor and VIN path to avoid
contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most
important when high value resistors are used to set the output voltage. TI recommends routing the voltage sense
trace on a different layer than the inductor, SW node and VIN path, such that there is a ground plane in between
the feedback trace and inductor / SW node / VIN polygon. This provides further shielding for the voltage feedback
path from switching noises.
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10.2 Layout Example
VOUT distribution point
is away from inductor
and past COUT
VOUT sense point is away
from inductor and past COUT
GND
GND
+
VOUT
As much copper area as possible,
for better thermal performance
COUT
L
Place ceramic bypass caps
close to VIN and PGND pins
CBOOT
SW
PAD (17)
PGND
16
PGND
15
2
SW
3
CBOOT
VIN
14
4
VCC
VIN
13
5
BIAS
EN
12
6
SYNC
SS/TRK
11
7
RT
AGND
10
8
PGOOD
CVCC
Place bypass
caps close to
pins
CBIAS
Ground
bypass caps
to DAP
FB
CIN
9
RFBT
GND
GND
+
1
Place CBOOT
close to pins
VIN
Place RFBB
close to FB
and AGND
RFBB
Trace to
FB short
and thin
Route VOUT
sense trace
away from
SW and VIN
nodes.
Preferably
shielded in an
alternative
layer
CFF
VOUT
sense
As much copper area as possible, for better thermal performance
Preferably use GND Plane as a middle layer for shielding and heat dissipation
Preferably place and route on top layer and use solid copper on bottom layer for heat dissipation
Figure 102. LM46002-Q1 PCB Layout Example and Guidelines
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM46002-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2015–2017, Texas Instruments Incorporated
Product Folder Links: LM46002-Q1 LM46002A-Q1
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PACKAGE OPTION ADDENDUM
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13-Jul-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM46002AQPWPRQ1
PREVIEW
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
46002AQ
LM46002AQPWPTQ1
PREVIEW
HTSSOP
PWP
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
46002AQ
LM46002QPWPRQ1
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
46002Q1
LM46002QPWPTQ1
ACTIVE
HTSSOP
PWP
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
46002Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM46002-Q1 :
• Catalog: LM46002
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM46002QPWPRQ1
HTSSOP
PWP
16
2000
330.0
12.4
LM46002QPWPTQ1
HTSSOP
PWP
16
250
180.0
12.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.9
5.6
1.6
8.0
12.0
Q1
6.9
5.6
1.6
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM46002QPWPRQ1
HTSSOP
PWP
16
2000
367.0
367.0
38.0
LM46002QPWPTQ1
HTSSOP
PWP
16
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM46002AQPWPRQ1
PREVIEW
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
46002AQ
LM46002AQPWPTQ1
PREVIEW
HTSSOP
PWP
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
46002AQ
LM46002QPWPRQ1
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
46002Q1
LM46002QPWPTQ1
ACTIVE
HTSSOP
PWP
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
46002Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM46002-Q1 :
• Catalog: LM46002
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM46002QPWPRQ1
HTSSOP
PWP
16
2000
330.0
12.4
LM46002QPWPTQ1
HTSSOP
PWP
16
250
180.0
12.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.9
5.6
1.6
8.0
12.0
Q1
6.9
5.6
1.6
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM46002QPWPRQ1
HTSSOP
PWP
16
2000
367.0
367.0
38.0
LM46002QPWPTQ1
HTSSOP
PWP
16
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016G
PowerPAD
TM
TSSOP - 1.2 mm max height
SCALE 2.400
PLASTIC SMALL OUTLINE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
16
1
0.1 C
14X 0.65
2X
4.55
5.1
4.9
NOTE 3
8
B
4.5
4.3
NOTE 4
9
16X
0.30
0.19
0.1
1.2 MAX
C A
B
0.18
TYP
0.12
SEE DETAIL A
2X 0.24 MAX
NOTE 6
2X 0.56 MAX
NOTE 6
THERMAL
PAD
0.25
GAGE PLANE
3.29
2.71
0 -8
0.15
0.05
0.75
0.50
(1)
2.41
1.77
DETAIL A
TYPICAL
4218975/B 01/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
6. Features may not present.
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EXAMPLE BOARD LAYOUT
PWP0016G
PowerPAD
TM
TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 10
(2.41)
SOLDER MASK
OPENING
16X (1.5)
SOLDER MASK
DEFINED PAD
SEE DETAILS
SYMM
1
16
16X (0.45)
(0.95)
TYP
SYMM
14X (0.65)
(3.29)
SOLDER MASK
OPENING
(5)
9
8
(0.95) TYP
( 0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4218975/B 01/2016
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
9. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016G
PowerPAD
TM
TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(2.41)
BASED ON
0.127 THICK
STENCIL
16X (1.5)
1
16
16X (0.45)
(3.29)
BASED ON
0.127 THICK
STENCIL
SYMM
14X (0.65)
9
8
(R0.05)
SYMM
METAL COVERED
BY SOLDER MASK
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.127
0.152
0.178
2.69 X 3.68
2.41 X 3.29 (SHOWN)
2.20 X 3.00
2.04 X 2.78
4218975/B 01/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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