ON NCV7708DWG Double hex driver Datasheet

NCV7708
Double Hex Driver
The NCV7708 is a fully protected Hex−Half Bridge−Driver
designed specifically for automotive and industrial motion control
applications. The six low and high side drivers are freely configurable
and can be controlled separately. This allows for high side, low side,
and H−Bridge control. H−Bridge control provides forward, reverse,
brake, and high impedance states. The drivers are controlled via a
standard SPI interface.
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Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Ultra Low Quiescent Current Sleep Mode
Six Independent High−Side and Six independent Low−Side Drivers
Integrated Freewheeling Protection (LS and HS)
Configurable as H−Bridge Drivers
0.5 A Continuous (1 A peak) Current
RDSon = 0.8 W (typ)
5 MHz SPI Control
Compliance with 5 V and 3.3 V Systems
Overvoltage Lockout
Undervoltage Lockout
Fault Reporting
Current Limit
Over−temperature Protection
Pb−Free Packages are Available*
SOIC−28
DW SUFFIX
CASE 751F
MARKING DIAGRAM
NCV7708
AWLYYWWG
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
1
Typical Applications
OUTL5
OUTH5
OUTH4
OUTL4
VS2
GND
GND
GND
GND
VS1
OUTL3
OUTH3
OUTH2
OUTL2
• Automotive
• Industrial
OUTH6
OUTL6
SI
SCLK
CSB
GND
GND
GND
GND
VCC
SO
EN
OUTL1
OUTH1
ORDERING INFORMATION
Package
Shipping †
NCV7708DW
SOIC−28W
26 Units/Rail
NCV7708DWG
SOIC−28W
(Pb−Free)
26 Units/Rail
NCV7708DWR2
SOIC−28W 1000/Tape & Reel
Device
NCV7708DWR2G SOIC−28W 1000/Tape & Reel
(Pb−Free)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 1
1
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NCV7708/D
NCV7708
VS1
VS
EN
CP
ENABLE
DRIVE 1
VS
Charge
Pump
High−Side
Driver
OUTH1
Waveshaping
Control
Logic
VCC
Fault
Detect
BIAS
POR
Low−Side
Driver
SPI
Control
SI
Fault
SO
16 Bit
Logic
and
Latch
SPI
SCLK
OUTL1
Waveshaping
Under−load
Overcurrent
Thermal
Warning/Shutdown
OUTH2
VS
DRIVE 2
CSB
CP
OUTL2
VS
OUTH3
DRIVE 3
CP
OUTL3
VS
OUTH4
VS1
Undervoltage
Lockout
VS2
DRIVE 4
CP
OUTL4
VS
VS1
Overvoltage
Lockout
OUTH5
DRIVE 5
VS2
CP
OUTL5
VS
OUTH6
DRIVE 6
CP
GND
VS2
Figure 1. Block Diagram
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2
OUTL6
NCV7708
PIN DESCRIPTION
Pin No.
Symbol
Description
1
OUTL5
Output Low Side 5. Open drain output driver with internal reverse diode.
2
OUTH5
Output High Side 5. Open source output driver with internal reverse diode. Drain connected to VS2.
3
OUTH4
Output High Side 4. Open source output driver with internal reverse diode. Drain connected to VS2.
4
OUTL4
Output Low Side 4. Open drain output driver with internal reverse diode.
5
VS2
Voltage Power Supply input for the High−Side Output Drivers 4, 5, and 6.
6
GND
Ground.
7
GND
Ground.
8
GND
Ground.
9
GND
Ground.
10
VS1
Voltage Power Supply input for the High−Side Output Drivers 1, 2, and 3, All Six Low−Side Pre
Drivers, and All Six Charge Pumps.
11
OUTL3
Output Low Side 3. Open drain output driver with internal reverse diode.
12
OUTH3
Output High Side 3. Open source output driver with internal reverse diode. Drain connected to VS1.
13
OUTH2
Output High Side 2. Open source output driver with internal reverse diode. Drain connected to VS1.
14
OUTL2
Output Low Side 2. Open drain output driver with internal reverse diode.
15
OUTH1
Output High Side 1. Open source output driver with internal reverse diode. Drain connected to VS1.
16
OUTL1
Output Low Side 1. Open drain output driver with internal reverse diode.
17
EN
Enable. Input high wakes the IC up from a sleep mode.
18
SO
Serial Output. 16 bit serial communications output.
19
VCC
Power supply input for Logic.
20
GND
Ground.
21
GND
Ground.
22
GND
Ground.
23
GND
Ground.
24
CSB
Chip Select Bar. Active low serial port operation.
25
SCLK
Serial Clock. Clock input for use with SPI communication.
26
SI
27
OUTL6
Output Low Side 6. Open drain output driver with internal reverse diode.
28
OUTH6
Output High Side 6. Open source output driver with internal reverse diode. Drain connected to VS2.
Serial Input. 16 bit serial communications input.
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3
NCV7708
MAXIMUM RATINGS
Rating
Value
Power Supply Voltage (VS1, VS2)
(DC)
(AC), t < 500 ms, Ivsx > −2 A
−0.3 to 40
−1.0
Output Pin OUTHx
(DC)
(AC – inductive clamping)
−0.3 to 40
−8.0
Output Pin OUTLx
(DC)
(AC), t < 500 ms, IOUTLx > −2 A
External Clamp Voltage (Note 3)
−0.3 to 34
−1.0
48
Pin Voltage (Logic Input pins, SI, SCLK, CSB, SO, EN, VCC)
−0.3 to 7.0
Unit
V
V
V
Output Current (OUTL1, OUTL2, OUTL3, OUTL4, OUTL5, OUTL6, OUTH1, OUTH2, OUTH3, OUTH4,
OUTH5, OUTH6)
(DC) Vds = 12 V
(DC) Vds = 20 V
(DC) Vds = 40 V
(AC) Vds = 12 V, (50 ms pulse, 1 s period)
(AC) Vds = 20 V, (50 ms pulse, 1 s period)
(AC) Vds = 40 V, (50 ms pulse, 1 s period)
V
A
−1.5 to 1.5
−0.7 to 0.7
−0.25 to 0.25
−2.0 to 2.0
−0.9 to 0.9
−0.3 to 0.3
Electrostatic Discharge, Human Body Model, VS1, VS2, OUTx
4.0
kV
Electrostatic Discharge, Human Body Model, all other pins
2.0
kV
Electrostatic Discharge, Machine Model
200
V
Operating Junction Temperature
−40 to 150
°C
Storage Temperature Range
−55 to 150
°C
3
−
Moisture Sensitivity Level
MAX 235°C Processing
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Test Conditions
Typical Value
Thermal Parameters
SOIC 28−pin Package
min−pad board
(Note 1)
1″−pad board
(Note 2)
Junction−to−Lead (psi−JL8, YJL8) or Pins 6−9, 20−23
10
11
°C/W
Junction−to−Ambient (RqJA, qJA)
73
56
°C/W
mm2
mm2
1. 1−oz copper, 240
copper area, 0.062″ thick FR4.
2. 1−oz copper, 986
copper area, 0.062″ thick FR4.
3. OUTLx must be protected against flyback voltages that exceed 48 V.
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NCV7708
ELECTRICAL CHARACTERISTICS
(−40°C < TJ < 150°C, 5.5 V < VSx < 40 V, 3 V < VCC < 5.25 V, EN = VCC, unless otherwise specified)
Characteristic
Test Conditions
Min
Typ
Max
Unit
GENERAL
Supply Current (VS1 + VS2)
Sleep Mode
VS1 = VS2 = 13.2 V, VCC = CSB = 5 V,
EN = SI = SCLK = 0 V
−
1.0
5.0
mA
Supply Current (VS1)
Active Mode
EN = VCC, 5.5 V < VSx < 35 V
No Load
−
2.0
4.0
mA
Supply Current (VS2)
Active Mode
EN = VCC, 5.5 V < VSx < 35 V
No Load
−
0.5
1.0
mA
Supply Current (VCC) − Sleep Mode (Note 5)
CSB = VCC, EN = SI = SCLK = 0 V
(−40°C to 85°C)
EN = CSB = VCC, SI = SCLK = 0 V
−
1.0
2.5
mA
−
1.5
3.0
mA
2.60
2.80
3.00
V
4.2
4.6
5.1
V
100
−
400
mV
35.0
37.5
40.0
V
VSx Overvoltage Detection Hysteresis
1.5
3.5
5.5
V
Thermal Warning (Note 4)
120
145
170
°C
−
30
−
°C
Thermal Shutdown (Note 4)
155
175
195
°C
Ratio of Thermal Shutdown to Thermal Warning (Note 4)
1.05
1.20
−
−
Iout = −500 mA
8 V < Vs < 40 V
8 V < Vs < 40 V, T = 25°C
5.5 V < Vs ≤ 8 V
5.5 V < Vs ≤ 8 V, T = 25°C
−
−
−
−
−
0.8
−
2.0
2.0
1.3
4.0
−
Iout = 500 mA
8 V < Vs < 40 V
8 V < Vs < 40 V, T = 25°C
5.5 V < Vs ≤ 8 V
5.5 V < Vs ≤ 8 V, T = 25°C
−
−
−
−
−
0.8
−
2.0
2.0
1.2
4.0
−
Supply Current (VCC) − Active Mode
VCC Power−On−Reset Threshold
VSx Undervoltage Detection Threshold
VSx decreasing
VSx Undervoltage Detection Hysteresis
VSx Overvoltage Detection Threshold
VSx increasing
Thermal Warning Hysteresis (Note 4)
OUTPUTS
Output High RDSon (source)
Output Low RDSon (sink)
W
W
Source Leakage Current
OUTH(1−6) = 0 V, VSx = 40 V, VCC = 5 V
OUTH(1−6) = 0 V, T = 25°C, VCC = 5 V
−5.0
−1.0
−
−
−
−
mA
Sink Leakage Current
OUTL(1−6) = 34 V, VCC = 5 V
OUTL(1−6) = 34 V, VCC = 5 V, T = 25°C
−
−
−
−
5.0
1.0
mA
Overcurrent Shutdown Threshold (OUTHx)
VCC = 5 V, Vsx = 13.2 V
−1.9
−1.45
−1.0
A
Current Limit (OUTHx)
VCC = 5 V, Vsx = 13.2 V
−5.0
−3.0
−2.0
A
Overcurrent Shutdown Threshold (OUTLx)
VCC = 5 V, Vsx = 13.2 V
1.0
1.45
1.9
A
Overcurrent Shutdown Delay Time − Source
Overcurrent Shutdown Delay Time − Sink
VCC = 5 V, Vsx = 13.2 V
10
10
25
25
50
50
ms
4.
5.
6.
7.
Thermal characteristics are not subject to production test.
Production tested @ −40°C, 125°C. Refer to graph 6 for VCC sleep current vs. temperature.
Refer to “Typical High−Side Negative Clamp Voltage Chart,” Figure 5
Not production tested.
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5
NCV7708
ELECTRICAL CHARACTERISTICS
(−40°C < TJ < 150°C, 5.5 V < VSx < 40 V, 3 V < VCC < 5.25 V, EN = VCC, unless otherwise specified)
Characteristic
Test Conditions
Min
Typ
Max
Unit
OUTPUTS
Current Limit (OUTLx)
VCC = 5 V, Vsx = 13.2 V
2.0
3.0
5.0
A
Under Load Detection Threshold (OUTLx)
VCC = 5 V, Vsx = 13.2 V
3.0
8.0
15
mA
Under Load Detection Threshold (OUTHx)
VCC = 5 V, Vsx = 13.2 V
−15
−6.0
−2.0
mA
Under Load Detection Delay Time
VCC = 5 V, Vsx = 13.2 V
200
350
600
ms
(Note 6)
−0.7
V
0.9
1.3
V
High−Side Clamping Voltage
I(OUTHx) = −50 mA
Power Transistor Body Diode Forward Voltage
If = 500 mA
Logic Inputs (EN, SI, SCLK, CSB)
Input Threshold − High
Input Threshold − Low
−
30
−
−
70
−
%VCC
Input Hysteresis
100
300
600
mV
5.0
10
10
50
50
100
mA
−50
−100
−10
−50
−5.0
−10
mA
−
10
15
pF
VCC – 1.0
VCC – 0.7
−
V
−
0.2
0.4
V
−10
−
10
mA
Input Pulldown Current (EN, SI, SCLK)
Sleep Mode (SI, SCLK)
EN = SI = SCLK = VCC
EN = 0, SI = SCLK = VCC
Input Pullup Current (CSB)
Sleep Mode
CSB = 0 V, EN = VCC
EN = 0 V, VCC = 5 V
Input Capacitance (Note 7)
Logic Output (SO)
Output High
Iout = 1 mA
Output Low
Iout = −1.6 mA
Tri−state Leakage
CSB = VCC, 0 V < SO < VCC
Tri−state Input Capacitance (Note 7)
CSB = VCC, 0 V < VCC < 5.25 V
−
10
15
pF
High Side Turn On Time
Vs = 13.2 V, Rload = 25 W
−
7.5
13
ms
High Side Turn Off Time
Vs = 13.2 V, Rload = 25 W
−
3.0
6.0
ms
Low Side Turn On Time
Vs = 13.2 V, Rload = 25 W
−
6.5
13
ms
Low Side Turn Off Time
Vs = 13.2 V, Rload = 25 W
−
2.0
5.0
ms
High Side Rise Time
Vs = 13.2 V, Rload = 25 W
−
4.0
8.0
ms
High Side Fall Time
Vs = 13.2 V, Rload = 25 W
−
2.0
3.0
ms
Low Side Rise Time
Vs = 13.2 V, Rload = 25 W
−
1.0
2.0
ms
Low Side Fall Time
Vs = 13.2 V, Rload = 25 W
−
1.0
3.0
ms
Non−Overlap Time
High Side Turn Off
To Low Side Turn On
1.5
−
−
ms
Non−Overlap Time
Low Side Turn Off
To High Side Turn On
2.5
−
−
ms
Timing Specifications
4.
5.
6.
7.
Thermal characteristics are not subject to production test.
Production tested @ −40°C, 125°C. Refer to graph 6 for VCC sleep current vs. temperature.
Refer to “Typical High−Side Negative Clamp Voltage Chart,” Figure 5
Not production tested.
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NCV7708
Serial Peripheral Interface
Characteristic
(VCC = 5 V)
Timing
Chart #
Conditions
SCLK Frequency
SCLK Clock Period
VCC = 5 V
VCC = 3.3 V
Maximum Input Capacitance (Note 8)
SI, SCLK
Min
Typ
Max
Unit
−
−
5.0
MHz
200
500
−
−
−
−
ns
−
−
−
12
pF
SCLK High Time
1
85
−
−
ns
SCLK Low Time
2
85
−
−
ns
SCLK Setup Time
3
4
85
85
−
−
−
−
ns
SI Setup Time
11
50
−
−
ns
SI Hold Time
12
50
−
−
ns
CSB Setup Time
5
6
100
100
−
−
−
−
ns
CSB High Time (Note 9)
7
200
−
−
ns
SO enable after CSB falling edge
8
−
−
50
ns
SO disable after CSB rising edge
9
−
−
50
ns
SO Rise Time
Cload = 40 pF
−
−
10
25
ns
SO Fall Time
Cload = 40 pF
−
−
10
25
ns
SO Valid Time
SCLK ↑ to SO 50%
10
−
20
50
ns
8. Not tested in production
9. This is the minimum time the user must wait between SPI commands.
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7
NCV7708
4
7
CSB
6
5
SCLK
3
1
2
CSB
SO
8
9
SI
12
SCLK
11
10
SO
Figure 2. SPI Timing Diagram
SPI Communication
Standard 16−bit communication has been implemented
for the communication of this IC to turn drivers on and off,
and to report faults. (Reference the SPI Communication
Frame Format Diagram). The LSB (Least Significant Bit) is
clocked in first.
Communication is implemented as follows:
1. CSB goes low to allow serial data transfer.
2. A 16 bit word is clocked (SCLK) into the SI
(serial input) pin.
3. CSB goes high to transfer the clocked in
information to the data registers.
(Note: SO is tristate when CSB is high.)
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8
NCV7708
CSB
SI
SRR
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3 OUTL4 OUTH4 OUTL5 OUTH5 OUTL6 OUTH6
OCD
ULD
OVLO
TW
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3 OUTL4 OUTH4 OUTL5 OUTH5 OUTL6 OUTH6
OLD
ULD
PSF
SCLK
SO
Figure 3. SPI Communication Frame Format
The table below defines the programming bits and
diagnostic bits. Fault information is sequentially clocked out
the SO pin of the NCV7708 as programming information is
clocked into the SI pin of the device. Daisy chain
communication between SPI compatible IC’s is possible by
connection of the serial output pin (SO) to the input of the
sequential IC (SI).
Input Data
Bit
Number
Bit Description
Output Data
Bit
Number
Bit Status
15
Over Voltage Lock Out
Control (OVLO)
0 = Disable
14
Under Load Detection Shut
Down Control (ULD)
0 = Disable
13
Over Current Detection Shut
Down Control (OCD)
0 = Disable
12
OUTH6
0 = No Fault
14
Under Load Detect Signal
(ULD)
0 = No Fault
13
Over Load Detect Signal
(OLD)
0 = No Fault
12
OUTH6
11
OUTL6
10
OUTH5
9
OUTL5
8
OUTH4
7
OUTL4
6
OUTH3
5
OUTL3
4
OUTH2
3
OUTL2
2
OUTH1
1
OUTL1
1 = Enable
1 = Enable
1 = On
11
OUTL6
OUTH5
OUTL5
8
OUTH4
OUTH3
OUTL3
4
OUTH2
OUTH1
OUTL1
Status Register Reset (SRR)
0 = Off
0 = Off
0 = Off
0 = Off
1 = On
0 = Off
1 = On
0
0 = Off
1 = On
0 = Off
1 = On
1
0 = Off
1 = On
0 = Off
1 = On
2
0 = Off
1 = On
0 = Off
1 = On
OUTL2
0 = Off
1 = On
0 = Off
1 = On
3
0 = Off
1 = On
0 = Off
1 = On
5
0 = Off
1 = On
0 = Off
1 = On
6
0 = Off
1 = On
0 = Off
1 = On
OUTL4
1 = Fault
1 = On
0 = Off
1 = On
7
1 = Fault
1 = On
0 = Off
1 = On
9
1 = Fault
1 = On
0 = Off
1 = On
10
Bit Status
Power Supply Fail Signal
(OVLO or UVLO = PSF)
1 = Enable
0 = Off
Bit Description
15
0 = Off
1 = On
0 = No Reset
0
1 = Reset
Thermal Warning (TW)
0 = Not in TW
1 = In TW
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NCV7708
DETAILED OPERATING DESCRIPTION
General
initialized in the off (high impedance) condition, and will
remain off regardless of the status of VCC. This allows
power up sequencing of VCC, VS1, and VS2 up to the user.
The voltage on VS1 and VS2 should be operated at the same
potential.
A built−in hysteresis on the under voltage threshold is
included to prevent an unknown region on the power pins.
After a device has powered up and the output drivers are
allowed to turn on, the output drivers will not turn off until
the voltage on the supply pins is reduced from the initial
under voltage threshold, or if shut down by either a SPI
command or a fault condition.
Internal power−up circuitry on the logic supply pin
supports a smooth turn on transition. VCC power up resets
the internal logic such that all output drivers will be off as
power is applied. Exceeding the under voltage lockout
threshold on VCC allows information to be input through the
SPI port for turn on control. Logic information remains
intact over the entire VS1 and VS2 voltage range.
The NCV7708 Double Hex Driver provides drive
capability for 3 independent H−Bridge configurations, or 6
High Side configurations with 6 Low Side configurations, or
any combination of arrangements. Each output drive is
characterized for a 500 mA load and has a typical 1.0 A surge
capability (at 12 V). Strict adherence to integrated circuit die
temperature is necessary. Maximum die temperature is
150°C. This may limit the number of drivers enabled at one
time. Output drive control and fault reporting is handled via
the SPI (Serial Peripheral Interface) port.
An Enable function (EN) provides a low quiescent sleep
current mode when the device is not being utilized. No data
is stored when the device is in sleep mode. A pull down
current source is provided on the EN input to ensure the
device is off if the input signal is lost. Pull down current
sources are also provided on the SI and SCLK inputs. A pull
up current source is provided for the CSB input for the same
reason. A loss of signal pulls the CSB input high to stop any
spurious signals into the SPI port.
Current Limitation
Power Up/Down Control
Input bit 13 (OCD) controls the action of driver shutoff
during current limit. With a 0 for bit 13, there is no driver
shutoff, and the drivers current limit at 3 A. With a 1 for input
bit 13, the output drivers shut off when the shutdown
threshold current is passed. Devices can be turned back on
via the SPI port. Note: high currents could cause a high rise
in die temperature. Devices will not turn on if the die
temperature exceeds the thermal shutdown temperature.
An under voltage lockout circuit prevents the output
drivers from turning on unintentionally. This control is
provided by monitoring the voltages on the VS1, VS2, and
VCC pins. Each analog power pin (VS1 or VS2) powers their
respective output drivers (VS1 powers OUTH1, OUTH2,
OUTH3, all 6 charge pumps and all 6 low side pre−drivers.
VS2 powers OUTH4, OUTH5, and OUTH6). All drivers are
Over Current Detection Shut Down
OCD Input
Bit 13
OUTx OCD
Condition
Output Data Bit 13 Over
Load Detect (OLD) Status
OUTx Status
Current Limit
of all Drivers
0
0
0
0
Unchanged
3A
1
1 (Need SRR to reset)
Unchanged
3A
1
0
0
Unchanged
3A
1
1
1 (Need SRR to reset)
OUTx Latches Off (Need SRR to reset)
3A
Under load Detection
The under−load detection is accomplished by monitoring
the current from each output driver. A minimum load current
(this is the maximum open circuit detection threshold) is
required when the drivers are turned on. If the under−load
circuit detection threshold has been crossed for more than
the under−load delay time, the bit indicator (output bit #14)
for open circuit will be set to a 1. In addition, the offending
driver will be turned off only if input bit 14 (ULD) is set to
1 (true).
Under Load Detection Shut Down
ULD Input
Bit 14
OUTx ULD
Condition
Output Data Bit 14 Under
Load Detect (ULD) Status
OUTx Status
0
0
0
Unchanged
0
1
1 (Need SRR to reset)
Unchanged
1
0
0
Unchanged
1
1
1 (Need SRR to reset)
OUTx Latches Off (Need SRR to reset)
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NCV7708
Over Voltage Shutdown
Over voltage shutdown circuitry monitors the voltage on
the VS1 and VS2 pins. When the Over−voltage Threshold
voltage level has been breached on both or either one of the
VSx supply inputs, output bit 15 will be set and, if input bit
15 (OVLO) is set to 1, all outputs will turn off. Turn on/off
status is maintained in the logic circuitry. When proper input
voltage levels are re−established, the programmed outputs
will turn back on. Over−voltage shutdown can be disabled
by using the SPI input bit 15 (OVLO = 0).
Over Voltage Lock Out (OVLO) Shut Down
OVLO Input Bit 15
VSx OVLO
Condition
Output Data Bit 15 Power
Supply Fail (PSF) Status
OUTx Status
0
0
0
0
Unchanged
1
1 (Need SRR to reset)
Unchanged
1
0
0
Unchanged
1
1
1 (Need SRR to reset)
All Outputs Off (Remain off until VSx is out of OVLO)
Thermal Shutdown
Six independent thermal shutdown circuits are featured
(one common sensor for each HS and LS transistor pair).
Each sensor has two levels, one to give a Thermal Warning
(TW) and a higher one, Over Temperature, which will shut
the drivers off. When the part reaches the temperature point
of Thermal Warning, the output data bit 0 (TW) will be set
to a 1, and the outputs will remain on. With one or more
sensors detecting the over temperature level, all channels
will be turned off simultaneously. All outputs will return to
normal operation when the part thermally recovers
(Thermal toggling), because the over temperature shutdown
does not change the actual channel selection. The output
data bit 0, Thermal Warning, will latch and remain set, even
after cooling, and is reset by using a software command to
input bit 0 (SRR). Since thermal warning precedes a thermal
shutdown, software polling of this bit will allow for load
control and possible prevention of thermal shutdown
conditions.
Thermal warning information can be retrieved
immediately without performing a complete SPI access
cycle. Figure 4 below displays how this is accomplished.
Bringing the CSB pin from a 1 to a 0 condition immediately
displays the information on the output data bit 0, thermal
warning, even in the absence of a SCLK signal. As the
temperature of the NCV7708 changes from a condition from
below the thermal warning threshold to above the thermal
warning threshold, the state of the SO pin changes and this
level is available immediately when the CSB goes to 0. A 0
on SO indicates there is no thermal warning, while a 1
indicates the IC is above the thermal warning threshold. This
warning bit is reset by using the input data bit 0, SRR.
CSB
CSB
SCLK
SCLK
TWH
SO
SO
Tristate Level
Tristate Level
NTW
Thermal Warning High
No Thermal Warning
Figure 4. Access to Temperature warning information shows the thermal information is available immediately
with activation of the CSB signal without having to toggle the SCLK line.
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NCV7708
Typical Operating Characteristics
4.0
VCC SUPPLY CURRENT (mA)
HIGH SIDE CURRENT (A)
−1.2
−1.0
−0.8
−0.6
−0.4
−0.2
3.0
2.0
1.0
0
0
−1.0
−2.0
−3.0
0
−50
−4.0
0
50
100
HIGH SIDE PIN VOLTAGE (V)
TJ, TEMPERATURE (°C)
Figure 5. Typical High−side Negative Clamp
Voltage vs. Reverse Current, Room Temperature
Figure 6. VCC Sleep Supply Current vs.
Temperature
150
Applications Drawing
The applications drawing below displays the range with
which this part can drive a multitude of loads. The dotted line
connecting the outputs exhibits the NCV7708 diversity.
+
1. H−Bridge Driver configuration
2. Low Side Driver
3. High Side Driver
VSx
3
OUTHx
OUTLx
1
2
GND
M
VSx
OUTHx
OUTLx
GND
Figure 7. Application Drawing
Any combination of motors and high side drivers can be designed in. This allows for flexibility in many systems.
H−Bridge Driver Configuration
Overvoltage Clamping − Driving Inductive Loads
The NCV7708 has the flexibility of controlling each
driver independently. When the device is set up in an
H−Bridge configuration, the software design has to take care
of avoiding simultaneous activation of connected HS and LS
transistors. Resulting high shoot through currents could
cause irreversible damage to the device.
To avoid excessive voltages when driving inductive loads
in a single−side−mode (LS or HS switch, no freewheeling
path), external clamping diodes for inductive turn off of the
low side driver must be provided. The maximum clamp
voltage is 48 V. Due to high power dissipation during
clamping, the maximum energy capability of the driver
transistor has to be considered.
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12
NCV7708
Thermal Model
Various copper areas used
for heat spreading
Lead #1
Package Construction
With and Without Mold Compound
Molded as 1/4 Symmetry
Active Area (red)
Lead #8 (one of 8 thermal leads)
110
100
qJA (°C/W)
90
80
70
1 oz
60
2 oz
50
40
0
100 200 300 400 500 600 700 800 900 1000
COPPER AREA (mm2)
Figure 8. qJA vs. Copper Spreader Area
100
Cu_Area = 239 mm2 1 oz
R(t) (°C/W)
10
Cu_Area = 986 mm2 1 oz 1 S
1.0
0.1
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1.0
TIME (sec)
Figure 9. SOIC 28−Lead Single Pulse Heating Curve
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13
10
100
1000
NCV7708
100
R(t) (°C/W)
D = 0.50
10
D = 0.20
D = 0.10
D = 0.05
1.0
D = 0.01
0.1
Cu_Area = 986 mm2 1 oz 1 S
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
PULSE DURATION (sec)
Figure 10. SOIC 28−Lead Thermal Duty Cycle Curves on 1, Spreader Test Board
SOIC 28−lead Thermal RC Network Models
239
mm2
986 mm2
239 mm2
Cauer Network
986 mm2
Foster Network
Cu
Area
C’s
C’s
Units
Tau
Tau
Units
2.68E−05
2.68E−05
W−s/C
1.00E−06
1.00E−06
sec
1.02E−04
1.02E−04
W−s/C
1.00E−05
1.00E−05
sec
2.82E−04
2.84E−04
W−s/C
1.00E−04
1.00E−04
sec
9.58E−04
9.73E−04
W−s/C
5.00E−04
5.00E−04
sec
2.72E−03
2.63E−03
W−s/C
1.00E−03
1.00E−03
sec
2.02E−03
1.95E−03
W−s/C
1.00E−02
1.00E−02
sec
2.93E−02
3.12E−02
W−s/C
8.00E−02
8.00E−02
sec
0.116
0.091
W−s/C
4.00E−01
4.00E−01
sec
0.16
0.21
W−s/C
2.00E+00
2.00E+00
sec
1
1
W−s/C
6.00E+01
5.50E+01
sec
R’s
R’s
R’s
R’s
0.048
0.048
°C/W
2.84E−02
2.84E−02
°C/W
0.115
0.115
°C/W
6.14E−02
6.14E−02
°C/W
0.352
0.349
°C/W
1.94E−01
1.94E−01
°C/W
0.777
0.776
°C/W
0.100
0.100
°C/W
0.599
0.630
°C/W
0.500
0.480
°C/W
1.677
1.667
°C/W
1.839
1.933
°C/W
2.968
3.151
°C/W
2.207
1.836
°C/W
6.424
5.527
°C/W
1.249
2.291
°C/W
6.940
6.689
°C/W
8.225
8.000
°C/W
53.503
36.970
°C/W
59.000
41.000
°C/W
Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items
in the Foster network are computed by the square root of time constant R(t) = 28.4 * sqrt(time(sec)). The constant is derived
based on the active area of the device with silicon and epoxy at the interface of the heat generation.
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NCV7708
The Cauer networks generally have physical significance
and may be divided between nodes to separate thermal
behavior due to one portion of the network from another.
The Foster networks, though when sorted by time constant
(as above) bear a rough correlation with the Cauer networks,
are really only convenient mathematical models. Both
Foster and Cauer networks can be easily implemented using
Junction
R1
C1
R2
C2
circuit simulating tools, whereas Foster networks may be
more easily implemented using mathematical tools (for
instance, in a spreadsheet program), according to the
following formula:
ȍ Ri ǒ1 * e
n
R(t) +
i+1
R3
C3
Rn
Cn
Time constants are not simple RC products. Amplitudes
of mathematical solution are not the resistance values.
Ambient
(thermal ground)
Figure 11. Grounded Capacitor Thermal Network (“Cauer” Ladder)
Junction
R1
C1
R2
C2
R3
C3
Rn
Cn
Each rung is exactly characterized by its RC−product
time constant; amplitudes are the resistances.
Ambient
(thermal ground)
Figure 12. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)
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15
Ǔ
*tńtaui
NCV7708
PACKAGE DIMENSIONS
SOIC−28 WB
CASE 751F−05
ISSUE G
−X−
D
28
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBER
PR5OTRUSION SHALL NOT BE 0.13 TOTATL IN
EXCESS OF B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
15
H
E
0.25
M
Y
M
DIM
A
A1
B
C
D
E
G
H
L
M
−Y−
1
14
PIN 1 IDENT
A
L
0.10
G
B
0.025
M
T X
S
A1
Y
−T−
SEATING
PLANE
MILLIMETERS
MIN
MAX
2.35
2.65
0.13
0.29
0.35
0.49
0.23
0.32
17.80
18.05
7.40
7.60
1.27 BSC
10.05
10.55
0.41
0.90
0_
8_
C
M
S
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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NCV7708/D