TI ISO721MD 3.3-v / 5-v high-speed digital isolator Datasheet

ISO721, ISO721M
ISO722, ISO722M
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SLLS629B – JANUARY 2006 – REVISED MAY 2006
3.3-V / 5-V HIGH-SPEED DIGITAL ISOLATORS
•
FEATURES
•
•
•
•
•
•
4000-V(peak) Isolation
– UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2)
IEC 61010-1 and CSA Approved
– 50 kV/µs Transient Immunity Typical
Signaling Rate 0 Mbps to 150 Mbps
– Low-Propagation Delay
– Low-Pulse Skew (Pulse-Width Distortion)
Low-Power Sleep Mode
High-Electromagnetic Immunity
Low-Input Current Requirement
Failsafe Output
Drop-In Replacement for Most Opto and
Magnetic Isolators
APPLICATIONS
•
•
•
•
Industrial Fieldbus
– Modbus
– Profibus
– DeviceNet™ Data Buses
– Smart Distributed Systems (SDS™)
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
DESCRIPTION
The ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated
by a silicon oxide (SiO2) insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in
conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits
from entering the local ground, and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets
or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to
ensure the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 µs, the input is
assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high
state.
FUNCTION DIAGRAM
DC Channel
Isolation Barrier
+
_
OSC
+
PWM
Vref
_
+
POR
BIAS
Filter
Pulse Width
Demodulation
Carrier Detect
POR
ISO722
Only
IN
Input
+
Filter
+
_
Vref
_
Data MUX
AC Detect
3-State
Output Buffer
EN
OUT
+
AC Channel
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SDS is a trademark of Honeywell.
DeviceNet is a trademark of Open Devicenet Vendors Association, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
ISO721, ISO721M
ISO722, ISO722M
www.ti.com
SLLS629B – JANUARY 2006 – REVISED MAY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The symmetry of the dielectric and capacitor within the integrated circuitry provides for close capacitive
matching, and allows fast transient voltage changes between the input and output grounds without corrupting the
output. The small capacitance and resulting time constant provide for fast operation with signaling rates(1) from 0
Mbps (dc) to 100 Mbps for the ISO721/ISO722, and 0 Mbps to 150 Mbps with the ISO721M/ISO722M.
These devices require two supply voltages of 3.3-V, 5-V, or any combination. All inputs are 5-V tolerant when
supplied from a 3.3-V supply and all outputs are 4-mA CMOS.
The ISO722 and ISO722M devices includes an active-low output enable that when driven to a high-logic level,
places the output in a high-impedance state, and turns off internal bias circuitry to conserve power.
Both the ISO721 and ISO722 have TTL input thresholds and a noise-filter at the input that prevents transient
pulses of up to 2 ns in duration from being passed to the output of the device.
The ISO721M and ISO722M have CMOS VCC/2 input thresholds, but do not have the noise-filter and the
additional propagation delay. These features of the ISO721M also provide for reduced jitter operation.
The ISO721, ISO721M, ISO722, and ISO722M are characterized for operation over the ambient temperature
range of –40°C to 125°C.
(1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in
the units bps (bits per second).
PACKAGE PIN ASSIGMENTS
ISO721D, ISO721MD
(TOP VIEW)
VCC1 3
8 VCC2
7 GND2
VCC1 1
IN 2
6 OUT
VCC1 3
5 GND2
GND1 4
GND1 4
Isolation
IN 2
Isolation
VCC1 1
PACKAGE PIN ASSIGMENTS
ISO722D, ISO722MD
(TOP VIEW)
8 VCC2
7 EN
6 OUT
5 GND2
AVAILABLE OPTIONS
(1)
PRODUCT
OUTPUT
ENABLED
INPUT
THRESHOLDS
NOISE
FILTER
PACKAGE (1)
MARKED
AS
ISO721
NO
TTL
YES
SOIC-8
ISO721
ISO721M
NO
CMOS
NO
SOIC-8
IS721M
ISO722
YES
TTL
YES
SOIC-8
ISO722
ISO722M
YES
CMOS
NO
SOIC-8
IS722M
ORDERING NUMBER
GREEN
ISO721D (rail)
ISO721DR (reel)
ISO721MD (rail)
ISO721MDR (reel)
ISO722D (rail)
Pb Free
Sb/Br Free
ISO722DR (reel)
ISO722MD (rail)
ISO722MDR (reel)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
REGULATORY INFORMATION
VDE
UL
Certified according to IEC 60747-5-2
Recognized under 1577
Component Recognition Program (1)
File Number: 40014131
File Number: 1698195
File Number: E181974
(1)
2
CSA
Approved under CSA Component
Acceptance Notice: CA-5A
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
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ISO721, ISO721M
ISO722, ISO722M
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ABSOLUTE MAXIMUM RATINGS (1)
UNIT
voltage (2),
VCC
Supply
VI
Voltage at IN, OUT, or EN terminal
IO
Output Current
ESD
Electrostatic
discharge
TJ
Maximum junction temperature
(1)
(2)
VCC1, VCC2
–0.5 V to 6 V
–0.5 V to 6 V
±15 mA
Human Body Model
JEDEC Standard 22, Test Method A114-C.01
Charged Device Model
JEDEC Standard 22, Test Method C101
±2 kV
All pins
±1 kV
170°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. Vrms
values are not listed in this publication.
RECOMMENDED OPERATING CONDITIONS
MIN
VCC
Supply voltage, VCC1, VCC2
IOH
MAX
5.5
3
3.6
4
Output current
IOL
TYP
4.5
-4
ISO72x
10
tui
Input pulse width
VIH
High-level input voltage (IN, EN)
VIL
Low-level input voltage (IN, EN)
VIH
High-level input voltage (IN, EN)
VIL
Low-level input voltage (IN, EN)
TJ
Junction temperature
H
External magnetic field intensity per IEC 61000-4-8 and IEC 61000-4-9
certification
ISO72xM
IOS72xM
V
mA
ns
6.67
ISO72x
UNIT
2
VCC
0
0.8
0.7 VCC
VCC
0
0.3 VCC
See the Thermal Characteristics table
V
V
150
°C
1000
A/m
SPECIFICATIONS
UNIT
560
V
After Input/Output Safety Test Subgroup 2/3
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
672
V
Method a, VPR = VIORM × 1.6,
Type and sample test with t = 10 s,
Partial discharge < 5 pC
896
V
Method b1, VPR = VIORM × 1.875,
100 % Production test with t = 1 s,
Partial discharge < 5 pC
1050
V
IEC 60747-5-2 INSULATION CHARACTERISTICS (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIORM
VPR
TEST CONDITIONS
Maximum working insulation voltage
Input to output test voltage
VIOTM
Transient overvoltage
t = 60 s
4000
V
RS
Insulation resistance
VIO = 500 V at TS
>109
Ω
Pollution degree
(1)
2
Climatic Classification 40/125/21
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ISO721, ISO721M
ISO722, ISO722M
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ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC1
TEST CONDITIONS
Quiescent
VCC1 supply current
VI = VCC or 0 V, No load
25 Mbps
ISO722/722M
Sleep Mode
ICC2
VCC2 supply current
VI = VCC or 0 V,
No load
Quiescent
25 Mbps
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
TYP
MAX
0.5
1
2
4
EN at VCC
UNIT
mA
µA
200
EN at 0 V or
ISO721/721M
VI = VCC or 0 V, No load
8
12
10
14
IOH = -4 mA, See Figure 1
VCC – 0.8
4.6
IOH = –20 µA, See Figure 1
VCC – 0.1
5
V
IOL = 4 mA, See Figure 1
0.2
0.4
IOL = 20 µA, See Figure 1
0
0.1
VI(HYS) Input voltage hysteresis
mA
V
150
IIH
High-level input current
EN, IN at 2 V
IIL
Low-level input current
EN, IN at 0.8 V
IOZ
High-impedance output
current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
ISO722, ISO722M
mV
10
µA
–10
EN, IN at VCC
µA
1
25
1
pF
50
kV/µs
SWITCHING CHARACTERISTICS: VCC1 and VCC2 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
13
17
24
Propagation delay, low-to-high-level output
tPHL
Propagation delay , high-to-low-level output
tsk(p)
Pulse skew |tPHL– tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL– tPLH|
tsk(pp) (1)
Part-to-part skew
tr
Output signal rise time
1
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpZH
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
ISO72xM
ISO722
ISO722M
tfs
Failsafe output delay time from input power loss
24
2
8
10
16
8
10
16
0.5
1
0
3
ns
ns
ns
1
6
8
15
ns
3.5
4
8
µs
5.5
8
15
ns
4
5
8
µs
See Figure 4
3
100 Mbps NRZ data input, See Figure 6
2
100 Mbps unrestricted bit run length data
input, See Figure 6
3
150 Mbps NRZ data input, See Figure 6
1
ISO72xM 150 Mbps unrestricted bit run length data
input, See Figure 6
(1)
17
0.5
See Figure 3
Sleep-mode propagation delay,
high-impedance-to-low-level output
Peak-to-peak eye-pattern jitter
13
EN at 0 V,
See Figure 1
UNIT
See Figure 2
tpZL
tjit(PP)
ISO72x
EN at 0 V,
See Figure 1
ISO72x
4
MIN
tPLH
µs
ns
2
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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ISO722, ISO722M
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ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC1
TEST CONDITIONS
Quiescent
VCC1 supply current
VI = VCC or 0 V, No load
25 Mbps
ISO722/722M
Sleep Mode
ICC2
VCC2 supply current
VI = VCC or 0 V,
No load
Quiescent
25 Mbps
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
TYP
MAX
0.5
1
2
4
EN at VCC
UNIT
mA
µA
150
EN at 0 V or
ISO721/721M
VI = VCC or 0 V, No load
4
6.5
5
7.5
IOH = –4 mA, See Figure 1
VCC – 0.4
3
IOH = –20 µA, See Figure 1
VCC – 0.1
3.3
V
IOL = 4 mA, See Figure 1
0.2
0.4
IOL = 20 µA, See Figure 1
0
0.1
VI(HYS) Input voltage hysteresis
mA
V
150
IIH
High-level input current
EN, IN at 2 V
IIL
Low-level input current
EN, IN at 0.8 V
IOZ
High-impedance output
current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
ISO722, ISO722M
mV
10
µA
–10
EN, IN at VCC
µA
1
1
pF
25
40
kV/µs
MIN
TYP
MAX
15
19
30
SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay , high-to-low-level output
tsk(p)
Pulse skew |tPHL– tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL– tPLH|
tsk(pp) (1)
Part-to-part skew
tr
Output signal rise time
2
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpZH
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
ISO72xM
ISO722
ISO722M
30
3
10
12
20
10
12
20
0.5
1
0
5
ns
ns
ns
2
7
11
25
ns
4.5
6
8
µs
7
13
25
ns
4.5
6
8
µs
See Figure 3
tfs
Failsafe output delay time from input power loss
ISO72x
See Figure 4
3
100 Mbps NRZ data input, See Figure 6
2
100 Mbps unrestricted bit run length data
input, See Figure 6
3
150 Mbps NRZ data input, See Figure 6
1
ISO72xM 150 Mbps unrestricted bit run length data
input, See Figure 6
(1)
19
0.5
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-low-level output
Peak-to-peak eye-pattern jitter
15
EN at 0 V,
See Figure 1
EN at 0 V,
See Figure 1
tpZL
tjit(PP)
ISO72x
UNIT
µs
ns
2
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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ISO721, ISO721M
ISO722, ISO722M
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ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC1
TEST CONDITIONS
Quiescent
VCC1 supply current
VI = VCC or 0 V, No load
25 Mbps
ISO722/722M
Sleep Mode
ICC2
VCC2 supply current
VI = VCC or 0 V,
No load
Quiescent
25 Mbps
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
TYP
MAX
0.3
0.5
1
2
EN at VCC
UNIT
mA
µA
200
EN at 0 V or
ISO721/721M
VI = VCC or 0 V, No load
8
12
10
14
IOH = –4 mA, See Figure 1
VCC – 0.8
4.6
IOH = –20 µA, See Figure 1
VCC – 0.1
5
V
IOL = 4 mA, See Figure 1
0.2
0.4
IOL = 20 µA, See Figure 1
0
0.1
VI(HYS) Input voltage hysteresis
mA
V
150
IIH
High-level input current
EN, IN at 2 V
IIL
Low-level input current
EN, IN at 0.8 V
IOZ
High-impedance output
current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
ISO722, ISO722M
mV
10
µA
–10
EN, IN at VCC
µA
1
25
1
pF
40
kV/µs
SWITCHING CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
15
17
30
Propagation delay, low-to-high-level output
tPHL
Propagation delay , high-to-low-level output
tsk(p)
Pulse skew |tPHL– tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL– tPLH|
tsk(pp) (1)
Part-to-part skew
tr
Output signal rise time
1
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpZH
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
ISO72xM
ISO722
ISO722M
tfs
Failsafe output delay time from input power loss
30
2
10
12
21
10
12
21
0.5
1
0
5
ns
ns
ns
1
7
9
15
ns
4.5
5
8
µs
7
9
15
ns
4.5
5
8
µs
See Figure 4
3
100 Mbps NRZ data input, See Figure 6
2
100 Mbps unrestricted bit run length data
input, See Figure 6
3
150 Mbps NRZ data input, See Figure 6
1
ISO72xM 150 Mbps unrestricted bit run length data
input, See Figure 6
(1)
17
0.5
See Figure 3
Sleep-mode propagation delay,
high-impedance-to-low-level output
Peak-to-peak eye-pattern jitter
15
EN at 0 V,
See Figure 1
UNIT
See Figure 2
tpZL
tjit(PP)
ISO72x
EN at 0 V,
See Figure 1
ISO72x
6
MIN
tPLH
µs
ns
2
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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ISO722, ISO722M
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ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC1
TEST CONDITIONS
Quiescent
VCC1 supply current
VI = VCC or 0 V, No load
25 Mbps
ISO722/722M
Sleep Mode
ICC2
VCC2 supply current
VI = VCC or 0 V,
No load
Quiescent
25 Mbps
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
TYP
MAX
0.3
0.5
1
2
EN at VCC
UNIT
mA
µA
150
EN at 0 V or
ISO721/721M
VI = VCC or 0 V, No load
4
6.5
5
7.5
IOH = –4 mA, See Figure 1
VCC – 0.4
3
IOH = –20 µA, See Figure 1
VCC – 0.1
3.3
V
IOL = 4 mA, See Figure 1
0.2
0.4
IOL = 20 µA, See Figure 1
0
0.1
VI(HYS) Input voltage hysteresis
mA
V
150
IIH
High-level input current
EN, IN at 2 V
IIL
Low-level input current
EN, IN at 0.8 V
IOZ
High-impedance output
ISO722, ISO722M
current
EN, IN at VCC
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
mV
10
µA
–10
µA
1
25
1
pF
40
kV/µs
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
17
20
34
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay , high-to-low-level output
tsk(p)
Pulse skew |tPHL– tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL– tPLH|
tsk(pp) (1)
Part-to-part skew
tr
Output signal rise time
2
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpZH
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
ISO72xM
ISO722
ISO722M
34
3
10
12
25
10
12
25
0.5
1
0
5
ns
ns
ns
2
7
13
25
ns
5
6
8
µs
7
13
25
ns
5
6
8
µs
See Figure 3
tfs
Failsafe output delay time from input power loss
ISO72x
See Figure 4
3
100 Mbps NRZ data input, See Figure 6
2
100 Mbps unrestricted bit run length data
input, See Figure 6
3
150 Mbps NRZ data input, See Figure 6
1
ISO72xM 150 Mbps unrestricted bit run length data
input, See Figure 6
(1)
20
0.5
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-low-level output
Peak-to-peak eye-pattern jitter
17
EN at 0 V,
See Figure 1
EN at 0 V,
See Figure 1
tpZL
tjit(PP)
ISO72x
UNIT
µs
ns
2
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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ISO722, ISO722M
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ISOLATION BARRIER
PARAMETER MEASUREMENT INFORMATION
IN
+
Input
Generator
VI
50 W
-
NOTE A
VCC1
IO
OUT
VCC1/2
VI
0V
EN
tPHL
VOH
tPLH
+
ISO722
and
ISO722M
VCC1/2
CL
Note B
VO
-
90%
50%
VO
50%
10%
VOL
tf
tr
3V
ISOLATION BARRIER
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
IN
Input
Generator
NOTE A
VO
OUT
VCC2
VI
VCC2/2
0V
EN
tPZH
RL = 1 kW ±1 %
CL
NOTE B
+
VOH
50%
VO
VI
VCC2/2
50 W
0.5 V
0V
tPHZ
-
Figure 2. ISO722 Sleep-Mode High-Level Output Test Circuit and Voltage Waveforms
0V
ISOLATION BARRIER
VCC2
IN
Input
Generator
NOTE A
RL = 1 kW ±1%
OUT
VO
EN
VCC2/2
VCC2/2
0V
tPZL
VO
CL
NOTE B
+
VI
VCC2
VI
tPLZ
50%
VOL
50 W
-
Figure 3. ISO722 Sleep-Mode Low-Level Output Test Circuit and Voltage Waveforms
NOTE:
A: The input pulse is supplied by a generator having the following characteristics:
•
PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B: CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
8
VCC2
0.5 V
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SLLS629B – JANUARY 2006 – REVISED MAY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
VCC1
0V
IN
ISOLATION BARRIER
VI
VCC1
VI
OUT
VO
0V
tfs
VO
CL
15 pF
±20%
EN
ISO722
and
ISO722M
2.7 V
VOH
50%
VOL
NOTE: VI transition time is 100 ns
VCC1
IN
VCC
or
0V
CI = 0.1 mF,
GND1
ISOLATION BARRIER
Figure 4. Failsafe Delay Time Test Circuit and Voltage Waveforms
VCC2
OUT
GND2
±1%
CL
15 pF
±20%
VO
VCM
NOTE: Pass/Fail criteria is no change in VO.
Figure 5. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
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ISO721, ISO721M
ISO722, ISO722M
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SLLS629B – JANUARY 2006 – REVISED MAY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Tektronix
HFS9009
Tektronix
784D
PATTERN
GENERATOR
VCC1
In p u t
0V
O u tp u t
VCC2/2
J itte r
NOTE: Bit pattern run length is 216 - 1. Transition Time is 800 ps. NRZ data input has no more than five consecutive
1s or 0s.
Figure 6. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
10
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ISO722, ISO722M
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SLLS629B – JANUARY 2006 – REVISED MAY 2006
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
L(101) Minimum air gap (Clearance)
(1)
L(102) Minimum external tracking (Creepage)
MIN
TYP
MAX
UNIT
Shortest terminal to terminal distance through air
4.8
mm
Shortest terminal to terminal distance across the
package surface
4.3
mm
Tracking resistance (comparative tracking
index)
DIN IEC 60112/VDE 0303 Part 1
≥ 175
V
Minimum internal gap (internal clearance)
Distance through insulation
0.008
mm
RIO
Isolation resistance
Input to output, VIO = 500 V, all pins on each side
of the barrier tied together creating a two-terminal
device
CIO
Barrier capacitance
Input-to-output
CI
Input capacitance to ground
CTI
(1)
>1012
Ω
VI = 0.4 sin (4E6πt)
1
pF
VI = 0.4 sin (4E6πt)
1
pF
Creepage and clearance requirements are applied according to the specific equipment isolation standards of an application. Care should
be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation
Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
IEC 60664-1 RATINGS TABLE
PARAMETER
TEST CONDITIONS
Basic isolation group
Installation classification
SPECIFICATION
Material group
IIIa
Rated mains voltage ≤150 VRMS
I-IV
Rated mains voltage ≤300 VRMS
I-III
DEVICE I/O SCHEMATIC
Equivalent Input and Output Schematic Diagrams
Enable
Input
Output
VCC2
VCC2
VCC1
VCC2
VCC1
1 MW
500 W
VCC1
8W
OUT
500 W
EN
IN
13 W
1 MW
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ISO721, ISO721M
ISO722, ISO722M
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SLLS629B – JANUARY 2006 – REVISED MAY 2006
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply, and without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply current
TS
Maximum case temperature
MIN
TYP
MAX
θJA = 263°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
100
θJA = 263°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
153
150
UNIT
mA
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The junction-to-air thermal resistance in the Thermal
Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test
Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input
voltage times the current. The junction temperature is then the ambient temperature plus the power times the
junction-to-air thermal resistance.
THERMAL CHARACTERISTICS
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low-K Thermal Resistance (1)
263
°C/W
High-K Thermal Resistance (1)
θJA
Junction-to-Air
125
°C/W
θJB
Junction-to-Board Thermal
Resistance
44
°C/W
θJC
Junction-to-Case Thermal
Resistance
75
°C/W
VCC1 = VCC2 = 5.5 V, TJ = 150°C,
CL = 15 pF, Input a 100 Mbps 50% duty
cycle square wave
159
VCC1 = VCC2 = 5.5 V, TJ = 150°C,
ISO72xM CL = 15 pF, Input a 150 Mbps 50% duty
cycle square wave
195
ISO72x
PD
(1)
Device Power Dissipation
mW
Tested in accordance with the Low-K or High-K thermal metric definition of EIA/JESD51-3 for leaded surface mount packages.
200
Safety Limiting Current − mA
175
VCC1 = 3.6 V,
VCC2 = 3.6 V
150
125
VCC1 = 5.5 V,
VCC2 = 5.5 V
100
75
50
25
0
0
50
100
150
200
o
Case Temperature − C
Figure 7. θJC THERMAL DERATING CURVE per IEC 60747-5-2
12
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ISO722, ISO722M
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FUNCTION TABLE
ISO721 (1)
(1)
VCC1
VCC2
PU
PU
PD
PU
INPUT
(IN)
OUTPUT
(OUT)
H
H
L
L
Open
H
X
H
PU = Powered Up (VCC ≥ 3 V); PD = Powered Down (VCC ≤ 2.5 V); X = Irrelevant; H = High Level;
L = Low Level
ISO722 (1)
VCC1
(1)
VCC2
INPUT
(IN)
ISO722/ISO722M
OUTPUT ENABLE (EN)
OUTPUT
(OUT)
H
L or Open
H
L
L or Open
L
X
H
Z
PU
PU
Open
L or Open
H
PD
PU
X
L or Open
H
PD
PU
X
H
Z
PU = Powered Up (VCC ≥ 3 V); PD = Powered Down (VCC ≤ 2.5 V); X = Irrelevant; Z = High Impedance; H = High Level; L = Low Level
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ISO721, ISO721M
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SLLS629B – JANUARY 2006 – REVISED MAY 2006
TYPICAL CHARACTERISTICS
RMS SUPPLY CURRENT vs SIGNALING RATE
RMS SUPPLY CURRENT vs SIGNALING RATE
10
15
VCC1 = 3.3 V,
VCC2 = 3.3 V,
TA = 25oC,
CL = 15 pF
8
VCC1 = 5 V,
VCC2 = 5 V,
TA = 25oC,
CL = 15 pF
14
13
ICC − Supply Current − (mARMS)
ICC − Supply Current − (mARMS)
9
7
6
ICC2
5
4
3
ICC1
2
12
11
10
ICC2
9
8
7
ICC1
6
5
4
3
2
1
1
0
0
0
25
50
75
100
0
25
Signaling Rate (Mbps)
PROPAGATION DELAY vs FREE-AIR TEMPERATURE
PROPAGATION DELAY vs FREE-AIR TEMPERATURE
20
16
tPLH
15
tPHL
ISO72xM
10
VCC1 = 3.3 V,
VCC2 = 3.3 V,
CL = 15 pF,
Air Flow at 7 cf/m
5
-10
5
20
35
50
80
65
95
Propagation Delay − ns
20
-25
ISO72x
tPHL
tPHL
ISO72x
0
-40
tPLH
18
tPLH
Propagation Delay − ns
100
Figure 9.
25
14
tPLH
12
tPHL
10
8
ISO72xM
6
VCC1 = 5 V,
VCC2 = 5 V,
CL = 15 pF,
Air Flow at 7 cf/m
4
2
0
-40
110 125
-25
-10
o
20
35
50
80
65
95
110 125
TA − Free-Air Temperature − C
Figure 10.
Figure 11.
ISO72x INPUT THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
ISO72xM INPUT THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
1.4
2.5
5-V (VIT+)
2.4
1.3
3.3-V (VIT+)
1.25
1.2
Air Flow at 7 cf/m
1.15
5-V (VIT- )
1.1
VIT − Input Voltage Threshold − V
1.35
5-V (VIT+)
2.3
2.2
5-V (VIT-)
2.1
2
Air Flow at 7 cf/m
1.9
1.8
3.3-V (VIT+)
1.7
1.6
1.05
3.3-V (VIT- )
1
-40
5
o
TA − Free-Air Temperature − C
VIT − Input Voltage Threshold − V
75
Figure 8.
30
-25
-10
5
20
35
50
3.3-V (VIT-)
1.5
80
65
95
110 125
1.4
-40
o
-25
-10
5
20
35
50
80
65
o
TA − Free-Air Temperature − C
TA − Free-Air Temperature − C
Figure 12.
14
50
Signaling Rate (Mbps)
Figure 13.
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110 125
ISO721, ISO721M
ISO722, ISO722M
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SLLS629B – JANUARY 2006 – REVISED MAY 2006
TYPICAL CHARACTERISTICS (continued)
HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT
VOLTAGE
-80
2.9
-70
IOH − High-Level Output Current − mA
2.92
Vfs+
2.88
VCC = 5 V or 3.3 V,
CL = 15 pF,
Air Flow at 7 cf/m
2.86
2.84
2.82
Vfs-
2.8
2.78
-40
o
TA = 25 C
VCC = 5 V
-60
-50
-40
VCC = 3.3 V
-30
-20
-10
0
-25
-10
5
20
35
50
80
65
95
0
110 125
1
2
3
4
5
6
VOH − High-Level Output Voltage − V
o
TA − Free-Air Temperature − C
Figure 14.
Figure 15.
LOW-LEVEL OUTPUT CURRENT vs
LOW-LEVEL OUTPUT VOLTAGE
70
o
TA = 25 C
IOL − Low-Level Output Current − mA
VCC1 Failsafe Voltage − V
VCC1 FAILSAFE THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
60
VCC = 5 V
50
40
30
VCC = 3.3 V
20
10
0
0
1
2
3
4
5
VOL − Low-Level Output Voltage − V
Figure 16.
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ISO721, ISO721M
ISO722, ISO722M
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SLLS629B – JANUARY 2006 – REVISED MAY 2006
APPLICATION INFORMATION
MANUFACTURER CROSS-REFERENCE DATA
The ISO72xx isolators have the same functional pin-out as most other vendors, and they are often pin-for-pin
drop-in replacements. The notable differences in the products are propagation delay, signaling rate, power
consumption, and transient protection rating. Table 1 is used as a guide for replacing other isolators with the
ISO72x family of single channel isolators.
GND1 4
IN 2
VCC1 3
6 OUT
6 OUT
5 GND2
GND1 4
5 GND2
8 VCC2
7 GND2
VI 2
VDD1 3
GND1 4
VI 2
*
3
GND1 4
IL710
8 VDD2
7 NC
VDD1 1
VI 2
6 VO
5 GND2
NC 3
GND1 4
Isolation
VCC1 1
VDD1 1
8 VDD2
7 GND2
6 VO
5 GND2
Isolation
8 VCC2
7 EN
Isolation
IN 2
VCC1 3
Isolation
VCC1 1
HCPL-xxxx
ADuM1100
VDD1 1
Isolation
ISO721
or
ISO721M
ISO722
or
ISO722M
8 VDD2
7 VOE
6 VO
5 GND2
Figure 17. Pin Cross Reference
Table 1. CROSS REFERENCE
PIN 7
ISOLATOR
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
ISO721
OR
ISO721M
ISO721 (1) (2)
VCC1
IN
VCC1
GND1
GND2
OUT
GND2
ADuM1100 (1) (2)
VDD1
VI
VDD1
GND1
GND2
VO
GND2
VDD2
HCPL-xxxx
VDD1
VI
*Leave
Open (3)
GND1
GND2
VO
NC (4)
VDD2
IL710
VDD1
VI
NC (5)
GND1
GND2
VO
VOE
VDD2
(1)
(2)
(3)
(4)
(5)
PIN 8
EN
VCC2
The ISO72xx pin 1 and pin 3 are internally connected together. Either or both may be used as VCC1.
The ISO721 and ISO721M pin 5 and pin 7 are internally connected together. Either or both may be used as GND2.
Pin 3 of the HCPL devices must be left open. This is not a problem when substituting an ISO72xx device since the extra VCC1 on pin 3
may be left an open circuit as well.
An HCPL device PIN 7 must be left floating (open) or grounded when an ISO722 or ISO722M device is to be used as a drop-in
replacement. If pin 7 of the ISO722 or ISO722M device is placed in a high logic state, the output of the device is disabled
Pin 3 of the IL710 must not be tied to ground on the circuit board since this shorts the ISO72xx's VCC1 to ground. The IL710 pin 3 may
only be tied to VCC or left open to drop in an ISO72xx.
VCC1
0.1 mF
VCC2
ISO721
or ISO721M
0.001 mF
INPUT
2
3
4
0.001 mF
0.1 mF
8
1
7
IN
OUT
6
OUTPUT
5
GND1
GND2
Figure 18. Basic Application Circuit
16
ISO722
OR
ISO722M
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SLLS629B – JANUARY 2006 – REVISED MAY 2006
ISOLATION GLOSSARY
Creepage Distance— The shortest path between two conductive input to output leads measured along the
surface of the insulation. The shortest distance path is found around the end of the package body.
Clearance— The shortest distance between two conductive input to output leads measured through air (line of
sight).
Input-to Output Barrier Capacitance -- The total capacitance between all input terminals connected together,
and all output terminals connected together.
Input-to Output Barrier Resistance -- The total resistance between all input terminals connected together, and
all output terminals connected together.
Primary Circuit -- An internal circuit directly connected to an external supply mains or other equivalent source
which supplies the primary circuit electric power.
Secondary Circuit -- A circuit with no direct connection to primary power, and derives its power from a separate
isolated source.
Comparative Tracking Index (CTI) -- CTI is an index used for electrical insulating materials which is defined as
the numerical value of the voltage which causes failure by tracking during standard testing. Tracking is the
process that produces a partially conducting path of localized deterioration on or through the surface of an
insulating material as a result of the action of electric discharges on or close to an insulation surface -- the
higher CTI value of the insulating material, the smaller the minimum creepage distance.
Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may
arise from flashover or from the progressive degradation of the insulation surface by small localized sparks.
Such sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The
resulting break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric
spark is generated. These sparks often cause carbonization on insulation material and lead to a carbon track
between points of different potential. This process is known as tracking.
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SLLS629B – JANUARY 2006 – REVISED MAY 2006
ISOLATION GLOSSARY (continued)
Insulation:
Operational insulation -- Insulation needed for the correct operation of the equipment.
Basic insulation -- Insulation to provide basic protection against electric shock.
Supplementary insulation -- Independent insulation applied in addition to basic insulation in order to ensure
protection against electric shock in the event of a failure of the basic insulation.
Double insulation -- Insulation comprising both basic and supplementary insulation.
Reinforced insulation -- A single insulation system which provides a degree of protection against electric shock
equivalent to double insulation.
Pollution Degree:
Pollution Degree 1 -- No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence.
Pollution Degree 2 -- Normally, only nonconductive pollution occurs. However, a temporary conductivity caused
by condensation must be expected.
Pollution Degree 3 -- Conductive pollution occurs or dry nonconductive pollution occurs which becomes
conductive due to condensation which is to be expected.
Pollution Degree 4– Continuous conductivity occurs due to conductive dust, rain, or other wet conditions.
Installation Category:
Overvoltage Category -- This section is directed at insulation co-ordination by identifying the transient
overvoltages which may occur, and by assigning 4 different levels as indicated in IEC 60664.
I: Signal Level -- Special equipment or parts of equipment.
II: Local Level -- Portable equipment etc.
III: Distribution Level -- Fixed installation
IV: Primary Supply Level -- Overhead lines, cable systems
Each category should be subject to smaller transients than the category above.
18
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PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ISO721D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO721DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO721DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO721DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO721MD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO721MDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO721MDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO721MDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO722D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO722DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO722DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO722DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO722MD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO722MDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO722MDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ISO722MDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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