LM2743
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SNVS276G – APRIL 2004 – REVISED MARCH 2013
LM2743 Low Voltage N-Channel MOSFET Synchronous Buck Regulator Controller
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FEATURES
DESCRIPTION
•
•
•
•
•
The LM2743 is a high-speed synchronous buck
regulator controller with an accurate feedback voltage
accuracy of ±2%. It can provide simple down
conversion to output voltages as low as 0.6V. Though
the control sections of the IC are rated for 3 to 6V,
the driver sections are designed to accept input
supply rails as high as 16V. The use of adaptive nonoverlapping MOSFET gate drivers helps avoid
potential shoot-through problems while maintaining
high efficiency. The IC is designed for the more costeffective option of driving only N-channel MOSFETs
in both the high-side and low-side positions. It senses
the low-side switch voltage drop for providing a
simple, adjustable current limit.
1
2
•
•
•
•
•
•
Power Stage Input Voltage from 1V to 16V
Control Stage Input Voltage from 3V to 6V
Output Voltage Adjustable down to 0.6V
Power Good Flag and Shutdown
Output Over-Voltage and Under-Voltage
Detection
±2% Feedback Voltage Accuracy Over
Temperature
Low-Side Adjustable Current Sensing
Adjustable Soft-Start
Tracking and Sequencing with Shutdown and
Soft-Start Pins
Switching Frequency from 50 kHz to 1 MHz
TSSOP-14 Package
The fixed-frequency voltage-mode PWM control
architecture is adjustable from 50 kHz to 1 MHz with
one external resistor. This wide range of switching
frequency gives the power supply designer the
flexibility to make better tradeoffs between
component size, cost and efficiency.
APPLICATIONS
•
•
•
•
•
3.3V Buck Regulation
Cable Modem, DSL and ADSL
Laser Jet and Ink Jet Printers
Low Voltage Power Modules
DSP, ASIC, Core and I/O
Features include soft-start, input under-voltage
lockout (UVLO) and Power Good (based on both
under-voltage and over-voltage detection). In
addition, the shutdown pin of the IC can be used for
providing startup delay, and the soft-start pin can be
used for implementing precise tracking, for the
purpose of sequencing with respect to an external
rail.
Typical Application
VCC = 3.3V
RCC
VIN = 3.3V
D1
CBOOT
RPULL-UP
VCC
BOOT
PWGD
CSS
RCS
L1
VOUT = 1.2V@4A
ISEN
LM2743
FREQ
RFADJ
CIN1,2
HG
SD
CCC
+
Q1
LG
SS/TRACK
PGND
SGND
PGND
EAO
FB
RFB2
RC2
CC3
+
CO1,2
RFB1
CC1
CC2
RC1
Figure 1. Typical Application Circuit
1
2
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM2743
SNVS276G – APRIL 2004 – REVISED MARCH 2013
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Connection Diagram
1
2
3
5
6
7
HG
LG
PGND
SGND
VCC
PWGD
ISEN
PGND
LM2743
4
BOOT
SD
FREQ
FB
SS/TRACK
EAO
14
13
12
11
10
9
8
Figure 2. 14-Lead Plastic TSSOP
θJA = 155°C/W
Pin Descriptions
BOOT (Pin 1) - Bootstrap pin. This is the supply rail for the gate drivers. When the high-side MOSFET turns on, the voltage on this pin
should be at least one gate threshold above the regulator input voltage VIN to properly turn on the MOSFET. See MOSFET GATE
DRIVERS in the Application Information section for more details on how to select MOSFETs.
LG (Pin 2) - Low-gate drive pin. This is the gate drive for the low-side N-channel MOSFET. This signal is interlocked with the high-side gate
drive HG (Pin 14), so as to avoid shoot-through.
PGND (Pins 3, 13) - Power ground. This is also the ground for the low-side MOSFET driver. Both the pins must be connected together on
the PCB and form a ground plane, which is usually also the system ground.
SGND (Pin 4) - Signal ground. It should be connected appropriately to the ground plane with due regard to good layout practices in
switching power regulator circuits.
VCC (Pin 5) Supply rail for the control sections of the IC.
PWGD (Pin 6) - Power Good pin. This is an open drain output, which is typically meant to be connected to VCC or any other low voltage
source through a pull-up resistor. Choose the pull-up resistor so that the current going into this pin is kept below 1 mA. For most
applications a recommended value for the pull-up resistor is 100 kΩ. The voltage on this pin is thus pulled low under output under-voltage
or over-voltage fault conditions and also under input UVLO.
ISEN (Pin 7) - Current limit threshold setting pin. This sources a fixed 40 µA current. A resistor of appropriate value should be connected
between this pin and the drain of the low-side MOSFET (switch node).
EAO (Pin 8) - Output of the error amplifier. The voltage level on this pin is compared with an internally generated ramp signal to determine
the duty cycle. This pin is necessary for compensating the control loop.
SS/TRACK (Pin 9) - Soft-start and tracking pin. This pin is internally connected to the non-inverting input of the error amplifier during softstart, and in fact any time the SS/TRACK pin voltage happens to be below the internal reference voltage. For the basic soft-start function, a
capacitor of minimum value 1 nF is connected from this pin to ground. To track the rising ramp of another power supply’s output, connect a
resistor divider from the output of that supply to this pin as described in Application Information.
FB (Pin 10) - Feedback pin. This is the inverting input of the error amplifier, which is used for sensing the output voltage and compensating
the control loop.
FREQ (Pin 11) - Frequency adjust pin. The switching frequency is set by connecting a resistor of suitable value between this pin and
ground. The equation for calculating the exact value is provided in Application Information, but some typical values (rounded up to the
nearest standard values) are 324 kΩ for 100 kHz, 97.6 kΩ for 300 kHz, 56.2 kΩ for 500 kHz, 24.9 kΩ for 1 MHz.
SD (Pin 12) - IC shutdown pin. Pull this pin to VCC to ensure the IC is enabled. Connect to ground to disable the IC. Under shutdown, both
high-side and low-side drives are off. This pin also features a precision threshold for power supply sequencing purposes, as well as a low
threshold to ensure minimal quiescent current.
HG (Pin 14) - High-gate drive pin. This is the gate drive for the high-side N-channel MOSFET. This signal is interlocked with LG (Pin 2) to
avoid shoot-through.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings (1) (2)
VCC
-0.3 to 7V
BOOT Voltage
-0.3 to 21V
ISEN
-0.3 to 9.5V
All other pins
-0.3 to VCC + 0.3V
Junction Temperature
150°C
Storage Temperature
−65°C to 150°C
Soldering Information
Lead Temperature (soldering, 10sec)
260°C
Infrared or Convection (20sec)
235°C
ESD Rating (3)
(1)
(2)
(3)
2 kV
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for
which the device operates correctly. Operating Ratings do not imply specified performance limits.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Operating Ratings
Supply Voltage Range (VCC)
3V to 6V
−40°C to +125°C
Junction Temperature Range (TJ)
Thermal Resistance (θJA)
155°C/W
Electrical Characteristics (1)
VCC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= 25°C. Limits appearing in
boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are specified by design,
test, or statistical analysis.
Symbol
Parameter
Conditions
VFB
FB Pin Voltage
VCC = 3V to 6V
VON
UVLO Thresholds
Rising
Falling
IQ_VCC
Operating VCC Current
Min
Typ
Max
Units
0.588
0.6
0.612
V
2.76
2.42
V
VCC = 3.3V, VSD = 3.3V
Fsw = 600kHz
1.0
1.5
2.1
VCC = 5V, VSD = 3.3V
Fsw = 600kHz
1.0
1.7
2.1
110
185
Shutdown VCC Current
VCC = 3.3V, VSD = 0V
tPWGD1
PWGD Pin Response Time
VFB Rising
tPWGD2
PWGD Pin Response Time
VFB Falling
ISS-ON
SS Pin Source Current
VSS = 0V
ISS-OC
SS Pin Sink Current During Over
Current
VSS = 2.5V
ISEN-TH
ISEN Pin Source Current Trip Point
mA
6
µs
6
7
10
µs
14
90
25
40
µA
µA
µA
55
µA
ERROR AMPLIFIER
GBW
(1)
Error Amplifier Unity Gain
Bandwidth
9
MHz
G
Error Amplifier DC Gain
106
dB
SR
Error Amplifier Slew Rate
3.2
V/µs
IEAO
EAO Pin Current Sourcing and
Sinking Capability
VEAO = 1.5, FB = 0.55V
VEAO = 1.5, FB = 0.65V
2.6
9.2
mA
VEA
Error Amplifier Output Voltage
Minimum
1
V
Maximum
2
V
The power MOSFETs can run on a separate 1V to 16V rail (Input voltage, VIN). Practical lower limit of VIN depends on selection of the
external MOSFET.
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Electrical Characteristics(1) (continued)
VCC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= 25°C. Limits appearing in
boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are specified by design,
test, or statistical analysis.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
18
90
µA
GATE DRIVE
IQ-BOOT
BOOT Pin Quiescent Current
VBOOT = 12V, VSD = 0
RHG_UP
High-Side MOSFET Driver Pull-Up
VBOOT = 5V @ 350mA Sourcing
ON resistance
3
Ω
RHG_DN
High-Side MOSFET Driver PullDown ON resistance
HG = 5V @ 350mA Sourcing
2
Ω
RLG_UP
Low-Side MOSFET Driver Pull-Up
ON resistance
VBOOT = 5V @ 350mA Sourcing
3
Ω
RLG_DN
Low-Side MOSFET Driver PullDown ON resistance
LG = 5V @ 350mA Sourcing
2
Ω
OSCILLATOR
fSW
PWM Frequency
RFADJ = 702.1 kΩ
50
RFADJ = 98.74 kΩ
300
RFADJ = 45.74 kΩ
475
RFADJ = 24.91 kΩ
D
Max High-Side Duty Cycle
600
725
kHz
1000
fSW = 300kHz
fSW = 600kHz
fSW = 1MHz
80
76
73
%
LOGIC INPUTS AND OUTPUTS
4
V STBY-IH
Standby High Trip Point
VFB = 0.575V, VBOOT = 3.3V, VSD
Rising
V STBY-IL
Standby Low Trip Point
VFB = 0.575V, VBOOT = 3.3V, VSD
Falling
V SD-IH
SD Pin Logic High Trip Point
VSD Rising
V SD-IL
SD Pin Logic Low Trip Point
VSD Falling
0.8
VPWGD-TH-LO
PWGD Pin Trip Points
FB Falling
0.408
0.434
0.457
V
VPWGD-TH-HI
PWGD Pin Trip Points
FB Rising
0.677
0.710
0.742
V
VPWGD-HYS
PWGD Hysteresis
FB Falling
FB Rising
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1.1
0.232
V
V
1.3
V
V
60
90
mV
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Typical Performance Characteristics
Efficiency (VOUT = 1.2V)
VCC = 3.3V, fSW = 300 kHz
Efficiency (VOUT = 2.5V)
VCC = 3.3V, fSW = 300 kHz
100
100
VIN = 3.3V
90
90
70
80
EFFICIENCY (%)
EFFICIENCY (%)
80
VIN = 12V
VIN = 5V
60
50
70
VIN = 3.3V
60
VIN = 5V
50
40
40
30
30
20
VIN = 12V
20
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 3.
Figure 4.
Efficiency (VOUT = 3.3V)
VCC = 5V, fSW = 300 kHz
VCC Operating Current plus BOOT Current
vs
Frequency
FDS6898A FET (TA = 25°C)
100
25
VCC OPERATING CURRENT
EFFICIENCY (%)
80
70
VIN = 5V
60
50
VIN = 12V
40
30
PLUS BOOT CURRENT (mA)
90
19
13
20
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
0
0.05
OUTPUT CURRENT (A)
0.25
0.45
0.65
0.85
1.05
FREQUENCY (MHz)
Figure 5.
Figure 6.
BOOT Pin Current
vs
Temperature for BOOT Voltage = 3.3V
fSW = 300 kHz, FDS6898A FET, No-Load
BOOT Pin Current
vs
Temperature for BOOT Voltage = 5V
fSW = 300 kHz, FDS6898A FET, No-Load
6.7
10
6.6
9.9
BOOT PIN CURRENT (mA)
BOOT PIN CURRENT (mA)
6
6.5
6.4
6.3
6.2
6.1
9.8
9.7
9.6
9.5
9.4
6
5.9
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (oC)
9.3
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (oC)
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
BOOT Pin Current
vs
Temperature for BOOT Voltage = 12V
fSW = 300 kHz, FDS6898A FET, No-Load
Internal Reference Voltage
vs
Temperature
24.9
0.2
0.1
24.7
INTERNAL REFERENCE
VOLTAGE ('%)
BOOT PIN CURRENT (mA)
24.8
24.6
24.5
24.4
24.3
24.2
24.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
24
23.9
-40 -25 -10 5 20 35 50 65 80 95 110125
-0.6
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (oC)
TEMPERATURE (oC)
Figure 9.
Figure 10.
Frequency
vs
Temperature
Output Voltage
vs
Output Current
1.210
640
1.209
1.208
OUTPUT VOLTAGE (V)
FREQUENCY (kHz)
620
600
580
560
1.207
1.206
1.205
1.204
1.203
1.202
540
1.201
520
-55 -35 -15
5
25
45
65 85 105 125
1.200
0
TEMPERATURE (oC)
0.4 0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
OUTPUT CURRENT (A)
Figure 11.
Figure 12.
Switch Waveforms (HG Rising)
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
IOUT = 4A, CSS = 12nF, fSW = 300 kHz
Switch Waveforms (HG Falling)
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
IOUT = 4A, CSS = 12nF, fSW = 300 kHz
1V/div
HG
LG
2V/div
1V/div
2V/div
HG
LG
SW
SW
5V/div
5V/div
100 ns/DIV
100 ns/DIV
Figure 13.
6
4
Figure 14.
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Typical Performance Characteristics (continued)
Start-Up (No-Load)
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
CSS = 12nF, fSW = 300 kHz
Start-Up (Full-Load)
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
IOUT = 4A, CSS = 12nF, fSW = 300 kHz
Figure 15.
Figure 16.
Shutdown (Full-Load)
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
IOUT = 4A, CSS = 12nF, fSW = 300 kHz
Load Transient Response (IOUT = 0A to 4A)
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
CSS = 12nF, fSW = 300 kHz
VOUT
50 mV/div
2A/div
IOUT
40 Ps/DIV
Figure 17.
Figure 18.
Load Transient Response (IOUT = 4A to 0A)
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
CSS = 12nF, fSW = 300 kHz
Load Transient Response
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
CSS = 12nF, fSW = 300 kHz
VOUT
VOUT
20 mV/div
20mV/div
IOUT
2A/div
2A/div
IOUT
40 Ps/DIV
100 Ps/DIV
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
Line Transient Response (VIN = 3V to 9V)
VCC = 3.3V, VOUT = 1.2V
IOUT = 2A, fSW = 300 kHz
Line Transient Response (VIN = 9V to 3V)
VCC = 3.3V, VOUT = 1.2V
IOUT = 2A, fSW = 300 kHz
100mV/div
100 mV/div
VOUT
VOUT
5V/div
VIN
5V/div
VIN
8
100 Ps/DIV
100 Ps/DIV
Figure 21.
Figure 22.
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Block Diagram
VCC
SD
FREQ
CLOCK &
RAMP
PGND
PGND
SGND
UVLO
SHUT DOWN
LOGIC
BOOT
10 Ps
DELAY
HG
SSDONE
PWGD
SYNCHRONOUS
DRIVER LOGIC
OV
UV
0.71V
LG
0.434V
10 PA
SS/TRACK
1VPP
PWM LOGIC
PWM
Soft-Start
Comparator
+ Logic
REF
40 PA
-
+
90 PA
ISEN
ILIM
EA
-
+
VREF = 0.6V
FB
EAO
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APPLICATION INFORMATION
THEORY OF OPERATION
The LM2743 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is
designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high
efficiency buck converters. It has output shutdown (SD), input under-voltage lock-out (UVLO) mode and power
good (PWGD) flag (based on over-voltage and under-voltage detection). The over-voltage and under-voltage
signals are logically OR'ed to drive the power good signal and provide a logic signal to the system if the output
voltage goes out of regulation. Current limit is achieved by sensing the voltage VDS across the low side MOSFET.
START UP/SOFT-START
When VCC exceeds 2.76V and the shutdown pin (SD) sees a logic high, the soft-start period begins. Then an
internal, fixed 10 µA source begins charging the soft-start capacitor. During soft-start the voltage on the soft-start
capacitor CSS is connected internally to the non-inverting input of the error amplifier. The soft-start period lasts
until the voltage on the soft-start capacitor exceeds the LM2743 reference voltage of 0.6V. At this point the
reference voltage takes over at the non-inverting error amplifier input. The capacitance of CSS determines the
length of the soft-start period, and can be approximated by:
CSS =
tSS
60
Where CSS is in µF and tSS is in ms.
During soft start the Power Good flag is forced low and it is released when the FB pin voltage reaches 70% of
0.6V. At this point the chip enters normal operation mode, and the output overvoltage and undervoltage
monitoring starts.
NORMAL OPERATION
While in normal operation mode, the LM2743 regulates the output voltage by controlling the duty cycle of the
high side and low side MOSFETs (see Figure 1). The equation governing output voltage is:
RFB1 + RFB2
VOUT =
RFB1
VFB
(VFB = 0.6V)
The PWM frequency is adjustable between 50 kHz and 1 MHz and is set by an external resistor, RFADJ, between
the FREQ pin and ground. The resistance needed for a desired frequency is approximately:
RFADJ = -5.93 + 3.06
12
107
10
+ 0.24
2
fSW
(fSW)
Where fSW is in Hz and RFADJ is in kΩ.
TRACKING A VOLTAGE LEVEL
The LM2743 can track the output of a master power supply during soft-start by connecting a resistor divider to
the SS/TRACK pin. In this way, the output voltage slew rate of the LM2743 will be controlled by the master
supply for loads that require precise sequencing. When the tracking function is used no soft-start capacitor
should be connected to the SS/TRACK pin. Otherwise, a CSS value of at least 1 nF between the soft-start pin
and ground should be used.
10
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Master Power
Supply
VOUT1 = 5V
RT2
1 k:
VOUT2 = 1.8V
SS/TRACK
VSS = 0.65V
RT1
150:
LM2743
FB
RFB2
10 k:
VFB
RFB1
5 k:
Figure 23. Tracking Circuit
One way to use the tracking feature is to design the tracking resistor divider so that the master supply’s output
voltage (VOUT1) and the LM2743’s output voltage (represented symbolically in Figure 23 as VOUT2, i.e. without
explicitly showing the power components) both rise together and reach their target values at the same time. For
this case, the equation governing the values of the tracking divider resistors RT1 and RT2 is:
0.65 = VOUT1
RT1
RT1 + RT2
The current through RT1 should be about 3 mA to 4 mA for precise tracking. The final voltage of the SS/TRACK
pin should be set higher than the feedback voltage of 0.6V (say about 0.65V as in the above equation). If the
master supply voltage was 5V and the LM2743 output voltage was 1.8V, for example, then the value of RT1
needed to give the two supplies identical soft-start times would be 150Ω. A timing diagram for the equal soft-start
time case is shown in Figure 24.
5V
VOUT1
1.8V
VOUT2
Figure 24. Tracking with Equal Soft-Start Time
TRACKING A VOLTAGE SLEW RATE
The tracking feature can alternatively be used not to make both rails reach regulation at the same time but rather
to have similar rise rates (in terms of output dV/dt). This method ensures that the output voltage of the LM2743
always reaches regulation before the output voltage of the master supply. Because the output of the master
supply is divided down, in order to track properly the output voltage of the LM2743 must be lower than the
voltage of the master supply. In this case, the tracking resistors can be determined based on the following
equation:
VOUT2 = VOUT1
RT1
RT1 + RT2
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For the example case of VOUT1 = 5V and VOUT2 = 1.8V, with RT1 set to 150Ω as before, RT2 is calculated from the
above equation to be 265Ω. A timing diagram for the case of equal slew rates is shown in Figure 25.
5V
1.8V
VOUT1
1.8V
VOUT2
Figure 25. Tracking with Equal Slew Rates
SEQUENCING
The start up/soft-start of the LM2743 can be delayed for the purpose of sequencing by connecting a resistor
divider from the output of a master power supply to the SD pin, as shown in Figure 26.
Master Power
Supply
VOUT1
RS2
VOUT2
SD
LM2743
RS1
RFB2
FB
VFB
RFB1
Figure 26. Sequencing Circuit
A desired delay time tDELAY between the startup of the master supply output voltage and the LM2743 output
voltage can be set based on the SD pin low-to-high threshold VSD-IH and the slew rate of the voltage at the SD
pin, SRSD:
tDELAY = VSD-IH / SRSD
Note again, that in Figure 26, the LM2743’s output voltage has been represented symbolically as VOUT2, i.e.
without explicitly showing the power components.
VSD-IH is typically 1.08V and SRSD is the slew rate of the SD pin voltage. The values of the sequencing divider
resistors RS1 and RS2 set the SRSD based on the master supply output voltage slew rate, SROUT1, using the
following equation:
SRSD = SROUT1
12
RS1
RS1 + RS2
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For example, if the master supply output voltage slew rate was 1V/ms and the desired delay time between the
startup of the master supply and LM2743 output voltage was 5ms, then the desired SD pin slew rate would be
(1.08V/5 ms) = 0.216V/ms. Due to the internal impedance of the SD pin, the maximum recommended value for
RS2 is 1kΩ. To achieve the desired slew rate, RS1 would then be 274Ω. A timing diagram for this example is
shown in Figure 27.
5V
VSD-IH
1.08V
VOUT1
1.8V
VOUT2
t = 5 ms
Figure 27. Delay for Sequencing
SD PIN IMPEDANCE
When connecting a resistor divider to the SD pin of the LM2743 some care has to be taken. Once the SD voltage
goes above VSD-IH, a 17 µA pull-up current is activated as shown in Figure 28. This current is used to create the
internal hysteresis (≊170 mV); however, high external impedances will affect the SD pin logic thresholds as well.
The external impedance used for the sequencing divider network should preferably be a small fraction of the
impedance of the SD pin for good performance (around 1kΩ).
17 PA
8 PA
Bias Enable
SD
10k
Soft-Start Enable
1.25V
+
-
Figure 28. SD Pin Logic
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MOSFET GATE DRIVERS
The LM2743 has two gate drivers designed for driving N-channel MOSFETs in a synchronous mode. Note that
unlike most other synchronous controllers, the bootstrap capacitor of the LM2743 provides power not only to the
driver of the upper MOSFET, but the lower MOSFET driver too (both drivers are ground referenced, i.e. no
floating driver). To fully turn the top MOSFET on, the BOOT voltage must be at least one gate threshold greater
than VIN when the high-side drive goes high. This bootstrap voltage is usually supplied from a local charge pump
structure. But looking at the Typical Application schematic, this also means that the difference voltage VCC - VD1,
which is the voltage the bootstrap capacitor charges up to, must be always greater than the maximum tolerance
limit of the threshold voltage of the upper MOSFET. Here VD1 is the forward voltage drop across the bootstrap
diode D1. This therefore may place restrictions on the minimum input voltage and/or type of MOSFET used.
The most basic charge bootstrap pump circuit can be built using one Schottky diode and a small capacitor, as
shown in Figure 29. The capacitor CBOOT serves to maintain enough voltage between the top MOSFET gate and
source to control the device even when the top MOSFET is on and its source has risen up to the input voltage
level. The charge pump circuitry is fed from VCC, which can operate over a range from 3.0V to 6.0V. Using this
basic method the voltage applied to the gates of both high-side and low-side MOSFETs is VCC - VD. This method
works well when VCC is 5V±10%, because the gate drives will get at least 4.0V of drive voltage during the worst
case of VCC-MIN = 4.5V and VD-MAX = 0.5V. Logic level MOSFETs generally specify their on-resistance at VGS =
4.5V. When VCC = 3.3V±10%, the gate drive at worst case could go as low as 2.5V. Logic level MOSFETs are
not specified to turn on, or may have much higher on-resistance at 2.5V. Sub-logic level MOSFETs, usually
specified at VGS = 2.5V, will work, but are more expensive, and tend to have higher on-resistance. The circuit in
Figure 29 works well for input voltages ranging from 1V up to 16V and VCC = 5V ±10%, because the drive
voltage depends only on VCC.
LM2743
BOOT
D1
VCC
CBOOT
VIN
HG
+
VO
+
LG
Figure 29. Basic Charge Pump (Bootstrap)
Note that the LM2743 can be paired with a low cost linear regulator like the LM78L05 to run from a single input
rail between 6.0 and 14V. The 5V output of the linear regulator powers both the VCC and the bootstrap circuit,
providing efficient drive for logic level MOSFETs. An example of this circuit is shown in Figure 30.
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LM2743
VCC
5V
LM78L05
D1
BOOT
CBOOT
VIN
+
HG
VO
LG
+
Figure 30. LM78L05 Feeding Basic Charge Pump
Figure 31 shows a second possibility for bootstrapping the MOSFET drives using a doubler. This circuit provides
an equal voltage drive of VCC - 3VD + VIN to both the high-side and low-side MOSFET drives. This method should
only be used in circuits that use 3.3V for both VCC and VIN. Even with VIN = VCC = 3.0V (10% lower tolerance on
3.3V) and VD = 0.5V both high-side and low-side gates will have at least 4.5V of drive. The power dissipation of
the gate drive circuitry is directly proportional to gate drive voltage, hence the thermal limits of the LM2743 IC will
quickly be reached if this circuit is used with VCC or VIN voltages over 5V.
LM2743
BOOT
D3
D2
D1
VCC
VIN
HG
+
VO
+
LG
Figure 31. Charge Pump with Added Gate Drive
All the gate drive circuits shown in the above figures typically use 100 nF ceramic capacitors in the bootstrap
locations.
POWER GOOD SIGNAL
The open drain output on the Power Good pin needs a pull-up resistor to a low voltage source. The pull-up
resistor should be chosen so that the current going into the Power Good pin is less than 1 mA. A 100 kΩ resistor
is recommended for most applications.
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The Power Good signal is an OR-gated flag which takes into account both output over-voltage and under-voltage
conditions. If the feedback pin (FB) voltage is 18% above its nominal value (118% x VFB = 0.708V) or falls 28%
below that value (72 %x VFB = 0.42V) the Power Good flag goes low. The Power Good flag can be used to signal
other circuits that the output voltage has fallen out of regulation, however the switching of the LM2743 continues
regardless of the state of the Power Good signal. The Power Good flag will return to logic high whenever the
feedback pin voltage is between 72% and 118% of 0.6V.
UVLO
The 2.76V turn-on threshold on VCC has a built in hysteresis of about 300 mV. If VCC drops below 2.42V, the chip
enters UVLO mode. UVLO consists of turning off the top and bottom MOSFETS and remaining in that condition
until VCC rises above 2.76V. As with shutdown, the soft-start capacitor is discharged through an internal
MOSFET, ensuring that the next start-up will be controlled by the soft-start circuitry.
CURRENT LIMIT
Current limit is realized by sensing the voltage across the low-side MOSFET while it is on. The RDS(ON) of the
MOSFET is a known value; hence the current through the MOSFET can be determined as:
VDS = IOUT x RDS(ON)
The current through the low-side MOSFET while it is on is also the falling portion of the inductor current. The
current limit threshold is determined by an external resistor, RCS, connected between the switching node and the
ISEN pin. A constant current of 40 µA is forced through RCS, causing a fixed voltage drop. This fixed voltage is
compared against VDS and if the latter is higher, the current limit of the chip has been reached. To obtain a more
accurate value for RCS you must consider the operating values of RDS(ON) and ISEN-TH at their operating
temperatures in your application and the effect of slight parameter differences from part to part. RCS can be found
by using the following equation using the RDS(ON) value of the low side MOSFET at it's expected hot temperature
and the absolute minimum value expected over the full temperature range for the for the ISEN-TH which is 25 µA:
RCS = RDSON-HOT x ILIM / 40 µA
For example, a conservative 15A current limit in a 10A design with a minimum RDS(ON) of 10 mΩ would require a
6 kΩ resistor. To prevent the ISEN pin from sinking too much current when the switch node goes above 9.5V, the
value of the current limit setting resistor RCS should not be too low. The criterion is as follows,
VIN ± 9.5V
RCS t
10 mA
where the 10 mA is the maximum current ISEN pin is allowed to sink. For example if VIN = 13.2V, the minimum
value of RCS is 370Ω. Because current sensing is done across the low-side MOSFET, no minimum high-side ontime is necessary. The LM2743 enters current limit mode if the inductor current exceeds the current limit
threshold at the point where the high-side MOSFET turns off and the low-side MOSFET turns on. (The point of
peak inductor current, see Figure 32). Note that in normal operation mode the high-side MOSFET always turns
on at the beginning of a clock cycle. In current limit mode, by contrast, the high-side MOSFET on-pulse is
skipped. This causes inductor current to fall. Unlike a normal operation switching cycle, however, in a current
limit mode switching cycle the high-side MOSFET will turn on as soon as inductor current has fallen to the
current limit threshold. The LM2743 will continue to skip high-side MOSFET pulses until the inductor current peak
is below the current limit threshold, at which point the system resumes normal operation.
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Normal Operation
Current Limit
ILIM
IL
D
Figure 32. Current Limit Threshold
Unlike a high-side MOSFET current sensing scheme, which limits the peaks of inductor current, low-side current
sensing is only allowed to limit the current during the converter off-time, when inductor current is falling.
Therefore in a typical current limit plot the valleys are normally well defined, but the peaks are variable, according
to the duty cycle. The PWM error amplifier and comparator control the off-pulse of the high-side MOSFET, even
during current limit mode, meaning that peak inductor current can exceed the current limit threshold. Assuming
that the output inductor does not saturate, the maximum peak inductor current during current limit mode can be
calculated with the following equation:
IPK-CL = ILIM + (TSW - 200 ns)
VIN - VO
L
Where TSW is the inverse of switching frequency fSW. The 200 ns term represents the minimum off-time of the
duty cycle, which ensures enough time for correct operation of the current sensing circuitry.
In order to minimize the time period in which peak inductor current exceeds the current limit threshold, the IC
also discharges the soft-start capacitor through a fixed 90 µA sink. The output of the LM2743 internal error
amplifier is limited by the voltage on the soft-start capacitor. Hence, discharging the soft-start capacitor reduces
the maximum duty cycle D of the controller. During severe current limit this reduction in duty cycle will reduce the
output voltage if the current limit conditions last for an extended time. Output inductor current will be reduced in
turn to a flat level equal to the current limit threshold. The third benefit of the soft-start capacitor discharge is a
smooth, controlled ramp of output voltage when the current limit condition is cleared.
FOLDBACK CURRENT LIMIT
In the case where extra protection is used to help an output short condition, a current foldback resistor (RCLF)
should be considered, see Figure 33. First select the percentage of current limit foldback (PLIM):
PLIM = ILIM x P
where P is a ratio between 0 and 1.
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VOUT
40 PA
RCLF
RCS
-
SW
ILIM
ISEN
+
Figure 33. Foldback Current Limit Circuit
Obtain the RCS with the following equation:
PLIM x RDS(ON)
= RCS
ISEN
where ISEN = 40 μA. If the switch node goes above 9.5V the following criterion must be satisfied:
VIN ± 9.5V
RCS t
10 mA
The equation for calculating the foldback resistance value is:
RCS x VOUT
RCLF =
(ILIM x RDS(ON)) ± (ISEN x RCS)
SHUTDOWN
If the shutdown pin is pulled low, (below 0.8V) the LM2743 enters shutdown mode, and discharges the soft-start
capacitor through a MOSFET switch. The high and low-side MOSFETs are turned off. The LM2743 remains in
this state as long as VSD sees a logic low (see the Electrical Characteristics table). To assure proper IC start-up
the shutdown pin should not be left floating. For normal operation this pin should be connected directly to VCC or
to another voltage between 1.3V to VCC (see the Electrical Characteristics table).
DESIGN CONSIDERATIONS
The following is a design procedure for all the components needed to create the Figure 1. This design converts
3.3V (VIN) to 1.2V (VOUT) at a maximum load of 4A with an efficiency of 89% and a switching frequency of 300
kHz. The same procedures can be followed to create many other designs with varying input voltages, output
voltages, and load currents.
Duty Cycle Calculation
The complete duty cycle for a buck converter is defined with the following equation:
VOUT + VSWL
D=
VIN - VSWH + VSWL
where VSWL and VSWH are the respective forward voltage drops that develop across the low side and high side
MOSFETs. Assuming the inductor ripple current is 20% to 30% of the output current, therefore:
VSWL = IOUT x RDS(ON)LOW (Low-Side MOSFET)
VSWH = IOUT x RDS(ON)HIGH (High-Side MOSFET)
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To calculate the maximum duty cycle use the estimated 'hot' RDS(on) value of the MOSFETs, the minimum input
voltage, and maximum load. As shown in Figure 34, the worst case maximum duty cycles of the LM2743 occurs
at 125°C junction temperature vs VCC (IC control section voltage). Ensure that the operating duty cycle is below
the curve in Figure 34, if this condition is not satisfied, the system will be unable to develop the required duty
cycle to derive the necessary system power and so the output voltage will fall out of regulation.
Figure 34. Maximum Duty Cycle vs VCC
TJ = 125°C
Input Capacitor
The input capacitors in a Buck converter are subjected to high stress due to the input current trapezoidal
waveform. Input capacitors are selected for their ripple current capability and their ability to withstand the heat
generated since that ripple current passes through their ESR. Input rms ripple current is approximately:
IRMS_RIP = IOUT x
D(1 - D)
The power dissipated by each input capacitor is:
(IRMS_RIP)2 x ESR
PCAP =
n2
where n is the number of capacitors, and ESR is the equivalent series resistance of each capacitor. The equation
above indicates that power loss in each capacitor decreases rapidly as the number of input capacitors increases.
The worst-case ripple for a Buck converter occurs during full load and when the duty cycle (D) is 0.5. For this
3.3V to 1.2V design the duty cycle is 0.364. For a 4A maximum load the ripple current is 1.92A.
Output Inductor
The output inductor forms the first half of the power stage in a Buck converter. It is responsible for smoothing the
square wave created by the switching action and for controlling the output current ripple (ΔIOUT). The inductance
is chosen by selecting between tradeoffs in efficiency and response time. The smaller the output inductor, the
more quickly the converter can respond to transients in the load current. However, as shown in the efficiency
calculations, a smaller inductor requires a higher switching frequency to maintain the same level of output current
ripple. An increase in frequency can mean increasing loss in the MOSFETs due to the charging and discharging
of the gates. Generally the switching frequency is chosen so that conduction loss outweighs switching loss. The
equation for output inductor selection is:
VIN - VOUT
L=
L=
xD
'IOUT x fSW
3.3V - 1.2V
1.2V
x
3.3V
0.4 x 4A x 300 kHz
L = 1.6µH
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Here we have plugged in the values for output current ripple, input voltage, output voltage, switching frequency,
and assumed a 40% peak-to-peak output current ripple. This yields an inductance of 1.6 µH. The output inductor
must be rated to handle the peak current (also equal to the peak switch current), which is (IOUT + (0.5 x ΔIOUT)) =
4.8A, for a 4A design. The Coilcraft DO3316P-222P is 2.2 µH, is rated to 7.4A peak, and has a direct current
resistance (DCR) of 12 mΩ.
After selecting an output inductor, inductor current ripple should be re-calculated with the new inductance value,
as this information is needed to select the output capacitor. Re-arranging the equation used to select inductance
yields the following:
VIN(MAX) - VO
'IOUT =
FSW x LACTUAL
xD
VIN(MAX) is assumed to be 10% above the steady state input voltage, or 3.6V. The actual current ripple will then
be 1.2A. Peak inductor/switch current will be 4.6A.
Output Capacitor
The output capacitor forms the second half of the power stage of a Buck switching converter. It is used to control
the output voltage ripple (ΔVOUT) and to supply load current during fast load transients.
In this example the output current is 4A and the expected type of capacitor is an aluminum electrolytic, as with
the input capacitors. Other possibilities include ceramic, tantalum, and solid electrolyte capacitors, however the
ceramic type often do not have the large capacitance needed to supply current for load transients, and tantalums
tend to be more expensive than aluminum electrolytic. Aluminum capacitors tend to have very high capacitance
and fairly low ESR, meaning that the ESR zero, which affects system stability, will be much lower than the
switching frequency. The large capacitance means that at the switching frequency, the ESR is dominant, hence
the type and number of output capacitors is selected on the basis of ESR. One simple formula to find the
maximum ESR based on the desired output voltage ripple, ΔVOUT and the designed output current ripple, ΔIOUT,
is:
ESRMAX =
'VOUT
'IOUT
In this example, in order to maintain a 2% peak-to-peak output voltage ripple and a 40% peak-to-peak inductor
current ripple, the required maximum ESR is 20 mΩ. The Sanyo 4SP560M electrolytic capacitor will give an
equivalent ESR of 14 mΩ. The capacitance of 560 µF is enough to supply energy even to meet severe load
transient demands.
MOSFETs
Selection of the power MOSFETs is governed by a tradeoff between cost, size, and efficiency. One method is to
determine the maximum cost that can be endured, and then select the most efficient device that fits that price.
Breaking down the losses in the high-side and low-side MOSFETs and then creating spreadsheets is one way to
determine relative efficiencies between different MOSFETs. Good correlation between the prediction and the
bench result is not specified, however. Single-channel buck regulators that use a controller IC and discrete
MOSFETs tend to be most efficient for output currents of 2A to 10A.
Losses in the high-side MOSFET can be broken down into conduction loss, gate charging loss, and switching
loss. Conduction loss, or I2R loss, is approximately:
PC = D ((IO)2 x RDSON-HI x 1.3) (High-Side MOSFET)
PC = (1 - D) x ((IO)2 x RDSON-LO x 1.3) (Low-Side MOSFET)
In the above equations the factor 1.3 accounts for the increase in MOSFET RDSON due to heating. Alternatively,
the 1.3 can be ignored and the RDSON of the MOSFET estimated using the RDSON Vs. Temperature curves in the
MOSFET datasheets.
Gate charging loss results from the current driving the gate capacitance of the power MOSFETs, and is
approximated as:
PGC = n x (VDD) x QG x fSW
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where ‘n’ is the number of MOSFETs (if multiple devices have been placed in parallel), VDD is the driving voltage
(see MOSFET GATE DRIVERS section) and QGS is the gate charge of the MOSFET. If different types of
MOSFETs are used, the ‘n’ term can be ignored and their gate charges simply summed to form a cumulative QG.
Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the
LM2743, and not in the MOSFET itself.
Switching loss occurs during the brief transition period as the high-side MOSFET turns on and off, during which
both current and voltage are present in the channel of the MOSFET. It can be approximated as:
PSW = 0.5 x VIN x IO x (tr + tf) x fSW
where tR and tF are the rise and fall times of the MOSFET. Switching loss occurs in the high-side MOSFET only.
For this example, the maximum drain-to-source voltage applied to either MOSFET is 3.6V. The maximum drive
voltage at the gate of the high-side MOSFET is 3.1V, and the maximum drive voltage for the low-side MOSFET
is 3.3V. Due to the low drive voltages in this example, a MOSFET that turns on fully with 3.1V of gate drive is
needed. For designs of 5A and under, dual MOSFETs in SOIC-8 package provide a good trade-off between size,
cost, and efficiency.
Support Components
CIN2 - A small value (0.1 µF to 1 µF) ceramic capacitor should be placed as close as possible to the drain of the
high-side MOSFET and source of the low-side MOSFET (dual MOSFETs make this easy). This capacitor should
be X5R type dielectric or better.
RCC, CCC- These are standard filter components designed to ensure smooth DC voltage for the chip supply. RCC
should be 1Ω to 10Ω. CCC should 1 µF, X5R type or better.
CBOOT- Bootstrap capacitor, typically 100 nF.
RPULL-UP – This is a standard pull-up resistor for the open-drain power good signal (PWGD). The recommended
value is 10 kΩ connected to VCC. If this feature is not necessary, the resistor can be omitted.
D1 - A small Schottky diode should be used for the bootstrap. It allows for a minimum drop for both high and lowside drivers. The MBR0520 or BAT54 work well in most designs.
RCS - Resistor used to set the current limit. Since the design calls for a peak current magnitude (IOUT+ (0.5 x
ΔIOUT)) of 4.8A, a safe setting would be 6A. (This is below the saturation current of the output inductor, which is
7A.) Following the equation from the CURRENT LIMIT section, a 1.3 kΩ resistor should be used.
RFADJ - This resistor is used to set the switching frequency of the chip. The resistor value is calculated from
equation in NORMAL OPERATION section. For 300 kHz operation, a 97.6 kΩ resistor should be used.
CSS - The soft-start capacitor depends on the user requirements and is calculated based on the equation given in
the section titled START UP/SOFT-START. Therefore, for a 700 μs delay, a 12 nF capacitor is suitable.
Control Loop Compensation
The LM2743 uses voltage-mode (‘VM’) PWM control to correct changes in output voltage due to line and load
transients. One of the attractive advantages of voltage mode control is its relative immunity to noise and layout.
However VM requires careful small signal compensation of the control loop for achieving high bandwidth and
good phase margin.
The control loop is comprised of two parts. The first is the power stage, which consists of the duty cycle
modulator, output inductor, output capacitor, and load. The second part is the error amplifier, which for the
LM2743 is a 9 MHz op-amp used in the classic inverting configuration. Figure 35 shows the regulator and control
loop components.
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L
RL
+ C
O
VIN
RO
+
-
RC
+
VRAMP
RC2
CC2
RC1
10 k:
CC3
CC1
+
10 k:
+
-
VREF
Figure 35. Power Stage and Error Amp
One popular method for selecting the compensation components is to create Bode plots of gain and phase for
the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the
regulator easy to see. Software tools such as Excel, MathCAD, and Matlab are useful for showing how changes
in compensation or the power stage affect system gain and phase.
The power stage modulator provides a DC gain ADC that is equal to the input voltage divided by the peak-to-peak
value of the PWM ramp. This ramp is 1.0VP-P for the LM2743. The inductor and output capacitor create a
double pole at frequency fDP, and the capacitor ESR and capacitance create a single zero at frequency fESR. For
this example, with VIN = 3.3V, these quantities are:
VIN
ADC =
fDP =
fESR =
VRAMP
1
2S
3.3
= 10.4 dB
1.0
=
RO + RL
LCO(RO + ESR)
1
2SCOESR
= 4.5 kHz
= 20.3 kHz
In the equation for fDP, the variable RL is the power stage resistance, and represents the inductor DCR plus the
on resistance of the top power MOSFET. RO is the output voltage divided by output current. The power stage
transfer function GPS is given by the following equation, and Figure 36 shows Bode plots of the phase and gain in
this example.
VIN x RO
GPS =
VRAMP
x
sCORC + 1
a x s2 + b x s + c
a = LCO(RO + RC)
b = L + CO(RORL + RORC + RCRL)
c = RO + RL
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20
GAIN (dB)
4
-12
-28
-44
-60
100
1k
10k
100k
1M
FREQUENCY (Hz)
0
PHASE (o)
-30
-60
-90
-120
-150
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 36. Power Stage Gain and Phase
The double pole at 4.5 kHz causes the phase to drop to approximately -130° at around 10 kHz. The ESR zero, at
20.3 kHz, provides a +90° boost that prevents the phase from dropping to -180º. If this loop were left
uncompensated, the bandwidth would be approximately 10 kHz and the phase margin 53°. In theory, the loop
would be stable, but would suffer from poor DC regulation (due to the low DC gain) and would be slow to
respond to load transients (due to the low bandwidth.) In practice, the loop could easily become unstable due to
tolerances in the output inductor, capacitor, or changes in output current, or input voltage. Therefore, the loop is
compensated using the error amplifier and a few passive components.
For this example, a Type III, or three-pole-two-zero approach gives optimal bandwidth and phase.
In most voltage mode compensation schemes, including Type III, a single pole is placed at the origin to boost DC
gain as high as possible. Two zeroes fZ1 and fZ2 are placed at the double pole frequency to cancel the double
pole phase lag. Then, a pole, fP1 is placed at the frequency of the ESR zero. A final pole fP2 is placed at one-half
of the switching frequency. The gain of the error amplifier transfer function is selected to give the best bandwidth
possible without violating the Nyquist stability criteria. In practice, a good crossover point is one-fifth of the
switching frequency, or 60 kHz for this example. The generic equation for the error amplifier transfer function is:
s
+1
2SfZ1
GEA = AEA x
s
s
+1
2SfP1
s
+1
2SfZ2
s
+1
2SfP2
In this equation the variable AEA is a ratio of the values of the capacitance and resistance of the compensation
components, arranged as shown in Figure 35. AEA is selected to provide the desired bandwidth. A starting value
of 80,000 for AEA should give a conservative bandwidth. Increasing the value will increase the bandwidth, but will
also decrease phase margin. Designs with 45° to 60° are usually best because they represent a good trade-off
between bandwidth and phase margin. In general, phase margin is lowest and gain highest (worst-case) for
maximum input voltage and minimum output current. One method to select AEA is to use an iterative process
beginning with these worst-case conditions.
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1.
2.
3.
4.
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Increase AEA
Check overall bandwidth and phase margin
Change VIN to minimum and recheck overall bandwidth and phase margin
Change IO to maximum and recheck overall bandwidth and phase margin
The process ends when the both bandwidth and the phase margin are sufficiently high. For this example input
voltage can vary from 3.0 to 3.6V and output current can vary from 0 to 4A, and after a few iterations a moderate
gain factor of 101dB is used.
The error amplifier of the LM2743 has a unity-gain bandwidth of 9 MHz. In order to model the effect of this
limitation, the open-loop gain can be calculated as:
OPG =
2S x 9 MHz
s
The new error amplifier transfer function that takes into account unity-gain bandwidth is:
GEA x OPG
HEA =
1 + GEA + OPG
The gain and phase of the error amplifier are shown in Figure 37.
60
GAIN (dB)
48
36
24
12
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
50
PHASE (o)
20
-10
-40
-70
-100
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 37. Error Amp. Gain and Phase
In VM regulators, the top feedback resistor RFB2 forms a part of the compensation. Setting RFB2 to 10 kΩ, ±1%
usually gives values for the other compensation resistors and capacitors that fall within a reasonable range.
(Capacitances > 1pF, resistances < 1MΩ) CC1, CC2, CC3, RC1, and RC2 are selected to provide the poles and
zeroes at the desired frequencies, using the following equations:
fZ1
CC1 =
24
AEA x 10,000 x fP2
= 27 pF
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CC2 =
CC3 =
RC1 =
RC2 =
SNVS276G – APRIL 2004 – REVISED MARCH 2013
1
AEA x 10,000
1
2S x 10,000
- CC1 = 882 pF
x
1
2S x CC2 x fZ1
1
2S x CC3 x fP1
1
1
= 2.73 nF
fZ2 fP1
= 39.8 k:
= 2.55 k:
In practice, a good trade off between phase margin and bandwidth can be obtained by selecting the closest
±10% capacitor values above what are suggested for CC1 and CC2, the closest ±10% capacitor value below the
suggestion for CC3, and the closest ±1% resistor values below the suggestions for RC1, RC2. Note that if the
suggested value for RC2 is less than 100Ω, it should be replaced by a short circuit. Following this guideline, the
compensation components will be:
CC1 = 27pF ±10%
CC2 = 820pF ±10%
CC3 = 2.7nF ±10%
RC1 = 39.2kΩ ±1%
RC2 = 2.55kΩ ±1%
The transfer function of the compensation block can be derived by considering the compensation components as
impedance blocks ZF and ZI around an inverting op-amp:
ZF
GEA-ACTUAL =
ZI
1
1
x 10,000 +
sCC2
sCC1
ZF =
10,000 +
RC1 RC2 +
1
1
+
sCC1 sCC2
1
sCC3
Z1 =
RC1 + RC2 +
1
sCC3
As with the generic equation, GEA-ACTUAL must be modified to take into account the limited bandwidth of the error
amplifier. The result is:
GEA-ACTUAL x OPG
HEA =
1 + GEA-ACTUAL+ OPG
The total control loop transfer function H is equal to the power stage transfer function multiplied by the error
amplifier transfer function.
H = GPS x HEA
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The bandwidth and phase margin can be read graphically from Bode plots of HEA are shown in Figure 38.
60
GAIN (dB)
40
20
0
-20
-40
100
1k
10k
100k
1M
FREQUENCY (Hz)
-60
PHASE (o)
-84
-108
-132
-156
-180
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 38. Overall Loop Gain and Phase
The bandwidth of this example circuit is 59 kHz, with a phase margin of 60°.
EFFICIENCY CALCULATIONS
The following is a sample calculation.
A reasonable estimation of the efficiency of a switching buck controller can be obtained by adding together the
Output Power (POUT) loss and the Total Power (PTOTAL) loss:
POUT
K=
x 100%
POUT + PTOTAL
The Output Power (POUT) for the Figure 1 design is (1.2V x 4A) = 4.8W. The Total Power (PTOTAL), with an
efficiency calculation to complement the design, is shown below.
The majority of the power losses are due to low and high side of MOSFET’s losses. The losses in any MOSFET
are group of switching (PSW) and conduction losses(PCND).
PFET = PSW + PCND = 61.38 mW + 270.42 mW
PFET = 331.8 mW
FET Switching Loss (PSW)
PSW =
PSW =
PSW =
PSW =
26
PSW(ON) + PSW(OFF)
0.5 x VIN x IOUT x (tr + tf) x fSW
0.5 x 3.3V x 4A x 300 kHz x 31 ns
61.38 mW
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The FDS6898A has a typical turn-on rise time tr and turn-off fall time tf of 15 ns and 16 ns, respectively. The
switching losses for this type of dual N-Channel MOSFETs are 0.061W.
FET Conduction Loss (PCND)
PCND = PCND1 + PCND2
PCND1 = (IOUT)2 x RDS(ON) x k x D
PCND2 = (IOUT)2 x RDS(ON) x k x (1-D)
RDS(ON) = 13 mΩ and the factor is a constant value (k = 1.3) to account for the increasing RDS(ON) of a FET due to
heating.
PCND1 = (4A)2 x 13 mΩ x 1.3 x 0.364
PCND2 = (4A)2 x 13 mΩ x 1.3 x (1 - 0.364)
PCND = 98.42 mW + 172 mW = 270.42 mW
There are few additional losses that are taken into account:
IC Operating Loss (PIC)
PIC = IQ_VCC x VCC,
where IQ-VCC is the typical operating VCC current
PIC= 1.5 mA x 3.3V = 4.95 mW
FET Gate Charging Loss (PGATE)
PGATE = n x VCC x QGS x fSW
PGATE = 2 x 3.3V x 3 nC x 300 kHz
PGATE = 5.94 mW
The value n is the total number of FETs used and QGS is the typical gate-source charge value, which is 3 nC. For
the FDS6898A the gate charging loss is 5.94 mW.
Input Capacitor Loss (PCAP)
(IRMS_RIP)2 x ESR
PCAP =
n2
where,
IRMS_RIP = IOUT x
D(1 - D)
Here n is the number of paralleled capacitors, ESR is the equivalent series resistance of each, and PCAP is the
dissipation in each. So for example if we use only one input capacitor of 24 mΩ.
PCAP =
(1.924A)2 x 24 m:
12
PCAP = 88.8 mW
Output Inductor Loss (PIND)
PIND = I2OUT x DCR
where DCR is the DC resistance. Therefore, for example
PIND = (4A)2 x 11 mΩ
PIND = 176 mW
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Total System Efficiency
PTOTAL = PFET + PIC + PGATE + PCAP + PIND
POUT
K=
K=
x 100%
POUT + PTOTAL
4.8W
= 89%
4.8W + 0.6W
Example Circuits
VCC = VIN= 3.3V
D1
RCC
CBOOT
RPULL-UP
VCC
HG
SD
CCC
BOOT
LM2743
FREQ
CSS
RCS
VOUT = 1.8V@2A
L1
ISEN
PWGD
RFADJ
+ CIN1,2
Q1
LG
SS/TRACK
PGND
SGND
PGND
EAO
FB
RFB2
RC2
CC3
+
CO1,2
RFB1
CC1
CC2
RC1
Figure 39. 3.3V to 1.8V @ 2A, fSW = 300kHz
Table 1. Bill of Materials
PART
PART NUMBER
TYPE
PACKAGE
U1
LM2743
Synchronous
Controller
TSSOP-14
Q1
FDS6898A
Dual N-MOSFET
SOIC-8
D1
MBR0520LTI
Schottky Diode
SOD-123
L1
DO3316P-472
Inductor
CIN1
16SP100M
Aluminum Electrolytic
10mm x 6mm
CO1
6SP220M
Aluminum Electrolytic
CCC, CBOOT,
CIN2, CO2
VJ1206Y104KXXA
CC3
DESCRIPTION
VENDOR
TI
20V, 10mΩ@ 4.5V,
16nC
Fairchild
4.7µH, 4.8Arms 18mΩ
Coilcraft
100µF, 16V, 2.89Arms
Sanyo
10mm x 6mm
220µF, 6.3V 3.1Arms
Sanyo
Capacitor
1206
0.1µF, 10%
Vishay
VJ0805Y332KXXA
Capacitor
805
3300pF, 10%
Vishay
CSS
VJ0805A123KXAA
Capacitor
805
12nF, 10%
Vishay
CC2
VJ0805A821KXAA
Capacitor
805
820pF 10%
Vishay
CC1
VJ0805A220KXAA
Capacitor
805
22pF, 10%
Vishay
RFB2
CRCW08051002F
Resistor
805
10.0kΩ 1%
Vishay
RFB1
CRCW08054991F
Resistor
805
4.99kΩ1%
Vishay
RFADJ
CRCW08051103F
Resistor
805
110kΩ 1%
Vishay
RC2
CRCW08052101F
Resistor
805
2.1kΩ 1%
Vishay
RCS
CRCW08052101F
Resistor
805
2.1 kΩ 1%
Vishay
28
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Table 1. Bill of Materials (continued)
PART
PART NUMBER
TYPE
PACKAGE
DESCRIPTION
VENDOR
RCC
CRCW080510R0F
Resistor
805
10.0Ω 1%
Vishay
RC1
CRCW08055492F
Resistor
805
54.9kΩ 1%
Vishay
RPULL-UP
CRCW08051003J
Resistor
805
100kΩ 5%
Vishay
VCC = 5V
D1
RCC
CBOOT
RPULL-UP
HG
SD
BOOT
PWGD
RFADJ
CSS
+ CIN1,2
Q1
VCC
CCC
VIN = 5V
LM2743
RCS
L1
VOUT = 2.5V@2A
ISEN
FREQ
LG
SS/TRACK
PGND
SGND
PGND
EAO
FB
RFB2
RC2
CC3
+
CO1,2
RFB1
CC1
CC2
RC1
Figure 40. 5V to 2.5V @ 2A, fSW = 300kHz
Table 2. Bill of Materials
PART
PART NUMBER
TYPE
PACKAGE
U1
LM2743
Synchronous
Controller
TSSOP-14
Q1
FDS6898A
Dual N-MOSFET
SOIC-8
D1
MBR0520LTI
Schottky Diode
SOD-123
L1
DO3316P-682
Inductor
CIN1
16SP100M
Aluminum
Electrolytic
10mm x 6mm
CO1
10SP56M
Aluminum
Electrolytic
CCC, CBOOT,
CIN2, CO2
VJ1206Y104KXXA
CC3
CSS
DESCRIPTION
VENDOR
TI
20V, 10mΩ@ 4.5V, 16nC
Fairchild
6.8µH, 4.4Arms, 27mΩ
Coilcraft
100µF, 16V, 2.89Arms
Sanyo
6.3mm x 6mm
56µF, 10V 1.7Arms
Sanyo
Capacitor
1206
0.1µF, 10%
Vishay
VJ0805Y182KXXA
Capacitor
805
1800pF, 10%
Vishay
VJ0805A123KXAA
Capacitor
805
12nF, 10%
Vishay
CC2
VJ0805A821KXAA
Capacitor
805
820pF 10%
Vishay
CC1
VJ0805A330KXAA
Capacitor
805
33pF, 10%
Vishay
RFB2
CRCW08051002F
Resistor
805
10.0kΩ 1%
Vishay
RFB1
CRCW08053161F
Resistor
805
3.16kΩ 1%
Vishay
RFADJ
CRCW08051103F
Resistor
805
110kΩ 1%
Vishay
RC2
CRCW08051301F
Resistor
805
1.3kΩ 1%
Vishay
RCS
CRCW08052101F
Resistor
805
2.1 kΩ 1%
Vishay
RCC
CRCW080510R0F
Resistor
805
10.0Ω 1%
Vishay
RC1
CRCW08053322F
Resistor
805
33.2kΩ 1%
Vishay
RPULL-UP
CRCW08051003J
Resistor
805
100kΩ 5%
Vishay
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VCC = 5V
D1
RCC
CBOOT
RPULL-UP
HG
SD
BOOT
PWGD
RFADJ
CSS
+ CIN1,2
Q1
VCC
CCC
VIN = 12V
RCS
L1
VOUT = 3.3V@4A
ISEN
LM2743
FREQ
LG
SS/TRACK
PGND
SGND
PGND
EAO
FB
RFB2
RC2
CC3
+
CO1,2
RFB1
CC1
CC2
RC1
Figure 41. 12V to 3.3V @ 4A, fSW = 300kHz
Table 3. Bill of Materials
PART
PART NUMBER
TYPE
PACKAGE
U1
LM2743
Synchronous
Controller
TSSOP-14
Q1
FDS6898A
Dual N-MOSFET
SOIC-8
D1
MBR0520LTI
Schottky Diode
SOD-123
L1
DO3316P-332
Inductor
CIN1
16SP100M
Aluminum Electrolytic
10mm x 6mm
CO1
6SP220M
Aluminum Electrolytic
CCC, CBOOT,
CIN2, CO2
VJ1206Y104KXXA
CC3
CSS
DESCRIPTION
VENDOR
TI
20V, 10mΩ@ 4.5V, 16nC
Fairchild
3.3µH, 5.4Arms 15mΩ
Coilcraft
100µF, 16V, 2.89Arms
Sanyo
10mm x 6mm
220µF, 6.3V 3.1Arms
Sanyo
Capacitor
1206
0.1µF, 10%
Vishay
VJ0805Y222KXXA
Capacitor
805
2200pF, 10%
Vishay
VJ0805A123KXAA
Capacitor
805
12nF, 10%
Vishay
CC2
VJ0805Y332KXXA
Capacitor
805
3300pF 10%
Vishay
CC1
VJ0805A820KXAA
Capacitor
805
82pF, 10%
Vishay
RFB2
CRCW08051002F
Resistor
805
10.0kΩ 1%
Vishay
RFB1
CRCW08052211F
Resistor
805
2.21kΩ 1%
Vishay
RFADJ
CRCW08051103F
Resistor
805
110kΩ 1%
Vishay
RC2
CRCW08052611F
Resistor
805
2.61kΩ 1%
Vishay
RCS
CRCW08054121F
Resistor
805
4.12 kΩ 1%
Vishay
RCC
CRCW080510R0F
Resistor
805
10.0Ω 1%
Vishay
RC1
CRCW08051272F
Resistor
805
12.7kΩ 1%
Vishay
RPULL-UP
CRCW08051003J
Resistor
805
100kΩ 5%
Vishay
30
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SNVS276G – APRIL 2004 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision F (March 2013) to Revision G
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 30
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM2743MTC
NRND
TSSOP
PW
14
94
TBD
Call TI
Call TI
-40 to 125
2743
MTC
LM2743MTC/NOPB
ACTIVE
TSSOP
PW
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
2743
MTC
LM2743MTCX
NRND
TSSOP
PW
14
2500
TBD
Call TI
Call TI
-40 to 125
2743
MTC
LM2743MTCX/NOPB
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-1-260C-UNLIM
-40 to 125
2743
MTC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Nov-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM2743, LM2743-Q1 :
• Catalog: LM2743
• Automotive: LM2743-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM2743MTCX
TSSOP
PW
14
2500
330.0
12.4
6.95
8.3
1.6
8.0
12.0
Q1
LM2743MTCX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
8.3
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM2743MTCX
TSSOP
PW
14
2500
367.0
367.0
35.0
LM2743MTCX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
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