ON MC74HCT574 Octal 3-state noninverting d flip-flop with lsttl-compatible input Datasheet

MC74HCT574A
Octal 3-State Noninverting
D Flip-Flop with
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT574A is identical in pinout to the LS574. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High Speed CMOS inputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the Clock. The Output Enable input does not affect the states
of the flip–flops, but when Output Enable is high, all device outputs
are forced to the high–impedance state. Thus, data may be stored even
when the outputs are not enabled.
The HCT574A is identical in function to the HCT374A but has the
flip–flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
•
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•
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Output Drive Capability: 15 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 286 FETs or 71.5 Equivalent Gates
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MARKING
DIAGRAMS
20
PDIP–20
N SUFFIX
CASE 738
20
MC74HCT574AN
AWLYYWW
1
20
1
20
1
SOIC WIDE–20
DW SUFFIX
CASE 751D
HCT574A
AWLYYWW
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
MC74HCT574AN
MC74HCT574ADW
Package
Shipping
PDIP–20
1440 / Box
SOIC–WIDE
MC74HCT574ADWR2 SOIC–WIDE
 Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 8
1
38 / Rail
1000 / Reel
Publication Order Number:
MC74HCT574A/D
MC74HCT574A
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
PIN ASSIGNMENT
Q0
Q1
Q2
Q3
Q4
NON–
INVERTING
OUTPUTS
Q5
Q6
Q7
11
OUTPUT ENABLE
PIN 20 = VCC
PIN 10 = GND
1
Inputs
L
L
L
H
Output
Clock
D
Q
L,H,
X
H
L
X
X
H
L
No Change
Z
X = don’t care
Z = high impedance
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Design Criteria
Value
Units
Internal Gate Count*
71.5
ea
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
µW
0.0075
pJ
Speed Power Product
1
20
VCC
2
19
Q0
D1
3
18
Q1
D2
4
17
Q2
D3
5
16
Q3
D4
6
15
Q4
D5
7
14
Q5
D6
8
13
Q6
D7
9
12
Q7
10
11
CLOCK
GND
FUNCTION TABLE
OE
OUTPUT
ENABLE
D0
*Equivalent to a two–input NAND gate.
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2
MC74HCT574A
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MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
Vin = VIH or VIL
|Iout|
6.0 mA
4.5
3.98
3.84
3.7
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout|
6.0 mA
4.5
0.26
0.33
0.4
Maximum Input Leakage
Current
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
µA
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
5.5
4.0
40
160
µA
VOH
VOL
Iin
ICC
Maximum Low–Level Output
Voltage
V
1. Output in high–impedance state.
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
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3
MC74HCT574A
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
IOZ
∆ICC
Parameter
Test Conditions
Maximum Three–State
Leakage
Current
Vin = VIL or VIH (Note 1)
Vout = VCC or GND
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND,
GND Other In
Inputs
uts
lout = 0 µA
VCC
V
– 55 to
25_C
5.5
– 0.5
85_C
125_C
– 5.0
– 10
≥ – 55_C
25_C to 125_C
2.9
2.4
5.5
Unit
µA
mA
1. Output in high–impedance state.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
– 55 to
25_C
Parameter
85_C
125_C
Unit
fMAX
Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4)
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
30
38
45
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
28
35
42
ns
tPZH,
tPZL
Maximum Propagation Delay Time, Output Enable to Q
(Figures 2 and 5)
28
35
42
ns
tTLH,
Maximum Output Transition Time, Any Output
(Figures 1, 2 and 4)
12
15
18
ns
Maximum Input Capacitance
10
10
10
pF
tTHL
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Flip–Flop)*
pF
58
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to 25_C
Fig.
Min
Minimum Setup Time, Data to Clock
3
10
13
15
ns
th
Minimum Hold Time, Clock to Data
3
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Clock
1
15
19
22
ns
Maximum Input Rise and Fall Times
1
tr, If
Parameter
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4
500
Min
Max
125_C
tsu
Symbol
Max
85_C
500
Min
Max
500
Unit
ns
MC74HCT574A
EXPANDED LOGIC DIAGRAM
D0
2
CLOCK
D1
3
D3
5
D4
6
D5
7
D6
8
D7
9
11
D
C
C
Q
ENABLE
OUTPUT
D2
4
D
C
Q
D
D
C
Q
C
Q
D
C
Q
D
D
C
Q
D
C
Q
Q
1
19
Q0
18
17
Q1
16
Q2
15
Q3
14
Q4
13
Q5
12
Q6
Q7
SWITCHING WAVEFORMS
tr
CLOCK
tf
3.0 V
3.0 V
2.7 V
1.3 V
0.3 V
tw
OUTPUT
ENABLE
GND
1.3 V
GND
tPZL
1/fmax
tPLH
Q
tPZH
Q
tTLH
HIGH
IMPEDANCE
1.3 V
Q
tPHL
90%
1.3 V
10%
tPLZ
tPHZ
10%
VOL
90%
VOH
1.3 V
HIGH
IMPEDANCE
tTHL
Figure 1.
Figure 2.
TEST POINT
VALID
OUTPUT
3.0 V
DEVICE
UNDER
TEST
1.3 V
DATA
GND
tsu
th
CL*
3.0 V
1.3 V
GND
CLOCK
*Includes all probe and jig capacitance
Figure 3.
Figure 4. Test Circuit
TEST POINT
1 kΩ
OUTPUT
DEVICE
UNDER
TEST
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 5. Test Circuit
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5
MC74HCT574A
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
–T–
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
M
T A
M
T B
M
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
q
A
20
X 45 _
M
E
h
0.25
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
18X
e
A1
SEATING
PLANE
DIM
A
A1
B
C
D
E
e
H
h
L
q
C
T
http://onsemi.com
6
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74HCT574A
Notes
http://onsemi.com
7
MC74HCT574A
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MC74HCT574A/D
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