Sanyo LC651304A 4-bit single-chip cmos microcontroller for small-scale control application Datasheet

Ordering number : ENN*6829
CMOS IC
LC65F1306A
4-Bit Single-Chip CMOS Microcontroller for
Small-Scale Control Applications
Preliminary
Overview
The LC65F1306A belongs to our 4-bit single-chip microcontroller LC6500 series fabricated using CMOS process
technology. They are ideally suited for use in small-scale control applications. Their basic architecture and instruction set
are the same. These microcontrollers include an 8-input 8-bit A/D converter and are appropriate for use in a wide range of
applications. That range includes applications with a small number of control circuits that were previously implemented in
standard logic, and applications with a larger scale such as home appliances, automotive equipment, communications
equipment, office equipment, and audio equipment such as decks and players. This microcontroller, with some exceptions,
has identical functions to the LC651306A, 1304A, 1302A and 1301A mask ROM version microcontrollers. It can also be
used as an OTP version microcontroller. Further, through a rewrite operation on the FLASH memory, the LC65F1306A can
be used in applications where previously microcontrollers of this type could not have been implemented.
Features
1) CMOS technology for a low-power consumption operation (A standby function that can be invoked under program
control is also provided.)
2) Flash ROM/RAM
LC65F1306A Flash ROM : 6K × 8 bits, RAM : 256 × 4 bits
3) Instruction set : 81 instructions common to all microcontrollers of the LC6500 series
4) Wide operating voltage range : 3.0 V to 5.5 V
5) Instruction cycle time : 0.92 µs
6) On-chip serial I/O port
Ver.1.01
62600
N3000 RM (IM) TY No.6829-1/22
LC65F1306A
7) Flexible I/O port
• Number of ports : 5 ports / 18 pins (max.)
• All ports
: Input / output common
Input / output capacity voltage 15V max. (open-drain specification C and D only)
Output current
20 mA max. sink current (Can drive an LED directly)
• Support option for system specification
Output level in the reset mode
: high/low level for port C and D specified in 4-bit unit
8) Interrupt function
Interrupt by timer overflow (can be tested under program control)
Interrupt by the state of the INT pin or completion of transmission/reception at serial I/O port (can be tested under
program control)
9) Stack level :
8 levels (common use with interrupt)
10) Timer :
4-bit variable prescaler + 8-bit programmable counter
11) Clock oscillation options for user’s intended system
• Oscillator circuit options : two-pin RC oscillator
two-pin ceramic oscillator
• Divider circuit options : No divider
built-in divide by 3
built-in divide by 4
12) Continuous square wave output (64 times of the cycle time)
13) AD converter (successive approximation)
• Precise conversion (expressed in 8 bits), 8 input channels
14) Watchdog timer
• RC circuit time constant
• Watchdog timer reset function can be assigned to an external pin by the option.
15) Low voltage detection circuit
• Can be implemented by the option.
16) Factory shipment
• DIP24S, MFP24S
17) Flash Memory
• Rewrite block size :
• Erase / write voltage :
• Rewritable limit :
• Operating temperature :
128 bytes / page
3.0 to 5.5V
10000 times (target number, to be decided after evaluation)
0 to +85°C (when writing to the flash memory)
-20 to +85°C (when reading from the flash memory)
No.6829-2/22
LC65F1306A
Function Table
Memory
Parameter
ROM
RAM
Instructions
On-chip
functions
Instruction set
Table reference
Interrupt
Timer
Stack level
Standby function
I/O ports
Characteristics
Oscillator
Other items
Port number
Serial port
LC651306A/04A/02A/01A
6144 × 8 bits (1306A)
4096 × 8 bits (1304A)
2048 × 8 bits (1302A)
1024 × 8 bits (1301A)
256 × 4 bits
(1306A/04A/02A/01A)
81
Supported
1 external, 1 internal
4-bit variable prescaler + 8-bit
timers
8
Standby mode by the HALT
instruction supported
18 I/O port pins
Input and output in 4 or 8 bit
units
LC65F1306A
6144 × 8 bits
256 × 4 bits
81
Supported
1 external, 1 internal
4-bit variable prescaler + 8-bit
timers
8
Standby mode by the HALT
instruction supported
22 I/O port pins
Input and output in 4 or 8 bit
units
I/O
voltage
15 V max.
15 V max.
capacity
Output current
10 mA typ. 20 mA max.
10 mA typ. 20 mA max.
I/O circuit type
Open drain (N-channel) or
Open drain (N-channel)
pull-up resistor output option
can be specified in 1- bit unit.
Output level at High or low level output can be selected in port unit (ports C and D
reset
only)
Square wave output
Supported
Supported
Minimum
cycle
0.92 µs (VDD ≥ 2.5 V)
0.92 µs (VDD ≥ 3.0 V)
time
Operating
-40°C to +85°C
0°C to +85°C (when writing)
temperature
-20°C to +85°C (when reading)
Supply voltage
2.5 to 6 V
3.0 to 5.5 V
Supply current
1.5 mA typ.
3 mA typ.
Oscillator
RC (800 kHz typ.)
RC (800 kHz typ.)
Ceramic (400k, 800k,1MHz,
Ceramic (400k, 800k,1MHz,
4MHz)
4MHz)
Divider
circuit
1/1, 1/3, 1/4
1/1, 1/3, 1/4
option
Package
DIP24S MFP24S SSOP24
DIP24S MFP24S
Watchdog timer
Supported
Supported
OTP
Only DIP24S MFP24S
-
Note: The above oscillator and oscillator circuit constants are tentative. They will be announced as the recommended circuits
for these microcontrollers are determined. Please confirm the progress of these developments periodically.
No.6829-3/22
LC65F1306A
Pin Assignment
DIP24S, MFP24S
CE/RES
1
24
OSC1
OE/PE0/SQR
2
23
OSC2
WE/PE1/WDR
3
22
TEST/EPMOD
ALE/PF0/SI/AD4
4
21
VSS
A0/A7/PF1/SO/AD5
5
20
PD3/D7
A1/A8/PF2/SCK/AD6
6
19
PD2/D6
A2/A9/PF3/INT/AD7
7
18
PD1/D5
A3/A10/PA0/AD0
8
17
PD0/D4
A4/A11/PA1/AD1
9
16
PC3/D3
A5/A12/PA2/AD2
10
15
PC2/D2
A6/PA3/AD3
11
14
PC1/D1
VDD
12
13
PC0/D0
: Pin function names used when writing data to on-chip Flash ROM with the PROM writer
Pin Functions
OSC1, OSC2
RES
PA0-3
PC0-3
PD0-3
PE0-1
PF0-3
:
:
:
:
:
:
:
Ceramic Oscillator for OSC, RC
Reset
Common I/O port A0-3
Common I/O port C0-3
Common I/O port D0-3
Common I/O port E0-1
Common I/O port F0-3
TEST
AD0-AD7
SQR
WDR
INT
SI
SO
SCK
:
:
:
:
:
:
:
:
Test
AD converter analog input
Square wave output
Watch Dog Reset pin
Interrupt Request pin
Serial Input pin
Serial Output pin
Serial Clock input/output pin
Notes: • SQR and WDR are common with PE0 and PE1 respectively.
• SI, SO, SCK, and INT are common with PF0 to PF3 respectively.
No.6829-4/22
LC65F1306A
Package Dimension
(unit : mm)
3067A
SANYO : DIP24S(300mil)
Package Dimension
(unit : mm)
3112A
SANYO : MFP24S(300mil)
No.6829-5/22
LC65F1306A
System Block Diagram
LC65F1306A
PA0-3
AD0-3
PF0-3
AD4-7
Port F
PC0-3
Port C
PD0-3
Port D
Serial
shift
register
PF1/SO
4/8 bit
STACK 1
to
DP
STACK 8
IR
I.DEC
System Bus
E
AC
STS
CF
ALU
Serial
mode
register
TM CTL
INT
Serial
mode
register
OSC
OSC1
OSC2
RES
TEST
VDD
VSS
I/O Bus
Serial
shift
register
ZF EXTF TMF
CSF ZSF
lower digit
4 bit
FLASH
ROM
PC
F WR
I/O Buffer
8-BIT
ADC
Shared with port F
RAM
Port A
Port E
higher digit
PF0/SI
PF2/SCK
4/8 bit
PE0-1
WDR
PF3/INT
RAM
F
WR
AC
ALU
DP
E
CTL
OSC
TM
STS
:
:
:
:
:
:
:
:
:
:
:
Data Memory
Flag
Working Register
Accumulator
Arithmetic and Logic Unit
Data Pointer
E register
Control register
Oscillation Circuit
Timer
Status register
FLASH ROM
PC
INT
IR
I.DEC
CF, CSF
ZF, ZSF
EXTF
TMF
:
:
:
:
:
:
:
:
:
Program Memory
Program Counter
Interrupt control
Instruction Register
Instruction Decoder
Carry Flag, Carry Save Flag
Zero Flag, Zero Save Flag
External Interrupt Request Flag
Internal Interrupt Request Flag
No.6829-6/22
LC65F1306A
Development Support
The following are currently in the development stage and will soon be available to the user for the development of the
LC65F1306A.
1.
2.
3.
4.
User’s manual
Refer to the “LC65F1306A/LC651300 series user’s manual.”
Development tool manual
Refer to the “EVA86000 Development Tool Manual for 4-bit microcontrollers.”
Software manual
“LC65/66 Series Software Manual”
Development tool
a. For program development (EVA86000 system)
b. For program evaluation
Microcontroller with Flash ROM (LC65F1306)
Pin Functions
Number
of pins
I/O
VDD
VSS
OSC1
1
1
1
Input
OSC2
1
PA0-PA3/
AD0-AD3
4
PC0-PC3
4
PD0-PD3
4
Symbol
Function
Power supply
Option
-
• Pins for connecting system clock (1) Two-pin RC oscillator,
oscillation RC or ceramic resonator.
external clock
• Leave OSC2 open when OSC1 is (2) Two-pin ceramic oscillator
Output
used for an external clock input
(3) Divider option
1. No divider
2. Divide by 3
3. Divide by 4
I/O
Open-drain output only
• I/O port A0 to A3
Input in 4-bit unit (IP instruction)
Output in 4-bit unit
(OP instruction)
Testing in 1-bit unit
(BP, BNP instructions)
Set and reset in 1-bit unit
(SPB, RPB instructions)
• PA3 is used for standby mode
control.
• Chattering should not be occurred
on the PA3 during HALT
instruction execution.
• All four pins have shared
function.
PA0/AD0:AD converter input AD0
PA1/AD1:AD converter input AD1
PA2/AD2:AD converter input AD2
PA3/AD3: converter input AD3
I/O
Open-drain output only
•I/O port C0 to C3
The port functions are identical to
(1) High level output during
those of PA0 to PA3 (See note).
reset.
(2) Low level output during
• The output during a reset can be
selected to be either high or low as
reset.
an option.
• (1) and (2) are specified
Note: This port has no standby
4 bits at a time
mode control function.
I/O
Same as PC0 to PC3.
•I/O port D0 to D3
The port functions and options are
identical to those of PC0 to PC3.
At reset
Handling
when unused
-
-
-
-
High-level
output (The
output
N-channel
transistors in
the off state.)
Select the
open-drain
output
option and
connect to
VSS.
• High-level Same as PA0 to
PA3.
output.
• Low-level
output.
(Depending
on options
selected)
Same as PC0 to Same as PA0 to
PC3.
PA3.
No.6829-7/22
LC65F1306A
Number
of pins
I/O
Function
Option
PE0-PE1
/WDR
2
I/O
Open -drain output only
(1) Normal port PE1
(2) Watchdog reset WDR
• Either options (1) or
(2) can be selected.
PF0/SI/A
D4
PF1/SO/
AD5
PF2/ SCK
/AD6
PF3/ INT
/AD7
4
I/O
• I/O port E0 to E1
Input in 4-bit unit (IP instruction)
Output in 4-bit unit (OP instruction)
Set and reset in 1-bit unit
(SPB and PRB instructions)
Testing in 1-bit unit
(BP and BNP instructions)
• PE0 also has a continuous pulse (64
Tcyc) output function.
• PE1 becomes the watchdog reset pin
WDR when selected as an option.
• I/O port F0 to F3
The port functions and options are
identical to those of PE0 to PE1 (See
note).
• PF0 to PF3 have shared functions
with the serial interface pins and the
INT input.
The function can be selected under
program control.
SI... Serial input pin
SO...Serial output pin
SCK...Input and output of the serial
clock signal.
INT...Interrupt request signal
The serial I/O function can be
switched between 4-bit and 8-bit
transfers under program control.
Note: There is no continuous pulse
output function.
• All four pins have shared function.
PF0/AD4: AD converter input AD4
PF1/AD5: AD converter input AD5
PF2/AD6: AD converter input AD6
PF3/AD7: AD converter input AD7
• System reset input
• Provide an external capacitor for the
power-on reset.
• Apply low level to this pin for 4 or
more clock cycles to reset and restart
the program.
• Test pin for LSI.
This pin must be connected to VSS
during normal operation.
Symbol
RES
1
Input
TEST
1
Input
At reset
Handling
when
unused
High level
output (The
output
N-channel
transistors in
the off state)
Identical to
those for
PA0 to
PA3.
Identical to those for PA0 to Identical to
those for PA0
PA3.
to PA3.
Identical to
those for
PA0 to
PA3.
The serial port
functions are
disabled.
The interrupt
source is set to
INT.
-
-
-
-
-
This pin
must be
connected
to VSS.
No.6829-8/22
LC65F1306A
User Option
User option is selected according to the information written to the user option area on the on-chip Flash ROM.
Oscillator Circuit Options
Option
External clock
Circuit
Conditions and notes
The OSC2 pin should be
left open.
OSC1
Two-pin RC oscillator
OSC1
Cext
OSC
Rext
Ceramic oscillator
OSC1
C1
Ceramic
Resonator
OSC2
C2
R
Divider Circuit Options
fOSC
fOSC
Divide by 3
fOSC
3
fOSC
4
Divide by 4
Timing
Generator
Oscillator circuit
fOSC
Timing
Generator
Built-in
divide-by-four
circuit
Oscillator circuit
Built-in
divide-by-three
circuit
Conditions and notes
• The oscillator frequency or external clock
frequency should not exceed 4330 kHz.
Timing
Generator
Circuit
Oscillator circuit
Option
No divider
(1/1)
• This option can only be used with the
external clock and the ceramic oscillator
options.
• The oscillator frequency or external clock
frequency should not exceed 4330 kHz.
• This option can only be used with the
external clock and the ceramic oscillator
options.
• The oscillator frequency or external clock
frequency should not exceed 4330 kHz.
Note: The following table summarizes the oscillator and divider circuit options. When selecting the divider option, the
relationship between frequency and cycle time must be taken into account.
No.6829-9/22
LC65F1306A
LC65F1306A Oscillator Options
Circuit type
Ceramic resonator
Frequency
400 kHz
Divider option
(Cycle time)
VDD
range
3 to 5.5V
1/1 (10µs)
Notes
Can not be used with the divide-by-three
and divide-by-four options.
800 kHz
1 MHz
4 MHz
External clock (used
with the 2-pin RC
oscillator circuit)
Two-pin RC
External clock used with
the ceramic oscillator
option
3 to 5.5V
1/1 (5µs)
3 to 5.5V
1/1 (4µs)
3 to 5.5V
1/1 (1µs)
3 to 5.5V
1/3 (3µs)
3 to 5.5V
1/4 (4µs)
384 k to 4330 kHz
3 to 5.5V
1/1 (10.4 to 0.92µs)
1152 k to 4330 kHz
3 to 5.5V
1/3 (10.4 to 2.77µs)
1536 k to 4330 kHz
3 to 5.5V
1/4 (10.4 to 3.70µs)
Use the no divider circuit option and the
3 to 5.5V
recommended circuit constants. When using
other constants by necessity, use the frequency
and VDD range identical to the external clock
written above.
External clock drive is not possible. To use external clock drive, select the 2-pin RC oscillator option.
Port C and D Output level Option During Reset
The Output level of the C and D ports at reset can be selected from the following two options in 4-bit unit.
Option
High level output at reset
Low level output at reset
Conditions and notes
Ports C and D in 4-bit unit
Ports C and D in 4-bit unit
Port Output Type
The I/O port type is open-drain output.
Option
Open-drain output
Circuit
Ports
Ports A, C, D, E and F
Watchdog Reset Option
This option allows the user to select how the PE1/WDR pin is to be used. It can be used as the normal port PE1, or used as the
watchdog reset pin WDR.
No.6829-10/22
LC65F1306A
1. Absolute Maximum Ratings at Ta=25°C, VSS=0V
Parameter
Symbol
Maximum
supply voltage
Output voltage
VDD max
Applicable pins
and notes
VDD
VO
OSC2
Input voltage
VI (1)
VI (2)
I/O voltage
VIO (1)
PC0 to 3, PD0 to 3
VIO (2)
PC0 to 3, PD0 to 3
OSC1 (Note 1)
TEST, RES
AV+, AVOpen-drain
-0.3 to +15
specification
ports
Pull-up resistor -0.3 to VDD+0.3
specification
ports
-0.3 to VDD+0.3
I/O Port
-2 to +20
VIO (3)
Peak
output IOP
current
Average
IOA
output current
∑IOA(1)
Maximum
power
consumption
Operating
temperature
Storage
temperature
Conditions
PA0 to 3, PE0, 1, PF0 to 3
Ratings
-0.3 to +6.5
unit
V
Output voltage
generated can be
over the
maximum limit
of the VDD.
-0.3 to VDD+0.3
-0.3 to VDD+0.3
Average current applied to a pin I/O Port
for 100 ms
The total current of PC0 to 3, PC0 to 3
PD0 to 3 and PE0 to 1. (Note 2)
PD0 to 3
PE0 to 1
The total current of PF0 to 3 and PF0 to 3
∑IOA(2)
PA0 to 3. (Note 2)
PA0 to 3
Pd max (1) Ta=-20 to +85°C (DIP package)
Pd max (2) Ta=-20 to +85°C (MFP package)
-2 to +20
Topr
-20 to +85
Tstg
-55 to +125
mA
-15 to +100
-15 to +100
310
220
mW
°C
No.6829-11/22
LC65F1306A
2. Recommended Operating Range at Ta=-20 to +85°C, VSS=0V, VDD=3.0 to 5.5V (Unless otherwise specified)
Parameter
Operating supply
voltage
Standby supply
voltage
High level input
voltage
Symbol
Conditions
VDD
VST
VIH(1)
RAM and register values retained.
(Note 3)
Output Nch Tr. off
VIH(2)
VIH(3)
Output Nch Tr. off
Output Nch Tr. off
VIH(4)
Low level
input voltage
VIH(5)
VIL(1)
VIL(2)
VIL(3)
External clock specifications
Output Nch Tr. off VDD=4 to 5.5V
Output Nch Tr. off 3 to 5.5V
Output Nch Tr. off VDD=4 to 5.5V
VIL(4)
Output Nch Tr. off 3 to 5.5V
VIL(5)
External
clock VDD=4 to 5.5V
specification
External
clock 3 to 5.5V
specification
VDD=4 to 5.5V
3 to 5.5V
VDD=4 to 5.5V
VIL(6)
VIL(7)
VIL(8)
VIL(9)
Operating frequency
(cycle time)
External clock
conditions
Frequency
Pulse width
Rising/falling time
Recommended
oscillation constants
Two-pin RC
oscillator
Ceramic oscillator
(Note 4)
min.
3.0
VDD
1.8
5.5
Port C, D with
open-drain
specifications.
Port A, E, F
0.7VDD
13.5
0.7VDD
0.8VDD
VDD
VDD
0.8VDD
VDD
INT, SCK, SI
0.8VDD
VSS
VSS
VSS
VDD
0.3VDD
0.25VDD
0.25VDD
INT, SCK, SI
OSC1
VSS
0.2VDD
VSS
0.25VDD
OSC1
VSS
0.2VDD
TEST
TEST
VSS
VSS
VSS
0.3VDD
0.25VDD
0.25VDD
The INT, SCK,
and SI pin with
open-drain
specifications.
VDD=1.8 to 5.5 V
VIL(10)
3 to 5.5V
fop
(Tcyc)
VDD=3 to 5.5V
Ratings
typ.
Applicable pins
and notes
VDD
RES
OSC1
Port
Port
RES
RES
max.
5.5
unit
V
VSS
0.2VDD
384
(10.4)
4330
(0.92)
kHz
(µs)
4330
kHz
Fig. 1
text
textH,
textL
textR,
textF
Cext
Rext
Fig. 2
Fig. 3
VDD=3 to 5.5V
OSC1
384
VDD=3 to 5.5V
OSC1
69
VDD=3 to 5.5V
OSC1
VDD=3 to 5.5V
OSC1, OSC2
ns
50
270±5%
5.6±1%
pF
kΩ
See Table
1
No.6829-12/22
LC65F1306A
3. Electrical Characteristics at Ta=-20 to +85°C, VSS=0V, VDD=3.0 to 5.5V (Unless otherwise specified)
Parameter
Input High level
current
Symbol
IIH(1)
IIH (2)
IIH (3)
Input Low level
current
Output High level
voltage
Output Low level
voltage
IIL(1)
Ports with the
pull-up
resistor
specifications
Ports with the
pull-up
resistor
specifications
Port
VDD-1.2
IOH=-10 µA
VOL(1)
IOL=10 mA
VDD=4.0 to 6.0 V
IOL=1 mA,
IOL of each Port : 1 mA or less
VtH
-1.3
-0.35
mA
RES
-45
-10
µA
OSC1
-1.0
VtL
Two-pin RC oscillator
IDDOP (1)
IDDOP (2)
IDDOP (3)
IDDOP (4)
IDDOP (5)
IDDOP (6)
IDDOP (7)
IDDOP (8)
IDDst
V
VDD-0.5
1.5
Port
RES, INT, SCK,
SI, and schmitt
specification
OSC1
(Note 5)
• Output N-channel transistors are
off when operating
• Port = VDD
• Fig. 2, fosc=800 kHz (typical)
• Fig. 3, 4 MHz, no divider
• Fig. 3, 4 MHz, divide-by-three
circuit
• Fig. 3, 4 MHz, divide-by-four
circuit
• Fig. 3, 400 kHz
• Fig. 3, 800 kHz
• 384 kHz to 4330 kHz, no divider
• 1152 kHz to 4330 kHz,
divide-by-three circuit
• 1536 kHz to 4330 kHz,
divide-by-four circuit
Output N-channel, VDD=6V
transistor off
Ports=VDD
VDD=2.5V
µA
-1.0
When external clock is used,
VIN=VSS
IOH=-50 µA
VDD=4.0 to 6.0V
VOH (2)
unit
1.0
VIN=VSS
High level
threshold
voltage
Low level
threshold
voltage
Current consumption
Schmitt characteristics
Ports with the
open-drain
specifications
Ports with the
pull-up
resistor
specifications
max.
5.0
1.0
IIL(3)
VOH (1)
Ratings
typ.
Port A, E and G
with
the
open-drain
specifications
OSC1
IIL(4)
VHIS
Standby mode
min.
Output Nch Tr. OFF
VIN=VSS
Hysteresis
Voltage
External clock
Output Nch Tr. OFF
(including OFF leak current
of Nch Tr.)
VIN=+13.5V
Output Nch Tr. OFF
(including OFF leak current
of Nch Tr.)
VIN=VDD
When external clock is used,
VIN=VDD
Output Nch Tr. OFF
VIN=VSS
Applicable pins
and notes
Port C and D with
the
open-drain
specifications
IIL(2)
VOL(2)
Ceramic oscillator
Conditions
0.5
0.1VDD
0.4VDD
0.8VDD
0.2VDD
0.6VDD
VDD
mA
3.0
6
VDD
VDD
4.0
3.0
10
8
VDD
3.0
6
VDD
VDD
VDD
VDD
2.0
3.0
4.0
3.0
5
6
10
8
VDD
0.05
10
VDD
0.025
5
µA
No.6829-13/22
LC65F1306A
Parameter
Oscillation
characteristics
Ceramic resonator
Frequency
Oscillation
stabilizing time
(Note 8)
Two-pin RC
oscillator frequency
Pull-up resistance
Symbol
fCFOSC
(Note 7)
tCFS
fMOSC
Ru
Conditions
• Fig. 3 fo=400kHz
• Fig. 3 fo=800kHz
• Fig. 3 fo=1MHz
• Fig. 3 fo=4MHz, with no divider,
divide-by-three, or divide-by-four
circuit
• Fig. 4 fo=400kHz
• Fig. 4 fo=800kHz, 1MHz, or
4MHz, with no divider,
divide-by-three, or divide-by-four
circuit
• Fig. 2 Cext=270pF±5%
• Fig. 2 Rext=5.6kΩ±1%
VIN=VSS VDD=5V
Pin
OSC1,OSC2
OSC1,OSC2
OSC1,OSC2
OSC1,OSC2
min.
392
784
980
3920
Ratings
typ.
400
800
1000
4000
max.
unit
408
816
1020
4080
kHz
10
10
ms
OSC1, OSC2
587
800
1298
kHz
RES
200
500
800
kΩ
RES
External reset
characteristics
Reset time
Pin capacitance
Serial clock
Input clock Cycle
time
Output clock Cycle
time
Input clock low
level pulse width
Output clock low
level pulse width
Input clock high
level pulse width
Output clock high
level pulse width
Serial input
Data setup time
Data hold time
tRST
Cp
See Fig.5
10
f=1MHz,
Pins except for tested pins,
VIN=VSS
pF
SCK
Fig. 6
tCKCY(2)
Fig. 6
SCK
tCKL(1)
Fig. 6
SCK
tCKL(2)
Fig. 6
SCK
tCKH(1)
Fig. 6
SCK
tCKH(2)
Fig. 6
SCK
tICK
tCKI
Specified for the rising edge of
SI
SI
SCK
µs
2.0
tCKCY(1)
64×tCYC
(Note 9)
0.6
32×tCYC
0.6
32×tCYC
0.2
0.2
Fig. 6
Serial output
Output delay time
tCKO
• Specified for the falling edge of
SO
0.4
SCK
• Select only Nch OD option, and
add external 1kΩ resistor and
external 50pF capacitor.
• Fig. 6
No.6829-14/22
LC65F1306A
Parameter
Pulse output
Period
High level pulse
width
Symbol
A/D converter characteristics
Applicable
pins and notes
Analog input
voltage range
Analog port
input current
PE0
PE0
tPL
• Select only Nch OD
option,
and add external 1kΩ
resistor and external 50pF
capacitor.
PE0
TCAD
8
±1
AV+=VDD
AV-=VSS
When AD speed is
1/1=26*TCYC
VAIN
IAIN
Cw
Including the output off
leakage current.
VAIN=VDD
VAIN=VSS
tWCT
tWCCY
Fig.8
Cw
tWCT
When PE1 is using
open-drain
When PE1 is using
open-drain
When PE1 is using
open-drain
Fig.8
tWCCY
Fig.8
Rw
Rw
Rl
Clear time
(discharge)
Clear period
(charge)
AD0 to AD7
When PE1 is using
open-drain
When PE1 is using
open-drain
When PE1 is using
open-drain
Fig.8
Ratings
typ.
max.
unit
64×TCYC
32×TCYC
±10%
32×TCYC
±10%
3 to 5.5
Rl
Clear time
(discharge)
Clear period
(charge)
Recommended
constants
(Note 10)
min.
µs
• Fig.7
• TCYC=4 × system clock
When AD speed is
1/2=51*TCYC
Recommended
constants
(Note 10)
Watch dog timer
VDD[V]
tPCY
tPH
Low level pulse
width
Resolution
Absolute
precision
Conversion
time
Conditions
3 to 5.5
3 to 5.5
AD0 to AD7
(The shared
I/O function
ports have
open-drain
specification)
WDR
24
(TCYC=
0.92µs)
47
(TCYC=
0.92µs)
VSS
±2
bit
LSB
260
(TCYC=
10µs)
510
(TCYC=
10µs)
VDD
µs
1
µA
V
-1
0.1±5%
µF
WDR
680±1%
kΩ
WDR
100±1%
Ω
WDR
100
µs
WDR
36
ms
WDR
0.01±5%
µF
WDR
680±1%
kΩ
WDR
100±1%
Ω
WDR
10
µs
WDR
4.2
ms
Notes:
(1) When oscillated internally under the oscillating conditions in Fig.3, generated voltage can be over the maximum limit of
the VDD.
(2) Average for 100 ms period.
(3) Operating supply voltage VDD must be held until the microcontroller enters in the standby mode after the execution of the
HALT instruction. Any chattering should not be generated at the PA3 pin during the HALT instruction execution cycle.
(4) Recommended circuit constants that are verified by the oscillator manufacturer, using oscillator characteristic evaluation
board selected by SANYO.
(5) The OSC1 pin will have schmitt characteristics when external clock oscillator or the two-pin RC oscillator is selected as
an oscillation option.
(6) These are the results of testing using the value at each part on the Fig.3 circuit which is recommended by SANYO. These
results do not include the current applied to the output transistor, nor the current applied to the transistor with a pull-up
resistor on the LSI.
(7) fCFOSC is the frequency when the values in table 1 are used.
(8) This indicates the elapsed time that is required before the oscillation becomes stable after the VDD exceeds the minimum
limit of the operation supply voltage.
(9) TCYC=4×system clock period
(10) When used in an environment that may result in condensation, note that a current leakage between PE1 and adjacent pins
No.6829-15/22
LC65F1306A
or a current leakage at external integration circuit using R and C could occur.
OSC1
(OSC2)
External Clock
OPEN
VDD
0.8VDD
0.2VDD
textL
textF
textR
VSS
textH
text
Figure 1 External Clock Input Waveform
OSC1
OSC1
OSC2
OSC2
R
Rext
Cext
C1
C2
Ceramic
Resonator
Figure 2 Two-pin RC Oscillator Circuit
Figure 3 Ceramic Resonator Circuit
No.6829-16/22
LC65F1306A
VDD
The lowest limit of
the operating VDD
0V
Stable oscillation
Oscillation
stabilizing time
tCFS
Figure 4 Oscillation Stabilizing Time
Table 1 Recommended Ceramic Resonator constants
Data will be added once evaluation has been
completed.
RES
CRES(=0.1 µF)
Figure 5 Reset Circuit
(Note) If measured from the instant the voltage level
reaches the lowest limit of the operating VDD
(i.e. not including the rising time), the reset
time when CRES=0.1 µF is used should be
between 10 ms to 100 ms.
No.6829-17/22
LC65F1306A
tCKCY
0.8VDD
tCKL
tCKH
0.2VDD
SCK
tICK
SI
tCKI
VDD
Input Data
1kΩ
Load circuit
tCKO
SO
50pF
Output Data
Figure 6 Serial I/O Timing
tPCY
tPH
0.7VDD
The load conditions are
the same as those in
Figure 5.
0.25VDD
tPL
Figure 7 Port PE0 Pulse Output Timing
Rw
RI
PE1/WDR
Cw
tWCCY
tWCT
tWCCY : Charge time made by the external Cw, Rw, and Rl time constants
tWCT
: Discharge time made by program control
Figure 8 Watchdog Timer Waveform
No.6829-18/22
LC65F1306A
RC Oscillator Characteristic of LC65F1306A
Data will be added once evaluation has been completed.
No.6829-19/22
LC65F1306A
Notes on Circuit Board Design
This section provides hints and countermeasure for noise problem in terms of microcontroller when designing circuit boards
using these microcontrollers for a mass production. These design techniques are effective to prevent and avoid the defects (e.g.
malfunctions of the microcontroller or a runaway program) caused by noise.
1. VDD, VSS : Power Supply Pins
Add capacitors between the VDD and VSS pins so that they meet the following conditions.
• The length of the line from the VDD to the two capacitors and the length of the line from the VSS to the two capacitors
should be as equal as possible (L1=L1’, L2=L2’), and should be as short as possible.
• Add the larger capacitor to ‘C1’ position and smaller capacitor to ‘C2’ position.
The VDD and VSS lines on the circuit board should be thicker than any other lines.
L2
L1
C1
VSS
C2
+
VDD
L1'
L2'
Lvss
L1
VSS
C1
L2
OSC1
C2
Rd
OSC2
Losc
Figure 2-1. Sample Oscillation Circuit 1
(Ceramic resonator)
Lvss
Lc
2. OSC1, OSC2 : Clock I/O Pins
• When the ceramic resonator option is selected : (Figure 2-1)
• The length of the lines (Losc in Fig.2-1) between the clock I/O
pins (input: OSC1, output: OSC2) and the external components
should be as short as possible.
• The length of the lines (Lvss+L1 or L2 ) between each capacitor
and the VSS pin should be as short as possible.
• The VSS line for the oscillation circuit and the VSS line for other
functions should be branched as close as possible to the
microcontroller's VSS pin.
• Oscillation constants written in this specification sheet (such as the
capacitor C1, C2 and the damping resistor Rd) may have to be
changed and the frequency should be adjusted, depending on the
pattern capacity of the circuit board. In this case, contact the
oscillator manufacturer about it.
• When two-pin RC oscillator option is selected: (Figure 2-2)
• The length of the lines (Losc) between the clock I/O pins (input:
OSC1, output: OSC2) and the external components (capacitor
Cext, resistor Rext) should be as short as possible.
• The length of the line (Lvss+Lc) between the capacitor and the
VSS pin should be as short as possible.
• The VSS line for the oscillation circuit and the VSS line for other
functions should be branched as close as possible to the
microcontroller's VSS pin.
• When the external oscillation option is selected: (Figure 2-3)
• The length of the line (Losc) between the clock input pin (OSC1)
and the external oscillator should be as short as possible.
• The clock output pin (OSC2) should be opened.
• The length of the line between the VSS and the external oscillator,
and the length of the line between the VDD and the external
oscillator should be as short as possible.
VSS
Cext
OSC1
Rext
OSC2
Losc
Figure 2-2. Sample Oscillation Circuit 2
(Two-pin RC Oscillator)
Losc
VSS
External
Oscillator
OPEN
OSC1
OSC2
VDD
Figure 2-3. Sample Oscillation Circuit 3
(External Oscillator)
No.6829-20/22
LC65F1306A
• Other note on all oscillator circuit:
• Place the lines for signals that can easily change suddenly, high amplitude signals connected to the higher capacity voltage
(+15 V) ports, and powerful current supplies as far as possible from the oscillation circuit, and do not cross these lines
with lines concerned to the clock.
3. RES : Reset Pin
• The length of line (Lres) between the RES pin and the external circuit should be as short as possible.
• The length of lines (L1 and L2) between the RES pin and the capacitor (Cres), and the VSS and the capacitor should
be as short as possible.
L2
External
Circuit
VSS
Cres
RES
L1
Lres
Figure 3. RES Pin Patterns
4. TEST : Test Pin
• The length of line (L) between the VSS and the TEST pin should be as short as possible.
• The TEST pin and the VSS pin should be connected as close as possible to the VSS pin.
VSS
L
TEST
Figure 4. Test Pin Patterns
5. AD0 to AD7 : Analog Input Pins
The connection for the analog input pins, such as A/D converter input pins and comparator input pin, should meet the
following conditions.
• The length of the line (L1) between the damping resistor (R1) and each analog pins should be as short as possible.
• The capacitor added between each analog pins and AV- pin (base voltage input pin for A/D converter) should be located
as close as possible to the AV- input pin.
L2
External circuit
(sensor block)
Analog
Input Pins
AD3-0
C
L1
AD4-7
Rl
AVVSS
Figure 5. Analog Input Pins Patterns
6. I/O Pins
All I/O pins on these microcontrollers have function of both input and output.
• When used as an input pin, add a damping resistor and keep the length of the line to that pin as short as possible.
No.6829-21/22
LC65F1306A
[Supplement]
In addition to the techniques for designing a circuit board, the following options and programming are effective to
prevent and avoid the defects (the malfunction or a runaway program).
• If signals are input from external sources when the microcontroller power supply is unstable, select the higher
capacity voltage (N-channel open drain) output type for the input pin, and add a damping resistor close to the
pin.
• When the external signals are input to pins, the chattering of the key must be removed.
• The data should be output periodically from the pins using the output instruction (OP or SPB).
• To read the data input to the I/O common pins, the output value should be set to ‘1’ using the output instruction
(OP or SPB).
7. Unused Pins
• See the user’s manual for each microcontrollers or the final edition of the specification sheet.
PS No.6829-22/22
Similar pages