FIDELIX FMP1617CA0-FXXX 1m x 16 bit super low power and low voltage full cmos ram Datasheet

FMP1617CA0(7)
CMOS LPRAM
Document Title
1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM
Revision History
Revision
No.
History
Draft date
Remark
0.0
Initial Draft
Apr.19th, 2006
Preliminary
0.1
Revised P/N according to the new P/N system
Jun.01st , 2006
Preliminary
1
Revision 0.1
Jun. 2006
FMP1617CA0(7)
CMOS LPRAM
1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM
FEATURES
• Process Technology : Full CMOS
• Three state output and TTL Compatible
• Package Type : 48-FBGA-6.00x8.00 mm2
• Organization : 1M x 16
• Power Supply Voltage : 2.7~3.3V
• Dual CS & Page Modes
FMP1617CA0(7)-FxxX : Normal
FMP1617CA0(7)-GxxX : Pb-Free
FMP1617CA0(7)-HxxX : Pb-Free & Halogen Free
FMP1617CA0 : Dual CS
FMP1617CA7 : Page mode with Dual CS
• Operating Temperature Ranges:
• Separated I/O power(VCCQ) & Core Power(VCC)
• Easy memory expansion with /CS1, CS2, and /OE features
• Automatic power-down when deselected
Special (-10’C to +60’C)
Commercial (0’C to +70’C)
Extended (-25’C to +85’C)
Industrial (-40’C to +85’C)
PRODUCT FAMILY
Power Dissipation
Operating
Voltage (V)
ICC1
ICC2
f = 1MHz
f = fmax
Speed
Product Family
Min. Typ. Max.
FMP1617CA0(7)-G60E
FMP1617CA0(7)-G70E
3.0
2.7
Typ.
60ns
70ns
3.3
1.5mA
ISB1
(CMOS Standby
Current)
Max.
Typ.
Max.
Typ.
Max.
3mA
15mA
12mA
20mA
70uA
100uA
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C.
2. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER
3. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C)
PIN DESCRIPTION
1
2
3
4
5
6
A
/LB
/OE
A0
A1
A2
CS2
B
I/O9
/UB
A3
A4
/CS1
I/O1
C
I/O10
I/O11
A5
A6
I/O2
I/O3
D
VSS
I/O12
A17
A7
I/O4
VCC
E
VCCQ
I/O13
DNU
A16
I/O5
VSS
F
I/O15
I/O14
A14
A15
I/O6
I/O7
G
I/O16
A19
A12
A13
WE
I/O8
H
A18
A8
A9
A10
A11
NC
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
VCC
VSS
Row
Addresses
I/O1~I/O8
Row
select
Data
cont
Memory array
I/O Circuit
Column select
Data
cont
I/O9~I/O16
Data
cont
48-FBGA : Top View(Ball Down)
Column Addresses
Name
Function
Name
Function
CS2
Chip Select Input
VCC
Core Power
/CS1
Chip Select Input
VCCQ
I/O Power
/CS1
/OE
Output Enable Input
VSS
Ground
CS2
/WE
Write Enable Input
/UB
Upper Byte(I/O9~16)
A0~A19
Address Inputs
/LB
Lower Byte(I/O 1~8)
I/O1~I/O16
Data Inputs/Outputs
DNU
Do Not Use
/OE
/WE
Control Logic
/UB
/LB
2
Revision 0.1
Jun. 2006
FMP1617CA0(7)
CMOS LPRAM
PRODUCT LIST
Part Name
Function
FMP1617CA0(7)-G60E
FMP1617CA0(7)-G70E
48-FBGA, 60ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V)
48-FBGA, 70ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V)
1. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER
2. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C)
FUNCTIONAL DESCRIPTION
/CS1
CS2
/OE
/WE
/LB
/UB
I/O1-8
I/O9-16
Mode
Power
X1)
X1)
X1)
H
H
X1)
High-Z
High-Z
Deselect/Power-down
Standby
X1)
L
X1)
X1)
X1)
X1)
High-Z
High-Z
Deselect/Power-down
Standby
X1)
H
X1)
X1)
H
H
High-Z
High-Z
Deselect/Power-down
Standby
H
H
H
L
X1)
High-Z
High-Z
Output Disabled
Active
H
X1)
L
High-Z
High-Z
Output Disabled
Active
L
H
Dout
High-Z
Lower Byte Read
Active
H
L
High-Z
Dout
Upper Byte Read
Active
L
L
Dout
Dout
Word Read
Active
L
H
Din
High-Z
Lower Byte Write
Active
H
L
High-Z
Din
Upper Byte Write
Active
L
L
Din
Din
Word Write
Active
L
H
H
L
L
H
H
X1)
L
1. X means don’t care.(Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Symbol
Ratings
VIN, VOUT
-0.2 to Vcc+0.3V
V
Vcc
-0.2 to 3.6
V
PD
1.0
W
TSTG
-65 to 150
’C
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Unit
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to
recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Item
Symbol
I/O operating voltage (VCCQ ≤ VCC)
VSS
Supply voltage
Ground
Input high voltage
FMP1617CA
Max
VCC
2.7
3.3
2.7
3.3
2.7
3.3
V
VCCQ
2.7
3.3
2.25
2.75
1.65
1.95
V
0
0
0
0
0
0
V
0.8VCCQ
VCC+0.211
)
0.8VCCQ
VCC+0.21)
0.8VCCQ
VCC+0.21)
V
0.2VCCQ
-0.22)
0.2VCCQ
-0.22)
0.2VCCQ
V
VIH
Input low voltage
VIL
Note :
1. Overshoot : Vcc+1.0V in case of pulse width≤20ns.
2. Undershoot : -1.0V in case of pulse width≤20ns.
3. Overshoot and undershoot are sampled, not 100% tested.
-0.22)
3
Min
Max
Min
Max
Unit
Min
Revision 0.1
Jun. 2006
FMP1617CA0(7)
CMOS LPRAM
CAPACITANCE1) (f=1MHz , TA=25’C)
Symbol
Test Condition
Min
Max
Input capacitance
Item
CIN
VIN=0V
-
8
Unit
pF
Input/Output capacitance
CIO
VIO=0V
-
8
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Min
Typ
Max
Unit
Input leakage current
Item
Symbol
ILI
VIN=VSS to VCC
-1
-
1
uA
Output leakage current
ILO
/CS=VIH, CS2=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC
-1
-
1
uA
ICC1
Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, CS2=VIH,
VIN≤0.2V or VIN≥VCC-0.2V
-
-
3
mA
ICC2
Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, CS2=VIH,
VIN=VIL or VIH
-
-
20
mA
Output low voltage
VOL
IOL=0.5mA
0.2VCCQ
V
Output high voltage
VOH
IOH=-0.5mA
Standby Current(TTL)
ISB
/CS=VIH, CS2=VIH, Other inputs=VIH or VIL
-
-
0.3
mA
Standby Current(CMOS)
ISB1
/CS≥VCC-0.2V, CS2≤0.2V, Other inputs=0~VCC
-
-
100
uA
Average operating current
Test Conditions
0.8VCCQ
V
Operating Range
Device
Range
Ambient Temperature
FMP1617CA0(7)-XxxS
Special
-10℃ to +60℃
FMP1617CA0(7)-XxxC
Commercial
0℃ to +70℃
FMP1617CA0(7)-XxxE
Extended
-25℃ to +85℃
FMP1617CA0(7)-XxxI
Industrial
-40℃ to +85℃
4
VDD
VDDQ
2.7V to 3.3V
1.65V to Vcc
Revision 0.1
Jun. 2006
FMP1617CA0(7)
CMOS LPRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
30pf
Input pulse level : 0.2 to VCC-0.2V
Input rising and falling time : 5ns
Input and output reference voltage : 0.5*VCCQ
Output load(see right) : CL=30pF+1TTL
1TTL
AC CHARACTERISTICS(VCC=2.7V~3.3V)
Speed Bins
Parameter List
Read Cycle Time
Read
Write
60ns
tRC
70ns
Units
Min
Max
Min
Max
60
20k
70
20k
ns
Address Access Time
tAA
-
60
-
70
ns
Chip Select to Output
tCO
-
60
-
70
ns
Output Enable to Valid Output
tOE
-
25
-
25
ns
/UB, /LB Access Time
tBA
-
60
-
70
ns
Chip Select to Low-Z Output
tLZ
10
-
10
-
ns
/UB, /LB Enable to Low-Z Output
tBLZ
10
-
10
-
ns
Output Enable to Low-Z Output
tOLZ
5
-
5
-
ns
Chip Disable to High- Z Output
tHZ
0
5
0
5
ns
/UB, /LB Disable to High- Z Output
tBHZ
0
5
0
5
ns
Output Disable to High- Z Output
tOHZ
0
5
0
5
ns
Output Hold from Address Change
tOH
5
-
5
-
ns
Write Cycle Time
tWC
60
20k
70
20k
ns
ns
Chip Select to End of Write
tCW
50
-
60
-
Address Set-up Time
tAS
0
-
0
-
ns
Address Valid to End of Write
tAW
50
-
60
-
ns
/UB, /LB Valid to End of Write
tBW
50
-
60
-
ns
Write Pulse Width
tWP
50
-
50
-
ns
Write Recovery Time
Write to Output High-Z
Page
Symbol
tWR
0
-
0
-
ns
tWHZ
0
5
0
5
ns
Data to Write Time Overlap
tDW
20
-
20
-
ns
Data Hold from Write Time
tDH
0
-
0
-
ns
End Write to Output Low-Z
tOW
5
-
5
-
ns
Page Mode Cycle Time
tPC
20
-
25
-
ns
Page Mode Address Access Time
tPAA
-
20
-
25
ns
Maximum Cycle Time
tMRC
-
20k
-
20k
ns
/CS High Pulse Width
tCP
10
-
10
-
ns
1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High.
5
Revision 0.1
Jun. 2006
FMP1617CA0(7)
CMOS LPRAM
Power Up Sequence
1. Apply Power.
2. Maintain stable power for a minimum of 200us with /CS1=VIH and CS2=VIH.
Timing Waveform of Power Up
Min. 200us
VCC
Vcc(Min
)
/CS1
CS2
Power up mode
Normal Operation
6
Revision 0.1
Jun. 2006
FMP1617CA0(7)
READ CYCLE (1)
CMOS LPRAM
(Address controlled,/CS1=/OE=VIL, CS2=/WE=VIH, /UB or/and /LB=VIL)
tRC
Address
tOH
Data Out
READ CYCLE (2)
tAA
Previous Data Valid
Data Valid
(CS2=/WE=VIH)
tRC
Address
tOH
tAA
tCO
/CS1
CS2
tHZ
tBA
/UB, /LB
tBHZ
tOE
/OE
tOLZ
Data Out
tOHZ
tBLZ
tLZ
High-Z
Data Valid
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device
to device interconnection.
3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.
PAGE READ CYCLE
(CS2=/WE=VIH, 16 words access)
tMRC
tRC
tPC
tPC
tPC
tPC
tPC
tPC
tPC
A0~A3
tAA
A4~A20
tOH
tCO
/CS1
CS2
tHZ
tBA
/UB, /LB
tBHZ
tOE
/OE
tOLZ
tBLZ
Data Out
High-Z
tLZ
tPAA
tPAA
Data Valid
Data Valid
tPAA
Data Valid
tPAA
Data Valid
tPAA
Data Valid
tPAA
Data Valid
tPAA
Data Valid
tOHZ
Data Valid
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device
to device interconnection.
3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.
4. In case page address skew is over 3ns, tPAA will be out of spec.
7
Revision 0.1
Jun. 2006
FMP1617CA0(7)
WRITE CYCLE (1)
CMOS LPRAM
(/WE controlled)
tWC
Address
tCW(2)
tWR(4)
/CS1
CS2
tAW
tBW
/UB, /LB
tWP(1)
/WE
tAS(3)
tDW
Data in
tWHZ
Data Out
WRITE CYCLE (2)
tDH
Data Valid
High-Z
High-Z
tOW
Data Undefined
(/CS1 controlled)
tWC
Address
tAS(3)
tWR(4)
tCW(2)
/CS1
CS2
tAW
tBW
/UB, /LB
tWP(1)
/WE
tDW
Data in
Data Out
WRITE CYCLE (3)
tDH
Data Valid
High-Z
High-Z
(CS2 controlled)
tWC
Address
tWR(4)
tCW(2)
/CS1
tAS(3)
CS2
tAW
tBW
/UB, /LB
tWP(1)
/WE
tDW
Data in
Data Out
tDH
Data Valid
High-Z
High-Z
8
Revision 0.1
Jun. 2006
FMP1617CA0(7)
WRITE CYCLE (4)
CMOS LPRAM
(/UB, /LB controlled)
tWC
Address
tWR(4)
tCW(2)
/CS1
CS2
tAW
tBW
/UB, /LB
tAS(3)
tWP(1)
/WE
tDW
Data in
tDH
Data Valid
Data Out
High-Z
High-Z
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write
ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to
the end of write.
2. tCW is measured from the /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.
PAGE WRITE CYCLE
(Address controlled, CS2=VIH)
tMRC
tPC
tWC
tPC
tPC
tPC
tPC
tPC
tPC
A0~A3
A4~A20
/CS1
CS2
/UB, /LB
tAS(3)
/WE
tDW
Data in
High-Z
tDH
Data Valid
tDW
tDH
Data Valid
tDW
Data Valid
tWHZ
Data Out
tDH
tDW
tDH
Data Valid
tDW
tDH
Data Valid
tDW
tDH
Data Valid
tDW
tDH
Data Valid
tDW
tDH
Data Valid
High-Z
tOW
Data Undefined
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write
ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to
the end of write.
2. tCW is measured from the /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.
6. In case page address is over 3ns, write to the invalid address can occur.
9
Revision 0.1
Jun. 2006
FMP1617CA0(7)
CMOS LPRAM
PACKAGE DIMENSION
Unit : millimeters
48 BALL FINE PITCH BGA(0.75mm ball pitch)
Top View
Bottom View
B
A1 INDEX MARK
B1
B
0.05
0.05
6
5
4
3
2
1
A
B
C
#A1
C
C
C1
D
C1/2
E
F
G
H
B/2
0.25/Typ.
E2
D
A
Y
0.85/Typ.
E
Detail A
E1
0.30
Side View
C
-
Min
Typ
A
-
0.75
Max
-
B
5.90
6.00
6.10
B1
-
3.75
-
C
7.90
8.00
8.10
C1
-
5.25
-
D
0.30
0.35
0.40
1.20
E
-
1.10
E1
-
0.85
-
E2
0.20
0.25
0.30
Y
-
-
0.08
10
NOTES.
1. Bump counts : 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerance are +/-0.050 unless
otherwise specified.
4. Typ : Typical
5. Y is coplanarity : 0.08(Max)
Revision 0.1
Jun. 2006
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