LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 LP5550 PowerWise™ Technology Compliant Energy Management Unit Check for Samples: LP5550 FEATURES DESCRIPTION • The LP5550 is a PWI 1.0 compliant Energy Management System for reducing power consumption of stand-alone mobile phone processors such as base-band or applications processors. 1 2 • • • • • • • Supports High-Efficiency PowerWise Technology Adaptive Voltage Scaling PWI Open Standard Interface for System Power Management Digitally Controlled Intelligent Voltage Scaling 1 MHz PWM Switching Frequency Auto or PWI Controlled PFM Mode Transition Internal Soft Start/Startup Sequencing 3 Programmable LDOs for I/O, PLL, and Memory Retention Supply Generation Power OK Output APPLICATIONS • • • • • GSM/GPRS/EDGE & UMTS Cellular Handsets Hand-Held Radios PDAs Battery Powered Devices Portable Instruments The LP5550 contains an advanced, digitally controlled switching regulator for supplying variable voltage to processor core and memory. The device also incorporates 3 programmable LDO-regulators for powering I/O, PLLs and maintaining memory retention in shutdown-mode. The device is controlled via the PWI open-standard interface. The LP5550 operates cooperatively with PowerWise technology compatible processors to optimize supply voltages adaptively over process and temperature variations or dynamically using frequency/voltage pre-characterized look-up tables. System Diagram VBAT LP5550 SoC + LDO3 ENABLE Embedded Memory Processor Core AVS/DVS domain SW SW RESETN VO3 FB AVS SCLK Slave Power Controller (SPC) Hardware Performance Monitor (HPM) SPWI PWROK PWI Advanced Power Controller (APC) VO1 LDO1 PLL VO2 I/O Bus LDO2 Figure 1. System Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com VO3 PWROK VFB DGND VO3 DGND VFB ABC VO1 VO1 AGND ENABLE SCLK VO2 Top View SPWI VBAT1 VO2 RESETN VBAT1 RESETN ENABLE SPWI VBAT2 PWROK ABC AGND SCLK SWGND SW VBATSW VBATSW SW SWGND VBAT2 Connection Diagrams Bottom View Figure 2. 16-Pin WQFN Package See Package Number RGH0016A Typical Application 1 4.7 PF SPWI RESETN VO2 VBAT1 SCLK 16 ENABLE VBATT VO1 AGND 2.2 PF LP5550SQ DGND VFB PWROK VBATSW VO3 SW SWGND VBAT2 1 PF VBATT VBATT 3.0V - 5.5V + - 10 PF 0.1 PF 10 PH 10 PF Figure 3. Typical Application Circuit Pin Descriptions Pin No. 2 Name I/O Type Description 1 SCLK I D PowerWise Interface (PWI) clock input 2 SPWI I/O D PowerWise Interface (PWI) bi-directional data 3 RESETN I D Reset, active low 4 VO2 O A LDO2 output, for supplying the I/O voltage on the SoC 5 VBAT1 P P Battery supply voltage 6 VO1 O A LDO1 output, for supplying a fixed voltage to a PLL etc. on the SoC 7 DGND G G Digital ground 8 PWROK O D Power OK, active high output signal Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 Pin Descriptions (continued) Pin No. I/O Type 9 VBATSW Name P P Battery supply voltage for switching regulator Description 10 SW O A Switcher pin connected to coil 11 SWGND G G Switcher ground 12 VBAT2 P P Battery supply voltage 13 VO3 O A LDO3 output, on-chip memory supply voltage 14 VFB I A Switcher output voltage for supplying SoC core logic 15 AGND G G Analog Ground 16 ENABLE I D Enable, active high A: Analog Pin D: Digital Pin I: Input Pin O: Output Pin I/O: Input/Output Pin P: Power Pin G: Ground Pin These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) (4) VBAT1, VBAT2, VBATSW -0.3 to +6.0V VO1, VO2, VO3 to GND -0.3 to +VBAT1+0.3V ENABLE, RESETN, VFB, SW, SPWI, SCLK, PWROK -0.3 to VBAT2+0.3V DGND, AGND, SWGND to GND SLUG ±0.3V Junction Temperature (TJ-MAX) 150°C Storage Temperature Range -65°C to 150°C Maximum Continuous Power Dissipation (PD-MAX) (5) 1.0 W Maximum Lead Temperature (Soldering) See (5) ESD Rating (1) (2) (3) (4) (5) (6) (6) Human Body Model All pins 2.0kV Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pin. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. For detailed soldering specifications and information, please refer to Application Note AN-1187 : Leadless Leadframe Package (LLP) (SNOA401). The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula P = (TJ – TA)/θJA, (1) where TJ is the junction temperature, TA is the ambient temperature, and JA is the junction-toambient thermal resistance. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=150°C (typ.) and disengages at TJ=140°C (typ.). The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 3 LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com Operating Ratings (1) (2) VBAT1, VBAT2, VBATSW 3.0V to 5.5V −40°C to +125°C Junction Temperature (TJ) Range Ambient Temperature (TA) Range (3) (1) −40°C to +85°C Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pin. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAXOP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). (2) (3) Thermal Properties (4) Junction-to-Ambient Thermal Resistance (θJA) (4) 39.8°C/W Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102mm x 76mm x 1.6mm with a 2x1 array of thermal vias. The ground plane on the board is 50mm x 50mm. Thickness of copper layers are 36µm/18µm/18µm/36µm (1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W.Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.The value of θJA of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note AN-1187: Leadless Leadframe Package (LLP) (SNOA401) and the Power Efficiency and Power Dissipation section of this datasheet. General Electrical Characteristics Unless otherwise noted, VBAT1,2,SW, RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C (1) (2) (3) Symbol IQ TSD (1) (2) Typ Max Unit Shutdown Supply current Parameter VBAT1,2,SW = 2.0V, all circuits off. Conditions Min 1 6 µA Sleep State Supply Current VBAT1,2,SW = 3.6V, LDO3 (VO3) on, PWI on. All other circuits off. 70 85 µA Acitve State Supply Current (No load, PFM mode) VBAT1,2,SW = 3.6V, LDOs 1 and 2 on, Switcher on, PWI on. 140 165 µA Thermal Shutdown Threshold 160 Thermal Shutdown Hysteresis 10 °C All voltages are with respect to the potential at the GND pin. Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics (3) LDO1 (PLL/Fixed Voltage) Characteristics Unless otherwise noted, VBAT1,2,SW, RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C (1) (2) (3) Symbol Min Typ Max Unit Output Voltage Accuracy 1mA ≤ IOUT ≤ 100mA, VOUT = 1.2V, 3.0V ≤ VBAT1,2,SW ≤ 5.5V -3% 1.2 3% V VOUT Range Programmable Output Voltage Range 0µA ≤ IOUT ≤ 100mA, Programming Resolution = 100mV 0.7 1.2 2.2 V IOUT Recommended Output Current 3.0V ≤ VBAT1,2,SW ≤ 5.5V Short Circuit Current Limit VOUT = 0V Quiescent Current IOUT = 0mA (4) VOUT Accuracy IQ (1) (2) (3) (4) 4 Parameter Conditions 100 350 35 45 mA µA All voltages are with respect to the potential at the GND pin. Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics Quiescent current for LDO1, LDO2, and LDO3 do not include shared functional blocks such as the bandgap reference. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 LDO1 (PLL/Fixed Voltage) Characteristics (continued) Unless otherwise noted, VBAT1,2,SW, RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C(1)(2)(3) Symbol ΔVOUT Parameter Conditions Max Unit 0.125 %/V 0.0085 %/mA -0.125 Load Regulation VIN = 3.6V, 1mA ≤ IOUT ≤ 100mA -0.0085 Line Transient Regulation 3.6V ≤ VIN ≤ 3.9V, TRISE,FALL = 10 µs 27 mV Load Transient Regulation VIN = 3.6V, 10mA ≤ IOUT ≤ 90 mA, TRISE,FALL = 100 ns 86 mV 0.103 mVRMS 56 dB Output Noise Voltage 10Hz ≤ f ≤ 100kHz, COUT = 2.2µF Power Supply Ripple Rejection Ratio f = 1kHz, COUT = 2.2µF COUT Output Capacitance Output Capacitor ESR 0µA ≤ IOUT ≤ 100mA Start-Up Time from Shut-down COUT = 1µF, IOUT = 100mA tSTART-UP Typ Line Regulation PSRR eN Min 3.0V ≤ VBAT1,2,SW ≤ 5.5V, IOUT = 50mA f = 10kHz, COUT = 2.2µF 36 1 2.2 5 dB 20 µF 500 mΩ 54 µs LDO2 (I/O Voltage) Characteristics Unless otherwise noted, VBAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C (1) (2) (3) Symbol Min Typ Max Unit Output Voltage Accuracy 1mA ≤ IOUT ≤ 250mA, VOUT = 2.5V, VOUT +0.4V ≤ VBAT1,2,SW ≤ 5.5V -3% 2.5 3% V VOUT Range Programmable Output Voltage Range 0µA ≤ IOUT ≤ 250mA, 1.5-2.3V =100mV step, 2.5V, 2.8V, 3.0V and 3.3V 1.5 3.3 3.3 V IOUT Recommended Output Current VOUT +0.4V ≤ VBAT1,2,SW ≤ 5.5V Output Current Limit VOUT = 0V Dropout Voltage (4) IOUT = 125mA 70 260 mV Quiescent Current IOUT = 0mA (5) 55 60 µA Line Regulation VOUT +0.4V ≤ VBAT1,2,SW ≤ 5.5V, IOUT = 125mA -0.125 0.125 %/V Load Regulation VIN = 3.6V, 1mA ≤ IOUT ≤ 250mA -0.011 0.011 %/mA Line Transient Regulation 3.6V ≤ VIN ≤ 3.9V, TRISE,FALL = 10 us 24 mV Load Transient Regulation VIN = 3.6V, 25mA ≤ IOUT ≤ 225 mA, TRISE,FALL = 100 ns 246 mV Output Noise Voltage 10Hz ≤ f ≤ 100kHz, COUT = 4.7µF 0.120 mVRMS Power Supply Ripple Rejection Ratio f = 1kHz, COUT = 4.7µF 46 dB f = 10kHz, COUT = 4.7µF 34 VOUT Accuracy IQ ΔVOUT eN PSRR COUT Parameter Output Capacitance Output Capacitor ESR tSTART-UP (1) (2) (3) (4) (5) Start-Up Time from Shut-down Conditions 0µA ≤ IOUT ≤ 250mA COUT = 4.7µF, IOUT = 250mA 250 mA 740 2 4.7 5 20 µF 500 mΩ 144 µs All voltages are with respect to the potential at the GND pin. Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 3.0V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V Quiescent current for LDO1, LDO2, and LDO3 do not include shared functional blocks such as the bandgap reference. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 5 LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com LDO3 (Memory Retention Voltage) Characteristics Unless otherwise noted, VBAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C (1) (2) (3) Symbol Parameter VOUT Accuracy Output Voltage Accuracy Min Typ Max Unit Active state: Tracking VAVS IOUT ≤ 50mA,VOUT = 1.2V, 3.0V ≤ VBAT1,2,SW ≤ 5.5V Conditions -3% 1.2 3% V Sleep state: Memory retention voltage regulation IOUT ≤ 5mA,VOUT = 1.2V, 3.0V ≤ VBAT1,2,SW ≤ 5.5V -3% 1.2 3% V VOFFSET Active State Buffer offset (= VO3-VFB) IOUT = 50 mA, VOUT = 0.6 V 13 mV IOUT = 50 mA, VOUT = 1.2V 28 mV VOUT Range Programmable Output Voltage Range (Sleep state) 0µA ≤ IOUT ≤ 5mA, Programming Resolution = 50mV 1.2 1.35 V Active mode, IOUT = 10µA (4) 33 44 µA Sleep mode, IOUT = 10µA (4) 10 16 µA Recommended Output Current, Active state 3.0V ≤ VBAT1,2,SW ≤ 5.5V 50 Recommended Output Current, Sleep state 3.0V ≤ VBAT1,2,SW ≤ 5.5V 5 Short Circuit Current Limit, Active state VOUT = 0V eN Output Voltage Noise 10Hz ≤ f ≤ 100kHz, COUT = 1µF PSRR Power Supply Ripple Rejection Ratio f = 217Hz, COUT = 1.0µF COUT Output Capacitance IQ Quiescent Current IOUT Output Capacitor ESR (1) (2) (3) (4) 0.6 mA 230 0µA ≤ IOUT ≤ 5mA 0.7 0.158 mVRMS 36 dB 1 5 2.2 µF 500 mΩ All voltages are with respect to the potential at the GND pin. Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics Quiescent current for LDO1, LDO2, and LDO3 do not include shared functional blocks such as the bandgap reference. Switcher (Core Voltage) Characteristics Unless otherwise noted, VBAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C (1) (2) (3) Symbol Parameter VOUT Accuracy Conditions IOUT = 150 mA, VOUT = 1.2V, 3.0V < VBAT1,2,SW <5.5V Min Typ Max Unit -3% 3% IOUT = 100-300 mA, VOUT = 1.2V, 3.0V < VBAT1,2,SW <5.5V -1.5% 1.5% Programmable Output Voltage Range 0mA ≤ IOUT ≤ 300mA, Programming Resolution = 4.7mV 0.6 Line regulation 3.0V < VBAT1,2,SW <5.5V, VOUT = 1.2V, IOUT = 10 mA Load regulation VBAT1,2,SW = 3.6V , VOUT = 1.2V, IOUT = 100-300mA IQ Quiescent current consumption IOUT = 0mA 15 30 µA RDSON(P) P-FET resistance VBAT1,2,SW = VGS = 3.6V 360 690 mΩ Output Voltage VOUT Range ΔVOUT (1) (2) (3) 6 V 1.2 1.2 V 0.18 %/V 0.0019 %/mA All voltages are with respect to the potential at the GND pin. Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 Switcher (Core Voltage) Characteristics (continued) Unless otherwise noted, VBAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C(1)(2)(3) Symbol Parameter Conditions RDSON(N) N-FET resistance VBAT1,2,SW = VGS = 3.6V ILIM Switch peak current limit 3.0V < VBAT1,2,SW <5.5V, Open Loop fOSC Internal oscillator frequency PWM-mode COUT Output Capacitance Output Capacitor ESR L Inductor inductance RVFB VFB pin resistance to ground Min Typ Max Unit 250 660 mΩ 350 620 750 mA 800 1000 1360 kHz 5 10 22 µF 500 mΩ 0mA ≤ IOUT ≤ 300mA 5 0uA ≤ IOUT ≤ 300mA 4.7 / 10 120 µH 650 kΩ Logic and Control Inputs Unless otherwise noted, VBAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C (1) (2) (3) Symbol Parameter Conditions Min Typ Max Unit 0.2 V VIL Input Low Level ENABLE, RESETN, SPWI, SCLK 3.0V ≤ VBAT1 ≤ 5.5V VIH Input High Level ENABLE, RESETN 3.0V ≤ VBAT1 ≤ 5.5V VIH_PWI Input High Level, PWI SPWI, SCLK, 1.5V ≤VO2 ≤ 3.3V IIL Logic Input Current ENABLE, RESETN, 0V ≤ VBAT1 ≤ 5.5V -5 5 µA IIL_PWI Logic Input Current, PWI SPWI, SCLK, 1.5V ≤ VO2 ≤ 3.3V -5 15 µA RPD_PWI Pull-down resistance for PWI signals 2.25 MΩ TEN_LOW Minimum low pulse width to enter STARTUP state (1) (2) 2 V VO2-0.2V 0.5 V 1 ENABLE pulsed high - low - high from SHUTDOWN state 100 ENABLE pulsed high - low - high from SLEEP or ACTIVE state 4 µsec All voltages are with respect to the potential at the GND pin. Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics (3) Logic and Control Outputs Unless otherwise noted, VBAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C (1) (2) (3) Symbol Parameter Conditions VOL Output low level PWROK, SPWI, ISINK ≤ 1 mA VOH Output high level PWROK, ISOURCE ≤ 1 mA VOH_PWI Output high level, PWI SPWI, ISOURCE ≤ 1 mA (1) (2) (3) Min Typ Max Unit 0.4 V VBAT1-0.4V V VO2-0.4V V All voltages are with respect to the potential at the GND pin. Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control. Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 7 LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com Simplified Functional Diagram VBATSW FB LP5550 Input Voltage Feed Forward SW + PWM Driver 10 PH FB 10 PF + PWM REF PWI Control VBAT1 VO1/2 VBAT2 2.2 PF, VO1 4.7 PF, VO2 PWI Control + VREF x 2 LDOs VO3 1 PF PWI Control SCLK SPWI + - EN SPC PWI Control 2 1: Active 2: Sleep 1 RESET + 6 50 mV PWROK VREF + FB + - AGND DGND PGND PGND Figure 4. Simplified Functional Diagram 8 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 Typical Performance Characteristics Unless otherwise stated: VIN=3.6V IQ vs. VIN Sleep, no load on LDO3 93.0 9.0 86.6 7.6 80.2 6.2 TA = -40oC Iq (PA) TA = 85oC Iq (PA) IQ vs. VIN Shutdown 73.8 4.8 67.4 TA = 85oC 3.4 TA = 25oC TA = 25oC o TA = -40 C 61.0 3.0 3.5 4.0 4.5 5.0 2.0 3.0 5.5 3.5 4.0 4.5 5.0 VIN (V) VIN (V) Figure 5. Figure 6. Start-up Sequence VO1, VO2, VOSW Start-up Sequence VOSW, VO3 5V/DIV EN and RESETN 5.5 5V/DIV EN and RESETN 1V/DIV 500 mV/DIV 500 mV/DIV 500 mV/DIV VO2 VO1 500 mV/DIV 0V VO3 0V 0V VOSW VOSW 0V 100 Ps/DIV 100 Ps/DIV Figure 7. Figure 8. Start-up Sequence Inrush Current Line Transient Response VOSW, VO3 5V/DIV EN and RESETN VIN LDO2 5V 3.6V LDO1 SW and LDO3 VOSW AC Coupled, 50 mV/DIV VO3 AC Coupled, 2 mV/DIV 200 mA/DIV IIN 50 Ps/DIV 100 Ps/DIV Figure 9. Figure 10. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 9 LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise stated: VIN=3.6V Line Transient Response VO1, VO2 Load Transient Response VO2 5V VIN 3.6V VO1 AC Coupled, 2 mV/DIV VO2 AC Coupled, 2 mV/DIV IOUT 100 mA/DIV VO2 100 mV/DIV AC Coupled, 100 Ps/DIV 50 Ps/DIV Figure 11. Figure 12. Load Transient Resoponse VO1 LDO1 PSRR 0 -10 IOUT 50 mA/DIV AC Coupled, VO1 MAGNITUDE (dB) -20 100 mA -30 -40 -50 No Load -60 50 mV/DIV -70 -80 2 10 100 Ps/DIV 10 3 10 4 5 10 10 6 FREQUENCY (Hz) Figure 13. Figure 14. LDO3 PSRR 0 -10 -10 -20 -20 -30 MAGNITUDE (dB) MAGNITUDE (dB) LDO2 PSRR 0 200 mA -40 No Load -50 -40 -60 -70 -70 10 2 10 3 10 4 5 10 10 6 FREQUENCY (Hz) No Load -50 -60 -80 -80 10 2 10 3 10 4 5 10 10 6 FREQUENCY (Hz) Figure 15. 10 -30 Figure 16. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise stated: VIN=3.6V CURRENT LOAD STEP (0 mA - 280 mA) T = A 85°C 1.07 M = TA 25°C 1.05 M 1.02 M 996.00 k CURRENT LOAD STEP (100 mA - 300 mA) 970.00 k3. 0 TA 3. 5 4. 0 =40°C 4. 5 VIN (V) 5. 0 5. 5 VOUT (50 mV/Div) ILOAD = 280 mA ILOAD = 0 mA TIME (100 Ps/DIV) Figure 17. Figure 18. Load Trainsient Response Switcher, PWM only Load Transient Response Switcher, PFM only CURRENT LOAD STEP (0 mA - 70 mA) SWITCHING FREQUENCY (Hz) 1.10 M Load Transient Response Switcher, Automatic PWM/PFM Transition Switching Frequency vs. VIN VOUT (50 mV/Div) Inductor Current = 200 mA/ Div ILOAD = 300 mA ILOAD = 100 mA VOUT (50 mV/Div) Inductor Current = 200 mA/Div ILOAD = 70 mA ILOAD = 0 mA TIME (100 Ps/DIV) TIME (100 Ps/DIV) Figure 19. Figure 20. VOUT Transient Response Min to Max Transient VOUT Transient Response Max to Min Transient 200 mV/DIV 200 mV/DIV VO3 VOSW 200 mV/DIV 200 mV/DIV VO3 VOSW SCLK 2V/DIV SCLK 20 Ps/DIV 2V/DIV 20 Ps/DIV Figure 21. Figure 22. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 11 LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise stated: VIN=3.6V 570.0 Switch Current Limit vs. VIN Efficiency vs. Load (Switcher) 95.0 TA = 85°C VIN = 3V TA = 25°C 90.0 EFFICIENCY (%) ICL (mA) 554.0 538.0 522.0 TA = -40°C 85.0 VIN = 3.6V 80.0 VIN = 4.2V 506.0 490.0 3.0 75.0 3.5 4.0 4.5 5.0 VIN = 5.5V 70.0 1.0e1 5.5 1.0e2 VIN (V) Figure 23. Figure 24. Switching Waveforms PWM Switching Waveforms PFM VSWITCH (5V/Div) VSWITCH (5V/Div) PFM MODE PWM MODE ILOAD = 150 mA VOUT (20 mV/Div) Inductor Current (200 mA/Div) TIME (1 Ps/DIV) VOUT (20 mV/Div) Inductor Current (100 mA/Div) TIME (2 Ps/DIV) Figure 25. 12 1.0e3 IOUT (mA) Figure 26. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 LP5550 PWI Register Map The PWI standard supports sixteen 8-bit registers on the PWI slave. The table below summarizes these registers and shows default register bit values after reset. The following sub-sections provide additional detail on the use of each individual register. Table 1. Summary Register Address Register Name 0x0 R0 Core voltage 0x1 R1 Unused 0x2 R2 0x3 Register Usage Type Reset Default Value 7 6 5 4 3 2 1 0 R/W 0 1 1 1 1 1 1 1 R/W - - - - - - - - Memory retention voltage R/W 0 1 1 0 0 - - - R3 Status register R/O 0 0 0 0 1 1 1 1 0x4 R4 PWI version number R/O 0 0 0 0 0 0 0 1 0x5 R5 Unused R/W - - - - - - - - 0x6 R6 Unused R/W - - - - - - - - 0x7 R7 LDO2 voltage R/W 0 1 1 1 1 - - - 0x8 R8 LDO1 voltage R/W 0 0 1 0 1 - - - 0x9 R9 PFM/PWM force R/W 0 0 - - - - - - 0xA R10 Unused R/W - - - - - - - - 0xB R11 Unused R/W - - - - - - - - 0xC R12 Unused R/W - - - - - - - - 0xD R13 Unused R/W - - - - - - - - 0xE R14 Unused R/W - - - - - - - - 0xF R15 Reserved R/W - - - - - - - - R0 - Core Voltage Register Address 0x0 Type R/W Reset Default 8h’7F Bit Field Name Description or Comment 7 Sign This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. 6:0 Voltage Core voltage value. Default value is in bold. Voltage Data Code [7:0] Voltage Value (V) 7h’00 0.6 7h’xx Linear scaling 7h’7f 1.2 (default) R1 - Unused Register Address 0x1 Type R/W Reset Default 8h’00 Bit 7:0 Field Name Unused Description or Comment Write transactions to this register are ignored. Read transactions will return a “No Response Frame.” A no response frame contains all zeros (see PWI 1.0 specification). Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 13 LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com R2 - VO3 Voltage Register (Memory Retention Voltage) Address 0x2 Type R/W Reset Default 8h’60 Bit Field Name Description or Comment 7 Sign This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. 6:3 Voltage Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. 2:0 Unused Voltage Data Code [6:3] Voltage Value (volts) 4h’0 0.6 4h’1 0.65 4h’2 0.7 4h’3 0.75 4h’4 0.8 4h’5 0.85 4h’6 0.9 4h’7 0.95 4h’8 1 4h’9 1.05 4h’A 1.1 4h’B 1.15 4h’C 1.20 (default) 4h’D 1.25 4h’E 1.3 4h’F 1.35 These bits are fixed to ‘0’. Reading these bits will result in a ‘000’. Any data written into these bits using the Register Write command is ignored. R3 - Status Register Address 0x3 Type Read Only Reset Default 8h’0F Bit Field Name Description or Comment 7 Reserved Reserved, read returns 0 6 Reserved Reserved, read returns 0 5 User Bit Unused, read returns 0 4 User Bit Unused, read returns 0 3 Fixed OK Unused, read returns 1 2 IO OK Unused, read returns 1 1 Memory OK Unused, read returns 1 0 Core OK Unused, read returns 1 14 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 R4 - PWI Version Number Register Address 0x4 Type Read Only Reset Default 8h’01 Bit 7:0 Field Name Version Description or Comment Read transaction will return 8h’01 indicating PWI 1.0 specification. Write transactions to this register are ignored. R5 - R6 - Unused Registers Address 0x5, 0x6 Type R/W Reset Default 8h’00 Bit 7:00 Field Name Unused Description or Comment Write transactions to this register are ignored. Read transactions will return a “No Response Frame.” A no response frame contains all zeros (see PWI 1.0 specification). R7 - VO2 Voltage Register (I/O Voltage) Address 0x7 Type R/W Reset Default 8h’78 Bit Field Name Description or Comment 7 Sign This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. 6:3 Voltage Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. 2:0 Unused Voltage Data Code [6:3] Voltage Value (volts) 4h’0 1.5 4h’1 1.5 4h’2 1.5 4h’3 1.5 4h’4 1.6 4h’5 1.7 4h’6 1.8 4h’7 1.9 4h’8 2 4h’9 2.1 4h’A 2.2 4h’B 2.3 4h’C 2.5 4h’D 2.8 4h’E 3 4h’F 3.3 (default) These bits are fixed to ‘0’. Reading these bits will result in a ‘000’. Any data written into these bits using the Register Write command is ignored. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 15 LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com R8 - VO1 Voltage Register (PLL/Fixed Voltage) Address 0x8 Type R/W Reset Default 8h’28 Bit Field Name Description or Comment 7 Sign This bit is fixed to ‘0’. Reading this bit will result in a ’0’. Any data written into this bit position using the Register Write command is ignored. 6:3 Voltage Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. 2:0 Unused Voltage Data Code [6:3] Voltage Value (volts) 4h’0 0.7 4h’1 0.8 4h’2 0.9 4h’3 1 4h’4 1.1 4h’5 1.2 (default) 4h’6 1.3 4h’7 1.4 4h’8 1.5 4h’9 1.6 4h’A 1.7 4h’B 1.8 4h’C 1.9 4h’D 2 4h’E 2.1 4h’F 2.2 These bits are fixed to ‘0’. Reading these bits will result in a 3b’000. Any data written into these bits using the Register Write command is ignored. R9 - PFM/PWM Force Register Address 0x9 Type R/W Reset Default 8h’00 Bit 7:6 5:0 16 Field Name Description or Comment PFM/PWM Force Unused User Register PFM Force (bit 7) PWM Force (bit 6) Automatic Transition 0 0 Automatic Transition 1 1 Forced PFM Mode 1 0 Forced PWM Mode 0 1 These bits are fixed to ‘0’. Reading these bits will result in a ‘000000’. Any data written into these bits using the Register Write command is ignored. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 R10 - R14 – Unused Registers Address 0xA, 0xB, 0xC, 0xD, 0xE Type R/W Reset Default 8h’00 Bit 7:0 Field Name Unused Description or Comment Write transactions to this register are ignored. Read transactions will return a “No Response Frame.” A no response frame contains all zeros (see PWI 1.0 specification) frame. R15 - Manufacturer Register Adress 0xF Type R/W Reset Default 8h'00 Bit 7:0 Field Name Reserved Description or Comment Do not write to this register Operation Description DEVICE INFORMATION The LP5550 is a PowerWise Interface (PWI) compliant power management unit (PMU) for application or baseband processors in mobile phones or other portable equipment. It operates cooperatively with processors using Texas Instruments' Advanced Power Controller (APC) to provide Adaptive or Dynamic Voltage Scaling (AVS, DVS) which drastically improves processor efficiencies compared to conventional power delivery methods. The LP5550 consists of a high efficiency switching DC/DC buck converter to supply the AVS or DVS voltage domain, three LDOs for supplying the logic, PLL, and memory, and PWI registers and logic. OPERATION STATE DIAGRAM The LP5550 has four operating states: Start-up, Active, Sleep and Standby. The Start-up state is the default state after reset. All regulators are off and PWROK output is ‘0’. The device will power up when the external enable-input is pulled high. After the power-up sequence LP5550 enters the Active state. In the Active state all regulators are on and PWROK-output is ‘1’. Immediately after Start-up the output voltages are at their default levels. LP5550 can be turned off by supplying the Shutdown command over PWI, or by setting ENABLE and/or RESETN to '0'. The LP5550 can be switched to the Sleep state by issuing the Sleep command. In the Sleep state the core voltage regulator is off, but the PWROK output is still ‘1’. The memory voltage regulator (VO3) provides the programmed memory retention voltage. LDO1 and LDO2 are on. The LP5550 can be activated from the Sleep state by giving the Wake-up command. This resumes the last programmed Active state configuration. The device can also be switched off by giving the Shutdown command, or by setting ENABLE and/or RESETN to ‘0’ In the Shutdown-state all output voltages are ‘0’, and PWROK-signal is ‘0’ as well. The LP5550 can exit the Shutdown-state if either ENABLE or RESETN is ‘0’. In either case the device moves to the Start-up state. See the ENABLE Figure 27 shows the LP5550 state diagram. The figure assumes that supply voltage to the regulator IC is in the valid range. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 17 LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com RESET (Command or External) From any state ENABLE = µ0¶ SHUTDOWN All regulators disabled Power OK = ¶0¶ ENABLE = µ0¶ Shutdown command STARTUP All regulators disabled Power OK = '0' ENABLE = µ0¶ Shutdown command Wakeup command ENABLE = µ1¶ SLEEP AVS regulator disabled memory supply at retention level enabled regulators on Power OK = '1' ACTIVE Enabled regulators on Power OK = '1' Sleep command Figure 27. LP5550 State Diagram VOLTAGE SCALING The LP5550 is designed to be used in a voltage scaling system to lower the power dissipation of baseband or application processors in mobile phones or other portable equipment. By scaling supply voltage with the clock frequency of a processor, dramatic power savings can be achieved. Two types of voltage scaling are supported, dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS). DVS systems switch between precharacterized voltages which are paired to clock frequencies used for frequency scaling in the processor. AVS systems track the processor performance and optimize the supply voltage to the required performance. AVS is a closed loop system that provides process and temperature compensation such that for any given processor, temperature, or clock frequency, the minimum supply voltage is delivered. DIGITALLY CONTROLLED VOLTAGE SCALING The LP5550 delivers fast, controlled voltage scaling transients with the help of a digital state machine. The state machine automatically optimizes the control loop in the LP5550 switching regulator to provide large signal transients with minimal over- and undershoot. This is an important characteristic for voltage scaling systems that rely on minimal over- and undershoot to set voltages as low as possible and save energy. LARGE SIGNAL TRANSIENT RESPONSE The switching converter in the LP5550 is designed to work in a voltage scaling system. This requires that the converter has a well controlled large signal transient response. Specifically, the under- and over-shoots have to be minimal or zero while maintaining settling times less than 100 usec. Typical response plots are shown in the Typical Performance Characteristics section. 18 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 PowerWise (TM) INTERFACE To support DVS and AVS, the LP5550 is programmable via the low power, 2 wire PowerWise Interface (PWI). This serial interface controls the various voltages and states of all the regulators in the LP5550. In particular, the switching regulator voltage can be controlled between 0.6V and 1.2V in 128 steps (linear scaling). This high resolution voltage control affords accurate temperature and process compensation in AVS. The LDO voltages can also be set, however they are not intended to be dynamic in operation. The LP5550 supports the full command set as described in PWI 1.0 specification: • Core Voltage Adjust • Reset • Sleep • Shutdown • Wakeup • Register Read • Register Write • Authenticate • Synchronize PWM/PFM OPERATION The switching converter in the LP5550 has two modes of operation: pulse width modulation (PWM) and pulse frequency modulation (PFM). In PWM the converter switches at 1MHz. Each period can be split into two cycles. During the first cycle, the high-side switch is on and the low-side switch is off, therefore the inductor current is rising. In the second cycle, the high-side switch is off and the low-side switch is on causing the inductor current to decrease. The output ripple voltage is lowest in PWM mode Figure 28. As the load current decreases, the converter efficiency becoms worse due to the increased percentage of overhead current needed to operate in PWM mode. The LP5550 can operate in PFM mode to increase efficiency at low loads. By default, the part will automatically transition into PFM mode when either of two conditions occurs for a duration of 64 or more clock cycles: A. The inductor valley current goes below 0 A B. The peak PMOS switch current drops below the IMODE level: VIN (typ) IMODE < 26 mA + 50: (1) During PFM operation, the converter positions the output voltage between two voltage limits, 'High PFM Threshold' and 'Low PFM Threshold' as shown in Figure 28. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between these two levels. If the output voltage is below the ‘low’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The peak current in PFM mode is: VIN (typ) IPFM = 117 mA + 64: (2) If IPFM is tripped, the PMOS switch conducts again once the inductor current reaches zero (the NMOS switch conducts while the PMOS switch is off). If the 'high' PFM threshold is tripped, the PMOS remains off until the 'low' PFM threshold is tripped. The NMOS turns off once the inductor current reaches zero. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 19 LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com Z A x i s PFM Mode at Light Load PWM Mode at Moderate to Heavy Loads High PFM Threshold Load current increases ZAxis Low PFM Threshold High PFM Voltage Threshold reached, go into sleep mode Current load increases, draws Vout towards PFM/PWM Threshold Low PFM Threshold, turn on PFET PFM/PWM Threshold is Nfet on drains conductor current until I inductor=0 x Z-A Pfet on until Ipfm limit reached Figure 28. Operation in PFM Mode and Transfer to PWM Mode APPLICATION INFORMATION PWM/PFM FORCE REGISTER (R9) By default, the LP5550 automatically transitions between PFM and PWM to optimize efficiency. The PWM/PFM force register (R9) provides the option to override the automatic transition and force PFM or PWM operation (see R9 - PFM/PWM Force Register). Note that if the operating mode of the regulator is forced to be PFM then the switch current limit is reduced to 100 mA (50 mA average load current). EN/RESETN The LP5550 can be shutdown via the ENABLE or RESETN pins, or by issuing a shutdown command from PWI. To disable the LP5550 via hardware (as opposed to the PWI shutdown command), pull the ENABLE and/or the RESETN pin(s) low. To enable the LP5550, both the ENABLE and the RESETN pins must be high. Once enabled, the LP5550 engages the power-up sequence and all voltages return to their default values. When using PWI to issue a shutdown command, the PWI will be disabled along with the regulators in the LP5550. To re-enable the part, either the ENABLE, RESETN, or both pins must be toggled (high – low – high). The part will then enter the power-up sequence and all voltages will return to their default values. Figure 29 summarizes the ENABLE/RESETN control. The ENABLE and RESETN pins provide flexibility for system control. In larger systems such as a mobile phone, it can be advantageous to enable/disable a subsystem independently. For example, the LP5550 may be powering the applications processor in a mobile phone. The system controller can power down the applications processor via the ENABLE pin, but leave on other subsystems. When the phone is turned off or in a fault condition, the system controller can have a global reset command that is connected to all the subsystems (RESETN for the LP5550). However, if this type of control is not needed, the ENABLE and RESETN pins can be tied together and used as a single enable/disable pin. 20 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 Shutdown Command PWI OFF OFF EN and RESETN Voltages On Off Figure 29. ENABLE and RESETN Operation INDUCTOR A 10uH or 4.7uH inductor should be used with the LP5550. The inductor should be rated to handle the peak load current plus the ripple current: IL(MAX) = ILOAD(MAX) + ' iL(MAX) = ILOAD(MAX) + = ILOAD(MAX) + D x (VIN(MAX) - VOUT) 2 x L x fS D x (VIN(MAX) - VOUT) 20 (A) , fS = 1 MHz, L = 10 PH D x (VIN(MAX) - VOUT) (A) , = ILOAD(MAX) + 9.4 fS = 1 MHz, L = 4.7 PH (3) CURRENT LIMIT The switching converter in the LP5550 detects the peak inductor current and limits it for protection (see Electrical Characteristics table and/or Typical Performance Characteristics section). To determine the average current limit from the peak current limit, the inductor size, input and output voltage, and switching frequency must be known. The LP5550 is designed to work with a 4.7uH or 10uH inductor, so: ICL_AVG = ICL_PK - ' iL = ICL_PK - | 0.4 | 0.4 - D x (VIN - VOUT) 2 x L x fS D x (VIN - VOUT) 20 D x (VIN - VOUT) , fS = 1 MHz, L = 10 PH , fS = 1 MHz, L = 4.7 PH 9.4 (4) INPUT CAPACITOR The input capacitor to the switching converter supplies the AC switching current drawn from the switching action of the internal power FETs. The input current of a buck converter is discontinuous, so the ripple current supplied by the input capacitor is large. The input capacitor must be rated to handle this current: IRMS_CIN = IOUT VOUT x (VIN - VOUT) VIN (A) (5) Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 21 LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com The power dissipated in the input capacitor is given by: PD_CIN = I2RMS_CIN x RESR_CIN (W) (6) The input capacitor must be rated to handle both the RMS current and the dissipated power. A 10 µF ceramic capacitor is recommended for the LP5550. OUTPUT CAPACITOR The switching converter in the LP5550 is designed to be used with a 10uF ceramic output capacitor. The dielectric should be X5R, X7R, or comparable material to maintain proper tolerances. The output capacitor of the switching converter absorbs the AC ripple current from the inductor and provides the initial response to a load transient. The ripple voltage at the output of the converter is the product of the ripple current flowing through the output capacitor and the impedance of the capacitor. The impedance of the capacitor can be dominated by capacitive, resistive, or inductive elements within the capacitor, depending on the frequency of the ripple current. Ceramic capacitors are predominately used in portable systems and have very low ESR and remain capacitive up to high frequencies. The switcher peak - to - peak output voltage ripple in steady state can be calculated as: 1 VPP = ILPP (RESR + ) FS x 8 x COUT (7) LDO INFORMATION The LDOs included in the LP5550 provide static supply voltages for various functions in the processor. Use the following sections to determine loading and external components. LDO LOADING CAPABILITY The LDOs in the LP5550 can regulate to a variety of output voltages, depending on the need of the processor. These voltages can be programmed through the PWI. Table 2 summarizes the parameters of the LP5550 LDOs. Table 2. LDO Parameters PWI Register Recommended Maximum Output Current Output Voltage Range Dropout Voltage (typical) Typical Load LDO1 R8 0.6 V – 2.2 V 100 mA 200 mV PLL LDO2 R7 1.5 V – 3.3 V 250 mA 150 mV I/O LDO3 R2 VOSW + 0.05 V (1) 0.7 V – 1.35 V (2) 50 mA 200 mV Memory/Memory retention (1) (2) LDO3 tracks the switching converter output voltage (VOSW) plus a 50 mV offset when the LP5550 is in active state. LDO3 regulates at the set memory retention voltage when the LP5550 is in shutdown state. LDO OUTPUT CAPACITOR The output capacitor sets a low frequency pole and a high frequency zero in the control loop of an LDO. The capacitance and the equivalent series resistance (ESR) of the capacitor must be within a specified range to meet stability requirements. The LDOs in the LP5550 are designed to be used with ceramic output capacitors. The dielectric should be X5R, X7R, or comparable material to maintain proper tolerances. Use the following table to choose a suitable output capacitor: Table 3. Output Capacitor Selection Guide Output Capacitance Range (Recommended Typical Value) ESR range LDO1 1 µF – 20 µF (2.2 µF) 5 mohm – 500 mohm LDO2 2 µF – 20 µF (4.7 µF) 5 mohm – 500 mohm LDO3 0.7 µF – 2.2 µF (1.0 µF) 5 mohm– 500 mohm 22 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 LP5550 www.ti.com SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 BOARD LAYOUT CONSIDERATIONS Shading represents different layers. (lightest is top layer, darkest is bottom layer) GND (can be a mid layer) VFB VO3 VFB AGND EN GND SCLK VBAT2 GND SPWI SWGND SW RESETN PWROK DGND VBAT1 VBATSW VO1 VO2 GND VBAT1/2/SW GND GND Figure 30. Board Layout Design Recommendations for the LP5550 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 23 LP5550 SNVS378G – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision F (April 2013) to Revision G • 24 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 23 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP5550 PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP5550SQ/NOPB OBSOLETE WQFN RGH 16 TBD Call TI Call TI -40 to 125 LP5550SQX/NOPB OBSOLETE WQFN RGH 16 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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