Cypress CY7C60445-32LQXC Encoreâ ¢ v low voltage microcontroller Datasheet

CY7C60445, CY7C6045x
enCoRe™ V Low Voltage Microcontroller
Features
■
Powerful Harvard Architecture Processor
❐ M8C processor speeds running up to 24 MHz
❐ Low power at high processing speeds
❐ Interrupt controller
❐ 1.71V to 3.6V operating voltage
❐ Temperature range: 0°C to 70°C
■
Flexible On-Chip Memory
❐ Up to 32K Flash program storage
50,000 Erase/write cycles
❐ Up to 2048 bytes SRAM data storage
❐ Flexible protection modes
❐ In-System Serial Programming (ISSP)
■
Complete Development Tools
❐ Free development tool (PSoC Designer™)
❐ Full featured, in-circuit emulator and programmer
❐ Full speed emulation
❐ Complex breakpoint structure
❐ 128K trace memory
■
Precision, Programmable Clocking
❐ Crystal-less oscillator with support for an external crystal or
resonator
❐ Internal ±5.0% 6, 12, or 24 MHz main oscillator
❐ Internal low speed oscillator at 32 kHz for watchdog and
sleep.The frequency range is 19–50 kHz with a 32 kHz typical
value
■
Programmable Pin Configurations
❐ 25 mA sink current on all GPIO
❐ Pull Up, High Z, Open Drain, CMOS drive modes on all GPIO
❐ Configurable inputs on all GPIO
❐ Low dropout voltage regulator for Port 1 pins. Programmable
to output 3.0, 2.5, or 1.8V at the I/O pins
❐ Selectable, regulated digital IO on Port 1
• Configurable input threshold for Port 1
• 3.0V, 20 mA total Port 1 source current
• Hot-swappable
❐ 5 mA strong drive mode on Ports 0 and 1
■
Additional System Resources
❐ Configurable communication speeds
2
❐ I C™ Slave
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Implementation requires no clock stretching
• Implementation during sleep modes with less than 100 mA
• Hardware address detection
❐ SPI™ master and SPI slave
• Configurable between 93.75 kHz and 12 MHz
❐ Three 16-bit timers
❐ 8-bit ADC used to monitor battery voltage or other signals with external components
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
enCoRe V LV Block Diagram
enCoRe V
Low Voltage
CORE
Port 4
Port 3
Port 2
Port 1
Port 0
Prog. LDO
System Bus
SRAM
2048 Bytes
Interrupt
Controller
SROM
Flash 32K
CPU Core
(M8C)
Sleep and
Watchdog
6/12/24 MHz Internal Main Oscillator
3 16-Bit
Timers
POR and LVD
I2C Slave/SPI
Master-Slave
System Resets
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-12395 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 7, 2008
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Functional Overview
The enCoRe V LV family of devices are designed to replace
multiple traditional low voltage microcontroller system components with one, low cost single chip programmable component.
Communication peripherals (I2C/SPI), a fast CPU, Flash
program memory, SRAM data memory, and configurable IO are
included in a range of convenient pinouts.
The architecture for this device family, as illustrated in enCoRe
V LV Block Diagram, is comprised of two main areas: the CPU
core and the system resources. Depending on the enCoRe V LV
package, up to 36 general purpose IO (GPIO) are also included.
Enhancements over the Cypress’ legacy low voltage microcontrollers include faster CPU at lower voltage operation, lower
current consumption, twice the RAM and Flash, hot-swapable
IOs, I2C hardware address recognition, new very low current
sleep mode, and new package options.
The enCoRe V LV Core
The enCoRe V LV Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard
architecture microprocessor.
System Resources provide additional capability, such as a
configurable I2C slave and SPI master-slave communication
interface and various system resets supported by the M8C.
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include low voltage detection and power on
reset. Brief statements describing the merits of each system
resource are presented below.
■
10-bit on-chip ADC shared between System Performance
manager (used to calculate parameters based on temperature
for flash write operations) and the user.
■
The I2C slave and SPI master-slave module provides 50, 100,
or 400 kHz communication over two wires. SPI communication
over 3 or 4 wires runs at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
■
■
In I2C slave mode the hardware address recognition feature
reduces the already low power consumption by eliminating the
need for CPU intervention until a packet addressed to the target
device has been received.
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
Document Number: 001-12395 Rev. *G
■
The 5V maximum input, 1.8, 2.5, or 3V selectable output, low
dropout regulator (LDO) provides regulation for IOs. A register
controlled bypass mode allows the user to disable the LDO.
■
Standard Cypress PSoC IDE tools are available for debugging
the enCoRe V LV family of parts.
Getting Started
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, reference the PSoC
Mixed-Signal Array Technical Reference Manual, which can be
found on http://www.cypress.com/psoc.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest PSoC device data sheets on the
web at http://www.cypress.com.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com/shop/. Under Product Categories click
PSoC® Mixed Signal Arrays to view a current list of available
items.
Technical Training Modules
Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced analog and CapSense. Go to
http://www.cypress.com/techtrain.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Support
located at the top of the web page, and select CYPros
Consultants.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a four hour guaranteed
response at http://www.cypress.com/support.
Application Notes
A long list of application notes assists you in every aspect of your
design effort. To view the PSoC application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Documentation list located at the top of the web page.
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Development Tools
PSoC Designer™ is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows XP and Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
The system-level view is a drag-and-drop visual embedded
system design environment based on PSoC Express. In this
view you solve design problems the same way you might think
about the system. Select input and output devices based upon
system requirements. Add a communication interface and define
the interface to the system (registers). Define when and how an
output device changes state based upon any/all other system
devices. Based upon the design, PSoC Designer automatically
selects one or more PSoC Mixed-Signal Controllers that match
your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.x. You choose a
base device to work with and then select different onboard
analog and digital components called user modules that use the
PSoC blocks. Examples of user modules are ADCs, DACs,
Amplifiers, and Filters. You configure the user modules for your
chosen application and connect them to each other and to the
proper pins. Then you generate your project. This prepopulates
your project with APIs and libraries that you can use to program
your application.
The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 001-12395 Rev. *G
Code Generation Tools
PSoC Designer supports multiple third-party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the IO pins, or connect system-level
inputs, outputs, and communication interfaces to each other with
valuator functions.
In the system-level view selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an
analog-to-digital converter (ADC) to convert the potentiometer’s
output to a digital signal, and a PWM to control the fan.
In the chip-level view, you perform the selection, configuration,
and routing so that you have complete control over the use of all
on-chip resources.
Both the system-level and chip-level views provide a library of
pre-built, pre-tested hardware peripheral components. In the
system-level view these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I2C-bus, for example), and the logic to control how they interact
with one another (called valuators).
Generate, Verify, and Debug
In the chip-level view the components are called “user modules.”
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed-signal
varieties.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high-level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by
selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 001-12395 Rev. *G
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the In-Circuit
Emulator (ICE) where it runs at full speed. PSoC Designer
debugging capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the debug interface provides a large
trace buffer and allows you to define complex breakpoint events
that include monitoring address and data bus values, memory
locations and external signals.
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Document Conventions
Acronyms Used
Units of Measure
The following table lists the acronyms that are used in this
document.
A units of measure table is located in the Electrical Specifications
section. Table 6 on page 13 lists all the abbreviations used to
measure the enCoRe V LV devices.
Acronym
Description
API
application programming interface
CPU
central processing unit
GPIO
general purpose IO
GUI
graphical user interface
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
IO
input/output
LSb
least significant bit
LVD
low voltage detect
MSb
most significant bit
POR
power on reset
PPOR
precision power on reset
PSoC®
Programmable System-on-Chip™
SLIMO
slow IMO
SRAM
static random access memory
Document Number: 001-12395 Rev. *G
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
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Pin Configuration
32-Pin Part Pinout
3
4
5
6
7
8
P0[5]
P0[7]
Vdd
P0[6]
P0[4]
P0[2]
29
28
27
26
25
QFN
P0[0]
P2[6]
22
21
20
P2[4]
P2[2]
P2[0]
P3[2]
P3[0]
XRES
12
13
14
15
16
Vss
P1[0]
P1[4]
P1[6]
P1[2]
11
19
18
17
P1[3]
(Top View)
24
23
P1[1]
P1[5]
P3[1]
P1[7]
1
2
9
10
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
30
P0[3]
Vss
32
31
Figure 1. CY7C60445 32-Pin enCoRe V LV Device
Table 1. 32-Pin Part Pinout (QFN)
Pin No.
Type
Name
Description
1
IOH
P0[1]
Digital IO
2
IO
P2[7]
Digital IO
3
IO
P2[5]
Digital IO, Crystal Out (Xout)
4
IO
P2[3]
Digital IO, Crystal In (Xin)
5
IO
P2[1]
Digital IO
6
IO
P3[3]
Digital IO
7
IO
P3[1]
Digital IO
8
IOHR
P1[7]
Digital IO, I2C SCL, SPI SS
9
IOHR
P1[5]
Digital IO, I2C SDA, SPI MISO
10
IOHR
P1[3]
Digital IO, SPI CLK
Digital IO, ISSP CLK, I2C SCL, SPI MOSI
11
IOHR
P1[1](1, 2)
12
Power
Vss
Ground connection
13
IOHR
P1[0](1, 2)
Digital IO, ISSP DATA, I2C SDA, SPI CLK
14
IOHR
P1[2]
Digital IO
15
IOHR
P1[4]
Digital IO, optional external clock input (EXTCLK)
16
IOHR
P1[6]
Digital IO
17
Reset Input
XRES
Active high external reset with internal pull down
18
IO
P3[0]
Digital IO
19
IO
P3[2]
Digital IO
20
IO
P2[0]
Digital IO
21
IO
P2[2]
Digital IO
Document Number: 001-12395 Rev. *G
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Table 1. 32-Pin Part Pinout (QFN) (continued)
Pin No.
Type
Name
Description
22
IO
P2[4]
Digital IO
23
IO
P2[6]
Digital IO
24
IOH
P0[0]
Digital IO
25
IOH
P0[2]
Digital IO
26
IOH
P0[4]
Digital IO
27
IOH
P0[6]
Digital IO
28
Power
Vdd
Supply voltage
29
IOH
P0[7]
Digital IO
30
IOH
P0[5]
Digital IO
31
IOH
P0[3]
Digital IO
32
Power
Vss
Ground connection
CP
Power
Vss
Center pad must be connected to ground
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
1. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered.
2. These are the in-system serial programming (ISSP) pins, that are not High Z at power on reset (POR)
Document Number: 001-12395 Rev. *G
Page 7 of 28
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48-Pin Part Pinout
P0[0]
37
P0[4]
P0[6]
P0[2]
38
39
Vdd
40
P0[7]
42
41
P0[5]
44
NC
NC
P0[3]
45
43
Vss
46
P0[1]
48
47
Figure 2. CY7C60455/CY7C60456 48-Pin enCoRe V LV Device
NC
1
36
P2[6]
P2[7]
2
35
P2[4]
P2[2]
P2[0]
P2[5]
3
34
P2[3]
4
33
P2[1]
P4[3]
5
P4[1]
7
32
P4[2]
31
P4[0]
30
P3[6]
P3[4]
9
29
28
10
27
P3[1]
11
P3[0]
XRES
P1[7]
12
26
25
17
18
19
20
21
22
23
24
P1[1]
Vss
NC
NC
Vdd
P1[0]
P1[2]
P3[2]
P1[6]
P1[4]
16
15
14
P1[3]
NC
P1[5]
P3[3]
13
P3[5]
(Top View)
8
NC
P3[7]
QFN
6
Table 2. 48-Pin Part Pinout (QFN)
Pin No.
Type
Name
Description
1
NC
NC
No connection
2
IO
P2[7]
Digital IO
3
IO
P2[5]
Digital IO, Crystal Out (Xout)
4
IO
P2[3]
Digital IO, Crystal In (Xin)
5
IO
P2[1]
Digital IO
6
IO
P4[3]
Digital IO
7
IO
P4[1]
Digital IO
8
IO
P3[7]
Digital IO
9
IO
P3[5]
Digital IO
10
IO
P3[3]
Digital IO
11
IO
P3[1]
Digital IO
12
IOHR
P1[7]
Digital IO, I2C SCL, SPI SS
13
IOHR
P1[5]
Digital IO, I2C SDA, SPI MISO
14
NC
NC
No connection
15
NC
NC
No connection
16
IOHR
17
IOHR
P1[3]
(1, 2)
P1[1]
Document Number: 001-12395 Rev. *G
Digital IO, SPI CLK
Digital IO, ISSP CLK, I2C SCL, SPI MOSI
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Table 2. 48-Pin Part Pinout (QFN) (continued)
Pin No.
Type
Name
Description
18
Power
Vss
Supply ground
19
NC
NC
No connection
20
NC
NC
No connection
21
Power
Vdd
Supply voltage
(1, 2)
22
IOHR
P1[0]
Digital IO, ISSP DATA, I2C SDA, SPI CLK
23
IOHR
P1[2]
Digital IO
24
IOHR
P1[4]
Digital IO, optional external clock input (EXTCLK)
25
IOHR
P1[6]
Digital IO
26
XRES
Ext Reset
Active high external reset with internal pull down
27
IO
P3[0]
Digital IO
28
IO
P3[2]
Digital IO
29
IO
P3[4]
Digital IO
30
IO
P3[6]
Digital IO
31
IO
P4[0]
Digital IO
32
IO
P4[2]
Digital IO
33
IO
P2[0]
Digital IO
34
IO
P2[2]
Digital IO
35
IO
P2[4]
Digital IO
36
IO
P2[6]
Digital IO
37
IOH
P0[0]
Digital IO
38
IOH
P0[2]
Digital IO
39
IOH
P0[4]
Digital IO
40
IOH
P0[6]
Digital IO
41
Power
Vdd
Supply voltage
42
NC
NC
No connection
43
NC
NC
No connection
44
IOH
P0[7]
Digital IO
45
IOH
P0[5]
Digital IO
46
IOH
P0[3]
Digital IO
47
Power
Vss
Supply ground
P0[1]
Digital IO
Vss
Center pad must be connected to ground
48
IOH
CP
Power
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Document Number: 001-12395 Rev. *G
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Register Reference
The section discusses the registers of the enCoRe V LV device. It lists all the registers in mapping tables, in address order.
Register Conventions
Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
The enCoRe V LV device has a total register address space of
512 bytes. The register space is also referred to as IO space and
is broken into two parts: Bank 0 (user space) and Bank 1 (configuration space). The XIO bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XIO bit is
set, the user is said to be in the “extended” address space or the
“configuration” registers.
Table 3. Register Conventions
Convention
Description
R
Read register or bits
W
Write register or bits
O
Only a read/write register or bits
L
Logical register or bits
C
Clearable register or bits
#
Access is bit specific
Document Number: 001-12395 Rev. *G
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Table 4. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
Addr (0,Hex)
00
Access
RW
01
RW
Name
Addr (0,Hex)
40
Access
Name
Addr (0,Hex)
80
Access
Name
Addr (0,Hex)
C0
41
81
C1
02
42
82
C2
03
43
83
C3
PRT1DR
04
RW
44
84
C4
PRT1IE
05
RW
45
85
C5
06
46
86
C6
07
47
87
Access
C7
PRT2DR
08
RW
48
88
I2C_XCFG
C8
PRT2IE
09
RW
49
89
I2C_XSTAT
C9
R
4A
8A
I2C_ADDR
CA
RW
R
0A
0B
RW
4B
8B
I2C_BP
CB
PRT3DR
0C
RW
4C
8C
I2C_CP
CC
R
PRT3IE
0D
RW
4D
8D
CPU_BP
CD
RW
0E
4E
8E
CPU_CP
CE
R
0F
4F
8F
I2C_BUF
CF
RW
PRT4DR
10
RW
50
90
CUR_PP
D0
RW
PRT4IE
11
RW
51
91
STK_PP
D1
RW
12
52
92
13
53
93
IDX_PP
D3
RW
14
54
94
MVR_PP
D4
RW
15
55
95
MVW_PP
D5
RW
16
56
96
I2C_CFG
D6
RW
17
57
97
I2C_SCR
D7
#
18
58
98
I2C_DR
D8
RW
D2
19
59
99
1A
5A
9A
INT_CLR0
DA
D9
1B
5B
9B
INT_CLR1
DB
RW
1C
5C
9C
INT_CLR2
DC
RW
1D
5D
9D
INT_CLR3
DD
RW
1E
5E
9E
INT_MSK2
DE
RW
1F
5F
9F
INT_MSK1
DF
RW
20
60
A0
INT_MSK0
E0
RW
21
61
A1
INT_SW_EN
E1
RW
22
62
A2
INT_VC
E2
RC
23
63
A3
RES_WDT
E3
W
24
64
A4
INT_MSK3
E4
RW
25
65
A5
E5
26
66
A6
E6
27
67
A7
E7
28
68
A8
E8
SPI_TXR
29
W
69
A9
E9
SPI_RXR
2A
R
6A
AA
EA
2B
#
SPI_CR
6B
AB
EB
2C
6C
AC
EC
2D
6D
AD
ED
2E
6E
AE
EE
2F
6F
AF
30
70
PT0_CFG
B0
RW
F0
31
71
PT0_DATA1
B1
RW
F1
32
72
PT0_DATA0
B2
RW
F2
33
73
PT1_CFG
B3
RW
F3
34
74
PT1_DATA1
B4
RW
F4
35
75
PT1_DATA0
B5
RW
F5
36
76
PT2_CFG
B6
RW
37
77
PT2_DATA1
B7
RW
38
78
PT2_DATA0
B8
RW
RW
EF
F6
CPU_F
F7
RL
F8
39
79
B9
F9
3A
7A
BA
FA
3B
7B
BB
FB
3C
7C
BC
FC
3D
7D
BD
3E
7E
BE
CPU_SCR1
FE
#
3F
7F
BF
CPU_SCR0
FF
#
Gray fields are reserved and should not be accessed.
FD
# Access is bit specific.
Document Number: 001-12395 Rev. *G
Page 11 of 28
[+] Feedback
CY7C60445, CY7C6045x
Table 5. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
Addr (1,Hex)
00
Access
RW
01
RW
Name
Addr (1,Hex)
40
Access
Name
Addr (1,Hex)
80
Access
Name
Addr (1,Hex)
C0
41
81
C1
02
42
82
C2
03
43
83
C3
PRT1DM0
04
RW
44
84
C4
PRT1DM1
05
RW
45
85
C5
06
46
86
C6
07
47
87
C7
PRT2DM0
08
RW
48
88
C8
PRT2DM1
09
RW
49
89
C9
0A
4A
8A
CA
0B
4B
8B
CB
PRT3DM0
0C
RW
4C
8C
CC
PRT3DM1
0D
RW
4D
8D
CD
0E
4E
8E
CE
0F
4F
8F
CF
Access
PRT4DM0
10
RW
50
90
D0
PRT4DM1
11
RW
51
91
D1
12
52
92
D2
13
53
93
D3
14
54
94
D4
15
55
95
D5
16
56
96
D6
17
57
97
D7
18
58
98
D8
19
59
99
D9
1A
5A
9A
DA
1B
5B
9B
1C
5C
9C
IO_CFG
DC
RW
1D
5D
9D
OUT_P1
DD
RW
1E
5E
9E
1F
5F
9F
20
60
A0
OSC_CR0
E0
21
61
A1
ECO_CFG
E1
#
22
62
A2
OSC_CR2
E2
RW
23
63
A3
VLT_CR
E3
RW
24
64
A4
VLT_CMP
E4
R
25
65
A5
E5
26
66
A6
E6
27
67
A7
28
68
A8
IMO_TR
E8
W
69
A9
ILO_TR
E9
W
2A
6A
AA
2B
6B
AB
SLP_CFG
SPI_CFG
29
RW
DB
DE
DF
RW
E7
EA
EB
RW
2C
TMP_DR0
6C
RW
AC
SLP_CFG2
EC
RW
2D
TMP_DR1
6D
RW
AD
SLP_CFG3
ED
RW
2E
TMP_DR2
6E
RW
AE
EE
2F
TMP_DR3
6F
RW
AF
EF
30
70
B0
F0
31
71
B1
F1
32
72
B2
F2
33
73
B3
F3
34
74
B4
F4
35
75
B5
F5
36
76
B6
37
77
B7
38
78
B8
F8
F6
CPU_F
F7
39
79
B9
F9
3A
7A
BA
FA
3B
7B
BB
FB
3C
7C
BC
FC
3D
7D
BD
FD
3E
7E
BE
FE
3F
7F
BF
FF
Gray fields are reserved and should not be accessed.
RL
# Access is bit specific.
Document Number: 001-12395 Rev. *G
Page 12 of 28
[+] Feedback
CY7C60445, CY7C6045x
Electrical Specifications
This section presents the DC and AC electrical specifications of the enCoRe V LV devices. For the most up to date electrical
specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com.
Figure 3. Voltage versus CPU Frequency
Figure 4. IMO Frequency Trim Options
3.6V
3.6V
lid ng
Va rati n
pe gio
Re
Vdd Voltage
Vdd Voltage
O
SLIMO
Mode
= 01
SLIMO
Mode
= 00
SLIMO
Mode
= 10
1.71V
1.71V
750 kHz
3 MHz
24 MHz
750 kHz
CPU Frequency
3 MHz
6 MHz 12 MHz 24 MHz
IMO Frequency
The following table lists the units of measure that are used in this chapter.
Table 6. Units of Measure
Symbol
oC
dB
fF
Hz
KB
Kbit
kHz
kΩ
MHz
MΩ
µA
µF
µH
µs
µV
µVrms
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
microvolts root-mean-square
Document Number: 001-12395 Rev. *G
Symbol
µW
mA
ms
mV
nA
ns
nV
Ω
pA
pF
pp
ppm
ps
sps
s
V
Unit of Measure
microwatts
milli-ampere
milli-second
milli-volts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Page 13 of 28
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CY7C60445, CY7C6045x
ADC Electrical Specifications
Table 7. ADC Electrical Specifications
Symbol
Description
Min
Input Voltage Range
Typ
Max
Units
Conditions
Vss
1.3
Volts
5
pF
8
10
Bits
Settings 8, 9, or 10
Input
Input Capacitance
Resolution
This gives 72% of maximum code
8-Bit Sample Rate
23.4375
ksps
Data Clock set to 6 MHz. Sample Rate
= 0.001/(2^Resolution/Data clock)
10-Bit Sample Rate
5.859
ksps
Data Clock set to 6 MHz. Sample Rate
= 0.001/(2^Resolution/Data clock)
+2
LSB
For any configuration
For any configuration
DC Accuracy
DNL
-1
INL
-2
Offset Error
0
Operating Current
Data Clock
+2
LSB
15
90
mV
275
350
µA
12
MHz
2.25
Monotonicity
Source is chip’s internal main oscillator.
See device data sheet of accuracy.
Not guaranteed. See DNL
Power Supply Rejection Ration
PSRR (Vdd>3.0V)
24
dB
PSRR (2.2 < Vdd < 3.0)
30
dB
PSRR (2.0 < Vdd < 2.2)
12
dB
0
dB
PSRR (Vdd < 2.0)
Gain Error
Input Resistance
Document Number: 001-12395 Rev. *G
1
5
1/(500fF*D 1/(400fF*D 1/(300fF*D
ata-Clock) ata-Clock) ata-Clock)
%FSR For any resolution
Ω
Equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution.
Page 14 of 28
[+] Feedback
CY7C60445, CY7C6045x
Electrical Characteristics
Absolute Maximum Ratings
Storage Temperature (TSTG) (3) ............................................. ...................................................... -55oC to 125oC (Typical +25oC)
Supply Voltage Relative to Vss (Vdd) .................................... ................................................................................. -0.5V to +4.0V
DC Input Voltage (VIO)........................................................... ................................................................. Vss - 0.5V to Vdd + 0.5V
DC Voltage Applied to Tri-state (VIOZ) ................................... ................................................................. Vss - 0.5V to Vdd + 0.5V
Maximum Current into any Port Pin (IMIO)............................. ............................................................................ -25mA to +50 mA
Electro Static Discharge Voltage (ESD) (4) ............................ .............................................................................................. 2000V
Latch-up Current (LU) (5) ....................................................... ............................................................................................ 200 mA
Operating Conditions
Ambient Temperature (TA) ..................................................... .....................................................................................0oC to 70oC
Operational Die Temperature (TJ)(6) ...................................... .....................................................................................0oC to 85oC
DC Electrical Characteristics
DC Chip Level Specifications
Table 8 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 8. DC Chip Level Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
1.71
–
3.6
V
Conditions are Vdd = 3.0V, TA = 25oC,
CPU = 24 MHz
No I2C/SPI
–
–
3.1
mA
Supply Current, IMO = 12 MHz
Conditions are Vdd = 3.0V, TA = 25oC,
CPU = 12 MHz
No I2C/SPI
–
–
2.0
mA
IDD6
Supply Current, IMO = 6 MHz
Conditions are Vdd = 3.0V, TA = 25oC,
CPU = 6 MHz
No I2C/SPI
–
–
1.5
mA
ISB0
Deep Sleep Current
Vdd = 3.0V, TA = 25oC, IO regulator
turned off
–
0.1
–
µA
ISB1
Standby Current with POR, LVD, and
Sleep Timer
Vdd = 3.0V, TA = 25oC, IO regulator
turned off
–
–
1.5
µA
Vdd
Supply Voltage
See table titled DC POR and LVD
Specifications on page 19.
IDD24
Supply Current, IMO = 24 MHz
IDD12
Notes
3. Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 85°C
degrade reliability.
4. Human Body Model ESD.
5. According to JESD78 standard.
6. The temperature rise from ambient to junction is package specific. See Thermal Impedances on page 26. The user must limit the power consumption to comply with
this requirement.
Document Number: 001-12395 Rev. *G
Page 15 of 28
[+] Feedback
CY7C60445, CY7C6045x
DC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 1.71V to 3.6V and
0°C ≤ TA ≤ 70°C. Typical parameters apply to 3.3V at 25°C. These are for design guidance only.
Table 9. 3.0V to 3.6V DC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
4
5.6
8
kΩ
IOH < 10 µA, maximum of 10 mA source
current in all IOs
Vdd - 0.2
–
–
V
High Output Voltage
Port 2 or 3 Pins
IOH = 1 mA, maximum of 20 mA source
current in all IOs
Vdd - 0.9
–
–
V
VOH3
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH < 10 µA, maximum of 10 mA source
current in all IOs
Vdd - 0.2
–
–
V
VOH4
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 5 mA, maximum of 20 mA source
current in all IOs
Vdd - 0.9
–
–
V
VOH5
High Output Voltage
Port 1 Pins with LDO Regulator
Enabled for 3V Out
IOH < 10 µA, Vdd > 3.1V, maximum of 4
IOs all sourcing 5 mA
2.85
3.00
3.3
V
VOH6
High Output Voltage
Port 1 Pins with LDO Regulator
Enabled for 3V Out
IOH = 5 mA, Vdd > 3.1V, maximum of 20
mA source current in all IOs
2.20
–
–
V
VOH7
High Output Voltage
IOH < 10 µA, Vdd > 2.7V, maximum of 20
Port 1 Pins with LDO Enabled for 2.5V mA source current in all IOs
Out
2.35
2.50
2.75
V
VOH8
High Output Voltage
IOH = 2 mA, Vdd > 2.7V, maximum of 20
Port 1 Pins with LDO Enabled for 2.5V mA source current in all IOs
Out
1.90
–
–
V
VOH9
IOH < 10 µA, Vdd > 2.7V, maximum of 20
High Output Voltage
Port 1 Pins with LDO Enabled for 1.8V mA source current in all IOs
Out
1.60
1.80
2.1
V
VOH10
High Output Voltage
IOH = 1 mA, Vdd > 2.7V, maximum of 20
Port 1 Pins with LDO Enabled for 1.8V mA source current in all IOs
Out
1.20
–
–
V
VOL
Low Output Voltage
–
–
0.75
V
VIL
Input Low Voltage
–
–
0.80
V
VIH
Input High Voltage
2.00
–
VH
Input Hysteresis Voltage
–
80
–
mV
IIL
Input Leakage (Absolute Value)
–
0.001
1
µA
CPIN
Pin Capacitance
0.5
1.7
5
pF
RPU
Pull Up Resistor
VOH1
High Output Voltage
Port 2 or 3 Pins
VOH2
Document Number: 001-12395 Rev. *G
Conditions
IOL = 25 mA, Vdd > 3.3V, maximum of 60
mA sink current on even port pins (for
example, P0[2] and P1[4]) and 60 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
Package and pin dependent
Temp = 25oC
V
Page 16 of 28
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CY7C60445, CY7C6045x
Table 10. 2.4V to 3.0V DC GPIO Specifications
Symbol
RPU
VOH1
VOL
Description
Pull Up Resistor
High Output Voltage
Port 2 or 3 Pins
High Output Voltage
Port 2 or 3 Pins
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
High Output Voltage
Port 1 Pins with LDO Enabled for 1.8V
Out
High Output Voltage
Port 1 Pins with LDO Enabled for 1.8V
Out
Low Output Voltage
VIL
VIH
VH
IIL
CPIN
Input Low Voltage
Input High Voltage
Input Hysteresis Voltage
Input Leakage (Absolute Value)
Capacitive Load on Pins
VOH2
VOH3
VOH4
VOH5A
VOH6A
Document Number: 001-12395 Rev. *G
Conditions
Min
4
Vdd - 0.2
IOH < 10 µA, maximum of 10 mA source
current in all IOs
IOH = 0.2 mA, maximum of 10 mA source Vdd - 0.4
current in all IOs
IOH < 10 µA, maximum of 10 mA source Vdd - 0.2
current in all IOs
Typ
5.6
–
Max
8
–
Units
kΩ
V
–
–
V
–
–
V
IOH = 2 mA, maximum of 10 mA source
current in all IOs
Vdd - 0.5
–
–
V
IOH < 10 µA, Vdd > 2.4V, maximum of 20
mA source current in all IOs.
1.50
1.80
2.10
V
IOH = 1 mA, Vdd > 2.4V, maximum of 20
mA source current in all IOs
1.20
–
–
V
IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink current
on odd port pins (for example, P0[3] and
P1[5])
–
–
0.75
V
–
1.6
–
–
0.5
–
–
80
0.001
1.7
0.72
V
V
mV
µA
pF
Package and pin dependent
Temp = 25oC
–
1
5
Page 17 of 28
[+] Feedback
CY7C60445, CY7C6045x
Table 11. 1.71V to 2.4V DC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
4
5.6
8
kΩ
IOH = 10 µA, maximum of 10 mA
source current in all IOs
Vdd - 0.2
–
–
V
High Output Voltage
Port 2 or 3 Pins
IOH = 0.5 mA, maximum of 10 mA
source current in all IOs
Vdd - 0.5
–
–
V
VOH3
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 100 µA, maximum of 10 mA
source current in all IOs
Vdd - 0.2
–
–
V
VOH4
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA
source current in all IOs
Vdd - 0.5
–
–
V
VOL
Low Output Voltage
IOL = 5 mA, maximum of 20 mA sink
current on even port pins (for
example, P0[2] and P1[4]) and 30 mA
sink current on odd port pins (for
example, P0[3] and P1[5])
–
–
0.4
V
VIL
Input Low Voltage
–
–
0.3 x Vdd
V
VIH
Input High Voltage
0.65 x Vdd
–
VH
Input Hysteresis Voltage
–
80
–
mV
IIL
Input Leakage (Absolute Value)
–
0.001
1
µA
CPIN
Capacitive Load on Pins
0.5
1.7
5
pF
RPU
Pull Up Resistor
VOH1
High Output Voltage
Port 2 or 3 Pins
VOH2
Document Number: 001-12395 Rev. *G
Conditions
Package and pin dependent.
Temp = 25oC
V
Page 18 of 28
[+] Feedback
CY7C60445, CY7C6045x
DC POR and LVD Specifications
Table 12 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 12. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
1.61
1.66
2.36
2.60
2.82
1.71
2.41
2.66
2.95
V
V
V
V
2.40
2.64
2.85
2.95
3.06
1.84
1.75
2.45
2.71
2.92
3.02
3.13
1.9
1.8
2.51
2.78
2.99
3.09
3.20
2.32
1.84
V
V
V
V
(7)
VPPOR0
VPPOR1
VPPOR2
VPPOR3
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b, HPOR = 0
PORLEV[1:0] = 00b, HPOR = 1
PORLEV[1:0] = 01b, HPOR = 1
PORLEV[1:0] = 10b, HPOR = 1
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
Vdd Value for LVD Trip
VM[2:0] = 000b(8)
VM[2:0] = 001b(9)
VM[2:0] = 010b(10)
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b(11)
DC Programming Specifications
Table 13 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 13. DC Programming Specifications
Symbol
VddIWRITE
IDDP
VILP
VIHP
IILP
IIHP
VOLV
VOHV
FlashENPB
FlashDR
Description
Supply Voltage for Flash Write Operations
Supply Current During Programming or Verify
Input Low Voltage During Programming or Verify
Input High Voltage During Programming or Verify
Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify(12)
Input Current when Applying Vihp to P1[0] or P1[1]
During Programming or Verify(12)
Output Low Voltage During Programming or Verify
Output High Voltage During Programming or Verify
Flash Write Endurance(14)
Flash Data Retention(15)
Min
1.71
–
–
VIH
–
Typ
–
5
–
–
–
Max
–
25
VIL
–
0.2
Units
V
mA
V
V
mA
–
–
1.5
mA
–
–
–
–
20
Vss + 0.75
Vdd
–
–
V
V
Cycles
Years
(13)
VOH
50,000
10
Notes
7. Vdd must be greater than or equal to 1.71V during startup, reset from the XRES pin, or reset from watchdog.
8. Always greater than 50 mV above VPPOR1 for falling supply.
9. Always greater than 50 mV above VPPOR2 for falling supply.
10. Always greater than 50 mV above VPPOR3 for falling supply.
11. Always greater than 50 mV above VPPOR0 voltage for falling supply.
12. Driving internal pull down resistor.
13. See appropriate DC General Purpose IO Specifications table. For Vdd > 3V use VOH4 in Table 9 on page
14. Erase/write cycles per block.
15. Following maximum Flash write cycles at Tamb = 55C and Tj = 70C.
Document Number: 001-12395 Rev. *G
16
Page 19 of 28
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CY7C60445, CY7C6045x
AC Electrical Characteristics
AC Chip Level Specifications
Table 14 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 14. AC Chip Level Specifications
Symbol
FMAX
FCPU
F32K1
FIMO24
FIMO12
FIMO6
DCIMO
TRAMP
Description
Maximum Operating Frequency(16)
Maximum Processing Frequency(17)
Internal Low Speed Oscillator Frequency
Internal Main Oscillator Stability for 24 MHz ± 5%(18)
Internal Main Oscillator Stability for 12 MHz(18)
Internal Main Oscillator Stability for 6 MHz(18)
Duty Cycle of IMO
Supply Ramp Time
Min
24
24
19
22.8
11.4
5.7
40
0
Typ
–
–
32
24
12
6.0
50
–
Max
–
–
50
25.2
12.6
6.3
60
–
Units
MHz
MHz
kHz
MHz
MHz
MHz
%
µs
AC General Purpose IO Specifications
Table 15 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 15. AC GPIO Specifications
Symbol
FGPIO
Description
GPIO Operating Frequency
Conditions
Normal Strong Mode, Port 0, 1
Normal Strong Mode, Port 2, 3
Min
Typ
Max
Units
0
–
6 MHz for
1.71V<Vdd<2.4V
MHz
0
–
12 MHz for
2.4V<Vdd<3.6V
0
-
3 MHz for
1.71V<Vdd<2.4V
MHz
6 MHz for
3.0V<Vdd<3.6V
TRise23
Rise Time, Strong Mode, Cload Vdd = 3.0 to 3.6V, 10% – 90%
= 50 pF
Ports 2 or 3
Vdd = 2.4 to 3.0V, 10% – 90%
15
–
80
15
–
100
TRise23L
Rise Time, Strong Mode Low
Supply, Cload = 50 pF
Ports 2 or 3
15
–
100
ns
TRise01
Rise Time, Strong Mode, Cload Vdd = 3.0 to 3.6V, 10% – 90%
LDO enabled or disabled
= 50 pF
Ports 0 or 1
Vdd = 2.4 to 3.0V, 10% – 90%
LDO enabled or disabled
10
–
50
ns
10
–
70
Vdd = 1.71 to 3.0V, 10% – 90%
ns
TRise01L
Rise Time, Strong Mode Low
Supply, Cload = 50 pF
Ports 0 or 1
Vdd = 1.71 to 3.0V, 10% – 90%
LDO enabled or disabled
15
–
100
ns
TFall
Fall Time, Strong Mode, Cload = Vdd = 3.0 to 3.6V, 10% – 90%
50 pF
All Ports
Vdd = 1.71 to 3.0V, 10% - 90%
10
–
80
ns
10
–
80
Notes
16. Digital clocking functions.
17. CPU speed.
18. Trimmed using factory trim values.
Document Number: 001-12395 Rev. *G
Page 20 of 28
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Figure 5. GPIO Timing Diagram
90%
GPIO Pin
Output
Voltage
10%
TRise23
TRise01
TFall
AC External Clock Specifications
Table 16 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 16. AC External Clock Specifications
Symbol
FOSCEXT
Min
Typ
Max
Units
Frequency
Description
0.750
–
25.2
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
µs
AC Programming Specifications
Table 17 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 17. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK1
TDSCLK2
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK,
3.0V<Vdd<3.6V
Data Out Delay from Falling Edge of SCLK,
1.71V<Vdd<3.0V
Document Number: 001-12395 Rev. *G
Min
1
1
40
40
0
–
–
–
Typ
–
–
–
–
–
–
–
–
Max
20
20
–
–
8
18
25
85
Units
ns
ns
ns
ns
MHz
ms
ms
ns
–
–
130
ns
Page 21 of 28
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Figure 6. Timing Diagram - AC Programming Cycle
AC SPI Specifications
Table 18 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 18. AC SPI Specifications
Symbol
FSPIM
FSPIS
TSS
Description
Min
Typ
Max
Master(19)
–
–
12
Maximum Input Clock Frequency Selection, Master(19)
1.71V<Vdd<2.4V
-
-
6
Maximum Input Clock Frequency Selection, Slave
2.4V<Vdd<3.6V
–
–
12
Maximum Input Clock Frequency Selection, Slave
1.71V<Vdd<2.4V
–
–
6
Width of SS_ Negated Between Transmissions
50
–
–
Maximum Input Clock Frequency Selection,
2.4V<Vdd<3.6V
Units
MHz
MHz
ns
Notes
19. Output clock frequency is half of input clock rate.
Document Number: 001-12395 Rev. *G
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AC I2C Specifications
Table 19 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 19. AC Characteristics of the I2C SDA and SCL Pins
Symbol
FSCLI2C
THDSTAI2C
TLOWI2C
THIGHI2C
TSUSTAI2C
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
TSPI2C
Description
SCL Clock Frequency
Hold Time (repeated) START Condition. After this period,
the first clock pulse is generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated START Condition
Data Hold Time
Data Setup Time
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START Condition
Pulse Width of Spikes are Suppressed by the Input Filter
Standard Mode
Min
Max
0
100
4.0
–
4.7
4.0
4.7
0
250
4.0
4.7
–
–
–
–
–
–
–
–
–
Fast Mode
Min
Max
0
400
0.6
–
1.3
0.6
0.6
0
100(20)
0.6
1.3
0
Units
kHz
µs
µs
µs
µs
µs
ns
µs
µs
ns
–
–
–
–
–
–
–
50
Figure 7. Definition of Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Notes
20. A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tSU;DAT Š 250 ns must then be met. This is automatically the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released.
Document Number: 001-12395 Rev. *G
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Package Diagram
This chapter illustrates the packaging specifications for the enCoRe V LV device, along with the thermal impedances for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the enCoRe V LV emulation tools and their dimensions, refer to the development kit..
Packaging Dimensions
Figure 8. 32-Pin (5 x 5 x 0.55 mm) QFN
001-42168 *B
Document Number: 001-12395 Rev. *G
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Figure 9. 48-Pin (7 x 7 x 0.9 mm) QFN
001-13191 *C
Document Number: 001-12395 Rev. *G
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Thermal Impedances
Table 20. Thermal Impedances per Package
Typical θJA (21)
19.51 oC/W
17.68 oC/W
Package
32 QFN(22)
48 QFN(22)
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 21. Solder Reflow Peak Temperature
Minimum Peak Temperature(23)
Package
Maximum Peak Temperature
o
32 QFN
240 C
260oC
48 QFN
240oC
260oC
Ordering Information
Ordering Code
Flash
SRAM
No. of GPIOs
Target Applications
16K
1K
28
Feature-Rich Wireless Mouse
CY7C60445-32LQXCT 32-Pin QFN - (Tape and Reel)
(5x5x0.55 mm)
16K
1K
28
Feature-Rich Wireless Mouse
CY7C60455-48LTXC
48-Pin QFN
(7x7x0.9 mm)
16K
1K
36
Mid-Tier Wireless Keyboard
CY7C60455-48LTXCT
48-Pin QFN - (Tape and Reel)
(7x7x0.9 mm)
16K
1K
36
Mid-Tier Wireless Keyboard
CY7C60456-48LTXC
48-Pin QFN
(7x7x0.9 mm)
32K
2K
36
Feature-Rich Wireless
Keyboard
CY7C60456-48LTXCT
48-Pin QFN - (Tape and Reel)
(7x7x0.9 mm)
32K
2K
36
Feature-Rich Wireless
Keyboard
CY7C60445-32LQXC
Package Information
32-Pin QFN
(5x5x0.55 mm)
Notes
21. TJ = TA + Power x θJA.
22. To achieve the thermal impedance specified for the package, solder the center thermal pad to the PCB ground plane.
23. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-12395 Rev. *G
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Document History Page
Document Title: CY7C60445, CY7C6045x, enCoRe™ V Low Voltage Microcontroller
Document Number: 001-12395
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
626516
TYJ
See ECN
New data sheet
*A
735721
TYJ/ARI
See ECN
Added new block diagram, replaced TBDs, corrected values, updated pinout information, changed part number to reflect new specifications.
*B
1120504
ARI
See ECN
Corrected the description to pin 29 on Table 1, the Typ/Max values for ISB0 on the
DC chip-level specifications, and the Min voltage value for VddIWRITE in the DC
Programming Specifications table.
Corrected Flash Write Endurance minimum value in the DC Programming Specifications table.
Corrected the Flash Erase Time max value and the Flash Block Write Time max
value in the AC Programming Specifications table.
Implemented new latest template.
*C
1225864
AESA/ARI
See ECN
Corrected the description to pin 13, 29 on Table 1 and 22,44 on Table 2.
Added sections Register Reference, Register Conventions and Register Mapping
Tables. Corrected Max values on the DC Chip-Level Specifications table.
*D
1446763
AESA
See ECN
Changed TERASEB parameter, max value to 18ms in Table 13, AC Programming
Specification.
*E
1639963
AESA
See ECN
Post to www.cypress.com
*F
2138889
TYJ/PYRS
See ECN
Updated Ordering Code table:
- Ordering code changed for 32-QFN package: From -32LKXC to -32LTXC
- Added a new package type – “LTXC” for 48-QFN
- Included Tape and Reel ordering code for 32-QFN and 48-QFN packages
Changed active current values at 24, 12 and 6MHz in table “DC Chip-Level Specifications”
- IDD24: 2.15 to 3.1mA
- IDD12: 1.45 to 2.0mA
- IDD6: 1.1 to 1.5mA
Added information on using P1[0] and P1[1] as the I2C interface during POR or
reset events
*G
2583853
TYJ/PYRS/
HMT
10/10/08
Converted from Preliminary to Final
ADC resolution changed from 10-bit to 8-bit
On Page1, SPI Master and Slave – speeds changed
Rephrased battery monitoring clause in page 1 to include “with external components”
Included ADC specifications table
Voh5, Voh7, Voh9 speca changed
Flash data retention – condition added to Note [15]
Input leakage spec changed to 25 nA max
Under AC Char, Frequency accuracy of ILO corrected
GPIO rise time for ports 0,1 and ports 2,3 made common
AC Programming specifications updated
Included AC Programming cycle timing diagram
AC SPI specification updated
Spec change for 32-QFN package
Input Leakage Current maximum value changed to 1 uA
Maximum specification for VOH5A parameter changed from 2.0 to 2.1V
Minimum voltages for FSPIM and FSPIS specifications changed from 1.8V to 1.71V
(Table 18)
Updated VOHV parameter in Table 13
Updated Thermal impedance values for the packages - Table 20.
Update Development Tools, add Designing with PSoC Designer. Edit, fix links and
table format. Update TMs. Update maximum data in Table 12. DC POR and LVD
Specifications.
Document Number: 001-12395 Rev. *G
Description of Change
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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psoc.cypress.com/can
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psoc.cypress.com/usb
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image.cypress.com
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© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-12395 Rev. *G
Revised October 7, 2008
Page 28 of 28
enCoRe™, PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation. All other trademarks
or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license
under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company
names mentioned in this document may be the trademarks of their respective holders.
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