HV256 32-Channel High Voltage Amplifier Array Features General Description ► ► ► ► ► ► ► ► ► The Supertex HV256 is a 32-channel high voltage amplifier array integrated circuit. It operates on a single high voltage supply, up to 300V, and two low voltage supplies, VDD and VNN. 32 independent high voltage amplifiers 300V operating voltage 295V output voltage 2.2V/µs typical output slew rate Adjustable output current source limit Adjustable output current sink limit Internal closed loop gain of 72V/V 12MΩ feedback impedance Layout ideal for die applications Applications ► MEMS (microelectromechanical systems) driver ► Piezoelectric transducer driver ► Optical crosspoint switches (using MEMS technology) The input voltage range is from 0V to 4.096V. The internal closed loop gain is 72V/V, giving an output voltage of 295V when 4.096V is applied. Input voltages of up to 5V can be applied, but will cause the output to saturate. The maximum output voltage swing is 5V below the VPP high voltage supply. The outputs can drive capacitive loads of up to 3000pF. The maximum output source and sink current can be adjusted by using two external resistors. An external RSOURCE resistor controls the maximum sourcing current and an external RSINK resistor controls the maximum sinking current. The current limit is approximately 12.5V divided by the external resistor value. The setting is common for all 32 outputs. A low voltage silicon junction diode is made available to help monitor the die temperature. Typical Application Circuit DAC DAC DAC DAC DAC DAC Supertex HV256 VDD VPP HVOUT0 VIN0 HVOUT1 VIN1 HVOUT2 VIN2 VIN3 VIN30 VIN31 High Voltage Op-Amp Array HVOUT3 HVOUT31 AGND VNN y x x y MEMS Array HVOUT30 RSOURCE RSINK Micro Processor HV256 Device Absolute Maximum Ratings Package Option 100-Lead MQFP HV256 HV256FG HV256FG-G -G indicates package is RoHS compliant (‘Green’) Parameter Value VPP, High voltage supply 310V AVDD, Analog low voltage positive supply 8.0V DVDD, Digital low voltage positive supply 8.0V AVNN, Analog low voltage negative supply -7.0V DVNN, Digital low voltage negative supply -7.0V Logic input voltage -0.5V to DVDD VSIG, Analog input signal 0V to 6.0V SRVPP, VPP ramp up/down TBDV/usec Storage temperature range -65°C to 150°C Maximum junction temperature 150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Operating Conditions Symbol Parameter Min Typ Max Units Conditions VPP High voltage positive supply 125 - 300 V --- VDD Low voltage positive supply 6.0 - 7.5 V --- VNN Low voltage negative supply -4.5 - -6.5 V --- IPP VPP supply current - - 0.8 mA VPP = 300V, All HVOUT = 0V No load IDD VDD supply current - - 5.0 mA VDD = 6.0V to 7.5V INN VNN supply current -6.0 - - mA VNN = -4.5V to -6.5V TJ Operating temperature range -10 - 85 °C --- Electrical Characteristics (over operating conditions, unless otherwise specified) High Voltage Amplifier Symbol Min Typ Max Units HVOUT HVOUT voltage swing 0 - VPP- 5.0 V --- VIN Input voltage range 0 - 5.0 V --- VINOS Input voltage offset - - ±50 mV Input referred HVOUT slew rate rise - 2.2 - V/µs No Load SR Parameter Conditions HVOUT slew rate fall - 2.0 - V/µs No Load BW HVOUT -3dB channel bandwidth - 4.0 - KHz VPP = 300V AO Open loop gain 70 100 - dB AV Closed loop gain 68.4 72 75.6 V/V --- RFB Feedback resistance from HVOUT to ground 9.6 12 - MΩ --- --- CLOAD HVOUTt capacitive load 0 - 3000 pF --- ISOURCE HVOUT sourcing current limiting range 385 550 715 µA RSOURCE = 25KΩ ISINK HVOUT sinking current limiting range External resistance range for setting maximum current source External resistance range for setting maximum current sink DC channel to channel crosstalk 385 550 715 µA RSINK = 25KΩ 25 - 250 KΩ --- 25 - 250 KΩ --- -80 - - dB --- Power supply rejection ratio for VPP, VDD, VNN -40 - - dB --- RSOURCE RSINK CTDC PSRR 2 HV256 Temperature Diode Symbol PIV VF IF TC Parameter Peak inverse voltage Forward diode drop Forward diode current VF temperature coefficient Min Typ Max Units Conditions - 0.6 -2.2 5.0 100 - V V µA mV/°C cathode to anode IF = 100µA, anode to cathode at TA = 25°C anode to cathode anode to cathode HV256 Block Diagram BYP-VPP To internal VPP bus BYP-VDD To internal VDD bus BYP-VNN To internal VNN bus RSOURCE RSINK Output Current Source Limiting for all HVOUT Output Current Sink Limiting for all HVOUT VPP VDD VIN0 + HVOUT0 71R VNN R VDD VPP VIN1 + HVOUT1 71R VNN R VDD VPP VIN31 + HVOUT31 71R R GND VNN Anode Cathode 3 HV256 Power Up/Down Issues External Diode Protection Connection External Diode Protection The device can be damaged due to improper power up / down sequence. To prevent damage, please follow the acceptable power up / down sequences, and add two external diodes as shown in the diagram on the right. The first diode is a high voltage diode across VPP and VDD , where the anode of the diode is connected to VDD and the cathode of the diode is connected to VPP. Any low current, high voltage diode, such as a 1N4004, will be adequate. The second diode is a Schottky diode across VNN and DGND , where the anode of the Schottky diode is connected to VNN , and the cathode is connected to DGND. Any low current Schottky diode such as a 1N5817 will be adequate. VDD VPP 1N4004 or similar VNN DGND 1N5817 or similar Suggested Power Up/Down Sequence The HV256 needs all power supplies to be fully up and all channels refreshed with VSIG = 0V to force all high voltage outputs to 0V. Before that time, the high voltage outputs may have temporary voltage excursions above or below GND level depending on selected power up sequence. To minimize the excursions: Acceptable Power Up Sequences The HV256 can be powered up with any of the following sequences listed below. 1) VPP 2) VNN 3) VDD 4) Inputs and Anode 1) VNN 2) VDD 3) VPP 4) Inputs and Anode 1) VDD & VNN 2) Inputs 3) VPP 4) Anode 1. The VDD and VNN power supplies should be applied at the same time (or within a few nanoseconds). Suggested VPP ramp up speed should be 10msec or longer and ramp down to be 1msec or longer. Acceptable Power Down Sequences The HV256 can be powered down with any of the following sequences listed below. 1) Inputs and Anode 2) VDD 3) VNN 4) VPP 1) Inputs and Anode 2) VPP 3) VDD 4) VNN 1) Anode 2) VPP 3) Inputs 4) VNN & VDD Recommended Power Up/Down Timing 300V VPP 0V 6.5V VDD 0V VNN 0V -5.5V VIN 0V Gnd +/- V offset X 72 HVOUT 0V HVOUT Level at Power UP Power Up Sequence VDD Before VNN VNN Before VDD VPP VDD VNN VPP 0V VDD 6.5V 0V VNN 0V -5.5V 0V 6.5V 0V 0V -5.5V HVOUT HVOUT 0V 6.5V 0V -5.5V 4 HV256 RSINK / RSOURCE The VDD_BYP ,VDD_BYP ,and VNN_BYP pins are internal. high impedance current. mirror gate nodes, brought out to mantain stable opamp biasing currents in noisy power supply environments. 0.1uF/25V bypass capacitors, added from VPP_BYP pin to VPP , from VDD_BYP pin to VDD , and from VNN_BYP to VNN,will force the high impedance gate nodes to follow fluctuation of power lines. The expected voltages at the VDD_BYP, and VNN_BYP pins are typically 1.5 volts from their respectful power supply. The expected voltage at VPP_BYP is typically 3V below VPP. VPP Current limit BYP _VPP Cap 0.1uF / 25V BYP _VPP Set by RSOURCE BYP _VDD To internal biasing BYP _VDD Cap 0.1uF / 25V VDD HVOpamp HVOUT31 HVOUT0 HVOpamp Set by RSINK BYP _VNN Current limit BYP _VNN Cap 0.1uF / 25V VNN Typical Characteristics ISOURCE vs RSOURCE (VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) ISINK vs RSINK 600 (VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) 600 500 ISOURCE (µA) 500 ISINK (µA) 400 300 400 300 200 200 max 100 max min 100 0 min 25k 150k RSOURCE (KΩ) 0 25k 150k 250k RSINK (KΩ) 5 250k HV256 Typical Characteristics (cont.) VNN PSSR vs Frequency (VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) Temperature Diode vs Temperature -50 (VPP = 300V, VDD = 6.5V, VNN = 5.5V) VNN PSSR (dB) -40 700 -10 C O max 25 C O min 600 Vf (mV) max min -20 -10 85OC 500 -30 max min 0 10 100 1k 400 10k 100k Frequency 300 1μA 20μA 40μA 60μA 80μA Input Offset vs VIN and Temperature 100μA (VPP = 300V, VDD = 6.5V, VNN = 5.5V ) Diode Biasing Current (µA) 3.5 3.0 VPP PSSR vs Frequency 2.5 (VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) -50 HVOUT (mV) 2.0 VPP PSSR (dB) -40 -30 -20 Offset at -10OC Offset at 25OC Offset at 85OC 1.5 -2.0 -2.5 -3.0 -10 -3.5 0 10 100 1k 10k 100k 1M -4.0 Frequency (Hz) -4.5 1 2 3 VIN (Volts) VDD PSSR vs Frequency (VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) Gain vs VIN -50 -40 73.97 -30 73.95 73.96 HVOUT (V) VDD PSSR (dB) (VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = -10O, +25O, +85OC ) -20 -10 0 10 100 1k 10 100 73.94 73.93 72.74 72.73 72.72 72.71 1M 72.70 Frequency (Hz) 72.69 1 2 VIN (Volts) 6 3 1M HV256 Pad Configuration (not drawn to scale) Do Not Bond. Leave Floating. GND VDD VNN GND VDD Byp-VNN Byp-VDD VNN Do Not Bond. For testing only. Anode Cathode RSINK RSOURCE Byp-VPP VPP HVOUT31 Do Not Bond. Leave Floating. HVOUT30 HVOUT29 VIN31 HVOUT28 VIN30 HVOUT27 VIN29 VIN28 HVOUT26 VIN27 HVOUT25 VIN26 HVOUT24 VIN25 HVOUT23 VIN24 HVOUT22 VIN23 HVOUT21 VIN22 HVOUT20 VIN21 VIN20 HVOUT19 VIN19 HVOUT18 VIN18 HVOUT17 VIN17 HVOUT16 VIN16 HVOUT15 VIN15 HVOUT14 HVOUT13 HVOUT12 VIN14 HVOUT11 VIN13 VIN12 HVOUT10 VIN11 HVOUT 9 VIN10 HVOUT 8 VIN9 HVOUT 7 VIN8 HVOUT 6 VIN7 HVOUT 5 VIN6 HVOUT 4 VIN5 VIN4 HVOUT 3 VIN3 HVOUT 2 VIN2 HVOUT 1 VIN1 HVOUT 0 VIN0 VPP VDD VNN GND VDD VNN GND 7 HV256 Pad Coordinates Chip size: 17160μm x 5830μm Center of die is (0,0) Pad Nam e X (µm ) Y( µm ) Pad Name X( µm) Y( µm) Pa d Name X( µm) Y(µm) V PP -8338.5 2708.5 HVOUT28 4620.5 2305.5 VIN20 588.5 -2686.0 HVOUT0 -7895.0 2305.5 HVOUT29 5067.5 2305.5 VIN19 183.5 -2686.0 HVOUT1 -7448.5 2305.5 HVOUT30 5514.5 2305.5 VIN18 -221.5 -2686.0 HVOUT2 -7001.5 2305.5 HVOUT31 5961.5 2305.5 VIN17 -626.5 -2686.0 HVOUT3 -6554.5 2305.5 VPP 6659 2709 VIN16 -1031.5 -2686.0 HVOUT4 -6107.5 2305.5 Byp-VPP 7045 2709 VIN15 -1436.5 -2686.0 HVOUT5 -5660.5 2305.5 RSOURCE 7489 2709 VIN14 -2412.0 -2686.0 HVOUT6 -5213.5 2305.5 RSINK 7969 2709 VIN13 -2817 -2686.0 HVOUT7 -4766.5 2305.5 Cathode 8366 2709 VIN12 -3222 -2686.0 HVOUT8 -4319.5 2305.5 Anode 8366 2199 VIN11 -3627 -2686.0 HVOUT9 -3872.5 2305.5 VNN 8047 425.0 VIN10 -4032 -2686.0 HVOUT10 -3425.5 2305.5 Byp-VDD 8047 125.5 VIN9 -4437 -2686.0 HVOUT11 -2978.5 2305.5 Byp-VNN 8047 -345.5 VIN8 -4842 -2686.0 HVOUT12 -2531.5 2305.5 VDD 8047 -704.5 VIN7 -5247 -2686.0 HVOUT13 -2084.5 2305.5 GND 8047 -1424.0 VIN6 -5652 -2686.0 HVOUT14 -1637.5 2305.5 VNN 8066.5 -1590.0 VIN5 -6052 -2686.0 -2686.0 HVOUT15 -1190.5 2305.5 VDD 8066.5 -1958.5 VIN4 -6462 HVOUT16 -743.5 2305.5 GND 7867.0 -2192.0 VIN3 -6867 -2686.0 HVOUT17 -296.5 2305.5 VIN31 5043.5 -2686.0 VIN2 -7272 -2686.0 -2686.0 HVOUT18 150.0 2305.5 VIN30 4638.5 -2686.0 VIN1 -7677 HVOUT19 597.5 2305.5 VIN29 4233.5 -2686.0 VIN0 -8082 -2686.0 HVOUT20 1044.5 2305.5 VIN28 3828.5 -2686.0 VDD -8373 -2250.5 -1949.0 HVOUT21 1491.5 2305.5 VIN27 3423.5 -2686.0 VNN -8373 HVOUT22 1938.5 2305.5 VIN26 3018.5 -2686.0 GND -8367 -1561. HVOUT23 2385.5 2305.5 VIN25 2613.5 -2686.0 VDD -8387 -1143.0 HVOUT24 2832.5 2305.5 VIN24 2208.5 -2686.0 VNN -8338.5 577.5 HVOUT25 3279.5 2305.5 VIN23 1803.5 -2686.0 GND -8341.0 916.5 HVOUT26 3726.5 2305.5 VIN22 1398.5 -2686.0 HVOUT27 4173.5 2305.5 VIN21 993.5 -2686.0 8 HV256 Pin Description Pin # Function 33, 100 VPP 99 BYP-VPP 42, 45, 87, 91 VDD 93 BYP-VDD 40, 44, 88, 94 VNN 92 BYP-VNN 39, 43, 86, 89 GND 98 RSOURCE 97 RSINK 95 Anode 96 Cathode 48-79 VIN0 to VIN31 1-32 HVOUT0 to HVOUT31 Description High voltage positive supply. There are two pads. A low voltage 1.0 to 10nF decoupling decoupling capacitor across VPP and BYP-VPP is required. Analog low voltage positive supply. There are four pads. A low voltage 1.0 to 10nF decoupling decoupling capacitor across VDD and BYP-VDD is required. Analog low voltage negative supply. There are four pads. A low voltage 1.0 to 10nF decoupling decoupling capacitor across VNN and BYP-VNN is required. Digital ground. There are four pads. External resistor from RSOURCE to VNN sets output current sourcing limit. Current limit is approximately 12.5V divided by RSOURCE resistor value. External resistor from RSINK to VNN sets output current sinking limit. Current limit is approximately 12.5V divided by RSINK resistor value. Anode side of of a low voltage silicon diode that can be used to monitor die temperature. Cathode side of of a low voltage silicon diode that can be used to monitor die temperature. Amplifier inputs. Amplifier outputs. 9 HV256 Pin Configuration 80 51 81 50 100 31 1 30 100-Lead MQFP (top view) Pin Configuration Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Function HVOUT31 HVOUT30 HVOUT29 HVOUT28 HVOUT27 HVOUT26 HVOUT25 HVOUT24 HVOUT23 HVOUT22 HVOUT21 HVOUT20 HVOUT19 HVOUT18 HVOUT17 HVOUT16 HVOUT15 HVOUT14 HVOUT13 HVOUT12 HVOUT11 HVOUT10 HVOUT9 HVOUT8 HVOUT7 Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Function HVOUT6 HVOUT5 HVOUT4 HVOUT3 HVOUT2 HVOUT1 HVOUT0 VPP NC NC NC NC NC GND VNN NC VDD GND VNN VDD NC NC VIN0 VIN1 VIN2 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Note: NC = No Connect 10 Function VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VIN9 VIN10 VIN11 VIN12 VIN13 VIN14 VIN15 VIN16 VIN17 VIN18 VIN19 VIN20 VIN21 VIN22 VIN23 VIN24 VIN25 VIN26 VIN27 Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Function VIN28 VIN29 VIN30 VIN31 NC NC NC NC NC NC GND VDD VNN GND NC VDD BYP-VNN BYP-VDD VNN Anode Cathode RSINK RSOURCE BYP-VPP VPP HV256 100-Lead MQFP Package Outline (FG) 20x14mm body, 3.15mm height (max.), 0.65mm pitch, 3.2mm footprint D D1 θ1 E E1 Note 1 (Index Area E1/4 x D1/4) Gauge Plane L2 L L1 100 1 e Seating Plane θ b View B Top View View B A A2 Seating Plane A1 Side View Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (mm) NOM MAX A A1 A2 b D D1 E E1 2.50 0.00 2.50 0.22 22.95 19.80 16.95 13.90 3.15 0.25 2.70 2.90 0.40 23.20 23.45 20.00 20.20 17.20 17.45 14.00 14.20 e L L1 L2 0.73 0.65 BSC 0.88 1.03 1.60 REF 0.25 BSC θ θ1 0O 5O - - 7 O 16O JEDEC Registration MS-022, Variation GC-2, Issue B, Dec. 1996. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV256 B120406 11