® LY62W102516 1024K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 REVISION HISTORY Revision Rev. 0.1 Rev. 1.0 Description Initial Issue Revised Notes item 1 and 2 in page 3 Issue Date Jul.13.2011 Aug.29.2013 1. VIH(max) = VCC + 2.0V for pulse width less than 6ns. 2. VIL(min) = VSS - 2.0V for pulse width less than 6ns. Rev. 1.1 Revised ORDERING INFORMATION Deleted WRITE CYCLE Notes : Jun.29.2016 1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions. In page 7 Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 ® LY62W102516 1024K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 FEATURES GENERAL DESCRIPTION Fast access time : 55/70ns Low power consumption: Operating current : 45/30mA (TYP.) Standby current : 10μA (TYP.) LL-version Single 2.7V ~ 5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 1.5V (MIN.) Green package available Package : 48-pin 12mm x 20mm TSOP-I The LY62W102516 is a 16,777,216-bit low power CMOS static random access memory organized as 1,048,576 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY62W102516 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The LY62W102516 operates from a single power supply of 2.7V ~ 5.5V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family LY62W102516 LY62W102516(I) Operating Temperature 0 ~ 70℃ -40 ~ 85℃ Vcc Range Speed 2.7 ~ 5.5V 2.7 ~ 5.5V 55/70ns 55/70ns FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION Vcc Vss A0-A19 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# CE2 WE# OE# LB# UB# Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 10µA(LL) 45/30mA 10µA(LL) 45/30mA SYMBOL DESCRIPTION A0 - A19 Address Inputs DQ0 – DQ15 Data Inputs/Outputs DECODER I/O DATA CIRCUIT 1024Kx16 MEMORY ARRAY CE#, CE2 Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground COLUMN I/O CONTROL CIRCUIT Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 ® LY62W102516 1024K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 PIN CONFIGURATION ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 Operating Temperature TA Storage Temperature Power Dissipation DC Output Current TSTG PD IOUT RATING -0.5 to 6.5 -0.5 to VCC+0.5 0 to 70(C grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# CE2 OE# WE# LB# UB# H X X L L L L L L L L X L X H H H H H H H H X X X H H L L L X X X X X X H H H H H L L L X X H L X L H L L H L X X H X L H L L H L L I/O OPERATION SUPPLY CURRENT DQ0-DQ7 DQ8-DQ15 High – Z High – Z ISB,ISB1 High – Z High – Z High – Z High – Z High – Z High – Z ICC,ICC1 High – Z High – Z DOUT High – Z ICC,ICC1 DOUT High – Z DOUT DOUT DIN High – Z ICC,ICC1 DIN High – Z DIN DIN H = VIH, L = VIL, X = Don't care. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 ® LY62W102516 1024K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage SYMBOL VCC Input High Voltage VIH Input Low Voltage Input Leakage Current Output Leakage Current VIL ILI Output High Voltage VOH Output Low Voltage VOL *1 VCC = 4.5~5.5V VCC = 2.7~4.5V *2 ILO ICC Average Operating Power supply Current ICC1 ISB Standby Power Supply Current TEST CONDITION ISB1 VCC ≧ VIN ≧ VSS VCC ≧ VOUT ≧ VSS Output Disabled IOH = -1mA, VCC = 4.5~5.5V IOH = -1mA, VCC = 2.7~4.5V IOL = 2mA Cycle time = Min. - 55 CE# = VIL and CE2 = VIH II/O = 0mA - 70 Other pins at VIL or VIH Cycle time = 1µs CE#≦0.2V and CE2≧VCC-0.2V II/O = 0mA Other pins at 0.2V or VCC-0.2V CE# = VIH or CE2 = VIL Other pins at VIL or VIH CE# ≧VCC-0.2V -LL or CE2≦0.2V Other pins at 0.2V or VCC-0.2V -LLI MIN. 2.7 2.4 2.2 - 0.2 -1 TYP. 3.0 - *4 MAX. 5.5 VCC+0.3 VCC+0.3 0.6 1 UNIT V V V V µA -1 - 1 µA 2.4 2.2 - - 0.4 V V V - 45 60 mA - 30 45 mA - 8 16 mA - 0.3 2 mA - 10 60 µA - 10 100 µA Notes: 1. VIH(max) = VCC + 2.0V for pulse width less than 6ns. 2. VIL(min) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25℃ CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 UNIT pF pF ® LY62W102516 1024K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW LY62W102516-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 55 25 10 - LY62W102516-70 MIN. MAX. 70 70 70 35 10 5 25 25 10 70 30 10 - UNIT LY62W102516-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 20 45 - LY62W102516-70 MIN. MAX. 70 60 60 0 55 0 30 0 5 25 60 - UNIT *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ® LY62W102516 1024K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 ® LY62W102516 1024K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 WRITE CYCLE 1 (WE# Controlled) (1,2,4,5) tWC Address tAW CE# tCW CE2 tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# and CE2 Controlled) (1,4,5) tWC Address tAW CE# tAS tWR tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 ® LY62W102516 1024K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 WRITE CYCLE 3 (LB#,UB# Controlled) (1,4,5) tWC Address tAW tWR CE# tAS tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low. 2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 3.During this period, I/O pins are in the output state, and input signals must not be applied. 4.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 ® LY62W102516 1024K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION VCC for Data Retention VDR CE#≧VCC - 0.2V or CE2≦0.2V VCC = 1.5V -LL Data Retention Current IDR CE# ≧VCC-0.2V or CE2≦0.2V other pins at 0.2V or VCC-0.2V -LLI Chip Disable to Data See Data Retention tCDR Retention Time Waveforms (below) Recovery Time tR tRC* = Read Cycle Time MIN. 1.5 TYP. - MAX. 5.5 UNIT V - 8 50 µA - 8 80 µA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ≧ 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ≧ Vcc-0.2V VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ≧ 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE2 tR CE2 ≦ 0.2V VIL VIL Low Vcc Data Retention Waveform (3) (LB#, UB# controlled) VDR ≧ 1.5V Vcc Vcc(min.) Vcc(min.) tCDR LB#,UB# VIH tR LB#,UB# ≧ Vcc-0.2V VIH Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 ® LY62W102516 Rev. 1.1 1024K X 16 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 48-pin 12mm x 20mm TSOP-I Package Outline Dimension Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 ® LY62W102516 1024K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 ORDERING INFORMATION Package Type 48-Pin 12mmx20mm TSOP-I Access Time (Speed)(ns) Power Type 55 Ultra Low Power Temperature Range(℃) 0℃~70℃ -40℃~85℃ 70 Ultra Low Power 0℃~70℃ -40℃~85℃ Packing Type Tray LY62W102516LL-55LL Tape Reel LY62W102516LL-55LLT Tray LY62W102516LL-55LLI Tape Reel LY62W102516LL-55LLIT Tray LY62W102516LL-70LL Tape Reel LY62W102516LL-70LLT Tray LY62W102516LL-70LLI Tape Reel LY62W102516LL-70LLIT Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 Lyontek Item No. ® LY62W102516 Rev. 1.1 1024K X 16 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11