Microchip MCP3422A7T-E/ST 18-bit, multi-channel î î£ analog-to-digital converter with i2câ ¢ interface and on-board reference Datasheet

MCP3422/3/4
18-Bit, Multi-Channel ΔΣ Analog-to-Digital Converter with
I2C™ Interface and On-Board Reference
Features
Description
• 18-bit ΔΣ ADC with Differential Inputs:
- 2 channels: MCP3422 and MCP3423
- 4 channels: MCP3424
• Differential Input Full Scale Range: -VREF to
+VREF
• Self Calibration of Internal Offset and Gain per
Each Conversion
• On-Board Voltage Reference (VREF):
- Accuracy: 2.048V ± 0.05%
- Drift: 15 ppm/°C
• On-Board Programmable Gain Amplifier (PGA):
- Gains of 1, 2, 4 or 8
• INL: 10 ppm of Full Scale Range
• Programmable Data Rate Options:
- 3.75 SPS (18 bits)
- 15 SPS (16 bits)
- 60 SPS (14 bits)
- 240 SPS (12 bits)
• One-Shot or Continuous Conversion Options
• Low Current Consumption:
- 135 µA typical
(VDD= 3V, Continuous Conversion)
- 36 µA typical
(VDD= 3V, One-Shot Conversion with 1 SPS)
• On-Board Oscillator
• I2C™ Interface:
- Standard, Fast and High Speed Modes
- User configurable two external address pins
for MCP3423 and MCP3424
• Single Supply Operation: 2.7V to 5.5V
• Extended Temperature Range: -40°C to +125°C
The MCP3422, MCP3423 and MCP3424 devices
(MCP3422/3/4) are the low noise and high accuracy
18-Bit delta-sigma analog-to-digital (ΔΣ A/D) converter
family members of the MCP342X series from Microchip
Technology Inc. These devices can convert analog
inputs to digital codes with up to 18 bits of resolution.
Typical Applications
• Portable Instrumentation and Consumer Goods
• Temperature Sensing with RTD, Thermistor, and
Thermocouple
• Bridge Sensing for Pressure, Strain, and Force
• Weigh Scales
• Battery Fuel Gauges
• Factory Automation Equipment
© 2009 Microchip Technology Inc.
The on-board 2.048V reference voltage enables an
input range of ± 2.048V differentially (full scale
range = 4.096V/PGA).
These devices can output analog-to-digital conversion
results at rates of 3.75, 15, 60, or 240 samples per
second depending on the user controllable
configuration bit settings using the two-wire I2C serial
interface. During each conversion, the device
calibrates offset and gain errors automatically. This
provides accurate conversion results from conversion
to conversion over variations in temperature and power
supply fluctuation.
The user can select the PGA gain of x1, x2, x4, or x8
before the analog-to-digital conversion takes place.
This allows the MCP3422/3/4 devices to convert a very
weak input signal with high resolution.
The MCP3422/3/4 devices have two conversion
modes: (a) One-Shot Conversion mode and (b)
Continuous Conversion mode. In One-Shot conversion
mode, the device performs a single conversion and
enters a low current standby mode automatically until it
receives another conversion command. This reduces
current consumption greatly during idle periods. In
Continuous conversion mode, the conversion takes
place continuously at the set conversion speed. The
device updates its output buffer with the most recent
conversion data.
The devices operate from a single 2.7V to 5.5V power
supply and have a two-wire I2C compatible serial
interface for a standard (100 kHz), fast (400 kHz), or
high-speed (3.4 MHz) mode.
The I2C address bits for the MCP3423 and MCP3424
are selected by using two external I2C address
selection pins (Adr0 and Adr1). The user can configure
the device to one of eight available addresses by
connecting these two address selection pins to VDD,
VSS or float. The I2C address bits of the MCP3422 are
programmed at the factory during production.
DS22088C-page 1
MCP3422/3/4
The MCP3422 is available in 8-pin SOIC, DFN, and
MSOP packages. The MCP3423 is available in 10-pin
DFN, and MSOP packages. The MCP3424 is available
in 14-pin SOIC and TSSOP packages.
The MCP3422 and MCP3423 devices have two
differential input channels and the MCP3424 has fourdifferential input channels. All electrical properties of
these three devices are the same except the
differences in the number of input channels and I2C
address bit selection options.
Package Types
MCP3422
MSOP, SOIC
SDA 4
CH1+ 1
CH1- 2
8 CH27 CH2+
6 VSS
5 SCL
3
VSS
CH2+ 4
CH2- 5
MCP3422
2x3 DFN*
CH1+ 1
CH1- 2
VDD 3
EP
9
SDA 4
10 Adr1
9
Adr0
8 SCL
7 SDA
6 VDD
MCP3423
3x3 DFN*
8 CH2-
CH1+ 1
7 CH2+
CH1- 2
CH1+
CH1-
1
14
2
13
CH2+
CH2VSS
3
VDD
SDA
6
9
7
8
4
5
MCP3424
CH1- 2
VDD 3
MCP3423
MCP3422
CH1+ 1
MCP3424
SOIC, TSSOP
MCP3423
MSOP
12
11
10
CH4CH4+
CH3CH3+
Adr1
Adr0
SCL
10 Adr1
9 Adr0
EP
11
6 VSS
VSS 3
5 SCL
CH2+ 4
7 SDA
CH2- 5
6 VDD
8 SCL
* Includes Exposed Thermal Pad (EP); see Table 3-1.
Functional Block Diagram
VDD
VSS
MCP3422
Voltage Reference
(2.048V)
VREF
CH1+
MUX
CH1-
SCL
PGA
ΔΣ ADC
Converter
I2C
Interface
SDA
CH2+
CH2-
Gain = 1,2,4, or 8
Clock
Oscillator
DS22088C-page 2
© 2009 Microchip Technology Inc.
MCP3422/3/4
Functional Block Diagram
VSS
VDD
MCP3423
Adr1
Voltage Reference
(2.048V)
Adr0
VREF
CH1-
MUX
CH1+
ΔΣ ADC
Converter
PGA
I2C
SCL
Interface
SDA
CH2+
CH2-
Gain = 1,2,4, or 8
Clock
Oscillator
Functional Block Diagram
VSS
VDD
MCP3424
CH1+
Adr1
Voltage Reference
(2.048V)
CH1-
Adr0
VREF
CH2-
MUX
CH2+
PGA
ΔΣ ADC
Converter
CH3+
CH3CH4+
I2C
Interface
SCL
SDA
Gain = 1,2,4, or 8
Clock
Oscillator
CH4-
© 2009 Microchip Technology Inc.
DS22088C-page 3
MCP3422/3/4
NOTES:
DS22088C-page 4
© 2009 Microchip Technology Inc.
MCP3422/3/4
1.0
ELECTRICAL
CHARACTERISTICS
†Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
Absolute Maximum Ratings†
VDD...................................................................................7.0V
All inputs and outputs ............. ..........VSS –0.4V to VDD+0.4V
Differential Input Voltage ...................................... |VDD - VSS|
Output Short Circuit Current ................................ Continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±10 mA
Storage Temperature ....................................-65°C to +150°C
Ambient Temp. with power applied ...............-55°C to +125°C
ESD protection on all pins ................ ≥ 6 kV HBM, ≥ 400V MM
Maximum Junction Temperature (TJ). .........................+150°C
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V,
CHn+ = CHn- = VREF/2, VINCOM = VREF /2. All ppm units use 2*VREF as differential full scale range.
Parameters
Sym
Min
Typ
Max
Units
FSR
—
±2.048/PGA
—
V
Conditions
Analog Inputs
Differential Full Scale Input
Voltage Range
Maximum Input Voltage Range
VIN = [CHn+ - CHn-]
VSS-0.3
—
VDD+0.3
V
Differential Input Impedance
ZIND (f)
—
2.25/PGA
—
MΩ
During normal mode operation
(Note 2)
Common Mode input
Impedance
ZINC (f)
—
25
—
MΩ
PGA = 1, 2, 4, 8
12
—
—
Bits
DR = 240 SPS
14
—
—
Bits
DR = 60 SPS
16
—
—
Bits
DR = 15 SPS
DR = 3.75 SPS
(Note 1)
System Performance
Resolution and No Missing
Codes
(Effective Number of Bits)
(Note 3)
Data Rate
(Note 4)
18
—
—
Bits
176
240
328
SPS
12 bits mode
44
60
82
SPS
14 bits mode
11
15
20.5
SPS
16 bits mode
2.75
3.75
5.1
SPS
18 bits mode
—
1.5
—
µVRMS
TA = +25°C, DR = 3.75 SPS,
PGA = 1, VIN+ = VIN- = GND
INL
—
10
35
ppm of
FSR
DR = 3.75 SPS, FSR = Full
Scale Range (Note 5)
VREF
—
2.048
—
V
—
0.05
0.35
%
DR
Output Noise
Integral Non-Linearity
Internal Reference Voltage
Gain Error (Note 6)
PGA = 1, DR = 3.75 SPS
Note 1:
Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.
This parameter is ensured by characterization and not 100% tested.
2: This input impedance is due to 3.2 pF internal input sampling capacitor.
3: This parameter is ensured by design and not 100% tested.
4: The total conversion speed includes auto-calibration of offset and gain.
5: INL is the difference between the endpoints line and the measured code at the center of the quantization band.
6: Includes all errors from on-board PGA and VREF.
7: This parameter is ensured by characterization and not 100% tested.
8: MCP3423 and MCP3424 only.
9: Addr_Float voltage is applied at address pin.
10: No voltage is applied at address pin (left “floating”).
© 2009 Microchip Technology Inc.
DS22088C-page 5
MCP3422/3/4
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V,
CHn+ = CHn- = VREF/2, VINCOM = VREF /2. All ppm units use 2*VREF as differential full scale range.
Parameters
Sym
PGA Gain Error Match (Note 6)
Gain Error Drift (Note 6)
Offset Error
VOS
Min
Typ
Max
Units
—
0.1
—
%
—
15
—
ppm/°C
—
15
55
µV
Conditions
Between any 2 PGA settings
PGA=1, DR=3.75 SPS
Tested at PGA = 1
DR = 3.75 SPS
Offset Drift vs. Temperature
—
50
—
nV/°C
Common-Mode Rejection
—
105
—
dB
at DC and PGA =1,
—
110
—
dB
at DC and PGA =8, TA = +25°C
Gain vs. VDD
—
5
—
ppm/V
TA = +25°C, VDD = 2.7V to 5.5V,
PGA = 1
Power Supply Rejection at DC
Input
—
100
—
dB
TA = +25°C, VDD = 2.7V to 5.5V,
PGA = 1
Power Requirements
Voltage Range
VDD
2.7
—
5.5
V
Supply Current during
Conversion
IDDA
—
145
180
µA
VDD = 5.0V
—
135
—
µA
VDD = 3.0V
Supply Current during Standby
Mode
IDDS
—
0.3
1
µA
VDD = 5.0V
at SDA and SCL pins
I2C Digital Inputs and Digital Outputs
High level input voltage
VIH
0.7VDD
—
VDD
V
Low level input voltage
VIL
—
—
0.3VDD
V
at SDA and SCL pins
Low level output voltage
VOL
—
—
0.4
V
IOL = 3 mA
Hysteresis of Schmidt Trigger
for inputs (Note 7)
VHYST
0.05VDD
—
—
V
fSCL = 100 kHz
Supply Current when I2C bus
line is active
IDDB
—
—
10
µA
Device is in standby mode while
I2C bus is active
Input Leakage Current
IILH
—
—
1
µA
VIH = 5.5V
IILL
-1
—
—
µA
VIL = GND
Logic Status of I2C Address Pins (Note 8)
Adr0 and Adr1 Pins
Addr_Low
VSS
—
0.2VDD
V
The device reads logic low.
Adr0 and Adr1 Pins
Addr_High
0.75VDD
—
VDD
V
The device reads logic high.
Adr0 and Adr1 Pins
Addr_Float
0.35VDD
—
0.6VDD
V
Read pin voltage if voltage is
applied to the address pin.
(Note 9)
—
VDD/2
—
Device outputs float output
voltage (VDD/2) on the address
pin, if left “floating”. (Note 10)
Pin Capacitance and I2C Bus Capacitance
Pin capacitance
I2C Bus Capacitance
CPIN
—
4
10
pF
Cb
—
—
400
pF
Note 1:
Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.
This parameter is ensured by characterization and not 100% tested.
2: This input impedance is due to 3.2 pF internal input sampling capacitor.
3: This parameter is ensured by design and not 100% tested.
4: The total conversion speed includes auto-calibration of offset and gain.
5: INL is the difference between the endpoints line and the measured code at the center of the quantization band.
6: Includes all errors from on-board PGA and VREF.
7: This parameter is ensured by characterization and not 100% tested.
8: MCP3423 and MCP3424 only.
9: Addr_Float voltage is applied at address pin.
10: No voltage is applied at address pin (left “floating”).
DS22088C-page 6
© 2009 Microchip Technology Inc.
MCP3422/3/4
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 8L-DFN (2x3)
θJA
—
68
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
211
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
149.5
—
°C/W
Thermal Resistance, 10L-DFN (3x3)
θJA
—
53.3
—
°C/W
Thermal Resistance, 10L-MSOP
θJA
—
202
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
95.3
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistances
© 2009 Microchip Technology Inc.
DS22088C-page 7
MCP3422/3/4
NOTES:
DS22088C-page 8
© 2009 Microchip Technology Inc.
MCP3422/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, CHn+ = CHn- = VREF/2,
VINCOM = VREF/2.
8
TA = +25°C
0.003
0.0025
0.002
PGA = 4
PGA = 8
0.0015
PGA = 2
0.001
PGA = 1
0.0005
OutPut Noise (µV,rms)
Integral Non-Linearity
(% of FSR)
0.0035
0
2.5
3
3.5
4
4.5
5
TA = +25°C
7
PGA = 1
6
PGA = 8
5
PGA = 4
3
2
1
0
-100
5.5
-75
-50
VDD (V)
FIGURE 2-1:
(VDD).
INL vs. Supply Voltage
FIGURE 2-4:
Voltage.
25
0.0025
0.002
2.7V
0.0015
0.001
5V
0.0005
0
100
TA = +25°C
PGA = 8
1
0.5
0
-0.5
PGA = 4
PGA = 2
-1
20
40
60
-2
-100
80 100 120 140
-75
o
Temperature ( C)
FIGURE 2-2:
75
-1.5
5.5V
-60 -40 -20
50
Output Noise vs. Input
PGA = 1
1.5
Total Error (mV)
Integral Non-Linearity
(% of FSR)
0
2
PGA = 1
0
INL vs. Temperature.
-50 -25
0
25
50
75
Input Voltage (% of Full-Scale)
FIGURE 2-5:
100
Total Error vs. Input Voltage.
0.2
15
10
PGA = 8
5
PGA = 4
0
-5
-10
PGA = 2
-15
PGA = 1
-20
Gain Error (% of FSR)
20
Offset Error (µV)
-25
Input Signal (% of FSR)
0.0035
0.003
PGA = 2
4
0.1
PGA = 8
0
PGA = 1
-0.1
-0.2
-0.3
-0.4
PGA = 2
-0.5
PGA = 4
-0.6
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
Temperature (°C)
FIGURE 2-3:
Temperature.
Offset Error vs.
© 2009 Microchip Technology Inc.
FIGURE 2-6:
0
20 40 60 80 100 120 140
Temperature (°C)
Gain Error vs. Temperature.
DS22088C-page 9
MCP3422/3/4
Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, CHn+ = CHn- = VREF/2,
VINCOM = VREF/2.
200
3
V DD = 5.5V
IDDA (µA)
160
140
120
VDD = 2.7V
100
V DD = 5.0V
80
Oscillator Drift (%)
Data Rate = 3.75 SPS
180
60
2
1
0
-1
-2
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40 -20
0
Temperature (°C)
IDDA vs. Temperature.
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V DD = 5.5V
VDD = 5.0V
VDD = 2.7V
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
IDDS vs. Temperature.
FIGURE 2-8:
40
60
80
100 120 140
Temperature (°C)
FIGURE 2-10:
Temperature.
Magnitude (dB)
IDDS (µA)
FIGURE 2-7:
20
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
Oscillator Drift vs.
Data Rate = 3.75 SPS
0.1
0.1
1
1
10
10
100
100
1000
1k
10000
10k
Input Signal Frequency (Hz)
FIGURE 2-11:
Frequency Response.
14
12
VDD = 5.5V
V DD = 5.0V
IDDB (µA)
10
8
6
VDD = 4.5V
4
2
VDD = 2.7V
0
-60 -40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
FIGURE 2-9:
DS22088C-page 10
IDDB vs. Temperature.
© 2009 Microchip Technology Inc.
MCP3422/3/4
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP3422
MCP3423
MCP3424
MSOP,
SOIC
DFN
MSOP
SOIC,
TSSOP
Sym
DFN
1
1
1
1
1
CH1+
2
2
2
2
2
CH1-
Negative Differential Analog Input Pin of Channel 1
7
7
4
4
3
CH2+
Positive Differential Analog Input Pin of Channel 2
8
8
5
5
4
CH2-
Negative Differential Analog Input Pin of Channel 2
6
6
3
3
5
VSS
Ground Pin
3
3
6
6
6
VDD
Positive Supply Voltage Pin
4
4
7
7
7
SDA
Bidirectional Serial Data Pin of the I2C Interface
5
5
8
8
8
SCL
Serial Clock Pin of the I2C Interface
—
—
9
9
9
Adr0
I2C Address Selection Pin. See Section 5.3.2.
—
—
10
10
10
Adr1
I2C Address Selection Pin. See Section 5.3.2.
—
—
—
—
11
CH3+
Positive Differential Analog Input Pin of Channel 3
3.1
Description
Positive Differential Analog Input Pin of Channel 1
—
—
—
—
12
CH3-
Negative Differential Analog Input Pin of Channel 3
—
—
—
—
13
CH4+
Positive Differential Analog Input Pin of Channel 4
—
—
—
—
14
CH4-
Negative Differential Analog Input Pin of Channel 4
9
—
11
—
—
EP
Exposed Thermal Pad (EP); must be connected to
VSS.
Analog Inputs (CHn+, CHn-)
CHn+ and CHn- are differential input pins for
channel n. The user can also connect CHn- pin to VSS
for a single-ended operation. See Figure 6-4 for
differential and single-ended connection examples.
The maximum voltage range on each differential input
pin is from VSS-0.3V to VDD+0.3V. Any voltage below or
above this range will cause leakage currents through
the Electrostatic Discharge (ESD) diodes at the input
pins.
This ESD current can cause unexpected performance
of the device. The input voltage at the input pins should
be within the specified operating range defined in
Section 1.0 “Electrical Characteristics” and
Section 4.0 “Description of Device Operation”.
See Section 4.5 “Input Voltage Range” for more
details of the input voltage range.
3.2
Supply Voltage (VDD, VSS)
VDD is the power supply pin for the device. This pin
requires an appropriate bypass ceramic capacitor of
about 0.1 µF to ground to attenuate high frequency
noise presented in application circuit board. An
additional 10 µF capacitor (tantalum) in parallel is also
recommended to further attenuate current spike
noises. The supply voltage (VDD) must be maintained
in the 2.7V to 5.5V range for specified operation.
VSS is the ground pin and the current return path of the
device. The user must connect the VSS pin to a ground
plane through a low impedance connection. If an
analog ground path is available in the application PCB
(printed circuit board), it is highly recommended that
the VSS pin be tied to the analog ground path or
isolated within an analog ground plane of the circuit
board.
Figure 3-1 shows the input structure of the device. The
device uses a switched capacitor input stage at the
front end. CPIN is the package pin capacitance and
typically about 4 pF. D1 and D2 are the ESD diodes.
CSAMPLE is the differential input sampling capacitor.
© 2009 Microchip Technology Inc.
DS22088C-page 11
MCP3422/3/4
VDD
RSS
D1
VT = 0.6V
CPIN D
2
4 pF
VT = 0.6V
CHn
V
Sampling
Switch
SS
ILEAKAGE
(~ ±1 nA)
RS
CSAMPLE
(3.2 pF)
VSS
LEGEND
V
RSS
CHn
CPIN
VT
FIGURE 3-1:
3.3
=
=
=
=
=
Signal Source
Source Impedance
Analog Input Pin
Input Pin Capacitance
Threshold Voltage
ILEAKEAGE
SS
RS
CSAMPLE
D1, D2
=
=
=
=
=
Leakage Current at Analog Pin
Sampling Switch
Sampling Switch Resistor
Sample Capacitance
ESD Protection Diode
Equivalent Analog Input Circuit.
Serial Clock Pin (SCL)
SCL is the serial clock pin of the I2C interface. The
device act only as a slave and the SCL pin accepts
only external serial clocks. The input data from the
Master device is shifted into the SDA pin on the rising
edges of the SCL clock and output from the slave
device occurs at the falling edges of the SCL clock.
The SCL pin is an open-drain N-channel driver.
Therefore, it needs a pull-up resistor from the VDD line
to the SCL pin. Refer to Section 5.3 “I2C Serial Communications” for more details of I2C Serial Interface
communication.
3.4
Serial Data Pin (SDA)
SDA is the serial data pin of the I2C interface. The SDA
pin is used for input and output data. In read mode, the
conversion result is read from the SDA pin (output). In
write mode, the device configuration bits are written
(input) though the SDA pin. The SDA pin is an opendrain N-channel driver. Therefore, it needs a pull-up
resistor from the VDD line to the SDA pin. Except for
start and stop conditions, the data on the SDA pin must
be stable during the high period of the clock. The high
or low state of the SDA pin can only change when the
clock signal on the SCL pin is low. Refer to Section 5.3
“I2C Serial Communications” for more details of I2C
Serial Interface communication.
Typical range of the pull-up resistor value for SCL and
SDA is from 5 kΩ to 10 kΩ for standard (100 kHz) and
fast (400 kHz) modes, and less than 1 kΩ for high
speed mode (3.4 MHz).
3.5
Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
DS22088C-page 12
© 2009 Microchip Technology Inc.
MCP3422/3/4
4.0
DESCRIPTION OF DEVICE
OPERATION
4.1
General Overview
The MCP3422/3/4 devices are differential multichannel low-power, 18-Bit Delta-Sigma A/D converters
with an I2C serial interface. The devices contain an
input channel selection multiplexer (mux), a
programmable gain amplifier (PGA), an on-board
voltage reference (2.048V), and an internal oscillator.
When the device powers up (POR is set), it
automatically resets the configuration bits to default
settings.
Device default settings are:
•
•
•
•
Conversion bit resolution: 12 bits (240 sps)
Input channel: Channel 1
PGA gain setting: x1
Continuous conversion
Once the device is powered-up, the user can
reprogram the configuration bits using I2C serial
interface any time. The configuration bits are stored in
volatile memory.
The threshold voltage is set at 2.2V with a tolerance of
approximately ±5%. If the supply voltage falls below
this threshold, the device will be held in a reset
condition. The typical hysteresis value is approximately
200 mV.
The POR circuit is shut-down during the low-power
standby mode. Once a power-up event has occurred,
the
device
requires
additional
delay
time
(approximately 300 µs) before a conversion takes
place. During this time, all internal analog circuitries are
settled before the first conversion occurs. Figure 4-1
illustrates the conditions for power-up and power-down
events under typical start-up conditions.
VDD
2.2V
2.0V
300 µS
Time
Reset Start-up
FIGURE 4-1:
4.3
User selectable options are:
•
•
•
•
Conversion bit resolution: 12, 14, 16, or 18 bits
Input channel selection: CH1, CH2, CH3, or CH4.
PGA Gain selection: x1, x2, x4, or x8
Continuous or one-shot conversion
In the Continuous Conversion mode, the device
converts the inputs continuously. While in the One-Shot
Conversion mode, the device converts the input one
time and stays in the low-power standby mode until it
receives another command for a new conversion.
During the standby mode, the device consumes less
than 1 µA maximum.
4.2
Power-On-Reset (POR)
The device contains an internal Power-On-Reset
(POR) circuit that monitors power supply voltage (VDD)
during operation. This circuit ensures correct device
start-up at system power-up and power-down events.
The device resets all configuration register bits to
default settings as soon as the POR is set.
Normal Operation
Reset
POR Operation.
Internal Voltage Reference
The device contains an on-board 2.048V voltage
reference. This reference voltage is for internal use
only and not directly measurable. The specification of
the reference voltage is part of the device’s gain and
drift specifications. Therefore, there is no separate
specification for the on-board reference.
4.4
Analog Input Channels
The user can select the input channel using the
configuration register bits. Each channel can be used
for differential or single-ended input.
Each input channel has a switched capacitor input
structure. The internal sampling capacitor (3.2 pF for
PGA = 1) is charged and discharged to process a
conversion. The charging and discharging of the input
sampling capacitor creates dynamic input currents at
each input pin. The current is a function of the
differential input voltages, and inversely proportional to
the internal sampling capacitance, sampling frequency,
and PGA setting.
The POR has built-in hysteresis and a timer to give a
high degree of immunity to potential ripples and noises
on the power supply. A 0.1 µF decoupling capacitor
should be mounted as close as possible to the VDD pin
for additional transient immunity.
© 2009 Microchip Technology Inc.
DS22088C-page 13
MCP3422/3/4
4.5
Input Voltage Range
The differential (VIN) and common mode voltage
(VINCOM) at the input pins without considering PGA
setting are defined by:
V IN = ( CHn+ ) – ( CHn- )
CHn+ ) + ( CHn- )V INCOM = (---------------------------------------------2
4.6
Input Impedance
The device uses a switched-capacitor input stage using
a 3.2 pF sampling capacitor. This capacitor is switched
(charged and discharged) at a rate of the sampling
frequency that is generated by on-board clock. The
differential input impedance varies with the PGA
settings. The typical differential input impedance during
a normal mode operation is given by:
Where:
n
=
The input signal levels are amplified by the internal
programmable gain amplifier (PGA) at the front end of
the ΔΣ modulator.
The user needs to consider two conditions for the input
voltage range: (a) Differential input voltage range and
(b) Absolute maximum input voltage range.
4.5.1
DIFFERENTIAL INPUT VOLTAGE
RANGE
The device performs conversions using its internal
reference voltage (VREF = 2.048V). Therefore, the
absolute value of the differential input voltage (VIN),
with PGA setting is included, needs to be less than the
internal reference voltage. The device will output saturated output codes (all 0s or all 1s except sign bit) if the
absolute value of the input voltage (VIN), with PGA
setting is included, is greater than the internal
reference voltage (VREF = 2.048V). The input full scale
voltage range is given by:
EQUATION 4-1:
– V REF ≤ ( V IN • PGA ) ≤ ( V REF – 1LSB )
Where:
VIN
=
CHn+ - CHn-
VREF
=
2.048V
If the input voltage level is greater than the above limit,
the user can use a voltage divider and bring down the
input level within the full scale range. See Figure 6-7 for
more details of the input voltage divider circuit.
4.5.2
ZIN(f) = 2.25 MΩ/PGA
nth input channel (n=1, 2, 3, or 4)
ABSOLUTE MAXIMUM INPUT
VOLTAGE RANGE
The input voltage at each input pin must be less than
the following absolute maximum input voltage limits:
Since the sampling capacitor is only switching to the
input pins during a conversion process, the above input
impedance is only valid during conversion periods. In a
low power standby mode, the above impedance is not
presented at the input pins. Therefore, only a leakage
current due to ESD diode is presented at the input pins.
The conversion accuracy can be affected by the input
signal source impedance when any external circuit is
connected to the input pins. The source impedance
adds to the internal impedance and directly affects the
time required to charge the internal sampling capacitor.
Therefore, a large input source impedance connected
to the input pins can degrade the system performance,
such as offset, gain, and Integral Non-Linearity (INL)
errors. Ideally, the input source impedance should be
zero. This can be achievable by using an operational
amplifier with a closed-loop output impedance of tens
of ohms.
4.7
Aliasing and Anti-aliasing Filter
Aliasing occurs when the input signal contains timevarying signal components with frequency greater than
half the sample rate. In the aliasing conditions, the
device can output unexpected output codes. For
applications that are operating in electrical noise
environments, the time-varying signal noise or high
frequency interference components can be easily
added to the input signals and cause aliasing. Although
the device has an internal first order sinc filter, the filter
response (Figure 2-11) may not give enough
attenuation to all aliasing signal components. To avoid
the aliasing, an external anti-aliasing filter, which can
be accomplished with a simple RC low-pass filter, is
typically used at the input pins. The low-pass filter cuts
off the high frequency noise components and provides
a band-limited input signal to the input pins.
• Input voltage < VDD+0.3V
• Input voltage > VSS-0.3V
4.8
Any input voltage outside this range can turn on the
input ESD protection diodes, and result in input
leakage current, causing conversion errors, or
permanently damage the device.
The device performs a self-calibration of offset and
gain for each conversion. This provides reliable
conversion results from conversion-to-conversion over
variations in temperature as well as power supply
fluctuations.
Care must be taken in setting the input voltage ranges
so that the input voltage does not exceed the absolute
maximum input voltage range.
DS22088C-page 14
Self-Calibration
© 2009 Microchip Technology Inc.
MCP3422/3/4
4.9
Digital Output Codes and
Conversion to Real Values
4.9.1
DIGITAL OUTPUT CODE FROM
DEVICE
The digital output code is proportional to the input
voltage and PGA settings. The output data format is a
binary two’s complement. With this code scheme, the
MSB can be considered a sign indicator. When the
MSB is a logic ‘0’, the input is positive. When the MSB
is a logic ‘1’, the input is negative. The following is an
example of the output code:
a.
b.
TABLE 4-1:
RESOLUTION SETTINGS VS.
LSB
Resolution Setting
LSB
12 bits
1 mV
14 bits
250 µV
for a negative full scale input voltage: 100...000
16 bits
62.5 µV
Example: (CHn+ - CHn-) •PGA = -2.048V
18 bits
15.625 µV
for a zero differential input voltage: 000...000
Example: (CHn+ - CHn-) = 0
c.
Table 4-1 shows the LSB size of each conversion rate
setting. The measured unknown input voltage is
obtained by multiplying the output codes with LSB. See
the following section for the input voltage calculation
using the output codes.
for a positive full scale input voltage: 011...111
Example: (CHn+ - CHn-) • PGA = 2.048V
The MSB (sign bit) is always transmitted first through
the I2C serial data line. The resolution for each
conversion is 18, 16, 14, or 12 bits depending on the
conversion rate selection bit settings by the user.
The output codes will not roll-over even if the input
voltage exceeds the maximum input range. In this
case, the code will be locked at 0111...11 for all
voltages greater than (VREF - 1 LSB)/PGA and
1000...00 for voltages less than -VREF/PGA.
Table 4-2 shows an example of output codes of various
input levels for 18 bit conversion mode. Table 4-3
shows an example of minimum and maximum output
codes for each conversion rate option.
TABLE 4-2: EXAMPLE OF OUTPUT CODE
FOR 18 BITS (NOTE 1, NOTE 2)
Input Voltage:
[CHn+ - CHn-] • PGA
Digital Output Code
≥ VREF
011111111111111111
VREF - 1 LSB
011111111111111111
2 LSB
000000000000000010
1 LSB
000000000000000001
0
000000000000000000
-1 LSB
111111111111111111
-2 LSB
111111111111111110
- VREF
100000000000000000
< -VREF
100000000000000000
Note 1:
The number of output code is given by:
2:
EQUATION 4-2:
Number of Output Code =
( CHn+ – CHn- )
= ( Maximum Code + 1 ) × PGA × ----------------------------------------2.048V
Where:
See Table 4-3 for Maximum Code
The LSB of the data conversion is given by:
EQUATION 4-3:
Where:
N
2 × V REF
2 × 2.048V
LSB = --------------------- = -------------------------N
N
2
2
=
MSB is a sign indicator:
0: Positive input (CHn+ > CHn-)
1: Negative input (CHn+ < CHn-)
Output data format is binary two’s
complement.
TABLE 4-3:
MINIMUM AND MAXIMUM
OUTPUT CODES (NOTE)
Resolution
Setting
Data Rate
Minimum
Code
Maximum
Code
12
240 SPS
-2048
2047
14
60 SPS
-8192
8191
16
15 SPS
-32768
32767
18
3.75 SPS
-131072
131071
Note:
Maximum n-bit code = 2N-1 - 1
Minimum n-bit code = -1 x 2N-1
Resolution, which is programmed in
the Configuration Register.
© 2009 Microchip Technology Inc.
DS22088C-page 15
MCP3422/3/4
4.9.2
CONVERTING THE DEVICE
OUTPUT CODE TO INPUT SIGNAL
VOLTAGE
EQUATION 4-4:
CONVERTING OUTPUT
CODES TO INPUT
VOLTAGE
When the user gets the digital output codes from the
device as described in Section 4.9.1 “Digital output
code from device”, the next step is converting the
digital output codes to a measured input voltage.
Equation 4-4 shows an example of converting the
output codes to its corresponding input voltage.
If MSB = 0 (Positive Output Code):
If the sign indicator bit (MSB) is ‘0’, the input voltage
is obtained by multiplying the output code with the LSB
and divided by the PGA setting.
Where:
If the sign indicator bit (MSB) is ‘1’, the output code
needs to be converted to two’s complement before
multiplied by LSB and divided by the PGA setting.
Table 4-4 shows an example of converting the device
output codes to input voltage.
TABLE 4-4:
LSB
Input Voltage = (Output Code) • -----------PGA
If MSB = 1 (Negative Output Code):
LSB
Input Voltage = (2 ′ s complement of Output Code) • -----------PGA
LSB
=
See Table 4-1
2’s complement
=
1’s complement + 1
EXAMPLE OF CONVERTING OUTPUT CODE TO VOLTAGE (WITH 18 BIT SETTING)
Input Voltage
[CHn+ - CHn-] • PGA]
Digital Output Code
MSB
≥ VREF
011111111111111111
0
(216+215+214+213+212+211+210+29+28+27+26+25+24+23+22+21+20)
x LSB(15.625μV)/PGA = 2.048 (V) for PGA = 1
VREF - 1 LSB
011111111111111111
0
(216+215+214+213+212+211+210+29+28+27+26+25+24+23+22+21+20)
x LSB(15.625μV)/PGA = 2.048 (V) for PGA = 1
2 LSB
000000000000000010
0
(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+21+0)x LSB(15.625μV)/PGA
= 31.25 (μV) for PGA = 1
1 LSB
000000000000000001
0
(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+20)x LSB(15.625μV)/PGA
= 15.625 (μV)for PGA = 1
0
000000000000000000
0
(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0)x LSB(15.625μV)/PGA
= 0 V (V) for PGA = 1
-1 LSB
111111111111111111
1
-(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+20)x LSB(15.625μV)/PGA
= - 15.625 (μV)for PGA = 1
-2 LSB
111111111111111110
1
-(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+21+0)x LSB(15.625μV)/PGA
= - 31.25 (μV)for PGA = 1
- VREF
100000000000000000
1
-(217+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0) x
LSB(15.625μV)/PGA = - 2.048 (V) for PGA = 1
≤ -VREF
100000000000000000
1
-(217+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0) x
LSB(15.625μV)/PGA = - 2.048 (V) for PGA = 1
DS22088C-page 16
Example of Converting Output Codes to Input Voltage
© 2009 Microchip Technology Inc.
MCP3422/3/4
5.0
5.1
USING THE DEVICES
Operating Modes
The user operates the device by setting up the device
configuration register using a write command
(see Figure 5-3) and reads the conversion data using a
read command (see Figure 5-4 and Figure 5-5).
The device operates in two modes: (a) Continuous
Conversion Mode or (b) One-Shot Conversion Mode
(single conversion). This mode selection is made by
setting the O/C bit in the Configuration Register. Refer
to Section 5.2 “Configuration Register” for more
information.
5.1.1
CONTINUOUS CONVERSION
MODE (O/C BIT = 1)
The device performs a Continuous Conversion if the O/
C bit is set to logic “high”. Once the conversion is
completed, RDY bit is toggled to ‘0’ and the result is
placed at the output data register. The device
immediately begins another conversion and overwrites
the output data register with the most recent result. The
device clears the data ready flag (RDY bit = 0) when
the conversion is completed. The device sets the ready
flag bit (RDY bit = 1), if the latest conversion result has
been read by the Master.
• When writing configuration register:
- Setting RDY bit in continuous mode does not
affect anything
• When reading conversion data:
- RDY bit = 0 means the latest conversion
result is ready
- RDY bit = 1 means the conversion result is
not updated since the last reading. A new
conversion is under processing and the RDY
bit will be cleared when the new conversion
result is ready
© 2009 Microchip Technology Inc.
5.1.2
ONE-SHOT CONVERSION MODE
(O/C BIT = 0)
Once the One-Shot Conversion Mode (single conversion) is selected, the device performs only one
conversion, updates the output data register, clears the
data ready flag (RDY = 0), and then enters a low power
standby mode. A new One-Shot Conversion is started
again when the device receives a new write command
with RDY = 1.
• When writing configuration register:
- The RDY bit needs to be set to begin a new
conversion in one-shot mode
• When reading conversion data:
- RDY bit = 0 means the latest conversion
result is ready
- RDY bit = 1 means the conversion result is
not updated since the last reading. A new
conversion is under processing and the RDY
bit will be cleared when the new conversion is
done
This One-Shot Conversion Mode is highly
recommended for low power operating applications
where the conversion result is needed by request on
demand. During the low current standby mode, the
device consumes less than 1 µA maximum (or 300 nA
typical). For example, if the user collects 18 bit
conversion data once a second in One-Shot
Conversion mode, the device draws only about one
fourth of its total operating current. In this example, the
device consumes approximately 36 µA (135 µA /
3.75 SPS = 36 µA), if the device performs only one
conversion per second (1 SPS) in 18-bit conversion
mode with 3V power supply.
DS22088C-page 17
MCP3422/3/4
5.2
Configuration Register
The user can rewrite the configuration byte any time
during the device operation. Register 5-1 shows the
configuration register bits.
The device has an 8-bit wide configuration register to
select for: input channel, conversion mode, conversion
rate, and PGA gain. This register allows the user to
change the operating condition of the device and check
the status of the device operation.
REGISTER 5-1:
CONFIGURATION REGISTER
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
RDY
C1
C0
O/C
S1
S0
G1
G0
1*
0*
0*
1*
0*
0*
0*
0*
bit 7
bit 0
* Default Configuration after Power-On Reset
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
x = Bit is unknown
RDY: Ready Bit
This bit is the data ready flag. In read mode, this bit indicates if the output register has been updated
with a latest conversion result. In One-Shot Conversion mode, writing this bit to “1” initiates a new
conversion.
Reading RDY bit with the read command:
1 = Output register has not been updated
0 = Output register has been updated with the latest conversion result
Writing RDY bit with the write command:
Continuous Conversion mode: No effect
One-Shot Conversion mode:
1 = Initiate a new conversion
0 = No effect
bit 6-5
C1-C0: Channel Selection Bits
00 = Select Channel 1 (Default)
01 = Select Channel 2
10 = Select Channel 3 (MCP3424 only, treated as “00” by the MCP3422/MCP3423)
11 = Select Channel 4 (MCP3424 only, treated as “01” by the MCP3422/MCP3423)
bit 4
O/C: Conversion Mode Bit
1 = Continuous Conversion Mode (Default). The device performs data conversions continuously
0 = One-Shot Conversion Mode. The device performs a single conversion and enters a low power
standby mode until it receives another write or read command
bit 3-2
S1-S0: Sample Rate Selection Bit
00 = 240 SPS (12 bits) (Default)
01 = 60 SPS (14 bits)
10 = 15 SPS (16 bits)
11 = 3.75 SPS (18 bits)
bit 1-0
G1-G0: PGA Gain Selection Bits
00 = x1 (Default)
01 = x2
10 = x4
11 = x8
DS22088C-page 18
© 2009 Microchip Technology Inc.
MCP3422/3/4
If the configuration byte is read repeatedly by clocking
continuously after reading the data bytes (i.e., after the
5th byte in the 18-bit conversion mode), the state of the
RDY bit indicates whether the device is ready with new
conversion result. When the Master finds the RDY bit is
cleared, it can send a not-acknowledge (NAK) bit and
a stop bit to exit the current read operation and send a
new read command for the latest conversion data.
Once the conversion data has been read, the ready bit
toggles to ‘1’ until the next new conversion data is
ready. The conversion data in the output register is
overwritten every time a new conversion is completed.
Figure 5-4 and Figure 5-5 show the examples of
reading the conversion data. The user can rewrite the
configuration byte any time for a new setting. Table 5-1
and Table 5-2 show the examples of the configuration
bit operation.
TABLE 5-1:
WRITE CONFIGURATION BITS
R/W O/C RDY
0
0
Operation
No effect if all other bits remain
the same - operation continues
with the previous settings.
0
0
0
1
Initiate One-Shot Conversion.
0
1
0
Initiate Continuous Conversion.
0
1
1
Initiate Continuous Conversion.
TABLE 5-2:
READ CONFIGURATION BITS
R/W O/C RDY
Operation
1
0
0
New conversion result in
One-Shot conversion mode has
just been read. The RDY bit
remains low until set by a new
write command.
1
0
1
One-Shot Conversion is in
progress. The conversion result
is not updated yet. The RDY bit
stays high until the current
conversion is completed.
1
1
0
New conversion result in
Continuous Conversion mode
has just been read. The RDY bit
changes to high after reading the
conversion data.
1
1
1
The conversion result in
Continuous Conversion mode
was already read. The next new
conversion data is not ready. The
RDY bit stays high until a new
conversion is completed.
© 2009 Microchip Technology Inc.
5.3
I2C Serial Communications
The
device
communicates
with
Master
(microcontroller) through a serial I2C (Inter-Integrated
Circuit) interface and support standard (100 kbits/sec),
fast (400 kbits/sec) and high-speed (3.4 Mbits/sec)
modes. The serial I2C is a bidirectional 2-wire data bus
communication protocol using open-drain SCL and
SDA lines.
The device can only be addressed as a slave. Once
addressed, it can receive configuration bits with a write
command or transmit the latest conversion results with
a read command. The serial clock pin (SCL) is an input
only and the serial data pin (SDA) is bidirectional. The
Master starts communication by sending a START bit
and terminates the communication by sending a STOP
bit. In read mode, the device releases the SDA line
after receiving NAK and STOP bits.
An example of a hardware connection diagram is
shown in Figure 6-1. More details of the I2C bus
characteristic is described in Section 5.6 “I2C Bus
Characteristics”.
5.3.1
I2C DEVICE ADDRESSING
The first byte after the START bit is always the address
byte of the device, which includes the device code
(4 bits), address bits (3 bits), and R/W bit. The device
code for the devices is 1101, which is programmed at
the factory. The I2C address bits (A2, A1, A0 bits) for
the MCP3423 and MCP3424 are user configurable and
determined by the logic status of the two external
address selection pins on the user’s application board
(Adr0 and Adr1 pins). The Master must know the Adr0
and Adr1 pin conditions before sending read or write
command. Figure 5-1 shows the details of the address
byte.
The three I2C address bits allow up to eight devices on
the same I2C bus line. The (R/W) bit determines if the
Master device wants to read the conversion data or
write to the Configuration register. If the (R/W) bit is set
(read mode), the device outputs the conversion data in
the following clocks. If the (R/W) bit is cleared (write
mode), the device expects a configuration byte in the
following clocks. When the device receives the correct
address byte, it outputs an acknowledge bit after the R/
W bit.
Figure 5-1 shows the address byte. Figure 5-3 through
Figure 5-5 show how to write the configuration register
bits and read the conversion results.
DS22088C-page 19
MCP3422/3/4
Acknowledge bit
Start bit
Read/Write bit
R/W ACK
Address
It is recommended to issue a General Call Reset or
General Call Latch command once after the device
has powered up. This will ensure that the device reads
the address pins in a stable condition, and avoid
latching the address bits while the power supply is
ramping up. This might cause inaccurate address pin
detection.
Address Byte
When the address pin is left “floating”:
Address Byte:
Device Code
Address Bits (Note 1)
1
Note 1:
2:
1
1
A2
A1
A0
MCP3423 and MCP3424: Configured by
the user. See Table 5-3 for address bit
configurations.
MCP3422: Programmed at the factory
during production.
FIGURE 5-1:
5.3.2
0
Address Byte.
DEVICE ADDRESS BITS (A2, A1, A0)
AND ADDRESS SELECTION PINS
(MCP3423 AND MCP3424)
The MCP3423 and MCP3424 have two external
device address pins (Adr1, Adr0). These pins can be
set to a logic high (or tied to VDD), low (or tied to VSS),
or left floating (not connected to anything, or tied to
VDD/2), These combinations of logic level using the
two pins allow eight possible addresses. Table 5-3
shows the device address depending on the logic
status of the address selection pins.
When the address pin is left “floating”, the address pin
momentarily outputs a short pulse with an amplitude of
about VDD/2 during the latch event. The device also
latches this pin voltage at the same time.
If the “floating” pin is connected to a large parasitic
capacitance (>20 pF) or to a long PCB trace, this short
floating voltage output can be altered. As a result, the
device may not latch the pin correctly.
It is strongly recommended to keep the “floating” pin
pad as short as possible in the customer application
PCB and minimize the parasitic capacitance to the pin
as small as possible (< 20 pF).
Figure 5-2 shows an example of the Latch voltage
output at the address pin when the address pin is left
“floating”. The waveform at the Adr0 pin is captured by
using an oscilloscope probe with 15 pF of capacitance.
The device latches the floating condition immediately
after the General Call Latch command.
Float waveform (output)
at address pin
The device samples the logic status of the Adr0 and
Adr1 pins in the following events:
SCL
a.
b.
SDA
c.
Device power-up.
General Call Reset
(See Section 5.4 “General Call”).
General Call Latch
(See Section 5.4 “General Call”).
The device samples the logic status (address pins)
during the above events, and latches the values until a
new latch event occurs. During normal operation (after
the address pins are latched), the address pins are
internally disabled from the rests of the internal circuit.
DS22088C-page 20
FIGURE 5-2:
General Call Latch
Command and Voltage Output at Address Pin
Left “Floating” (MCP3423 and MCP3424).
© 2009 Microchip Technology Inc.
MCP3422/3/4
TABLE 5-3:
I2C Device
Address Bits
A2
A1
A0
Adr1 Pin
0
0
0
0 (Addr_Low)
0 (Addr_Low)
0
0
1
0 (Addr_Low)
Float
0
1
0
0 (Addr_Low)
1 (Addr_High)
1
0
0
1 (Addr_High)
0 (Addr_Low)
1
0
1
1 (Addr_High)
Float
1
1
0
1 (Addr_High)
1 (Addr_High)
0
1
1
Float
0 (Addr_Low)
1
1
1
Float
1 (Addr_High)
0
0
0
Float
Float
2:
3:
WRITING A CONFIGURATION BYTE
TO THE DEVICE
When the Master sends an address byte with the R/W
bit low (R/W = 0), the device expects one configuration
byte following the address. Any byte sent after this
second byte will be ignored. The user can change the
operating mode of the device by writing the
configuration register bits.
Logic Status of Address
Selection Pins
Adr0 Pin
Note 1:
5.3.3
ADDRESS BITS VS. ADDRESS
SELECTION PINS FOR
(MCP3423 AND MCP3424
ONLY) (NOTES 1, 2, 3)
If the device receives a write command with a new
configuration setting, the device immediately begins a
new conversion and updates the conversion data.
Float: (a) Leave pin without connecting to
anything (left floating), or (b) apply
Addr_Float voltage.
The user can tie the pins to VSS or VDD:
- Tie to VSS for Addr_Low
- Tie to VDD for Addr_High
See Addr_Low, Addr_High, and
Addr_Float parameters in Electrical
Characteristics Table.
1
9
1
9
SCL
1
SDA
1
0
Start Bit by
Master
1
A2 A1 A0
R/W
ACK by
MCP3422/3/4
C1 C0
S1 S0 G1 G0
O/C
ACK by
MCP3422/3/4
Stop Bit by
Master
RDY
(a) One-Shot Mode: 1
(b) Continuous Mode: not effected
1st Byte:
Address Byte
with Write command
Note:
2nd Byte:
Configuration Byte
– Stop bit can be issued any time during writing.
– MCP3422/3/4 device code is 1101 (programmed at the factory).
– See Figure 5-1 for details in Address Byte.
FIGURE 5-3:
Timing Diagram For Writing To The MCP3422/3/4.
© 2009 Microchip Technology Inc.
DS22088C-page 21
MCP3422/3/4
5.3.4
READING OUTPUT CODES AND
CONFIGURATION BYTE FROM THE
DEVICE
When the Master sends a read command (R/W = 1),
the device outputs both the conversion data and
configuration bytes. Each byte consists of 8 bits with
one acknowledge (ACK) bit. The ACK bit after the
address byte is issued by the device and the ACK bits
after each conversion data bytes are issued by the
Master.
When the device is configured for 18-bit conversion
mode, it outputs three data bytes followed by a
configuration byte. The first 6 data bits in the first data
byte are repeated MSB (= sign bit) of the conversion
data. The user can ignore the first 6 data bits, and take
the 7th data bit (D17) as the MSB of the conversion
data. The LSB of the 3rd data byte is the LSB of the
conversion data (D0).
The configuration byte follows the output data bytes.
The device repeatedly outputs the configuration byte
only if the Master sends clocks repeatedly after the
data bytes.
The device terminates the current outputs when it
receives a Not-Acknowledge (NAK), a repeated start or
a stop bit at any time during the output bit stream. It is
not required to read the configuration byte. However,
the Master may read the configuration byte to check
the RDY bit condition.The Master may continuously
send clock (SCL) to repeatedly read the configuration
byte (to check the RDY bit status).
Figures 5-4 and 5-5 show the timing diagrams of the
reading.
If the device is configured for 12, 14, or 16 bit-mode, the
device outputs two data bytes followed by a
configuration byte. In 16 bit-conversion mode, the MSB
(= sign bit) of the first data byte is D15. In 14-bit
conversion mode, the first two bits in the first data byte
are repeated MSB bits and can be ignored, and the 3rd
bit (D13) is the MSB (=sign bit) of the conversion data.
In 12-bit conversion mode, the first four bits are
repeated MSB bits and can be ignored. The 5th bit
(D11) of the byte represents the MSB (= sign bit) of the
conversion data. Table 5-3 summarizes the conversion
data output of each conversion mode.
TABLE 5-3:
OUTPUT CODES OF EACH RESOLUTION OPTION
Conversion
Option
Digital Output Codes
18-bits
MMMMMMD17D16 (1st data byte) - D15 ~ D8 (2nd data byte) - D7 ~ D0 (3rd data byte) - Configuration
byte. (Note 1)
16-bits
D15 ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 2)
14-bits
MMD13D ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 3)
12-bits
MMMMD11 ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 4)
Note 1: D17 is MSB (= sign bit), M is repeated MSB of the data byte.
2: D15 is MSB (= sign bit).
3: D13 is MSB (= sign bit), M is repeated MSB of the data byte.
4: D11 is MSB (= sign bit), M is repeated MSB of the data byte.
DS22088C-page 22
© 2009 Microchip Technology Inc.
FIGURE 5-4:
© 2009 Microchip Technology Inc.
Note:
Start Bit by
Master
SDA
SCL
1
0
R/W
1 A2 A1 A0
9
1
RDY
C
1
3rd Byte
Middle Data Byte
D D D D D D D
15 14 13 12 11 10 9
1
9
D
7
1
O/C
S
1
D
6
D D
4 3
(Optional)
D
2
D
1
S
0
G
1
NAK by
Master
G
0
9
1
ACK by
Master
D
0
9
Stop Bit by
Master
4th Byte
Lower Data Byte
D
5
Nth Repeated Byte:
Configuration Byte
C
0
ACK by
Master
D
8
– MCP3422/3/4 device code is 1101.
– See Figure 5-1 for details in Address Byte.
– Stop bit or NAK bit can be issued any time during reading.
– Data bits on clocks 1 - 6th in 2nd byte are repeated MSB and can be ignored.
– Configuration byte repeats as long as clock is provided after the 5th byte.
2nd Byte
Upper Data Byte
(Data on Clocks 1-6th
can be ignored)
9
ACK by
Master
Repeat of D17 (MSB) D D
17 16
1
ACK by
MCP3422/3/4
1st Byte
MCP3422/3/4 Address Byte
1
1
C
0
O/C
S
1
S
0
G G
1 0
To continue: ACK by Master
To end: NAK by Master
(Optional)
5th Byte
Configuration Byte
RDY
C
1
9
MCP3422/3/4
Timing Diagram For Reading From The MCP3422/3/4 With 18-Bit Mode.
DS22088C-page 23
FIGURE 5-5:
DS22088C-page 24
Note:
Start Bit by
Master
SDA
SCL
0
1
R/W
A2 A1 A0
1st Byte
MCP3422/3/4 Address Byte
1
D
15
1
D
12
D
11
D
10
2nd Byte
Upper Data Byte
D D
14 13
ACK by
MCP3422/3/4
9
D
9
D
8
D
7
1
1
ACK by
Master
9
RDY
C
1
D
6
– MCP3422/3/4 device code is 1101.
– See Figure 5-1 for details in Address Byte.
– Stop bit or NAK bit can be issued any time during reading.
– In 14 - bit mode: D15 and D14 are repeated MSB and can be ignored.
– In 12 - bit mode: D15 - D12 are repeated MSB and can be ignored.
– Configuration byte repeats as long as clock is provided after the 4th byte.
1
1
D
4
D
3
D
2
O/C
S
1
S
0
(Optional)
G
0
D
0
9
1
RDY
C
1
Stop Bit by
Master
ACK by
Master
NAK by
Master
D
1
G
1
Nth Repeated Byte:
Configuration Byte
C
0
3rd Byte
Lower Data Byte
D
5
9
C
0
S
0
G
1
G
0
To continue: ACK by Master
To end: NAK by Master
(Optional)
4th Byte
Configuration Byte
O/C
S
1
9
MCP3422/3/4
Timing Diagram For Reading From The MCP3422/3/4 With 12-Bit to 16-Bit Modes.
© 2009 Microchip Technology Inc.
MCP3422/3/4
5.4
General Call
5.5
The device acknowledges the general call address
(0x00 in the first byte). The meaning of the general call
address is always specified in the second byte. Refer
to Figure 5-6. The device supports the following three
general calls.
For more information on the general call, or other I2C
modes, please refer to the Phillips I2C specification.
5.4.1
GENERAL CALL RESET
The general call reset occurs if the second byte is
‘00000110’ (06h). At the acknowledgement of this
byte, the device will abort current conversion and
perform the following tasks:
(a) Internal reset similar to a Power-On-Reset (POR).
All configuration and data register bits are reset to
default values.
(b) Latch the logic status of external address selection
pins (Adr0 and Adr1 pins).
5.4.2
GENERAL CALL LATCH (MCP3423
AND MCP3424)
The general call latch occurs if the second byte is
‘00000100’ (04h). The device will latch the logic
status of the external address selection pins (Adr0 and
Adr1 pins), but will not perform a reset.
5.4.3
GENERAL CALL CONVERSION
The general call conversion occurs if the second byte
is ‘00001000’ (08h). All devices on the bus initiate a
conversion simultaneously. When the device receives
this command, the configuration will be set to the OneShot Conversion mode and a single conversion will be
performed. The PGA and data rate settings are
unchanged with this general call.
START
LSB STOP
S 0 0 0 0 0 0 0 0 A X X X X X X X X A S
ACK
First Byte
(General Call Address)
Note:
Second Byte
ACK
The I2C specification does not allow
‘00000000’ (00h) in the second byte.
FIGURE 5-6:
Format.
General Call Address
© 2009 Microchip Technology Inc.
High-Speed (HS) Mode
The I2C specification requires that a high-speed mode
device must be ‘activated’ to operate in high-speed
mode. This is done by sending a special address byte
of “00001XXX” following the START bit. The “XXX” bits
are unique to the High-Speed (HS) mode Master. This
byte is referred to as the High-Speed (HS) Master
Mode Code (HSMMC). The MCP3422/3/4 devices do
not acknowledge this byte. However, upon receiving
this code, the device switches on its HS mode filters
and communicates up to 3.4 MHz on SDA and SCL
bus lines. The device will switch out of the HS mode on
the next STOP condition.
For more information on the HS mode, or other I2C
modes, please refer to the Philips I2C specification.
5.6
I2C Bus Characteristics
The I2C specification defines the following bus
protocol:
• Data transfer may be initiated only when the bus
is not busy
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition
Accordingly, the following bus conditions have been
defined using Figure 5-7.
5.6.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
5.6.2
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
5.6.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations can be ended with a STOP condition.
5.6.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition.
DS22088C-page 25
MCP3422/3/4
5.6.5
ACKNOWLEDGE AND NONACKNOWLEDGE
The Master (microcontroller) and the slave (MCP3422/
3/4) use an acknowledge pulse as a hand shake of
communication for each byte. The ninth clock pulse of
each byte is used for the acknowledgement. The clock
pulse is always provided by the Master
(microcontroller) and the acknowledgement is issued
by the receiving device of the byte (Note: The
transmitting device must release the SDA line during
the acknowledge pulse.). The acknowledgement is
achieved by pulling-down the SDA line “LOW” during
the 9th clock pulse by the receiving device.
(A)
(B)
During reads, the Master (microcontroller) can
terminate the current read operation by not providing
an acknowledge bit (not Acknowledge (NAK)) on the
last byte. In this case, the MCP3422/3/4 devices
release the SDA line to allow the Master
(microcontroller) to generate a STOP or repeated
START condition.
The non-acknowledgement (NAK) is issued by
providing the SDA line to “HIGH” during the 9th clock
pulse.
(D)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
FIGURE 5-7:
DS22088C-page 26
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
2
STOP
CONDITION
Data Transfer Sequence on I C Serial Bus.
© 2009 Microchip Technology Inc.
MCP3422/3/4
TABLE 5-4:
I2C SERIAL TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V to +5.0V,
VSS = 0V, CHn+ = CHn- = VREF/2.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Standard Mode (100 kHz)
Clock frequency
fSCL
0
—
100
kHz
Clock high time
THIGH
4000
—
—
ns
Clock low time
TLOW
4700
—
—
ns
SDA and SCL rise time
TR
—
—
1000
ns
SDA and SCL fall time
TF
—
—
300
ns
From VIH to VIL (Note 1)
START condition hold time
THD:STA
4000
—
—
ns
After this period, the first clock
pulse is generated.
START (Repeated) condition
setup time
TSU:STA
4700
—
—
ns
Data hold time
THD:DAT
0
—
3450
ns
Data input setup time
TSU:DAT
250
—
—
ns
STOP condition setup time
TSU:STO
4000
—
—
ns
TAA
0
—
3750
ns
(Note 2, Note 3)
TBUF
4700
—
—
ns
Time between START and STOP
conditions.
kHz
Output valid from clock
Bus free time
From VIL to VIH (Note 1)
(Note 3)
Fast Mode (400 kHz)
Clock frequency
TSCL
0
—
400
Clock high time
THIGH
600
—
—
ns
Clock low time
TLOW
1300
—
—
ns
SDA and SCL rise time
TR
20 + 0.1Cb
—
300
ns
SDA and SCL fall time
TF
20 + 0.1Cb
—
300
ns
From VIH to VIL (Note 1)
START condition hold time
THD:STA
600
—
—
ns
After this period, the first clock
pulse is generated
START (Repeated) condition
setup time
TSU:STA
600
—
—
ns
Data hold time
THD:DAT
0
—
900
ns
Data input setup time
TSU:DAT
100
—
—
ns
STOP condition setup time
TSU:STO
600
—
—
ns
TAA
0
—
1200
ns
(Note 2, Note 3)
TBUF
1300
—
—
ns
Time between START and STOP
conditions.
Output valid from clock
Bus free time
Note 1:
2:
3:
4:
From VIL to VIH (Note 1)
(Note 4)
This parameter is ensured by characterization and not 100% tested.
This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT)
plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).
If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this
parameter is too long, Clock Low time (TLOW) can be affected.
For Data Input: If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
© 2009 Microchip Technology Inc.
DS22088C-page 27
MCP3422/3/4
TABLE 5-4:
I2C SERIAL TIMING SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V to +5.0V,
VSS = 0V, CHn+ = CHn- = VREF/2.
Parameters
Sym
Min
Typ
Max
Units
Conditions
High Speed Mode (3.4 MHz)
Clock frequency
Clock high time
Clock low time
SCL rise time
(Note 1)
SCL fall time
(Note 1)
SDA rise time
(Note 1)
SDA fall time
(Note 1)
Data hold time
(Note 4)
Output valid from clock
(Notes 2 and 3)
fSCL
THIGH
TLOW
TR
TF
TR: DAT
TF: DATA
THD:DAT
TAA
0
—
3.4
MHz
Cb = 100 pF
0
—
1.7
MHz
Cb = 400 pF
60
—
—
ns
Cb = 100 pF, fSCL = 3.4 MHz
120
—
—
ns
Cb = 400 pF, fSCL = 1.7 MHz
160
—
—
ns
Cb = 100 pF, fSCL = 3.4 MHz
320
—
—
ns
Cb = 400 pF, fSCL = 1.7 MHz
—
—
40
ns
From VIL to VIH,
Cb = 100 pF, fSCL = 3.4 MHz
—
—
80
ns
From VIL to VIH,
Cb = 400 pF, fSCL = 1.7 MHz
—
—
40
ns
From VIH to VIL,
Cb = 100 pF, fSCL = 3.4 MHz
—
—
80
ns
From VIH to VIL,
Cb = 400 pF, fSCL = 1.7 MHz
—
—
80
ns
From VIL to VIH,
Cb = 100 pF, fSCL = 3.4 MHz
—
—
160
ns
From VIL to VIH,
Cb = 400 pF, fSCL = 1.7 MHz
—
—
80
ns
From VIH to VIL,
Cb = 100 pF, fSCL = 3.4 MHz
—
—
160
ns
From VIH to VIL,
Cb = 400 pF, fSCL = 1.7 MHz
0
—
70
ns
Cb = 100 pF, fSCL = 3.4 MHz
0
—
150
ns
Cb = 400 pF, fSCL = 1.7 MHz
—
—
150
ns
Cb = 100 pF, fSCL = 3.4 MHz
—
—
310
ns
Cb = 400 pF, fSCL = 1.7 MHz
After this period, the first clock
pulse is generated
START condition hold time
THD:STA
160
—
—
ns
START (Repeated) condition
setup time
TSU:STA
160
—
—
ns
Data input setup time
TSU:DAT
10
—
—
ns
STOP condition setup time
TSU:STO
160
—
—
ns
Note 1:
2:
3:
4:
This parameter is ensured by characterization and not 100% tested.
This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT)
plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).
If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this
parameter is too long, Clock Low time (TLOW) can be affected.
For Data Input: If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
DS22088C-page 28
© 2009 Microchip Technology Inc.
MCP3422/3/4
TF
SCL
TSU:STA
TLOW
SDA
TR
THIGH
TSP
THD:STA
TSU:DAT
THD:DAT
TSU:STO
TBUF
0.7VDD
0.3VDD
TAA
FIGURE 5-8:
I2C Bus Timing Data.
© 2009 Microchip Technology Inc.
DS22088C-page 29
MCP3422/3/4
NOTES:
DS22088C-page 30
© 2009 Microchip Technology Inc.
MCP3422/3/4
6.0
BASIC APPLICATION
CONFIGURATION
The MCP3422/3/4 devices can be used for various
precision analog-to-digital converter applications.
These devices operate with very simple connections to
the application circuit. The following sections discuss
the examples of the device connections and
applications.
6.1
6.1.1
Connecting to the Application
Circuits
The user can tie the Adr0 and Adr1 pins to VSS, VDD,
or left floating. See more details in Section 5.3.2
“Device Address Bits (A2, A1, A0) and Address
Selection Pins (MCP3423 and MCP3424)”.
MCP3424
Input
Input
Signal 1
1 CH1+
2 CH13 CH2+
Input
Signal 2
BYPASS CAPACITORS ON VDD PIN
For an accurate measurement, the application circuit
needs a clean supply voltage and must block any noise
signal to the MCP3422/3/4 devices. Figure 6-1 shows
an example of using two bypass capacitors (a 10 µF
tantalum capacitor and a 0.1 µF ceramic capacitor) on
the VDD line of the MCP3424. These capacitors are
helpful to filter out any high frequency noises on the
VDD line and also provide the momentary bursts of
extra currents when the device needs from the supply.
These capacitors should be placed as close to the VDD
pin as possible (within one inch). If the application
circuit has separate digital and analog power supplies,
the VDD and VSS of the MCP3422/3/4 devices should
reside on the analog plane.
6.1.2
I2C ADDRESS SELECTION PINS
(MCP3423 AND MCP3424)
6.1.3
CONNECTING TO I2C BUS USING
PULL-UP RESISTORS
The SCL and SDA pins of the MCP3422/3/4 are opendrain configurations. These pins require a pull-up
resistor as shown in Figure 6-1. The value of these
pull-up resistors depends on the operating speed
(standard, fast, and high speed) and loading
capacitance of the I2C bus line. Higher value of pull-up
resistor consumes less power, but increases the signal
transition time (higher RC time constant) on the bus.
Therefore, it can limit the bus operating speed. The
lower value of resistor, on the other hand, consumes
higher power, but allows higher operating speed. If the
bus line has higher capacitance due to long bus line or
high number of devices connected to the bus, a smaller
pull-up resistor is needed to compensate the long RC
time constant. The pull-up resistor is typically chosen
between 5 kΩ and 10 kΩ ranges for standard and fast
modes, and less than 1 kΩ for high speed mode
depending on the presence of bus loading capacitance.
C1
CH4- 14
Signal 4
CH4+ 13
CH3- 12
4 CH25 VSS
CH3+ 11
6 VDD
7 SDA
Adr0 9
SCL 8
Input
Signal 3
I2C Address
Selection
Pins
Adr1 10
C2
TO MCU
(MASTER)
RP
RP
VDD
Rp is the pull-up resistor:
5 kΩ - 10 kΩ for fSCL = 100 kHz to 400 kHz
~700Ω for fSCL = 3.45 MHz
C1: 0.1 µF, Ceramic capacitor
C2: 10 µF, Tantalum capacitor
FIGURE 6-1:
Typical Connection.
Figure 6-2 shows an example of multiple device
connections. The I2C bus loading capacitance
increases as the number of device connected to the I2C
bus line increases. The bus loading capacitance affects
on the bus operating speed. For example, the highest
bus operating speed for the 400 pF bus capacitance is
1.7 MHz, and 3.4 MHz for 100 pF. Therefore, the user
needs to consider the relationship between the
maximum operation speed versus. the number of I2C
devices that are connected to the I2C bus line.
SDA SCL
Microcontroller
(PIC16F876)
MCP3422
MCP3423
MCP3424
MCP4725
FIGURE 6-2:
Example of Multiple Device
Connection on I2C Bus.
© 2009 Microchip Technology Inc.
DS22088C-page 31
MCP3422/3/4
6.1.4
DEVICE CONNECTION TEST
6.1.5
The user can test the presence of the MCP3422/3/4 on
the I2C bus line without performing an input data
conversion. This test can be achieved by checking an
acknowledge response from the MCP3422/3/4 after
sending a read or write command. Here is an example
using Figure 6-3:
a.
b.
Set the R/W bit “HIGH” in the address byte.
Check the ACK pulse after sending the address
byte.
If the device acknowledges (ACK = 0), then the
device is connected, otherwise it is not
connected.
c.
DIFFERENTIAL AND SINGLEENDED CONFIGURATION
Figure 6-4 shows typical connection examples for
differential and single-ended inputs. Differential input
signals can be connected to the CHn+ and CHn- input
pins, where n = the channel number (1, 2, 3, or 4). For
the single-ended input, the input signal is applied to one
of the input pins (typically connected to the CHn+ pin)
while the other input pin (typically CHn- pin) is
grounded. All device characteristics hold for the singleended configuration, but this configuration loses one bit
resolution because the input can only stand in positive
half scale. Refer to Section 1.0 “Electrical Characteristics”.
Send STOP or START bit.
(a) Differential Input Signal Connection:
Address Byte
Excitation
Sensor
1
SCL
2
3
4
5
6
7
8
9
CHn+
1
SDA
Start
Bit
1
1 A2 A1 A0 1
0
Device bits
ACK
Input Signal
CHnMCP342X
Stop
Bit
Address bits
R/W
MCP342X
Response
FIGURE 6-3:
(b) Single-ended Input Signal Connection:
Excitation
R1
I2C Bus Connection Test.
CHn+
Sensor
Input Signal
R2
CHnMCP342X
FIGURE 6-4:
Differential and SingleEnded Input Connections.
DS22088C-page 32
© 2009 Microchip Technology Inc.
MCP3422/3/4
6.2
Application Examples
For the current measurement, the device measure the
voltage across the current sensor, and converts it by
dividing the measured voltage by a known resistance
value. The voltage drops across the sensor is waste.
Therefore, the current measurement often prefers to
use a current sensor with smaller resistance value,
which, in turn, requires high resolution ADC device.
The MCP3422/3/4 devices can be used for broad
ranges of sensor and data acquisition applications.
Figure 6-5 shows a circuit example measuring both the
battery voltage and current using the MCP3422 device.
Channels 1 and 2 are measuring the voltage and the
current, respectively.
The device can measure the input voltage as low as
2 µV range (or current in ~ µA range) with 18 bit
resolution and PGA = 8 settings.
When the input voltage is greater than the internal reference voltage (VREF = 2.048V), it needs a voltage
divider circuit to prevent the output code from being
saturated. In the example, R1 and R2 form a voltage
divider. The R1 and R2 are set to yield VIN to be less
than the internal reference voltage (VREF = 2.048V).
The MSB (= sign bit) of the output code determines the
direction of the current, which identifies the charging or
the discharging current.
Discharging Current
Current Sensor
Charging
Current
To Load
To Battery
R1
Battery
(Rechargeable)
VBAT
MCP3422
VIN
R2
0.1 µF
1 CH1+ CH2-8
2 CH1- CH2+7
VSS 6
3 VDD
4 SDA
SCL 5
SCL
10 µF
R2
V IN = ------------------ × V BAT
R1 + R2
To MCU
(MASTER)
SDA
5 kΩ
5 kΩ
R1 and R2 = Voltage Divider
FIGURE 6-5:
VDD
Battery Voltage and Charging/Discharging Current Measurement.
© 2009 Microchip Technology Inc.
DS22088C-page 33
MCP3422/3/4
Figure 6-6, shows an example of using the
MCP3424 for four-channel thermocouple temperature
measurement applications.
Thermocouple Sensor
Isothermal Block
Isothermal Block
MCP3424
MCP9800
SCL
SDA
0.1 µF
1
2
3
4
5
6
7
CH1+
CH1CH2+
CH2VSS
VDD
SDA
MCP9800
CH4- 14
13
12
11
CH4+
CH3CH3+
Adr1
Adr0
SCL
SDA
SCL
10
9
8
VDD
MCP9800
MCP9800
10 µF
SDA
Heat
SCL
SCL
SCL
SDA
TO MCU
(MASTER)
SDA
5 kΩ
FIGURE 6-6:
VDD
Four-Channel Thermocouple Applications.
With Type K thermocouple, it can measure
temperature from 0°C to 1250°C degrees. The full
scale output range of the Type K thermocouple is
about 50 mV. This provides 40 µV/°C (= 50 mV/
1250°C) of measurement resolution. Equation 6-1
shows the measurement budget for sensor signal using
the MCP3422/3/4 device with 18 bits and
PGA = 8 settings. With this configuration, the
MCP3424 can detect the input signal level as low as
approximately 2 µV. The internal PGA boosts the input
signal level eight times. The 40 µV/°C input from the
thermocouple is amplified internally to 320 µV/°C
before the conversion takes place. This results in
20.48 LSB/°C output codes. This means there are
about 20 LSB output codes (or about 4.32 bits) per 1°C
of change in temperature.
DS22088C-page 34
5 kΩ
EQUATION 6-1:
Detectable Input Signal Level = 15.625 μ V/PGA
= 1.953125 μ V for PGA = 8
Input Signal Level after gain of 8:
= ( 40 μ V/°C ) • 8 = 320 μ V/°C
μ V/°C- = 20.48 Codes/°C
No. of LSB/°C = 320
-----------------------15.625 μ V
Where:
1 LSB
=
15.625 µV with 18 bit configuration
© 2009 Microchip Technology Inc.
MCP3422/3/4
Equation 6-2 shows an example of calculating the
expected number of output code with various PGA gain
settings for Type K thermocouple output.
EQUATION 6-2:
EXPECTED NUMBER OF
OUTPUT CODE FOR TYPE
K THERMOCOUPLE
Expected
⎛
⎞
50 mV
Number of Output Code = log 2 ⎜⎜ ------------------------⎟⎟
15.625 μ V
⎝ ------------------------⎠
PGA
= 11.6 bits for PGA = 1
= 12.6 bits for PGA = 2
= 13.6 bits for PGA = 4
= 14.6 bits for PGA = 8
Where:
1 LSB
=
15.625 µV with 18 Bit configuration.
VDD
VDD
Pressure Sensor
(NPP301)
Pressure Sensor
(NPP301)
MCP3424
VIN
1 CH1+
CH4- 14
2 CH1-
CH4+
CH3CH3+
Adr1
3 CH2+
4 CH2-
VDD
5 VSS
0.1 µF
R1
6 VDD
7 SDA
13
12
11
10
VDD
R1
Adr0 9
SCL 8
R2
10 µF
Thermistor
VDD
VIN
Thermistor
TO MCU
(MASTER)
R2
5 kΩ
5 kΩ
VDD
R2
V IN = ------------------- × V DD
R1 + R2
R1 and R2 = Voltage Divider
FIGURE 6-7:
Example of Pressure and Temperature Measurement.
Figure 6-7 shows an example of measuring both
pressure and temperature. The pressure is measured
by using NPP 301 (manufactured by GE NovaSensor),
and temperature is measured by a thermistor.
The pressure sensor output is 20 mV/V. This gives
100 mV of full scale output for VDD of 5V (sensor
© 2009 Microchip Technology Inc.
excitation voltage). Equation 6-3 shows an example of
calculating the number of output code for the full scale
output of the NPP301.
DS22088C-page 35
MCP3422/3/4
EQUATION 6-3:
EXPECTED NUMBER OF
OUTPUT CODE FOR
NPP301 PRESSURE
SENSOR
⎛
⎞
Expected
⎜ 100 mV-⎟
Number of Output Code = log 2 ⎜ ----------------------15.625 μ V⎟
⎝ ------------------------⎠
PGA
= 12.64 bits for PGA = 1
= 13.64 bits for PGA = 2
= 14.64 bits for PGA = 4
= 15.64 bits for PGA = 8
Where:
1 LSB
=
15.625 µV with 18 Bit configuration.
The thermistor temperature sensor can measure the
temperature range from -100°C to 300°C. The
resistance of the thermistor sensor decreases as
temperature
increases
(negative
temperature
coefficient). As shown in Figure 6-7, the thermistor (R2)
forms a voltage divider with R1.
The thermistor sensor is simple to use and widely used
for the temperature measurement applications. It has
both linear and non-linear responses over temperature
range. R1 is used to adjust the linear region of interest
for measurement.
DS22088C-page 36
© 2009 Microchip Technology Inc.
MCP3422/3/4
7.0
7.1
DEVELOPMENT TOOL
SUPPORT
USB Cable
to PC
MCP3422/3/4 Evaluation Boards
The Evaluation Boards for MCP3422/3/4 devices are
available from Microchip Technology Inc. The boards
work with Microchip’s PICkit™ Serial Analyzer. The
user can simply connect any sensing voltage to the
input test pads of the board and read conversion codes
using the easy-to-use PICkit™ Serial Analyzer. Refer
to www.microchip.com for further information on this
product’s capabilities and availability.
PICkit
Serial
Analog
Input
MCP3424 Evaluation Board
FIGURE 7-2:
Setup for the MCP3424
Evaluation Board with PICkit™ Serial Analyzer.
FIGURE 7-1:
MCP3424 Evaluation Board.
FIGURE 7-3:
Example of PICkit™ Serial User Interface.
© 2009 Microchip Technology Inc.
DS22088C-page 37
MCP3422/3/4
NOTES:
DS22088C-page 38
© 2009 Microchip Technology Inc.
MCP3422/3/4
8.0
PACKAGING INFORMATION
8.1
Package Marking Information
8-Lead DFN (2x3) (MCP3422)
XXX
YWW
NN
Example:
AGM
929
25
8-Lead MSOP (MCP3422)
Example:
XXXXXX
3422A0
YWWNNN
929256
8-Lead SOIC (300 mil) (MCP3422)
XXXXXXXX
XXXXXNNN
YYWW
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
3422A0E
e3
SN^^256
0929
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
DS22088C-page 39
MCP3422/3/4
Package Marking Information (Continued)
10-Lead DFN (3x3) (MCP3423)
1
2
3
4
10
1
9
2
8
3
7
4
6
5
XXXX
XYWW
NNN
5
10-Lead MSOP (MCP3423)
XXXXXX
YWWNNN
14-Lead SOIC (150 mil) (MCP3424)
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
14-Lead TSSOP (4.4 mm) (MCP3424)
XXXXXXXX
DS22088C-page 40
Example:
10
3423
0929
256
9
8
7
6
Example:
3423E
929256
Example:
MCP3424
e3
E/SL^^
0929256
Example:
MCP3424E
YYWW
0929
NNN
256
© 2009 Microchip Technology Inc.
MCP3422/3/4
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© 2009 Microchip Technology Inc.
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© 2009 Microchip Technology Inc.
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DS22088C-page 51
MCP3422/3/4
NOTES:
DS22088C-page 52
© 2009 Microchip Technology Inc.
MCP3422/3/4
APPENDIX A:
REVISION HISTORY
Revision C (August 2009)
The following is the list of modifications:
1.
2.
Updated the EDS protection parameters.
Updated the package marking information and
package outline drawings.
Revision B (October 2008)
The following is the list of modifications:
1.
2.
3.
Added MCP3422 and MCP3423 devices
throughout this data sheet.
Added new package marking information and
package outline drawings for MCP3422 and
MCP3423 devices.
Added MCP3422 and MCP3423 devices to
Product Identification System page.
Revision A (June 2008)
• Original Release of this Document.
© 2009 Microchip Technology Inc.
DS22088C-page 53
MCP3422/3/4
NOTES:
DS22088C-page 54
© 2009 Microchip Technology Inc.
MCP3422/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
XX
X
X
/XX
Examples:
Device
Address
Options
Tape and
Reel
Temperature
Range
Package
MCP3422
a)
Device:
MCP3422:
MCP3423:
MCP3424:
Address Options:
Tape and Reel
2-Channel 18-Bit ADC
2-Channel 18-Bit ADC
4-Channel 18-Bit ADC
b)
XX = Address Options. Refer to table below.
For MCP3422 only.
T
c)
= Tape and Reel
d)
Temperature Range: E
= -40°C to +125°C
Package:
=
=
=
=
=
=
=
MC
MF
MS
SL
SN
ST
UN
Plastic Dual Flat, No Lead (2x3 DFN), 8-lead
Plastic Dual Flat, No Lead (3x3 DFN) 10-lead
Plastic Micro Small Outline (MSOP), 8-lead
Plastic SOIC (150 mil Body), 14-lead
Plastic SOIC (3.90mm Body), 8-lead,
Plastic TSSOP (4.4mm Body), 14-lead
Plastic Micro Small Outline (MSOP), 10-lead
Address Options for MCP3422:
A2
A1
A0
A0 * =
0
0
0
A1 =
0
0
1
A2 =
0
1
0
A3 =
0
1
1
A4 =
1
0
0
A5 =
1
0
1
A6 =
1
1
0
A7 =
1
1
1
*
Default option. Contact Microchip factory for other address
options.
© 2009 Microchip Technology Inc.
f)
MCP3423
Address Options
* XX
e)
MCP3422A0-E/MC: 2-Channel ADC,
A0 Address Option,
8LD DFN package.
MCP3422A0T-E/MC: Tape and Reel,
2-Channel ADC,
A0 Address Option,
8LD DFN package.
MCP3422A0-E/MS: 2-Channel ADC,
A0 Address Option,
8LD MSOP package.
MCP3422A0T-E/MS: Tape and Reel,
2-Channel ADC,
A0 Address Option,
8LD MSOP package.
MCP3422A0-E/SN: 2-Channel ADC,
A0 Address Option,
8LD SOIC package.
MCP3422A0T-E/SN: Tape and Reel,
2-Channel ADC,
A0 Address Option,
8LD SOIC package.
a)
MCP3423-E/MF:
b)
MCP3423T-E/MF:
c)
MCP3423-E/UN:
d)
MCP3423T-E/UN:
2-Channel ADC,
10LD DFN package.
Tape and Reel,
2-Channel ADC,
10LD DFN package.
2-Channel ADC,
10LD MSOP pkg.
Tape and Reel,
2-Channel ADC,
10LD MSOP pkg.
MCP3424
a)
MCP3424-E/SL:
b)
MCP3424T-E/SL:
c)
MCP3424-E/ST:
d)
MCP3424T-E/ST:
4-Channel ADC,
14LD SOIC package.
Tape and Reel,
4-Channel ADC,
14LD SOIC package.
4-Channel ADC,
14LD TSSOP pkg.
Tape and Reel,
4-Channel ADC,
14LD TSSOP pkg.
DS22088C-page 55
MCP3422/3/4
NOTES:
DS22088C-page 56
© 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICkit, PICDEM, PICDEM.net,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, WiperLock and ZENA are trademarks
of Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc.
DS22088C-page 57
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03/26/09
DS22088C-page 58
© 2009 Microchip Technology Inc.